ICS PCA9513

INTEGRATED CIRCUITS
PCA9513; PCA9514
Hot swappable I2C and SMBus bus buffer
Product data sheet
Supersedes data of 2004 Jan 07
Philips
Semiconductors
2004 Oct 05
Philips Semiconductors
Product data sheet
Hot swappable I2C and SMBus bus buffer
PCA9513; PCA9514
DESCRIPTION
The PCA9513 and PCA9514 are hot swappable I2C and SMBus
buffers that allows I/O card insertion into a live backplane without
corrupting the data and clock buses. Control circuitry prevents the
backplane from being connected to the card until a stop command
or bus idle occurs on the backplane without bus contention on the
card. When the connection is made, the PCA9511, PCA9513, and
PCA9514 provides bi-directional buffering, keeping the backplane
and card capacitances isolated.
Rise time accelerator circuitry allows the use of weaker DC pull-up
currents while still meeting rise time requirements. The PCA9513
and PCA9514 incorporate a digital ENABLE input pin, which
enables the device when asserted HIGH and forces the device into
a low current mode when asserted LOW, and an open-drain READY
output pin, which indicates that the backplane and card sides are
connected together (HIGH) or not (LOW).
FEATURES
• Bi-directional buffer for SDA and SCL lines increases fanout and
prevents SDA and SCL corruption during live board insertion and
removal from multi-point backplane systems
• Compatible with I2C standard mode, I2C fast mode, and SMBus
The PCA9513 supplies a 92 µA current source to SCLIN and SDAIN
in lieu of using pull-up resistors for PICMG backplane applications.
Including the current source in the device provides for a consistent
RC time constant as cards are removed and inserted into the
backplane. The current source is high-impedance whenever the pin
voltage is greater than the part VCC.
standards
• ∆V/∆t rise time accelerators on all SDA and SCL lines
• Rise time accelerator threshold moved from 0.6 V to 0.8 V for
improved noise margin
• Active HIGH ENABLE input
• Active HIGH READY open-drain output
• High-impedance SDA and SCL pins for VCC = 0 V
• 92 µA current source on SCLIN and SDAIN for PICMG backplane
PCA9513 and PCA9514 rise time accelerator threshold is 0.8 V to
provide improved noise margin over the PCA9510 and PCA9511.
The dynamic offset design of the PCA9510/11/12/13/14 I/O drivers
allow them to be connected to another PCA9510/11/12/13/14 device
in series or in parallel and to the A side of the PCA9517. The
PCA9510/11/12/13/14 can not connect to the static offset I/Os used
on the PCA9515/15A/16/16A/17 B side and PCA9518.
applications (PCA9513 only)
• Supports clock stretching and multiple master
arbitration/synchronization
• Operating power supply voltage range: 2.7 V to 5.5 V
• 5.5 V tolerant I/Os
• 0 kHz to 400 kHz clock frequency
• ESD protection exceeds 2000 V HBM per JESD22-A114,
APPLICATION
• cPCI, VME, AdvancedTCA cards and other multi-point backplane
cards that are required to be inserted or removed from an
operating system.
200 V MM per JESD22-A115, and 1000 V CDM per
JESD22-C101
• Latch-up testing is done to JEDEC Standard JESD78 which
exceeds 100 mA
• Packages offered: SO8, TSSOP8 (MSOP8)
ORDERING INFORMATION
TEMPERATURE RANGE
ORDER CODE
TOPSIDE MARK
DRAWING NUMBER
8-pin plastic SO
PACKAGES
–40 °C to +85 °C
PCA9513D
PCA9513
SOT96-1
8-pin plastic SO
–40 °C to +85 °C
PCA9514D
PCA9514
SOT96-1
8-pin plastic TSSOP (MSOP)
–40 °C to +85 °C
PCA9513DP
9513
SOT505-1
8-pin plastic TSSOP (MSOP)
–40 °C to +85 °C
PCA9514DP
9514
SOT505-1
Standard packing quantities and other packaging data are available at www.standardproducts.philips.com/packaging.
2004 Oct 05
2
Philips Semiconductors
Product data sheet
Hot swappable I2C and SMBus bus buffer
PIN CONFIGURATION
PCA9513; PCA9514
PIN DESCRIPTION
TOP VIEW
ENABLE 1
8
VCC
SCLOUT
2
7
SDAOUT
SCLIN
3
6
SDAIN
GND
4
5
READY
PIN
SYMBOL
DESCRIPTION
1
ENABLE
Chip enable pin. Grounding this pin puts the
part in a low current (< 1 µA) mode. It also
disables the rise time accelerators, isolates
SDAIN from SDAOUT and isolates SCLIN
from SCLOUT.
2
SCLOUT
Serial clock output to and from the SCL bus
on the card.
3
SCLIN
Serial clock input to and from the SCL bus
on the backplane.
4
GND
Ground. Connect this pin to a ground plane
for best results.
5
READY
This is an open-drain output which pulls
LOW when SDAIN and SCLIN are
disconnected from SDAOUT and SCLOUT,
and turns off when the two sides are
connected.
6
SDAIN
Serial data input to and from the SDA bus on
the backplane.
7
SDAOUT
Serial data output to and from the SDA bus
on the card.
8
VCC
Power supply.
SW01045
Figure 1. Pin configuration.
FEATURE SELECTION CHART
FEATURES
PCA9510
PCA9511
PCA9512
PCA9513
PCA9514
Idle detect
Yes
Yes
Yes
Yes
Yes
high-impedance SDA, SCL pins for VCC = 0 V
Yes
Yes
Yes
Yes
Yes
Rise time accelerator circuitry on all SDA and SCL lines
—
Yes
Yes
Yes
Yes
Rise time accelerator circuitry hardware disable pin for lightly loaded systems
—
—
Yes
—
—
Rise time accelerator threshold 0.8 V vs 0.6 V improves noise margin
Ready open drain output
Two VCC pins to support 5 V to 3.3 V level translation with improved noise
margins
1 V precharge on all SDA and SCL lines
92 µA current source on SCLIN and SDAIN for PICMG applications
2004 Oct 05
3
—
—
—
Yes
Yes
Yes
Yes
—
Yes
Yes
—
—
Yes
—
—
IN only
Yes
Yes
—
—
—
—
—
Yes
—
Philips Semiconductors
Product data sheet
Hot swappable I2C and SMBus bus buffer
PCA9513; PCA9514
TYPICAL APPLICATION — PCA9513
VCC
(2.7 V to
5.5 V)
C1
0.01 µF
8
SCLIN
SDAIN
R5
10 kΩ
3
2
6
7
1
ENABLE
R3
10 kΩ
R4
10 kΩ
SCLOUT
SDAOUT
5
ENABLE
READY
GND
4
SW02158
Figure 2. Typical application — PCA9513
BLOCK DIAGRAM — PCA9513
92 mA
OVERVOLTAGE
CUTOFF
2 mA
2 mA
SLEW RATE
DETECTOR
SLEW RATE
DETECTOR
BACKPLANE-TO-CARD
CONNECTION
SDAIN 6
8
VCC
7
SDAOUT
2
SCLOUT
CONNECT
CONNECT
PCA9513
92 mA
OVERVOLTAGE
CUTOFF
2 mA
2 mA
SLEW RATE
DETECTOR
SLEW RATE
DETECTOR
BACKPLANE-TO-CARD
CONNECTION
SCLIN 3
CONNECT
CONNECT
0.55VCC/
0.45VCC
0.5 µA
0.55VCC/
0.45VCC
UVLO
ENABLE 1
STOP BIT AND
BUS IDLE
CONNECT
20 pF
130 µs
DELAY
UVLO
RD
QB
5
READY
4
GND
S
CONNECT
0.5 pF
SW02159
Figure 3. Block diagram — PCA9513
2004 Oct 05
4
Philips Semiconductors
Product data sheet
Hot swappable I2C and SMBus bus buffer
PCA9513; PCA9514
TYPICAL APPLICATION — PCA9514
VCC
(2.7 V to
5.5 V)
R1
10 kΩ
R2
10 kΩ
SCLIN
SDAIN
C1
0.01 µF
8
R5
10 kΩ
3
2
6
7
R4
10 kΩ
SCLOUT
SDAOUT
5
1
ENABLE
R3
10 kΩ
ENABLE
READY
GND
4
SW02160
Figure 4. Typical application — PCA9514
BLOCK DIAGRAM — PCA9514
2 mA
2 mA
SLEW RATE
DETECTOR
SLEW RATE
DETECTOR
BACKPLANE-TO-CARD
CONNECTION
SDAIN 6
8
VCC
7
SDAOUT
2
SCLOUT
CONNECT
CONNECT
PCA9514
2 mA
2 mA
SLEW RATE
DETECTOR
SLEW RATE
DETECTOR
BACKPLANE-TO-CARD
CONNECTION
SCLIN 3
CONNECT
CONNECT
0.55VCC/
0.45VCC
0.5 µA
0.55VCC/
0.45VCC
UVLO
ENABLE 1
STOP BIT AND
BUS IDLE
CONNECT
20 pF
130 µs
DELAY
UVLO
RD
QB
5
READY
4
GND
S
CONNECT
0.5 pF
SW02161
Figure 5. Block diagram — PCA9514
2004 Oct 05
5
Philips Semiconductors
Product data sheet
Hot swappable I2C and SMBus bus buffer
OPERATION
PCA9513; PCA9514
Maximum number of devices in series
Each buffer adds about 0.065 V dynamic level offset at 25 °C with
the offset larger at higher temperatures. Maximum offset (VOS) is
0.150 V. The LOW level at the signal origination end (master) is
dependent upon the load and the only specification point is the
I2C-bus specification of 3 mA will produce VOL < 0.4 V, although if
lightly loaded the VOL may be ∼0.1 V. Assuming VOL = 0.1 V and
VOS = 0.1 V, the level after four buffers would be 0.5 V, which is only
about 0.1 V below the threshold of the rising edge accelerator (about
0.6 V). With great care a system with four buffers may work, but as
the VOL moves up from 0.1 V, noise or bounces on the line will result
in firing the rising edge accelerator thus introducing false clock
edges. Generally it is recommended to limit the number of buffers in
series to two.
Start-up
An under voltage/initialization circuit holds the parts in a
disconnected state which presents high-impedance to all SDA and
SCL pins during power-up. A LOW on the enable pin also forces the
parts into the low current disconnected state when the ICC is
essentially zero. As the power supply is brought up and the enable
is HIGH or the part is powered and the enable is taken from LOW to
HIGH it enters an initialization state where the internal references
are stabilized. The 92 µA input pull-ups on PCA9513 are also
enabled in the initialization state. At the end of the initialization state
the “Stop Bit And Bus Idle” detect circuit is enabled. With the
ENABLE pin HIGH long enough to complete the initialization state
and remaining HIGH when all the SDA and SCl pins have been
HIGH for the bus idle time or when all pins are HIGH and a stop
condition is seen on the SDAIN and SCLIN pins, SDAIN is
connected to SDAOUT and SCLIN is connected to SCLOUT.
The PCA9510 (rise time accelerator is permanently disabled) and
the PCA9512 (rise time accelerator can be turned off) are a little
different with the rise time accelerator turned off because the rise
time accelerator will not pull the node up, but the same logic that
turns on the accelerator turns the pull-down off. If the VIL is above
∼0.6 V and a rising edge is detected, the pull-down will turn off and
will not turn back on until a falling edge is detected; so if the noise is
small enough it may be possible to use more than two PCA9510 or
PCA9512 parts in series but is not recommended.
A 92 µA pull-up current source on SDAIN and SCLIN of PCA9513 is
activated during the initialization state and remain active until the
power is removed or the enable is taken LOW. When the 92 µA
pull-up is active it will become high-impedance any time the pin
voltage is greater than VCC, otherwise it provides current to pull the
pin up to VCC.
Connect Circuitry
buffer A
Once the connection circuitry is activated, the behavior of SDAIN
and SDAOUT as well as SCLIN and SCLOUT become identical with
each acting as a bidirectional buffer that isolates the input
capacitance from the output bus capacitance while communicating
the logic levels. A LOW forced on either SDAIN or SDAOUT will
cause the other pin to be driven to a LOW by the part. The same is
also true for the SCL pins. Noise between 0.7VCC and VCC is
generally ignored because a falling edge is only recognized when it
falls below 0.7VCC with a slew rate of at least 1.25 V/µs. When a
falling edge is seen on one pin the other pin in the pair turns on a
pull down driver that is referenced to a small voltage above the
falling pin. The driver will pull the pin down at a slew rate determined
by the driver and the load initially, because it does not start until the
first falling pin is below 0.7VCC. The first falling pin may have a fast
or slow slew rate, if it is faster than the pull down slew rate then the
initial pull down rate will continue. If the first falling pin has a slow
slew rate then the second pin will be pulled down at its initial slew
rate only until it is just above the first pin voltage the they will both
continue down at the slew rate of the first.
SLAVE B
common
node
buffer C
SLAVE C
SW02353
Figure 6.
Consider a system with three buffers connected to a common node
and communication between the Master and Slave B that are
connected at either end of Buffer A and Buffer B in series as shown
in Figure 6. Consider if the VOL at the input of Buffer A is 0.3 V and
the VOL of Slave B (when acknowledging) is 0.4 V with the direction
changing from Master to Slave B and then from Slave B to Master.
Before the direction change you would observe VIL at the input of
Buffer A of 0.3 V and its output, the common node, is ∼0.4 V. The
output of Buffer B and Buffer C would be ∼0.5 V, but Slave B is
driving 0.4 V, so the voltage at Slave B is 0.4 V. The output of
Buffer C is ∼0.5 V. When the Master pull-down turns off, the input of
Buffer A rises and so does its output, the common node, because it
is the only part driving the node. The common node will rise to 0.5 V
before Buffer B’s output turns on, if the pull-up is strong the node will
bounce. If the bounce goes above the threshold for the rising edge
accelerator ∼0.6 V the accelerators on both Buffer A and Buffer C
will fire contending with the output of Buffer B. The node on the input
of Buffer A will go HIGH as will the input node of Buffer C. After the
common node voltage is stable for a while the rising edge
accelerators will turn off and the common node will return to ∼0.5 V
because the Buffer B is still on. The voltage at both the Master and
Slave C nodes would then fall to ∼0.6 V until Slave B turned off. This
would not cause a failure on the data line as long as the return to
0.5 V on the common node (∼0.6 V at the Master and Slave C)
occurred before the data setup time. If this were the SCL line, the
parts on Buffer A and Buffer C would see a false clock rather than a
stretched clock, which would cause a system error.
Once both sides are LOW they will remain LOW until all the external
drivers have stopped driving LOWs. If both sides are being driven
LOW to the same value for instance, 10 mV by external drivers,
which is the case for clock stretching and is typically the case for
acknowledge, and one side external driver stops driving that pin will
rise and rise above the nominal offset voltage until the internal driver
catches up and pulls it back down to the offset voltage. This bounce
is worst for low capacitances and low resistances, and may become
excessive. When the last external driver stops driving a LOW, that
pin will bounce up and settle out just above the other pin as both rise
together with a slew rate determined by the internal slew rate control
and the RC time constant. As long as the slew rate is at least
1.25 V/µs, when the pin voltage exceeds 0.8 V for PCA9513 and
PCA9514, rise time accelerators circuits are turned on and the pull
down driver is turned off.
2004 Oct 05
buffer B
MASTER
6
Philips Semiconductors
Product data sheet
Hot swappable I2C and SMBus bus buffer
PCA9513; PCA9514
Propagation Delays
30
The delay for a rising edge is determined by the combined pull-up
current from the bus resistors and the rise time accelerator current
source and the effective capacitance on the lines. If the pull-up
currents are the same, any difference in rise time is directly
proportional to the difference in capacitance between the two sides.
The tPLH may be negative if the output capacitance is less than the
input capacitance and would be positive if the output capacitance is
larger than the input capacitance, when the currents are the same.
RPULLUP
(kΩ)
25
RMAX = 24 kΩ
20
15
The tPHL can never be negative because the output does not start to
fall until the input is below 0.7VCC, and the output turn on has a non
zero delay, and the output has a limited maximum slew rate, and
even if the input slew rate is slow enough that the output catches up
it will still lag the falling voltage of the input by the offset voltage. The
maximum tPHL occurs when the input is driven LOW with zero delay
and the output is still limited by its turn on delay and the falling edge
slew rate. The output falling edge slew rate is a function of the
internal maximum slew rate which is a function of temperature, VCC,
and process, as well as the load current and the load capacitance.
RISE-TIME > 300 ns
21
RECOMMENDED
PULL-UP
5
0
0
100
200
300
400
CBUS (pF)
Rise Time Accelerators
During positive bus transitions a 2 mA current source is switched on
to quickly slew the SDA and SCL lines HIGH once the input level of
0.8 V for the PCA9513 and PCA9514 are exceeded. The rising edge
rate should be at least 1.25 V/µs to guarantee turn on of the
accelerators. The 0.8 V threshold of PCA9513 and PCA9514 allows
for larger bounce-or-noise without falsely triggering the rise time
accelerators.
SW02115
Figure 7. Bus requirements for 3.3 V systems
20
RPULLUP
(kΩ)
RMAX = 16 kΩ
15
READY Digital Output
RISE-TIME
> 300 ns
This pin provides a digital flag which is LOW when either ENABLE is
LOW or the start-up sequence described earlier in this section has
not been completed. READY goes HIGH when ENABLE is HIGH
and start-up is complete. The pin is driven by an open drain
pull-down capable of sinking 3 mA while holding 0.4 V on the pin.
Connect a resistor of 10 kΩ to VCC to provide the pull-up.
21
RECOMMENDED
PULL-UP
5
ENABLE Low Current Disable
Grounding the ENABLE pin disconnects the backplane side from the
card side, disables the rise-time accelerators, drives READY LOW,
disables the bus precharge circuitry, and puts the part in a LOW
current state. When the pin voltage is driven all the way to VCC, the
part waits for data transactions on both the backplane and card
sides to be complete before reconnecting the two sides.
0
0
300
400
SW02116
Figure 8. Bus requirements for 5 V systems
The system pull-up resistors must be strong enough to provide a
positive slew rate of 1.25 V/µs on the SDA and SCL pins, in order to
activate the boost pull-up currents during rising edges. Choose
maximum resistor value using the formula:
Minimum SDA and SCL Capacitance Requirements
The device connection circuitry requires a minimum capacitance
loading on the SDA and SCL pins in order to function properly. The
value of this capacitance is a function of VCC and the bus pull-up
resistance. Estimate the bus capacitance on both the backplane and
the card data and clock buses, and refer to Figures 7 and 8 to
choose appropriate pull-up resistor values. Note from the figures
that 5 V systems should have at least 47 pF capacitance on their
buses and 3.3 V systems should have at least 22 pF capacitance for
proper operation. Although the device has been designed to be
marginally stable with smaller capacitance loads, for applications
with less capacitance, provisions need to be made to add a
capacitor to ground to ensure these minimum capacitance
conditions if oscillations are noticed during initial signal integrity
verification.
* where R is the pull-up resistor value in Ω, VCC(MIN) is the
minimum VCC voltage in volts and C is the equivalent bus
capacitance in picofarads (pF).
In addition, regardless of the bus capacitance, always choose R ≤
16 kΩ for VCC = 5.5 V maximum, R ≤ 24 kΩ for VCC = 3.6 V
maximum. The start-up circuitry requires logic high voltages on
SDAOUT and SCLOUT to connect the backplane to the card, and
these pull-up values are needed to overcome the precharge voltage
(PCA9511 only). See the curves in Figures 7 and 8 for guidance in
resistor pull-up selection.
2004 Oct 05
200
CBUS (pF)
Resistor Pull-up Value Selection
v @ 100
7
Philips Semiconductors
Product data sheet
Hot swappable I2C and SMBus bus buffer
PCA9513; PCA9514
meet. Placing a bus buffer on the edge of each card, however,
isolates the card capacitance from the backplane. For a given I/O
card, the PCA9513 or PCA9514 drives the capacitance of
everything on the card and the backplane must drive only the the
capacitance of the bus buffer, which is less than 10 pF, the
connector, trace, and all additional cards on the backplane.
Hot Swapping and Capacitance Buffering
Application
Figures 9 through 12 illustrate the usage of the PCA9513 and
PCA9514 in applications that take advantage of both its hot
swapping and capacitance buffering features. In all of these
applications, note that if the I/O cards were plugged directly into the
backplane, all of the backplane and card capacitances would add
directly together, making rise- and fall-time requirements difficult to
See Application Note AN10160, Hot Swap Bus Buffer for more
information on applications and technical assistance.
BACKPLANE
CONNECTOR
I/O PERIPHERAL CARD 1
VCC
R1
10 kΩ
BD_SEL
SDA
SCL
R2
10 kΩ
STAGGERED CONNECTOR
BACKPLANE
POWER SUPPLY
HOT SWAP
C1
0.01 µF
R3
10 kΩ
VCC
ENABLE
SDAIN
SCLIN
GND
R4
10 kΩ
R5
10 kΩ
R6
10 kΩ
SDAOUT
CARD1_SDA
SCLOUT
CARD1_SCL
READY
I/O PERIPHERAL CARD 2
STAGGERED CONNECTOR
POWER SUPPLY
HOT SWAP
C3
0.01 µF
R7
10 kΩ
VCC
ENABLE
SDAIN
SCLIN
GND
R8
10 kΩ
R9
10 kΩ
R10
10 kΩ
SDAOUT
CARD2_SDA
SCLOUT
CARD2_SCL
READY
I/O PERIPHERAL CARD N
STAGGERED CONNECTOR
POWER SUPPLY
HOT SWAP
C5
0.01 µF
R11
10 kΩ
ENABLE
VCC
SDAIN
SCLIN
GND
R12
10 kΩ
R13
10 kΩ
R14
10 kΩ
SDAOUT
CARDN_SDA
SCLOUT
CARDN_SCL
READY
SW02126
Figure 9. Hot swapping multiple I/O cards into a backplane using the PCA9514 in a CompactPCI, VME, and AdvancedTCA system
2004 Oct 05
8
Philips Semiconductors
Product data sheet
Hot swappable I2C and SMBus bus buffer
PCA9513; PCA9514
BACKPLANE
CONNECTOR
I/O PERIPHERAL CARD 1
BACKPLANE
R1
10 kΩ
BD_SEL
SDA
SCL
R2
10 kΩ
STAGGERED CONNECTOR
VCC
POWER SUPPLY
HOT SWAP
C1
0.01 µF
ENABLE
VCC
SDAIN
R4
10 kΩ
R5
10 kΩ
R6
10 kΩ
SDAOUT
CARD_SDA
SCLOUT
CARD_SCL
SCLIN
ACC
GND
I/O PERIPHERAL CARD 2
STAGGERED CONNECTOR
POWER SUPPLY
HOT SWAP
C3
0.01 µF
VCC
R8
10 kΩ
R9
10 kΩ
R10
10 kΩ
SDAOUT
CARD2_SDA
SDAIN
SCLOUT
CARD2_SCL
SCLIN
ACC
ENABLE
GND
I/O PERIPHERAL CARD N
STAGGERED CONNECTOR
POWER SUPPLY
HOT SWAP
C5
0.01 µF
ENABLE
VCC
R12
10 kΩ
R13
10 kΩ
R14
10 kΩ
SDAOUT
CARDN_SDA
SDAIN
SCLOUT
CARDN_SCL
SCLIN
ACC
GND
SW02120
Figure 10. Hot swapping multiple I/O cards into a backplane using the PCA9513 in a CompactPCI, VME, and AdvancedTCA system
2004 Oct 05
9
Philips Semiconductors
Product data sheet
Hot swappable I2C and SMBus bus buffer
PCA9513; PCA9514
BACKPLANE
CONNECTOR
I/O PERIPHERAL CARD 1
BACKPLANE
R1
10 kΩ
STAGGERED CONNECTOR
VCC
R2
10 kΩ
SDA
SCL
C1
0.01 µF
VCC
ENABLE
SDAIN
R4
10 kΩ
R5
10 kΩ
R6
10 kΩ
SDAOUT
CARD_SDA
SCLOUT
CARD_SCL
SCLIN
ACC
GND
C2 0.01 µF
STAGGERED CONNECTOR
I/O PERIPHERAL CARD 2
C3
0.01 µF
VCC
ENABLE
SDAIN
R8
10 kΩ
R9
10 kΩ
R10
10 kΩ
SDAOUT
CARD2_SDA
SCLOUT
CARD2_SCL
SCLIN
ACC
GND
C4 0.01 µF
SW02121
Figure 11. Hot swapping multiple I/O cards into a backplane using the PCA9514 in a PCI system
RDROP
VCC
R1
10 kΩ
VCC_LOW
C2
0.01 µF
R4
10 kΩ
R2
1 kΩ
R3
1 kΩ
R5
10 kΩ
VCC
ENABLE
SDAOUT
SDA2
SDA
SDAIN
SCLOUT
SCL2
SCL
SCLIN
READY
GND
SW02123
Figure 12. System with disparate VCC voltages
2004 Oct 05
10
Philips Semiconductors
Product data sheet
Hot swappable I2C and SMBus bus buffer
PCA9513; PCA9514
ABSOLUTE MAXIMUM RATINGS
Limiting values in accordance with the Absolute Maximum System (IEC 134).
Voltages with respect to pin GND.
LIMITS
SYMBOL
PARAMETER
MIN.
MAX.
UNIT
+7
V
VCC
Supply voltage range VCC
–0.5
Vn
SDAIN, SCLIN, SDAOUT, SCLOUT, READY, ENABLE
–0.5
+7
V
II
Maximum current for inputs
–
±20
mA
IIO
Maximum current for I/O pins
–
±50
mA
Topr
Operating temperature range
–40
+85
°C
Tstg
Storage temperature range
–65
+125
°C
Tsld
Lead soldering temperature (10 sec max)
—
+300
°C
Tj(max)
Maximum junction temperature
—
+125
°C
NOTE:
1. Stresses beyond those listed may cause permanent damage to the device. These are stress ratings only and functional operation of the
device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to
absolute-maximum-rated conditions for extended periods may affect device reliability.
2004 Oct 05
11
Philips Semiconductors
Product data sheet
Hot swappable I2C and SMBus bus buffer
PCA9513; PCA9514
ELECTRICAL CHARACTERISTICS
VCC = 2.7 V to 5.5 V; Tamb = –40 to +85 °C unless otherwise noted.
LIMITS
SYMBOL
PARAMETER
TEST CONDITIONS
MIN.
TYP.
MAX.
UNIT
Power supply
VCC
Supply voltage
Note 1
2.7
—
5.5
V
ICC
Supply current
VCC = 5.5 V;
VSDAIN = VSCLIN = 0 V; Note 1
—
2.8
6
mA
ICC(sd)
Supply current in shut-down mode
VENABLE = 0 V, all other pins at
VCC or GND
—
200
—
µA
Start-up circuitry
VEN
Enable threshold voltage
—
0.5 × VCC
0.7 × VCC
V
VDIS
Disable threshold voltage
0.3 × VCC
0.5 × VCC
—
V
IEN
Enable input current
—
± 0.1
±1
µA
tEN
Enable delay or initialization time
—
130
—
µs
tIDLE
Bus idle time
50
140
250
µs
tDIS
Disable time, ENABLE to Ready
—
15
—
ns
tSTOP
SDAIN to READY delay after STOP
Note 7
—
1.3
—
µs
tREADY
SCLOUT/SDAOUT to READY
Note 7
—
1.2
—
µs
IOFF
Ready off state leakage current
VEN = VCC
—
± 0.3
—
µA
Ci
ENABLE capacitance
VI = VCC or GND; Note 4
—
2
—
pF
CO
Ready capacitance
VI = VCC or GND; Note 4
—
2
—
pF
VOL(READY)
LOW-level output voltage on
READY pin
Ipull-up = 3 mA; VEN = VCC;
Note 1.
—
—
0.4
V
Positive transition on SDA, SCL,
VCC = 2.7 V;
Slew rate = 1.25 V/µs; Note 2
1
2
—
mA
10 kΩ to VCC on SDA, SCL;
VCC = 3.3 V; Note 1; Note 3.
0
65
150
mV
0
—
400
kHz
Enable from 0 V to VCC
Note 1
Rise time accelerators
IPULLUPAC
Transient boosted pull-up current
Input–output connection
VOS
Input–output offset voltage
fSCL_SDA
operating frequency
tPLH
SCL to SCL and SDA to SDA
10 kΩ to VCC;
CL = 100 pF each side
—
20
—
ns
tPHL
SCL to SCL and SDA to SDA
10 kΩ to VCC;
CL = 100 pF each side
—
380
—
ns
CIN
Digital input capacitance
Note 4
—
—
10
pF
VOL
LOW-level output voltage
Input = 0 V;
SDA, SCL pins, ISINK = 3 mA;
VCC = 2.7 V; Note 1
0
—
0.4
V
IPULLUP
SDAIN/SCLIN pull-up current
VENABLE = VCC; Note 6
65
100
125
µA
ILI
Input leakage current
SDA, SCL pins = VCC = 5.5 V
—
—
±5
µA
2004 Oct 05
12
Philips Semiconductors
Product data sheet
Hot swappable I2C and SMBus bus buffer
PCA9513; PCA9514
LIMITS
SYMBOL
PARAMETER
TEST CONDITIONS
UNIT
MIN.
TYP.
MAX.
0
—
400
kHz
System characteristics
fI2C
I2C operating frequency
tBUF
Bus free time between stop and
start condition
Note 4
1.3
—
—
µs
thD,STA
Hold time after (repeated) start
condition
Note 4
0.6
—
—
µs
tsu,STA
Repeated start condition setup time
Note 4
0.6
—
—
µs
tsu,STO
Stop condition setup time
Note 4
0.6
—
—
µs
thD,DAT
Data hold time
Note 4
300
—
—
ns
tsu,DAT
Data setup time
Note 4
100
—
—
ns
tLOW
Clock LOW period
Note 4
1.3
—
—
µs
tHIGH
Clock HIGH period
Note 4
0.6
—
—
µs
tt
Clock, data fall time
Notes 4 and 5
20 + 0.1 × CB
—
300
ns
tr
Clock, data rise time
Notes 4 and 5
20 + 0.1 × CB
—
300
ns
NOTES:
1. This specification applies over the full operating temperature range.
2. IPULLUPAC varies with temperature and VCC voltage, as shown in the Typical Performance Characteristics section.
3. The connection circuitry always regulates its output to a higher voltage than its input. The magnitude of this offset voltage as a function of the
pull-up resistor and VCC voltage is shown in the Typical Performance Characteristics section.
4. Guaranteed by design, not production tested.
5. CB = total capacitance of one bus line in pF.
6. SDAIN/SCLIN = 0.1 V, SDAOUT/SCLOUT through resistor to VCC.
7. Delays that can occur after ENABLE and/or idle times have passed.
2004 Oct 05
13
Philips Semiconductors
Product data sheet
Hot swappable I2C and SMBus bus buffer
PCA9513; PCA9514
TYPICAL PERFORMANCE CHARACTERISTICS
2.5
450
2.4
VCC = 5.5 V
425
VCC = 2.7 V
2.3
400
(ns)
VCC = 3.3 V
VCC = 3.3 V
PHL
2.1
VCC = 2.7 V
t
I CC (mA)
2.2
2.0
375
VCC = 5.5 V
1.9
350
CIN = COUT = 100 pF
RPULLUPIN = RPULLUPOUT = 10 kΩ
1.8
1.7
–40
+25
325
+85
–40
TEMPERATURE (°C)
+25
TEMPERATURE (°C)
+85
SW02153
SW02152
Figure 13. ICC versus Temperature.
Figure 15. Input–output tPHL versus Temperature.
12
100
10
90
VCC = 5 V
VOUT – VIN (mV)
I PULLUPAC (mA)
8
6
VCC = 3.3 V
4
2
0
+25
VCC = 3.3 V OR 5.5 V
70
60
50
VCC = 2.7 V
–40
80
40
+85
0
TEMPERATURE (°C)
10,000
20,000
30,000
40,000
RPULLUP (Ω)
SW02346
SW02154
Figure 14. IPULLUPAC versus Temperature.
2004 Oct 05
Figure 16. Connection circuitry VOUT – VIN.
14
Philips Semiconductors
Product data sheet
Hot swappable I2C and SMBus bus buffer
PCA9513; PCA9514
SDAx/SCLx
ENABLE
READY
tEN
tIDLE
tDIS
SW02155
Figure 17. Timing for tENABLE, tIDLE, and tDISABLE
SDAIN
SCLIN
SCLOUT
SDAOUT
ENABLE
READY
tEN
tSTOP
Figure 18. tSTOP that can occur after tENALBE
2004 Oct 05
15
SW02156
Philips Semiconductors
Product data sheet
Hot swappable I2C and SMBus bus buffer
PCA9513; PCA9514
SCLIN/SDAIN
SCLOUT/SDAOUT
ENABLE
tEN
tIDLE
READY
tREADY
Figure 19. tREADY delay that can occur after tENALBE and tIDLE
VCC
VCC
RL = 10 kΩ
VI
VO
PULSE
GENERATOR
D.U.T.
RT
CL= 100 pF
DEFINITIONS
RL = Load resistor.
CL = Load capacitance includes jig and probe capacitance
RT = Termination resistance should be equal to the output
impedance ZO of the pulse generators.
SW02345
Figure 20. Test circuitry for switching times
2004 Oct 05
16
SW02157
Philips Semiconductors
Product data sheet
Hot swappable I2C and SMBus bus buffer
SO8: plastic small outline package; 8 leads; body width 3.9 mm
2004 Oct 05
17
PCA9513; PCA9514
SOT96-1
Philips Semiconductors
Product data sheet
Hot swappable I2C and SMBus bus buffer
PCA9513; PCA9514
TSSOP8: plastic thin shrink small outline package; 8 leads; body width 3 mm
2004 Oct 05
18
SOT505-1
Philips Semiconductors
Product data sheet
Hot swappable I2C and SMBus bus buffer
PCA9513; PCA9514
REVISION HISTORY
Rev
Date
Description
_3
20041005
Product data (9397 750 14001). Supersedes data of 2004 Jan 07 (9397 750 12609).
Modifications:
• ‘Description’ section on page 2:
– Fourth paragraph: add “over the PCA9510 and PCA9511” to end of sentence.
– Add fifth paragraph.
• ‘Features’ section on page 2:
– fourth bullet: delete “(PCA9513 and PCA9514 only)”
– last bullet: add “(MSOP8)”
• Add section “Maximum number of devices in series” on page 6
• Section “Minimum SDA and SCL Capacitance Requirements” on page 7 re-written.
• Delete (old) Figure 11 “Repeater/bus extender application using the PCA9514”
• ‘Absolute Maximum Ratings’ table on page 12: add parameters II and IIO.
• Electrical characteristics table, subsection “System characteristics”: change Unit for thD,DAT and tsu,DAT
from µs to ns.
• Figure 20 modified.
_2
20040107
Product data (9397 750 12609); ECN 853-2441 01-A15108 dated 06 January 2004.
Supersedes data of 18 Dec 2003 (9397 750 12559).
_1
20031202
Product data (9397 750 12559); ECN 853-2441 01-A14986 dated 15 December 2003.
2004 Oct 05
19
Philips Semiconductors
Product data sheet
Hot swappable I2C and SMBus bus buffer
PCA9513; PCA9514
Purchase of Philips I2C components conveys a license under the Philips’ I2C patent
to use the components in the I2C system provided the system conforms to the
I2C specifications defined by Philips. This specification can be ordered using the
code 9398 393 40011.
Data sheet status
Level
Data sheet status [1]
Product
status [2] [3]
Definitions
I
Objective data
Development
This data sheet contains data from the objective specification for product development.
Philips Semiconductors reserves the right to change the specification in any manner without notice.
II
Preliminary data
Qualification
This data sheet contains data from the preliminary specification. Supplementary data will be published
at a later date. Philips Semiconductors reserves the right to change the specification without notice, in
order to improve the design and supply the best possible product.
III
Product data
Production
This data sheet contains data from the product specification. Philips Semiconductors reserves the
right to make changes at any time in order to improve the design, manufacturing and supply. Relevant
changes will be communicated via a Customer Product/Process Change Notification (CPCN).
[1] Please consult the most recently issued data sheet before initiating or completing a design.
[2] The product status of the device(s) described in this data sheet may have changed since this data sheet was published. The latest information is available on the Internet at URL
http://www.semiconductors.philips.com.
[3] For data sheets describing multiple type numbers, the highest-level product status determines the data sheet status.
Definitions
Short-form specification — The data in a short-form specification is extracted from a full data sheet with the same type number and title. For detailed information see
the relevant data sheet or data handbook.
Limiting values definition — Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 60134). Stress above one or more of the limiting
values may cause permanent damage to the device. These are stress ratings only and operation of the device at these or at any other conditions above those given
in the Characteristics sections of the specification is not implied. Exposure to limiting values for extended periods may affect device reliability.
Application information — Applications that are described herein for any of these products are for illustrative purposes only. Philips Semiconductors make no
representation or warranty that such applications will be suitable for the specified use without further testing or modification.
Disclaimers
Life support — These products are not designed for use in life support appliances, devices, or systems where malfunction of these products can reasonably be
expected to result in personal injury. Philips Semiconductors customers using or selling these products for use in such applications do so at their own risk and agree
to fully indemnify Philips Semiconductors for any damages resulting from such application.
Right to make changes — Philips Semiconductors reserves the right to make changes in the products—including circuits, standard cells, and/or software—described
or contained herein in order to improve design and/or performance. When the product is in full production (status ‘Production’), relevant changes will be communicated
via a Customer Product/Process Change Notification (CPCN). Philips Semiconductors assumes no responsibility or liability for the use of any of these products, conveys
no license or title under any patent, copyright, or mask work right to these products, and makes no representations or warranties that these products are free from patent,
copyright, or mask work right infringement, unless otherwise specified.
 Koninklijke Philips Electronics N.V. 2004
All rights reserved. Published in the U.S.A.
Contact information
For additional information please visit
http://www.semiconductors.philips.com.
Fax: +31 40 27 24825
Date of release: 10-04
For sales offices addresses send e-mail to:
[email protected].
Document number:
Philips
Semiconductors
2004 Oct 05
20
9397 750 14001