L7C108 L7C109 128K x 8 Static RAM Pin Configuration 32-pin Ceramic DIP 32-pin Ceramic SOJ NC A16 A14 A12 A7 A6 A5 A4 A3 A2 A1 A0 DQ1 DQ2 DQ3 VSS 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 VCC A15 CE2 WE A13 A8 A9 A11 OE A10 CE DQ8 DQ7 DQ6 DQ5 DQ4 32-pin Quad CLCC 32-pin Ceramic LCC A2 A1 A0 NC VCC A16 NC 128K x 8 Static RAM with Chip Select Powerdown, Output Enable and Single or Dual Chip Selects High Speed — to 15 ns maximum Operational Power, -L Version Active: 140 mA at 15 ns Standby: 1 mA max Data Retention at 2 V for Battery Backup Operation Screened to MIL-STD-883, Class B or to SMD 5962-89598 Package Styles Available: xSLQ&HUDPLFPLO',3' xSLQ&HUDPLF/&&. xSLQ&HUDPLF62-< xSLQ4XDG&HUDPLF/&&.$ 4 A7 A6 A5 A4 A3 A2 A1 A0 DQ1 3 2 1 32 31 30 5 29 6 28 7 27 8 9 10 Top View 26 25 24 11 23 12 22 13 21 14 15 16 17 18 19 20 DQ2 DQ3 VSS DQ4 DQ5 DQ6 DQ7 FEATURES WE A13 A8 A9 A11 OE A10 CE1 DQ8 NC A16 A14 A12 A7 A6 A5 A4 A3 A2 A1 A0 DQ1 DQ2 DQ3 VSS 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 VCC A15 CE2 WE A13 A8 A9 A11 OE A10 CE DQ8 DQ7 DQ6 DQ5 DQ4 OVERVIEW The L7C108 and L7C109 are high-performance, low-power CMOS static RAMs. The storage circuitry is organized as 131,072 words by 8 bits per word. The 8 Data In and Data Out signals share I/O pins. The L7C108 has a single activelow Chip Enable. The L7C109 has two &KLS (QDEOHV RQH DFWLYHORZ 7KHVH devices are available in three speeds with maximum access times from 15 ns to 45 ns. Inputs and outputs are TTL compatible. Operation is from a single +5 V power supply. Power consumption is 140 mA / 9HUVLRQ DW QV 'DWD PD\ EH retained in inactive storage with a supply voltage as low as 2 V. The L7C108 and L7C109 provide asynFKURQRXV XQFORFNHG RSHUDWLRQ ZLWK matching access and cycle times. The LOGIC Devices Incorporated www.logicdevices.com Chip Enables and a three-state I/O bus with a separate Output Enable control simplify the connection of several chips for increased storage capacity. Memory locations are specified on address pins A0 through A16. For the L7C108, reading from a designated location is accomplished by presenting an address and driving CE1 and OE LOW while WE remains HIGH. For the L7C109, CE1 and OE must be LOW while CE2 and WE are HIGH.The data in the addressed memory location will then appear on the Data Out pins within one access time. The output pins stay in a high-impedance state when CE1 or OE is HIGH, or CE2/&RU:(LV/2: Writing to an addressed location is accomplished when the active-low CE1 and WE inputs are both LOW, and CE2 /&LV+,*+$Q\RIWKHVHVLJQDOV 1 may be used to terminate the write operation. Data In and Data Out signals have the same polarity. Latchup and static discharge protection are provided on-chip. The L7C108 and L7C109 can withstand an injection current of up to 200 mA on any pin without damage. 1M Static RAMs Feb 17, 2012 LDS-L7C108/9-G L7C108 L7C109 128K x 8 Static RAM ROW ADDRESS 9 CE1 WE OE CE2 (L7C109 only) ROW SELECT L7C108-109 Block Diagram 128 K x 8 MEMORY ARRAY 8 COLUMN SELECT & COLUMN SENSE CONTROL I/O7 - 0 8 COLUMN ADDRESS TRUTH TABLE Mode OE CE1 CE2* WE DQ POWER Standby X t VIH X X High - Z 6WDQGE\I&& Standby X X d VIL X High - Z 6WDQGE\I&& Standby X t VCC - 0.2 V X X High - Z 6WDQGE\I&& Standby X X d GND + 0.2 V X High - Z 6WDQGE\I&& Read L L H H 4 Active Read H L H H High - Z Active Write X L H L D Active * Note: LOGIC Devices Incorporated for L7C109 only www.logicdevices.com 2 1M Static RAMs Feb 17, 2012 LDS-L7C108/9-G L7C108 L7C109 128K x 8 Static RAM MAXIMUM RATINGS Above which useful life may be impaired (Notes 1, 2) Storage temperature…………………………………………...….……............……-65°C to +150°C Operating ambient temperature………………………………………......….......…-55°C to +125°C Vcc supply voltage with respect to ground…………….…………………….......….-0.5 V to +7.0 V Input signal with respect to ground.………………………….………………..…..…-3.0 V to +7.0 V Signal applied to high impedance output……………………………………........…-3.0 V to +7.0 V Output current into low outputs………………………………………….…......................……25 mA Latchup current….........................……………..…………………………...……................ >200 mA OPERATING CONDITIONS To meet specified electrical and switching characteristics Temperature Range (Ambient) Supply Voltage Active, Operation, Military -55°C to +125°C 4.5 V d VCC d 5.5 V Data Retention, Military -55°C to +125°C 2.0 V d VCC d 5.5 V Mode ELECTRICAL CHARACTERISTICS Over Operating Conditions (Note 5) L7C108/109 Symbol Parameter Test Condition VOH Output High Voltage VCC = 4.5V, IOH = -4 mA VOL Output Low Voltage IOL = 8 mA VIH Input High Voltage Min L7C108/109-L Max Min 2.4 Max Unit V 2.4 0.4 Vcc 2.2 2.2 +0.5 0.4 V Vcc V +0.3 VIL Input Low Voltage 1RWH -0.5 0.8 -3.0 0.8 V IIx Input Leakage Current GND < VIN < VCC -10 +10 -10 +10 μA IOZ Output Leakage Current 1RWH -10 +10 -10 +10 μA ICC2 VCC Current, TTL Standby 1RWH 25 25 mA ICC3 VCC Current, CMOS Standby 1RWH 10 5 mA ICC4 VCC Current, Data Retention VCC = 91RWHV - 0.75 mA CIN Input Capacitance Ambient Temp = 25°C, VCC = 5 V 8 8 pF Output Capacitance 7HVW)UHTXHQF\ 0+]1RWH 8 8 pF COUT L7C108/109 Symbol Parameter ICC1 VCC Current, Active LOGIC Devices Incorporated L7C108/109-L Test Condition 15 20 1RWH 140 140 140 135 125 www.logicdevices.com 3 25 35 45 15 20 140 140 25 35 45 Unit 140 130 125 mA 1M Static RAMs Feb 17, 2012 LDS-L7C108/9-G L7C108 L7C109 128K x 8 Static RAM SWITCHING CHARACTERISTICS Over Operating Range READ CYCLE Notes 5, 11, 12, 22, 23, 24 (ns) L7C108/109 15/15-L 20/20-L 25/25-L Symbol Parameter 35/35-L 45/45-L Min Max Min Max Min Max Min Max Min Max tAVAV Read Cycle Time t$949 $GGUHVV9DOLGWR2XWSXW9DOLG1RWHV t$94; Address Change to Output Change t(/49 &KLS(QDEOH/RZWR2XWSXW9DOLG1RWHV t(/4; &KLS(QDEOH/RZWR2XWSXW/RZ=1RWHV t(+4= &KLS(QDEOH+LJKWR2XWSXW+LJK=1RWHV 7 8 10 15 20 t*/49 Output Enable Low to Output Valid 8 10 10 15 20 t*/4; 2XWSXW(QDEOH/RZWR2XWSXW/RZ=1RWHV t*+4= 2XWSXW(QDEOH+LJKWR2XWSXW+LJK=1RWHV tPU 15 20 15 3 20 3 3 20 6 0 3 3 0 35 0 45 3 0 10 0 45 3 3 0 6 45 35 25 3 0 35 25 3 15 ,QSXW7UDQVLWLRQWR3RZHU8S1RWHV 25 0 15 0 20 0 READ CYCLE - ADDRESS CONTROLLED Notes 13, 14 tAVAV ADDRESS tAVQV DATA OUT PREVIOUS DATA VALID DATA VALID tAVQX tPD tPU ICC READ CYCLE - CE/OE CONTROLLED NOTES 13, 15 tAVAV CE tEHQZ tELQV tELQX OE DATA OUT HIGH IMPEDANCE DATA VALID 50% Icc www.logicdevices.com HIGH IMPEDANCE tPD tPU LOGIC Devices Incorporated tGHQZ tGLQV tGLQX 50% 4 1M Static RAMs Feb 17, 2012 LDS-L7C108/9-G L7C108 L7C109 128K x 8 Static RAM SWITCHING CHARACTERISTICS Over Operating Range READ CYCLE Notes 5, 11, 12, 22, 23, 24 (ns) L7C108/109 15/15-L 20/20-L 25/25-L 35/35-L 45/45-L Symbol Parameter Min Max Min Max Min Max Min Max Min Max tPD 2SHUDWLRQ5HFRYHU\7LPH1RWHV tCDR &KLS(QDEOH+LJKWR'DWD5HWHQWLRQ1RWH 15 20 0 0 25 35 0 0 45 0 DATA RETENTION Notes 9, 10 DATA RETENTION MODE VCC 4.5 V 4.5 V ≥2V tCDR tPD VIH CE VIH WRITE CYCLE Notes 5, 11, 12, 22, 23, 24 (ns) L7C108/109 15/15-L 20/20-L 25/25-L 35/35-L 45/45-L Symbol Min Max Min Max Min Max Min Max Min Max Parameter tAVAV Write Cycle Time 15 20 25 35 45 tELWH Chip Enable Low to End of Write Cycle 12 12 20 25 35 tAVWL Address Valid to Beginning of Write Cycle 0 0 0 0 0 tAVWH Address Setup to End of Write Cycle 15 17 20 25 35 tWHAX Address Hold After End Of Write 0 0 0 0 0 tWLWH Write Enable Pulse Width Low 12 15 20 30 40 tDVWH Data Setup to End of Write Cycle 7 10 12 20 20 tWHDX Data Hold to End of Write 0 0 0 0 0 t:+4; :ULWH(QDEOH+LJKWR2XWSXW/RZ=1RWHV 5 5 5 5 5 t:/4= :ULWH(QDEOH/RZWR2XWSXW+LJK=1RWHV LOGIC Devices Incorporated www.logicdevices.com 7 5 8 10 25 30 1M Static RAMs Feb 17, 2012 LDS-L7C108/9-G L7C108 L7C109 128K x 8 Static RAM SWITCHING CHARACTERISTICS Over Operating Range WRITE CYCLE - WE CONTROLLED Notes 16, 17, 18, 19 tAVAV ADDRESS tELWH CE tAVWH WE tWHAX tWLWH tDVWH tAVWL tWHDX DATA -IN VALID DATA IN tWLQZ HIGH IMPEDANCE DATA OUT tPD tPU tPU tWHQX ICC WRITE CYCLE - CE CONTROLLED Notes 16, 17, 18, 19 tAVAV ADDRESS tAVWL tAELWH CE tAVWH tWHAX tWLWH WE tDVWH DATA IN tWHDX DATA-IN VALID HIGH IMPEDANCE DATA OUT tPU tPD ICC LOGIC Devices Incorporated www.logicdevices.com 6 1M Static RAMs Feb 17, 2012 LDS-L7C108/9-G L7C108 L7C109 128K x 8 Static RAM PACKAGE INFORMATION PKG K: 32L CERAMIC DUAL LCC (MD-K11) PIN 1 IDENTIFIER 0.070 ± 0.007 0.082 ± 0.0083 0.825 ± 0.008 0.055 ± 0.006 0.400 ± 0.005 0.085 ± 0.008 0.050 TYP See detail A 0.006 ~ 0.22 TYP 0.025 ± 0.003 0.003 ~ 0.015 0.050 TYP SMD 5962-89598 Case ‘U’ / Ordering Code ‘K’ LOGIC Devices Incorporated www.logicdevices.com detail A *All measurements in inches 7 1M Static RAMs Feb 17, 2012 LDS-L7C108/9-G L7C108 L7C109 128K x 8 Static RAM PACKAGE INFORMATION PKG KA: 32L CERAMIC QUAD LCC (MD-KA1) 0.065 ± 0.006 0.450 + 0.008 - 0.005 0.0821 ± 0.0073 0.550 + 0.10 - 0.05 0.020 ± 0.002 0.300 ± 0.005 0.085 ± 0.008 0.050 TYP 0.400 ± 0.005 See detail A 0.008R detail A 0.025 ± 0.003 0.050 ± 0.005 SMD 5962-89598 Case ‘M’ / Ordering Code “KA” LOGIC Devices Incorporated www.logicdevices.com *All measurements in inches 8 1M Static RAMs Feb 17, 2012 LDS-L7C108/9-G L7C108 L7C109 128K x 8 Static RAM PACKAGE INFORMATION PKG Y: 32L CERAMIC SOJ (MD-Y1) 0.132 ± 0.0203 0.005 TYP 1 32 0.822 ± 0.008 16 0.750 ± 0.007 17 0.050 BSC 0.425 ± 0.006 0.0205 ± 0.091 0.012 ± 0.0013 0.445 MAX 0.005 MIN 0.010 REF 0.025 ± 0.003 TYP 0.038 TYP 0.025 REF 0.075 REF 0.035 ± 0.010 CHAMFER 0.020 REF 0.035R TYP 0.017 ± 0.002 0.370 ± 0.010 (Note: Case ‘Y’ ships for Case ‘7’ as compatible replacement) SMD 5962-89598 Case ‘Y’ and ‘7’ / Ordering Code ‘Y’ LOGIC Devices Incorporated www.logicdevices.com *All measurements in inches 9 1M Static RAMs Feb 17, 2012 LDS-L7C108/9-G L7C108 L7C109 128K x 8 Static RAM PACKAGE INFORMATION PKG D: 32L CERAMIC DIP (MD-D12) 0.135 ± 0.005 0.05 ± 0.0775 0.1471 ± 0.0063 0.100 ± 0.05 TYP 1.600 ± 0.016 0.018 ± 0.002 0.050 ± 0.002 TYP 0.317 ± 0.011 0.378 ± 0.005 0.050 ± 0.010 0.170 ± 0.005 0.22 ± 0.015 Lead Location Guage Plane Seating Plane 0.010 + 0.002 - 0.001 Base Plane 0.400 ± 0.005 SMD 5962-89598 Case ‘Z’ / Ordering Code ‘D’ LOGIC Devices Incorporated www.logicdevices.com *All measurements in inches 10 1M Static RAMs Feb 17, 2012 LDS-L7C108/9-G L7C108 L7C109 128K x 8 Static RAM SMD Cross Reference Table LOGIC Part # L7C109DMB45 L7C109DMB35 L7C109DMB25 L7C109DMB20 L7C109DMB15 L7C109YMB45 L7C109YMB35 L7C109YMB25 L7C109YMB20 L7C109YMB15 L7C109YMB45 L7C109YMB35 L7C109YMB25 L7C109YMB20 L7C109YMB15 L7C109KAMB45 L7C109KAMB35 L7C109KAMB25 L7C109KAMB20 L7C109KAMB15 L7C109KMB45 L7C109KMB35 L7C109KMB25 L7C109KMB20 L7C109KMB15 LOGIC Devices Incorporated SMD Part # 5962-8959835MZA 5962-8959836MZA 5962-8959837MZA 5962-8959838MZA 5962-8959841MZA 5962-8959835M7A 5962-8959836M7A 5962-8959837M7A 5962-8959838M7A 5962-8959841M7A 5962-8959835MYA 5962-8959836MYA 5962-8959837MYA 5962-8959838MYA 5962-8959841MYA 5962-8959835MMA 5962-8959836MMA 5962-8959837MMA 5962-8959838MMA 5962-8959841MMA 5962-8959835MUA 5962-8959836MUA 5962-8959837MUA 5962-8959838MUA 5962-8959841MUA www.logicdevices.com 11 LOGIC Part # SMD Part # L7C108DMB45 L7C108DMB35 L7C108DMB25 L7C108DMB20 L7C108DMB15 L7C108YMB45 L7C108YMB35 L7C108YMB25 L7C108YMB20 L7C108YMB15 L7C108YMB45 L7C108YMB35 L7C108YMB25 L7C108YMB20 L7C108YMB15 5962-8959827MZA 5962-8959828MZA 5962-8959829MZA 5962-8959839MZA 5962-8959844MZA 5962-8959827M7A 5962-8959828M7A 5962-8959829M7A 5962-8959839M7A 5962-8959844M7A 5962-8959827MYA 5962-8959828MYA 5962-8959829MYA 5962-8959839MYA 5962-8959844MYA 1M Static RAMs Feb 17, 2012 LDS-L7C108/9-G L7C108 L7C109 128K x 8 Static RAM SMD Cross Reference Table SMD Part # LOGIC Part # L7C109DMB45L L7C109DMB35L L7C109DMB25L L7C109DMB20L L7C109YMB45L L7C109YMB35L L7C109YMB25L L7C109YMB20L L7C109YMB45L L7C109YMB35L L7C109YMB25L L7C109YMB20L L7C109KAMB45L L7C109KAMB35L L7C109KAMB25L L7C109KAMB20L L7C109KMB45L L7C109KMB35L L7C109KMB25L L7C109KMB20L L7C109FMB20L L7C108DMB45L L7C108DMB35L L7C108DMB25L L7C108DMB20L L7C108DMB15L LOGIC Devices Incorporated LOGIC Part # 5962-8959818MZA 5962-8959819MZA 5962-8959820MZA 5962-8959821MZA 5962-8959818M7A 5962-8959819M7A 5962-8959820M7A 5962-8959821M7A 5962-8959818MYA 5962-8959819MYA 5962-8959820MYA 5962-8959821MYA 5962-8959818MMA 5962-8959819MMA 5962-8959820MMA 5962-8959821MMA 5962-8959818MUA 5962-8959819MUA 5962-8959820MUA 5962-8959821MUA 5962-8959821MTA 5962-8959810MZA 5962-8959811MZA 5962-8959812MZA 5962-8959840MZA 5962-8959848MZA www.logicdevices.com L7C108YMB45L L7C108YMB35L L7C108YMB25L L7C108YMB20L L7C108YMB15L L7C108YAMB45L L7C108YMB35L L7C108YMB25L L7C108YMB20L L7C108YMB15L 12 SMD Part # 5962-8959810M7A 5962-8959811M7A 5962-8959812M7A 5962-8959840M7A 5962-8959848M7A 5962-8959810MYA 5962-8959811MYA 5962-8959812MYA 5962-8959840MYA 5962-8959848MYA 1M Static RAMs Feb 17, 2012 LDS-L7C108/9-G L7C108 L7C109 128K x 8 Static RAM ORDERING INFORMATION L 7C 108 D M B 15 L Indicates a LOGIC Devices product SRAM PART NUMBER: 108 = 1M SRAM with single chip enable (available in packages ‘D’ and ‘Y’) 109 = 1M SRAM with dual chip enables (available in ALL packages) PACKAGE CODE: D = 32 pin Sidebrazed DIP 400mil K = 32 pin Ceramic LCC KA = 32 pin Quad Ceramic LCC Y = 32 pin Ceramic SOJ SCREENING LEVEL: M = Military Temperature, -55ºC to +125ºC E = Extended Temperature, -40ºC to +105ºC I = Industrial Temperature, -40ºC to +85ºC COMPLIANCE: B = MIL-STD-883 Compliant SPEED GRADE: [M]: 15/20/25/35/45 [E]: 15/20/25/35/45 [I]: 15/20/25/35/45 LOW POWER OPTION: L = Low Power No Mark Means Standard Power LOGIC Devices Incorporated www.logicdevices.com 13 1M Static RAMs Feb 17, 2012 LDS-L7C108/9-G L7C108 L7C109 128K x 8 Static RAM NOTES 1. Maximum Ratings indicate stress specifications only. Functional operation of these products at values beyond those indicated in the Operating Conditions table is not implied. Exposure to maximum rating conditions for extended periods may affect reliability of the tested device. 2. The products described by this specification include internal circuitry designed to protect the chip from damaging substrate injection currents and accumulations of static charge. Nevertheless, conventional precautions should be observed during storage, handling, and use of these circuits in order to avoid exposure to excessive electrical stress values. 3. This product provides hard clamping of transient undershoot. Input levels below ground will be clamped beginning at –0.6 V. A current in excess of 100 mA is required to reach –2.0 V. The device can withstand indefinite operation with inputs as low as –3 V subject only to power dissipation and bond wire fusing constraints. 4. Tested with GND d VOUT d VCC. The device is disabled, i.e., CE1 = VCC, CE2 = GND. 5. A series of normalized curves is available to supply the designer with typical DC and AC parametric information for Logic Devices Static RAMs. These curves may be used to determine device characteristics at various temperatures and voltage levels. 6. Tested with all address and data inputs changing at the maximum cycle rate. The device is continuously enabled for reading, i.e., CE1 d VIL, CE2 t VIH, WE t VIH, with outputs disabled, OE t VIH. Input pulse levels are 0 to 3.0 V. 7. Tested with outputs open and all address and data inputs stable. The device is continuously disabled, i.e., CE1 t VIH, CE2 d VIL. 8. Tested with outputs open and all address and data inputs stable. The device is continuously disabled, i.e. CE1 = VCC, CE2 = GND. Input levels are within 0.2 V of VCC or GND. 9. Data retention operation requires that VCC never drop below 2.0V. CE1 must be t VCC 0.2 V or CE2 must be d 0.2 V. All other inputs must meet VIN t VCC - 0.2 V or VIN d 0.2 V to HQVXUHIXOOSRZHUGRZQ)RUORZSRZHUYHUVLRQLI DSSOLFDEOHWKLVUHTXLUHPHQWDSSOLHVRQO\WR&(1, CE2, and WE; there are no restrictions on data and address. 10. These parameters are guaranteed but not 100% tested. 11. Test conditions assume input transition times of less than 3 ns, reference levels of 1.5 V, output LOGIC Devices Incorporated www.logicdevices.com loading for specified IOL and IO+SOXVS))LJ DDQGLQSXWSXOVHOHYHOVRIWR9)LJ 12. Each parameter is shown as a minimum or maximum value. Input requirements are specified from the point of view of the external system driving the chip. For example, tAVEW is specified as a minimum since the external system must supply at least that much time to meet the worstcase requirements of all parts. Responses from the internal circuitry are specified from the point of view of the device. Access time, for example, is specified as a maximum since worst-case operation of any device always provides data within that time. 13. WE is high for the read cycle. 7KH FKLS LV FRQWLQXRXVO\ VHOHFWHG &(1 low, CE2KLJK 15. All address lines are valid prior-to or coincident-with the CE1 and CE2 transition to active. 16. The internal write cycle of the memory is defined by the overlap of CE1 and CE2 active and WE low. All three signals must be active to initiate a write. Any signal can terminate a write by going inactive. The address, data, and control input setup and hold times should be referenced to the signal that becomes active last or becomes inactive first. 17. If WE goes low before or concurrent with the latter of CE1 and CE2 going active, the output remains in a high impedance state. 21. Transition is measured ±200 mV from steady state voltage with specified loading in Fig. 1b. This parameter is sampled and not 100% tested. 22. All address timings are referenced from the last valid address line to the first transitioning address line. 23. CE1, CE2, or WE must be inactive during address transitions. 24. This product is a very high speed device and care must be taken during testing in order to realize valid test information. Inadequate attention to setups and procedures can cause a good part to be rejected as faulty. Long high inductance leads that cause supply bounce must be avoided by bringing the VCC and ground planes directly up to the contactor fingers. A 0.01 μF high frequency capacitor is also required between VCC and ground. To avoid signal reflections, proper terminations must be used. Figure 1a. OUTPUT a. Rising edge of CE2&(1DFWLYHRUWKHIDOOLQJ edge of CE1&(2DFWLYH E)DOOLQJHGJHRI:(&(1, CE2DFWLYH Figure 1b. OUTPUT INCLUDING JIG AND SCOPE G7UDQVLWLRQRQDQ\GDWDOLQH&(1, CE2, and :(DFWLYH 20. At any given temperature and voltage condition, output disable time is less than output enable time for any given device. 14 R1 480 +5 V F7UDQVLWLRQRQDQ\DGGUHVVOLQH&(1, CE2, DFWLYH The device automatically powers down from ICC1 to ICC2 after tPD has elapsed from any of the prior conditions. This means that power dissipation is dependent on only cycle rate, and is not on Chip Select pulse width. R2 255 30 pF INCLUDING JIG AND SCOPE 18. If CE1 and CE2 goes inactive before or concurrent with WE going high, the output remains in a high impedance state. 19. Powerup from ICC2 to ICC1 occurs as a result of any of the following conditions: R 1 480 +5 V R2 255 5 pF Figure 2 +3.0 V GND 90% 10% <3 ns 90% 10% <3 ns 1M Static RAMs Feb 17, 2012 LDS-L7C108/9-G L7C108 L7C109 128K x 8 Static RAM Revision History L7C108/L7C109 Revision Engineer Issue Date Description Of Change A COM 10/8/2008 Initial Release B -0 10/30/2008 Datasheet Format Revision C '+-0 07/02/2009 D DH 06/11/10 Revisions: E -0 07/30/10 Updated mechanical drawings for all packages F DH 08/11/10 Revisions: Updated specs: 1. 2. 3. 4. 5. 6. 7. 1. 2. 3. 4. 5. 6. 7. 8. 9. 1. 2. 3. 4. Added 10ns & 12 speed columns in ICC1 table Added 10ns speed and AC specs in the AC table Updated all DC power specs in DC table Corrected symbol names in AC and Timing diagrams Added speed bin to ordering info table Removed commercial temp offering Added an extended temp offering Removed 10 & 12ns bins 5HPRYHG/')3WREHUHLQWURGXFHGZLKWRXUVLOLFRQLIPDUNHWZDUUDQWV 5HPRYHG62-SDFNDJHYDULDQWv<$w $GGQRWDWLRQIRU60'WKDW3DFNDJHt<uZLOOEHVXSSOLHGDVDvwFRPSDWLEOHSDFNDJH Increased ICC1, ICC2, and ICC4@2V for standard power Increased ICC2 and ICC4@2V for low power Removed appropriate DSCC and LOGIC part numbers from ordering tables and PN generator 0RGLILHG/2*,&'HYLFHVv<$wSDFNDJHUHIHUHQFHWRt<u &RUUHFWLRQVWRSDFNDJHGLPHQVLRQVIRU0'.DQG0'< 5HPRYHGDOO.$TXDG/&&DQG.GXDO/&&SDFNDJHYDULDQWVIURP60'FURVVUHIHUHQFHWDEOH Updated order information chart to reflect current package availabilities. Changed ICC2 conditions to match ICC3 conditions. Changed operating current to be calculated during the READ cycle. LOGIC Devices Incorporated reserves the right to make corrections, modifications, enhancements, improvements, and other changes to its products and services at any time and to discontinue any product or service without notice. Customers should obtain the latest relevant information before placing orders and should verify that such information is current and complete. LOGIC Devices does not assume any liability arising out of the application or use of any product or circuit described herein. In no event shall any liability exceed the product purchase price. Products of LOGIC Devices are not warranted nor intended to be used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with LOGIC Devices. Furthermore, LOGIC Devices does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. LOGIC Devices Incorporated www.logicdevices.com 15 1M Static RAMs Feb 17, 2012 LDS-L7C108/9-G