CY7C1049DV33 4-Mbit (512K x 8) Static RAM Features Functional Description ■ Pin and function compatible with CY7C1049CV33 The CY7C1049DV33 is a high performance CMOS Static RAM organized as 512K words by 8-bits. Easy memory expansion is provided by an Active LOW Chip Enable (CE), an Active LOW Output Enable (OE), and tri-state drivers. You can write to the device by taking Chip Enable (CE) and Write Enable (WE) inputs LOW. Data on the eight IO pins (IO0 through IO7) is then written into the location specified on the address pins (A0 through A18). ■ High speed ❐ tAA = 10 ns ■ Low active power ❐ ICC = 90 mA @ 10 ns (Industrial) ■ Low CMOS standby power ❐ ISB2 = 10 mA ■ 2.0V data retention ■ Automatic power down when deselected ■ TTL compatible inputs and outputs ■ Easy memory expansion with CE and OE features ■ Available in Pb-free 36-pin (400 Mil) Molded SOJ and 44-pin TSOP II packages You can read from the device by taking Chip Enable (CE) and Output Enable (OE) LOW while forcing Write Enable (WE) HIGH. Under these conditions, the contents of the memory location specified by the address pins appear on the IO pins. The eight input or output pins (IO0 through IO7) are placed in a high impedance state when the device is deselected (CE HIGH), the outputs are disabled (OE HIGH), or during a write operation (CE LOW, and WE LOW). The CY7C1049DV33 is available in standard 400 Mil wide 36 -pin SOJ package and 44-pin TSOP II package with center power and ground (revolutionary) pinout. Refer to the Cypress application note AN1064, SRAM System Guidelines for best practice recommendations. Logic Block Diagram IO0 INPUT BUFFER IO1 512K x 8 ARRAY IO3 IO4 IO5 IO6 CE COLUMN DECODER WE IO7 POWER DOWN A11 A12 A13 A14 A15 A16 A17 A18 OE Cypress Semiconductor Corporation Document Number: 38-05475 Rev. *D IO2 SENSE AMPS ROW DECODER A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 • 198 Champion Court • San Jose, CA 95134-1709 • 408-943-2600 Revised July 23, 2007 CY7C1049DV33 Pin Configuration 44-Pin TSOP II Top View 36-Pin SOJ Top View A0 A1 A2 A3 A4 CE IO0 IO1 VCC GND IO2 IO3 WE A5 A6 A7 A8 A9 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 20 19 NC NC A0 A1 A2 A3 A4 CE IO0 IO1 VCC VSS IO2 IO3 WE A5 A6 A7 A8 A9 NC NC NC A18 A17 A16 A15 OE IO7 IO6 GND VCC IO5 IO4 A14 A13 A12 A11 A10 NC 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 NC NC NC A18 A17 A16 A15 OE IO7 IO6 VSS VCC IO5 IO4 A14 A13 A12 A11 A10 NC NC NC Selection Guide -10 (Industrial) -12 (Automotive)[1] Unit Maximum Access Time 10 12 ns Maximum Operating Current 90 95 mA Maximum CMOS Standby Current 10 15 mA Note 1. Automotive product information is preliminary. Document Number: 38-05475 Rev. *D Page 2 of 10 CY7C1049DV33 Maximum Ratings Current into Outputs (LOW)......................................... 20 mA Exceeding the maximum ratings may impair the useful life of the device. User guidelines are not tested. (MIL-STD-883, Method 3015) Storage Temperature ................................. –65°C to +150°C Latch up Current...................................................... >200 mA Static Discharge Voltage............. ...............................>2001V Operating Range Ambient Temperature with Power Applied ............................................ –55°C to +125°C Ambient Temperature VCC Speed Industrial –40°C to +85°C 3.3V ± 0.3V 10 ns Automotive –40°C to +125°C 3.3V ± 0.3V 12 ns Range Supply Voltage on VCC to Relative GND[2] .....–0.3V to +4.6V DC Voltage Applied to Outputs in High Z State[2] .................................... –0.3V to VCC + 0.3V DC Input Voltage[2] ................................ –0.3V to VCC + 0.3V Electrical Characteristics Over the Operating Range -10 (Industrial) Parameter Description Test Conditions VOH Output HIGH Voltage VCC = Min, IOH = –4.0 mA VOL Output LOW Voltage VCC = Min, IOL = 8.0 mA VIH[2] Input HIGH Voltage Min Max 2.4 -12 (Automotive) Min Max Unit 2.4 V 0.4 0.4 V 2.0 VCC + 0.3 2.0 VCC + 0.3 V –0.3 0.8 –0.3 0.8 V GND < VI < VCC –1 +1 –1 +1 µA Output Leakage Current GND < VOUT < VCC, Output Disabled –1 +1 –1 +1 µA VCC Operating Supply Current VCC = Max, f = fMAX = 1/tRC VIL[2] Input LOW IIX Input Leakage Current IOZ ICC Voltage[2] 100 MHz 90 - mA 83 MHz 80 95 mA 66 MHz 70 85 mA 40 MHz 60 75 mA ISB1 Automatic CE Power down Current —TTL Inputs Max VCC, CE > VIH; VIN > VIH or VIN < VIL, f = fMAX 20 25 mA ISB2 Automatic CE Power down Current —CMOS Inputs Max VCC, CE > VCC – 0.3V, VIN > VCC – 0.3V, or VIN < 0.3V, f = 0 10 15 mA Capacitance Tested initially and after any design or process changes that may affect these parameters. Parameter Description CIN Input Capacitance COUT IO Capacitance Test Conditions Max Unit TA = 25°C, f = 1 MHz, VCC = 3.3V 8 pF 8 pF Note 2. VIL (min.) = –2.0V and VIH(max) = VCC + 2V for pulse durations of less than 20 ns. Document Number: 38-05475 Rev. *D Page 3 of 10 CY7C1049DV33 Thermal Resistance Tested initially and after any design or process changes that may affect these parameters. Parameter Description ΘJA Thermal Resistance (Junction to Ambient) ΘJC Thermal Resistance (Junction to Case) Test Conditions SOJ Package TSOP II Package Unit 57.91 50.66 °C/W 36.73 17.17 °C/W Still Air, soldered on a 3 × 4.5 inch, two layer printed circuit board AC Test Loads and Waveforms Figure 1. AC Test Loads and Waveforms [4] 10 ns device Z = 50Ω ALL INPUT PULSES 3.0V 90% OUTPUT 50Ω * CAPACITIVE LOAD CONSISTS OF ALL COMPONENTS OF THE TEST ENVIRONMENT 30 pF* 90% 10% 10% GND 1.5V Rise Time: 1 V/ns (a) High Z characteristics: (b) Fall Time: 1 V/ns R 317Ω 3.3V OUTPUT R2 351Ω 5 pF (c) Data Retention Characteristics Over the Operating Range Parameter VDR VCC for Data Retention ICCDR Data Retention Current tCDR tR [3] Conditions [5] Description Min 2.0 Unit V VCC = VDR = 2.0V, CE > VCC – 0.3V Ind’l 10 mA VIN > VCC – 0.3V or VIN < 0.3V Auto 15 mA Chip Deselect to Data Retention Time [6] Max Operation Recovery Time 0 ns tRC ns Figure 2. Data Retention Waveform DATA RETENTION MODE VCC 3.0V tCDR VDR > 2V 3.0V tR CE Note 3. Tested initially and after any design or process changes that may affect these parameters. 4. AC characteristics (except High Z) are tested using the load conditions shown in Figure 1. High Z characteristics are tested for all speeds using the test load shown in Figure (c). 5. No input may exceed VCC + 0.3V. 6. Full device operation requires linear VCC ramp from VDR to VCC(min.) > 50 µs or stable at VCC(min.) > 50 µs. Document Number: 38-05475 Rev. *D Page 4 of 10 CY7C1049DV33 AC Switching Characteristics Over the Operating Range [7] -10 (Industrial) Parameter Description Min Max -12 (Automotive) Min Max Unit Read Cycle tpower[8] VCC(typical) to the first access 100 100 µs tRC Read Cycle Time 10 12 ns tAA Address to Data Valid tOHA Data Hold from Address Change tACE CE LOW to Data Valid tDOE OE LOW to Data Valid tLZOE OE LOW to Low Z tHZOE OE HIGH to High 10 3 10 5 0 Z[9, 10] Z[10] 12 3 ns 12 ns 6 ns 0 5 ns ns 6 ns 6 ns 12 ns tLZCE CE LOW to Low tHZCE CE HIGH to High-Z[9, 10] tPU CE LOW to Power up tPD CE HIGH to Power down tWC Write Cycle Time 10 12 ns tSCE CE LOW to Write End 7 8 ns tAW Address Set up to Write End 7 8 ns tHA Address Hold from Write End 0 0 ns tSA Address Set up to Write Start 0 0 ns tPWE WE Pulse Width 7 8 ns tSD Data Set up to Write End 5 6 ns tHD Data Hold from Write End 0 0 ns 3 3 ns 3 3 5 0 ns 0 10 ns Write Cycle[11, 12] tLZWE tHZWE WE HIGH to Low Z[10] WE LOW to High Z[9, 10] 5 6 ns Notes 7. Test conditions assume signal transition time of 3 ns or less, timing reference levels of 1.5V, input pulse levels of 0 to 3.0V, and output loading of the specified IOL/IOH and 30 pF load capacitance. 8. tPOWER gives the minimum amount of time that the power supply must be at stable, typical VCC values until the first memory access is performed. 9. tHZOE, tHZCE, and tHZWE are specified with a load capacitance of 5 pF as in part (d) of AC Test Loads. Transition is measured when the outputs enter a high impedance state. 10. At any temperature and voltage condition, tHZCE is less than tLZCE, tHZOE is less than tLZOE, and tHZWE is less than tLZWE for any given device. 11. The internal write time of the memory is defined by the overlap of CE LOW, and WE LOW. CE and WE must be LOW to initiate a write, and the transition of either of these signals can terminate the write. The input data set up and hold timing must be referred to the leading edge of the signal that terminates the write. 12. The minimum write cycle time for Write Cycle No. 2 (WE controlled, OE LOW) is the sum of tHZWE and tSD. Document Number: 38-05475 Rev. *D Page 5 of 10 CY7C1049DV33 Switching Waveforms Figure 3. Read Cycle No. 1[13, 14] tRC ADDRESS tOHA DATA OUT tAA PREVIOUS DATA VALID DATA VALID Figure 4. Read Cycle No. 2 (OE Controlled)[14, 15] ADDRESS tRC CE tACE OE tHZOE tDOE DATA OUT tHZCE tLZOE HIGH IMPEDANCE DATA VALID tLZCE tPD tPU VCC SUPPLY CURRENT HIGH IMPEDANCE 50% 50% ICC ISB Figure 5. Write Cycle No. 1 (WE Controlled, OE HIGH During Write)[16, 17] tWC ADDRESS tSCE CE tAW tSA tHA tPWE WE OE tSD DATA I/O tHD DATAIN VALID NOTE 17 tHZOE Notes 13. Device is continuously selected. OE, CE = VIL. 14. WE is HIGH for read cycle. 15. Address valid prior to or coincident with CE transition LOW. 16. Data IO is high impedance if OE = VIH. 17. If CE goes HIGH simultaneously with WE going HIGH, the output remains in a high impedance state. Document Number: 38-05475 Rev. *D Page 6 of 10 CY7C1049DV33 Switching Waveforms (continued) Figure 6. Write Cycle No. 2 (WE Controlled, OE LOW)[17] tWC ADDRESS tSCE CE tAW tSA tHA tPWE WE tSD DATA I/O NOTE 18 tHD DATA VALID tLZWE tHZWE Figure 7. Write Cycle No. 3 (CE Controlled)[16, 17] tWC ADDRESS tSCE CE tSA tSCE tAW tHA tPWE WE tSD DATA I/O tHD DATA VALID Note 18. During this period the IOs are in the output state and input signals must not be applied. Document Number: 38-05475 Rev. *D Page 7 of 10 CY7C1049DV33 Truth Table CE H OE X WE X L L H IO0–IO7 Mode Power High Z Power down Standby (ISB) Data Out Read Active (ICC) L X L Data In Write Active (ICC) L H H High Z Selected, Outputs Disabled Active (ICC) Ordering Information Speed (ns) 10 12 Ordering Code Package Name Package Type CY7C1049DV33-10VXI 51-85090 36-pin (400-Mil) Molded SOJ (Pb-free) CY7C1049DV33-10ZSXI 51-85087 44-pin TSOP II (Pb-free) CY7C1049DV33-12VXE 51-85090 36-pin (400-Mil) Molded SOJ (Pb-free) CY7C1049DV33-12ZSXE 51-85087 44-pin TSOP II (Pb-free) Operating Range Industrial Automotive Contact your local Cypress sales representative for availability of these parts. Package Diagrams Figure 8. 36-Pin (400-Mil) Molded SOJ (51-85090) 5 1-85 090 -*C Document Number: 38-05475 Rev. *D Page 8 of 10 CY7C1049DV33 Package Diagrams (continued) Figure 9. 44-Pin Thin Small Outline Package Type II (51-85087) 51-85087-*A Document Number: 38-05475 Rev. *D Page 9 of 10 CY7C1049DV33 Document History Page Document Title: CY7C1049DV33, 4-Mbit (512K x 8) Static RAM Document Number: 38-05475 REV. ECN NO. Issue Date Orig. of Change ** 201560 See ECN SWI Advance Datasheet for C9 IPP *A 233729 See ECN SYT 1.AC, DC parameters are modified as per EROS (Specification # 01-2165) 2.Pb-free offering in the Ordering Information Table *B 351096 See ECN PCI Changed from Advance to Preliminary Removed 20 ns Speed bin Corrected DC voltage (min) value in maximum ratings section from - 0.5 to - 0.3V Redefined ICC values for Com’l and Ind’l temperature ranges ICC (Com’l): Changed from 100, 80, and 67 mA to 90, 80 and, 75 mA for 8, 10, and 12ns speed bins respectively ICC (Ind’l): Changed from 80 and 67 mA to 90 and 85 mA for 10 and 12ns speed bins respectively Added VIH(max) specification in Note# 2 Changed reference voltage level for measurement of High Z parameters from ±500 mV to ±200 mV Added Data Retention Characteristics, Waveform, and footnotes 11 and 12 Changed Package Diagram name from 44-pin TSOP II Z44 to 44-pin TSOP II ZS44 Changed part names from Z to ZS in the Ordering Information Table Added 8 ns parts in the Ordering Information Table Added Pb-free Ordering Information Shaded Ordering Information Table *C 446328 See ECN NXR Converted from Preliminary to Final Removed -8 speed bin Removed Commercial Operating Range product information Added Automotive Operating Range product information Updated Thermal Resistance table Updated footnote #8 on High Z parameter measurement Replaced Package Name column with Package Diagram in the Ordering Information table *D 1274726 See ECN VKN/AESA Corrected typo in the 44-Pin TSOP II pinout Description of Change © Cypress Semiconductor Corporation, 2004-2007. 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Document Number: 38-05475 Rev. *D Revised July 23, 2007 All products and company names mentioned in this document may be the trademarks of their respective holders. Page 10 of 10