MPQ6400 Low Quiescent Current Programmable-Delay Supervisory Circuit AEC-Q100 Qualified The Future of Analog IC Technology FEATURES The MPQ6400 family is the microprocessor (µP) supervisory circuit which can monitor and provide reset function for system voltages from 0.4V. When either the SENSE voltage falls below its threshold (VIT) or the voltage of ) is pulled to a logic low, the manual reset ( signal will be asserted. The reset voltage can be factory-set for standard voltage rails from 0.9V to 5V, while the MPQ6400DG01 reset voltage is adjustable with an external resistor divider. When SENSE voltage and exceed their thresholds, is driven to a logic high after a user-programmable delay time. The MPQ6400 has a very low quiescent current of 1.6μA typically, which makes it ideal suitable for battery-powered applications. It provides a precision reference to achieve ±1% threshold accuracy. The reset delay time can be selected by a capacitor which is connected between CDELAY and GND, allowing the user to select any delay time from 2.1ms to 10s. 380ms delay time is selected by connecting the CDELAY pin to VCC, while 24ms delay time by leaving the CDELAY pin float. MPQ6400 is available in 2mm×2mm 6-pin QFN package. APPLICATIONS R M DESCRIPTION T E S E R T R E M S E R R M T E S E R Guaranteed Industrial/Automotive Temp Range Limits Fixed Threshold Voltages for Standard Voltage Rails From 0.9V to 5V and Adjustable Voltage From 0.4V are Available Low Quiescent Current: 1.6μA Typ Power-On Reset Generator with Adjustable Delay Time: 2.1ms to 10s High Threshold Accuracy: ±1% Typ Manual Reset ( ) Input Open-Drain Output Immune to Short Negative SENSE Voltage Guaranteed Reset Valid to VCC=0.8V 2×2mm QFN DSP or Micro controller Applications Laptop/Desktop Computers PDAs/Hand-Held Products Portable/Battery-Powered Products FPGA/ASIC Applications For MPS green status, please visit MPS website under Quality Assurance. “MPS” and “The Future of Analog IC Technology” are Registered Trademarks of Monolithic Power Systems, Inc. TYPICAL APPLICATION MPQ6400 Rev. 1.0 www.MonolithicPower.com 12/5/2011 MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited. © 2011 MPS. All Rights Reserved. 1 TM MPQ6400 -- LOW QUIESCENT CURRENT PROGRAMMABLE-DELAY SUPERVISORY CIRCUIT VCC R1 VCC Microprocessor SENSE R3 MPQ6400 C1 Microcontroller C2 R2 MR GND DSP RESET CDELAY C3 RESET GND CDELAY MPQ6400 Rev. 1.0 www.MonolithicPower.com 12/5/2011 MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited. © 2011 MPS. All Rights Reserved. 2 TM MPQ6400 -- LOW QUIESCENT CURRENT PROGRAMMABLE-DELAY SUPERVISORY CIRCUIT ORDERING INFORMATION Part Number* Package TJ MPQ6400DG-33** QFN6 (2x2mm) -40C to +125C MPQ6400DG-33-AEC1 QFN6 (2x2mm) -40C to +125C *For Tape & Reel, add suffix –Z (e.g. MPQ6400DG–XX-Z); For RoHS compliant packaging, add suffix –LF (e.g. MPQ6400DG–XX-LF–Z). ** Check factory for availability in other options. PACKAGE REFERENCE TOP VIEW VCC 1 6 RESET SENSE 2 5 GND CDELAY 3 4 MR QFN6 (2 x 2mm) ABSOLUTE MAXIMUM RATINGS (1) Supply Voltage VCC .......................... -0.3 to 6.0V CDELAY Voltage VCDELAY ........ -0.3V to VCC + 0.3V SENSE Voltage VSENSE ..................... -0.3V to 6V All Other Pins ...............................-0.3V to +6.0V RESET Current IRESET ................................ 5mA Continuous Power Dissipation (TA = +25°C) (2) QFN6 (2mmx2mm) .................................... 2.5W Junction Temperature ...............................150°C Lead Temperature ....................................260°C Storage Temperature ............... -65°C to +150°C Recommended Operating Conditions (3) Thermal Resistance (4) θJA θJC QFN6 (2x2mm) ...................... 50 ...... 12 ... C/W Notes: 1) Exceeding these ratings may damage the device. 2) The maximum allowable power dissipation is a function of the maximum junction temperature TJ(MAX), the junction-toambient thermal resistance θJA, and the ambient temperature TA. The maximum allowable continuous power dissipation at any ambient temperature is calculated by PD(MAX)=(TJ(MAX)TA)/θJA. Exceeding the maximum allowable power dissipation will cause excessive die temperature, and the regulator will go into thermal shutdown. Internal thermal shutdown circuitry protects the device from permanent damage. 3) The device is not guaranteed to function outside of its operating conditions. 4) Measured on JESD51-7 4-layer board. Supply Voltage VCC ......................... 1.8V to 5.5V Maximum Junction Temp. (TJ) ............. +125°C MPQ6400 Rev. 1.0 www.MonolithicPower.com 12/5/2011 MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited. © 2011 MPS. All Rights Reserved. 3 MPQ6400 – LOW QUIESCENT CURRENT PROGRAMMABLE-DELAY SUPERVISORY CIRCUIT ELECTRICAL CHARACTERISTICS 1.8V≤VCC≤5.5V, R3 = 100kΩ, C3 = 47pF, TJ= -40°C to +125°C, Typical values are at Tj=+25°C, unless otherwise noted. Parameters Symbol Max Units 5.5 V 1.6 5 µA 1.85 15 µA 1.3V ≤ VCC < 1.8V, IOL = 0.4mA 0.3 V 1.8V ≤ VCC ≤ 5.5V, IOL = 1.0mA 0.4 V 0.8 V VCC ICC 1.8 not , VOL not , CDELAY T E S E R Low-level Output Voltage VCC = 5.5V, asserted. , open Typ T E S E VCC = 3.3V, asserted. , CDELAY open RR M Supply Current (current into VCC pin) Min T E T S E E S R E RR M Input Supply Range Condition T E S E A u 5 1 IR VOL (max) = 0.2V, Power-up Reset Voltage(5) Trise(Vcc)≥15µs/V Negative-going (7) Accuracy Input Threshold -40°C to +85°C -2.5 -40°C to +125°C -3 VHYS 50 R M R M Internal Pull-up Resistance ISENSE T E S E T E S E R Leakage Current R R M M VIL Logic High Input VIH SENSE Maximum Transient Duration = 5.5V, tw 2.4 µA T E S E R T E S E R R M T E S E R T E S E R Delay, nA 0.25VCC V V µs CDELAY = Open 15 24 34 ms VCC(6) 230 380 530 ms 1.3 2.1 3 ms 61 102 142 ms CDELAY = CDELAY = 150pF tpHL1 VIH = 0.7 VCC, VIL = 0.25 VCC 160 ns tpHL2 VIH = 1.05 VIT, VIL = 0.95 VIT 17.5 µs T E S E R Note: 5) The lowest supply voltage (VCC) at which 6) Guaranteed by design. 7) VSENSE Falling Slowly 500 17.5 CDELAY = 10nF High to Low Level SENSE to VIT% kΩ 0.7VCC (6) Propagation Delay 4 % 110 not VIH = 1.05 VIT, VIL = 0.95 VIT td Delay Time to 1.7 asserted Logic Low Input 1.5 T E S E R Fixed versions VSENSE = 6V VR Input Current at SENSE Pin ±1.0 1.5 R Hysteresis on VIT Pin VIT becomes active. MPQ6400 Rev. 1.0 www.MonolithicPower.com 12/5/2011 MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited. © 2011 MPS. All Rights Reserved. 4 TM MPQ6400 -- LOW QUIESCENT CURRENT PROGRAMMABLE-DELAY SUPERVISORY CIRCUIT ORDERING INFORMATION Product MPQ6400DG-33 Package QFN Top Mark Nominal Supply Voltage 3.3V Threshold Voltage (VIT) 3.07V PIN FUNCTIONS QFN Pin # 1 3 Supply voltage. A 0.1uF decoupling ceramic capacitor should be put close to this pin. SENSE pin is connected to the monitored system voltage. When the monitored voltage is SENSE below desired threshold, is asserted. CDELAY ) can introduce another logic signal to control the The manual reset ( internally connected to VCC through a 90kΩ resistor. Ground. T E S E R GND Programmable reset delay time pin. When CDELAY connected to VCC through a resistor between 50kΩ and 200kΩ, a 380ms delay time is selected. When CDELAY floated, the delay time is 24ms. A capacitor bigger than 150pF connected CDELAY to GND could be used to get the user’s programmable time from 2.1ms to 10s. R M 5 VCC R M 4 Description T E S E R 2 Name . It is T E S E R T E S E R R M T E S E R T E S E R 6 is an open drain signal which will be asserted when the SENSE voltage drops below a preset threshold or when the manual reset ( ) pin drops to a logic low. The delay time is programmable from 2.1ms to 10s by using external capacitors. A pull-up resistor bigger than 10k should be connected this pin to supply line, and the outputting a higher voltage than VCC is allowable. T E S E R DETAIL DESCRIPTION R M T E S E R output remains asserted for a user’s programmable delay time. Two fixed delay times are user-selectable: 380ms delay time by connecting the CDELAY pin to VCC, and 24ms delay time by leaving the CDELAY pin float. Any delay time from 2.1ms to 10s could be gotten by connecting a capacitor between CDELAY and GND. The wide monitor voltage and programmable reset delay time make MPQ6400 product family suitable for a broad array of applications. MPQ6400 Rev. 1.0 www.MonolithicPower.com 12/5/2011 MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited. © 2011 MPS. All Rights Reserved. T E S E R R M The MPQ6400 product family asserts a signal when either the SENSE pin voltage is lower than VIT or the manual reset ( ) is driven low. The MPQ6400-XX family, other than the MPQ6400DG-01, can monitor a fixed voltage from 0.9V to 5.0V. The MPQ6400DG-01 can monitor any voltage above 0.4V by adjusting the external resistor divider. After both the manual reset ( ) and SENSE voltages exceed their thresholds, the 5 MPQ6400 – LOW QUIESCENT CURRENT PROGRAMMABLE-DELAY SUPERVISORY CIRCUIT TYPICAL PERFORMANCE CHARACTERISTICS VCC=3.3V, R3 = 100kΩ, C3 = 47pF, TA= -40°C to +125°C, Typical values are at TA=+25°C, unless otherwise noted. Supply Current vs. VCC Reset Delay Time vs. CDELAY 100 10 100 Maximum SENSE Transient Duration vs.SENSE Threshold Overdrive Voltage 9 RESET DELAY TIME(s) 8 7 6 5 4 3 2 10 1 10 0.1 0.01 1 0 1.5 2.5 3.5 4.5 5.5 0.001 0.0001 0.001 0.01 6.5 0.1 1 1 10 0 10 20 30 40 50 60 Reset Delay vs.Temperature Reset Delay vs.Temperature (CDELAY=open) (CDELAY=VCC) Reset Delay vs.Temperature (CDELAY=150pF Cap) 500 3 29 480 2.8 28 27 26 VCC=3.3V 24 23 VCC=6V 22 21 440 400 Normalized VIT vs. Temperature 340 -40 -20 VCC=1.8V 3.5 0.1 3 VCC=1.8V 0 -0.3 VCC=3.3V -0.5 -0.6 -40 -20 0 20 40 60 80 100 120140 VCC=3.3V 1.8 1.6 1.4 VCC=6V 12 VCC=6V 10 VCC=6V 1 0-40 -20 VCC=1.8V 2 IRESET vs. Low Level Reset Voltage VCC=1.8V 1.5 0.5 2.2 14 2 VCC=6V 2.4 1 -40 -20 0 20 40 60 80 100 120140 0 20 40 60 80 100 120 140 2.5 -0.1 2.6 1.2 VHYS vs. Temperature 0.2 -0.4 VCC=3.3V 380 360 VCC=1.8V 20 -40 -20 0 20 40 60 80 100 120 140 -0.2 VCC=6V 420 VCC=3.3V 0 20 40 60 80 100 120 140 IRESET(mA) 25 460 RESET DELAY(ms) 30 RESET DELAY(ms) RESET DELAY(ms) V CC(V) 8 VCC=1.8V 6 4 VCC=3.3V 2 00 0.2 0.4 0.6 0.8 1 LOW LEVEL RESET VOLTAGE(V) MPQ6400 Rev. 1.0 www.MonolithicPower.com 12/5/2011 MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited. © 2011 MPS. All Rights Reserved. 6 MPQ6400 – LOW QUIESCENT CURRENT PROGRAMMABLE-DELAY SUPERVISORY CIRCUIT FUNCTIONAL BLOCK DIAGRAM VCC VCC VCC 90k VCC MPQ6400DG-01 Adjustable Voltage MR 0.4V SENSE RESET MR SENSE -- R1 Reset Logic Timer + MPQ6400DG-XX 90k RESET Reset Logic Timer + R2 0.4V -CDELAY CDELAY GND GND Adjustable Voltage Version Fixed Voltage Version Figure 1—Functional Block Diagram TIMING DIAGRAM VCC 0.8V 0.0V RESET tD tD tD tD=Reset Delay =Undefined State SENSE VIT+VHYS VIT MR 0.7VCC 0.25VCC Time Figure 2—MPQ6400 Timing Diagram T E S E R R M L L H H TRUTH TABLE SENSE > VIT 0 1 0 1 L L L H MPQ6400 Rev. 1.0 www.MonolithicPower.com 12/5/2011 MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited. © 2011 MPS. All Rights Reserved. 7 MPQ6400 – LOW QUIESCENT CURRENT PROGRAMMABLE-DELAY SUPERVISORY CIRCUIT APPLICATION INFORMATION T E S E R Reset Output Function The MPQ6400 output is typically connected to the input of a microprocessor, is not as shown in Figure 3. When asserted, a pull up resistor must be connected to hold this signal high. The voltage of reset signal is allowed to be higher than VCC (up to 6V) through a resistor pulling up from supply line. If the voltage is below 0.8V, output is undefined. This condition can be ignored generally because that most microprocessors do not function at this state. When both SENSE and are higher than their threshold voltage, output holds logic high. Once either of the two drops below their threshold, will be asserted. T E S E R T E S E R divider from monitored voltage to GND. Its tap connects to the SENSE pin. The circuit can be used to monitor any voltage higher than 0.4V. VSEN VCC VIT = (1+ R1 T E S E R T E S E R SENSE 1nF R2 GND Figure 4—MPQ6400DG-01 Monitoring a UserDefined Voltage Monitor Multiple System Voltages The manual reset ( ) can introduce another logic signal to control the . When is a logic low (0.25VCC), will be asserted. After are above their thresholds, both SENSE and will be driven to a logic high after a reset is internally connected to VCC delay time. The through a 90kΩ resistor so this pin can float. See how multiple system voltages are monitored by in Figure 5. If the signal on isn’t up to VCC, there will be an additional current through internal 90kΩ pull up resistor. A logic-level FET can be used to minimize the leakage, as shown in Figure 6. R M VCC MR RESET GND CDELAY RESET 47pF GND R M 1nF T E S E R Microcontroller T E S E DSP 100k RR M Microprocessor SENSE R2 R M T E S E R R1 0.1uF MPQ6400DG-01 R1 )0.4 R2 RESET T E S E R R M VCC VOUT R M Figure 3—Typical Application of MPQ6400 with Microprocessor 3.3V 1.2V T E S E R From the point that is again logic high and SENSE is above VIT + VHYS (the threshold hysteresis), will be driven to a logic high after a reset delay time. The reset delay time is programmable by CDELAY pin. Due to the finite impedance of pin, the pull up resistor should be bigger than 10kΩ. R M R M CDELAY T E S E R MPQ6400DG-12 RESET CDELAY GND SENSE VCC MPQ6400DG-33 MR RESET CDELAY GND VI/O VCORE DSP RESET GND T E S E R Monitor a Voltage The SENSE input pin is connected to the monitored system voltage directly or through a resistor network (on MPQ6400DG-01). When the voltage on the pin is below VIT, is asserted. A threshold hysteresis will prevent the chip from responding perturbation on SENSE pin. A 1nF to 10nF bypass capacitor should be put on this pin to increase its immunity to noise. A typical application of the MPQ6400DG-01 is shown in Figure 4. Two external resistors form a voltage SENSE VCC Figure 5— MPQ6400 Family Monitoring Multiple System Voltages MPQ6400 Rev. 1.0 www.MonolithicPower.com 12/5/2011 MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited. © 2011 MPS. All Rights Reserved. 8 MPQ6400 – LOW QUIESCENT CURRENT PROGRAMMABLE-DELAY SUPERVISORY CIRCUIT 3.3V R M VCC The reset delay time is determined by the charge time of external capacitor. While SENSE is above VIT and is a logic high, the internal 140nA current source is enabled and starts to charge the capacitor to set the delay time. When the capacitor voltage rises to 1.13V, the is deasserted. The capacitor will be discharged when is again asserted. Stray capacitance the may cause errors of the delay time. A ceramic capacitor with low leakage is strongly recommended. SENSE T E S E R MR RESET T E S E R MPQ6400DG-33 GND Figure 6—Minimizing ICC When MR Signal isn’t over VCC by External MOSFET 3.3V SENSE Voltage Transients Immunity The MPQ6400 can be immune to SENSE pin short negative transient. The maximum immune duration is 17us while overdrive is 5%. A shorter negative transient can not assert the output. The effective duration is relative to the threshold overdrive, as shown in Figure 8. T E S E R Programmable Reset Delay Time The reset delay time can be programmed by CDELAY configure. When CDELAY is connected to VCC through a resistor between 50kΩ and 200kΩ, the delay time is 380ms. When CDELAY floated, the delay time is 24ms. In addition, a capacitor connected CDELAY to GND could be used to get the user’s programmable delay time from 2.1ms to 10s. The three configures can be found in Figure 7(a)(b)(c). 100 Maximum SENSE Transient Duration vs.SENSE Threshold Overdrive Voltage 3.3V SENSE SENSE VCC 50k VCC MPQ6400DG-33 MPQ6400DG-33 RESET RESET CDELAY 10 CDELAY GND GND 24ms Delay (b) 380ms Delay (a) 1 0 10 20 30 40 50 60 3.3V SENSE VCC MPQ6400DG-33 Figure 8—Maximum Transient Duration vs. Sense Threshold Overdrive Voltage RESET CDELAY CDELAY GND (c) Figure 7—Programmable Configurations to the Reset Delay Time The external capacitor CDELAY must be larger than 150pF. For a given delay time, the capacitor value can be calculated using the following equation: C DELAY (nF) [t D (s) 4.99 10 4 (s)] 107 MPQ6400 Rev. 1.0 www.MonolithicPower.com 12/5/2011 MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited. © 2011 MPS. All Rights Reserved. 9 MPQ6400 – LOW QUIESCENT CURRENT PROGRAMMABLE-DELAY SUPERVISORY CIRCUIT PACKAGE INFORMATION QFN6 (2 x 2mm) PIN 1 ID MARKING 1.90 2.10 0.30 0.40 0.20 0.30 1.90 2.10 PIN 1 ID INDEX AREA 0.65 0.85 PIN 1 ID SEE DETAIL A 1 6 1.25 1.45 0.65 BSC 3 4 TOP VIEW BOTTOM VIEW 0.80 1.00 0.20 REF PIN 1 ID OPTION A 0.30x45º TYP. PIN 1 ID OPTION B R0.20 TYP. 0.00 0.05 SIDE VIEW DETAIL A NOTE: 1.90 0.70 0.70 1) ALL DIMENSIONS ARE IN MILLIMETERS. 2) EXPOSED PADDLE SIZE DOES NOT INCLUDE MOLD FLASH. 3) LEAD COPLANARITY SHALL BE 0.10 MILLIMETER MAX. 4) JEDEC REFERENCE IS MO-229, VARIATION VCCC. 5) DRAWING IS NOT TO SCALE. 0.25 1.40 0.65 RECOMMENDED LAND PATTERN NOTICE: The information in this document is subject to change without notice. Users should warrant and guarantee that third party Intellectual Property rights are not infringed upon when integrating MPS products into any application. MPS will not assume any legal responsibility for any said applications. MPQ6400 Rev. 1.0 www.MonolithicPower.com 12/5/2011 MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited. © 2011 MPS. All Rights Reserved. 10