TPS3808-EP www.ti.com ................................................................................................................................................. SBVS103C – APRIL 2008 – REVISED NOVEMBER 2008 LOW QUIESCENT CURRENT, PROGRAMMABLE DELAY SUPERVISORY CIRCUIT FEATURES SUPPORTS DEFENSE, AEROSPACE, AND MEDICAL APPLICATIONS 1 • Power-On Reset Generator With Adjustable Delay Time: 1.25 ms to 10 s • Very Low Quiescent Current: 2.4 µA Typical • High Threshold Accuracy: 0.5% Typical • Fixed Threshold Voltages for Standard Voltage Rails from 0.9 V to 5 V and Adjustable Voltage Down to 0.4 V Are Available • Manual Reset (MR) Input • Open-Drain RESET Output • Temperature Range: –55°C to 125°C • Small SOT23 Package 2 • • • • • • • Controlled Baseline One Assembly/Test Site One Fabrication Site Available in Military (–55°C/125°C) Temperature Range (1) Extended Product Life Cycle Extended Product-Change Notification Product Traceability APPLICATIONS • • • • • (1) DSP or Microcontroller Applications Notebook/Desktop Computers PDAs/Hand-Held Products Portable/Battery Powered Products FPGA/ASIC Applications Custom temperature ranges available DESCRIPTION/ORDERING INFORMATION The TPS3808xxx family of microprocessor supervisory circuits monitors system voltages from 0.4 V to 5.0 V, asserting an open-drain RESET signal when the SENSE voltage drops below a preset threshold or when the manual reset (MR) pin drops to a logic low. The RESET output remains low for the user-adjustable delay time after the SENSE voltage and manual reset (MR) return above the respective thresholds. The TPS3808 uses a precision reference to achieve 0.5% threshold accuracy for VIT ≤ 3.3 V. The reset delay time can be set to 20 ms by disconnecting the CT pin, 300 ms by connecting the CT pin to VDD using a resistor, or can be user-adjusted between 1.25 ms and 10 s by connecting the CT pin to an external capacitor. The TPS3808 has a very low typical quiescent current of 2.4 µA, so it is well-suited to battery-powered applications. It is available in a small SOT23 package, and is fully specified over a temperature range of –55°C to +125°C (TJ). 1.2 V 3.3 V DBV (SOT-23) PACKAGE (TOP VIEW) SENSE VDD SENSE VDD TPS3808G12 TPS3808G33 RESET CT GND MR CT RESET GND VI/O VCORE RESET 1 6 VDD GND 2 5 SENSE MR 3 4 CT DSP GPIO GND Typical Application Circuit 1 2 Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. All trademarks are the property of their respective owners. PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. Copyright © 2008, Texas Instruments Incorporated TPS3808-EP SBVS103C – APRIL 2008 – REVISED NOVEMBER 2008 ................................................................................................................................................. www.ti.com This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage. ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more susceptible to damage because very small parametric changes could cause the device not to meet its published specifications. ORDERING INFORMATION (1) PRODUCT (2) NOMINAL SUPPLY VOLTAGE (3) THRESHOLD VOLTAGE (VIT) TPS3808G01MDBVTEP Adjustable 0.405 V NXS TPS3808G09MDBVTEP (4) 0.9 V 0.84 V PREVIEW TPS3808G12MDBVTEP (4) 1.2 V 1.12 V PREVIEW TPS3808G125MDBVTEP (2) (3) (4) (4) 1.25 V 1.16 V PREVIEW TPS3808G15MDBVTEP (4) 1.5 V 1.40 V PREVIEW TPS3808G18MDBVTEP (4) 1.8 V 1.67 V PREVIEW (4) 2.5 V 2.33 V PREVIEW TPS3808G30MDBVTEP (4) 3.0 V 2.79 V PREVIEW TPS3808G33MDBVREP 3.3 V 3.07 V CHK TPS3808G50MDBVTEP (4) 5.0 V 4.65 V PREVIEW TPS3808G25MDBVTEP (1) TOP-SIDE MARKING For the most current package and ordering information see the Package Option Addendum at the end of this document, or see the TI web site at www.ti.com. Devices are shipped on tape and reel with either 250 units per reel (part numbers ending with 'TEP') or 3000 units per reel (part numbers ending with 'REP'). Package drawings, thermal data, and symbolization are available at www.ti.com/packaging. Custom threshold voltages from 0.82 V to 3.3 V, 4.4 V to 5.0 V are available through the use of factory EEPROM programming. Minimum order quantities apply. Contact factory for details and availability. Product Preview. Contact your TI sales representative for availability. ABSOLUTE MAXIMUM RATINGS (1) Over operating junction temperature range, unless otherwise noted. Input voltage range, VDD CT voltage range, VCT Other voltage ranges: VRESET, VMR, VSENSE TPS3808 UNIT –0.3 to 7.0 V –0.3 to VDD + 0.3 V –0.3 to 7 V 5 mA Operating junction temperature range, TJ (2) –55 to +150 °C Storage temperature range, Tstg –65 to +150 °C ESD rating, HBM 2 kV ESD rating, CDM 500 V RESET pin current (1) (2) 2 Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under the Electrical Characteristics is not implied. Exposure to absolute maximum rated conditions for extended periods may affect device reliability. As a result of the low dissipated power in this device, it is assumed that TJ = TA. Submit Documentation Feedback Copyright © 2008, Texas Instruments Incorporated Product Folder Link(s): TPS3808-EP TPS3808-EP www.ti.com ................................................................................................................................................. SBVS103C – APRIL 2008 – REVISED NOVEMBER 2008 ELECTRICAL CHARACTERISTICS 1.7 V ≤ VDD ≤ 6.5 V, RLRESET = 100 kΩ, CLRESET = 50 pF, over operating temperature range (TJ = –55°C to +125°C), unless otherwise noted. Typical values are at TJ = +25°C. PARAMETER VDD TEST CONDITIONS Input supply range IDD Low-level output voltage Power-up reset voltage (1) Negative-going input threshold accuracy VIT V VDD = 3.3 V, RESET not asserted MR, RESET, CT open 2.4 5.0 µA VDD = 6.5 V, RESET not asserted MR, RESET, CT open 2.7 6.0 µA 1.3 V ≤ VDD < 1.8 V, IOL = 0.4 mA 0.3 V 1.8 V ≤ VDD ≤ 6.5 V, IOL = 1.0 mA 0.4 V VOL (max) = 0.2 V, IRESET = 15 µA 0.8 V ±1.0 +2.0 VIT ≤ 3.3 V –1.7 ±0.5 +1.7 3.3 V < VIT ≤ 5.0 V –2.0 ±1.0 +2.0 TPS3808G01 1.5 3.0 Fixed versions 1.0 2.5 RMR MR Internal pullup resistance ISENSE Input current at SENSE pin IOH RESET leakage current CIN Input capacitance, any pin VIL MR logic low input VIH MR logic high input tw Input pulse width to RESET 70 TPS3808G01 VSENSE = VIT Fixed versions VSENSE = 6.5 V 90 –25 300 VIN = 0 V to VDD 5 Other pins VIN = 0 V to 6.5 V 5 0.3 VDD 0.7 VDD VDD VIH = 1.05 VIT, VIL = 0.95 VIT 20 MR VIH = 0.7 VDD, VIL = 0.3 VDD 0.001 CT = Open See Timing Diagram CT = 100 pF CT = 180 nF nA nA pF 0 SENSE %VIT µA 1.7 VRESET = 6.5 V, RESET not asserted % kΩ 25 CT pin CT = VDD UNIT 6.5 –2.0 Hysteresis on VIT pin RESET delay time MAX TPS3808G01 VHYS td TYP 1.7 Supply current (current into VDD pin) VOL MIN V µs 12 20 29 ms 180 300 440 ms 0.75 1.25 1.8 ms 1.2 1.8 0.7 s Propagation delay MR to RESET VIH = 0.7 VDD, VIL = 0.3 VDD 150 ns tpHL High-to-low level RESET delay SENSE to RESET VIH = 1.05 VIT, VIL = 0.95 VIT 20 µs θJA Thermal resistance, junction-to-ambient 290 °C/W (1) The lowest supply voltage (VDD) at which RESET becomes active. Trise(VDD) ≥ 15 µs/V. Submit Documentation Feedback Copyright © 2008, Texas Instruments Incorporated Product Folder Link(s): TPS3808-EP 3 TPS3808-EP SBVS103C – APRIL 2008 – REVISED NOVEMBER 2008 ................................................................................................................................................. www.ti.com FUNCTIONAL BLOCK DIAGRAMS VDD VDD VDD TPS3808G01 Adjustable Voltage VDD 90k 90k RESET MR SENSE Reset Logic Timer Reset Logic Timer R1 − − SENSE RESET MR CT + CT + R2 0.4V VREF 0.4V VREF R1 + R2 = 4MΩ GND GND Adjustable Voltage Version Fixed Voltage Version Figure 1. Adjustable and Fixed Voltage Versions PIN ASSIGNMENTS DBV PACKAGE SOT23 (TOP VIEW) RESET 1 6 VDD GND 2 5 SENSE MR 3 4 CT Table 1. TERMINAL FUNCTIONS TERMINAL 4 NAME SOT23 (DBV) PIN NO. RESET 1 RESET is an open-drain output that is driven to a low impedance state when RESET is asserted (either the SENSE input is lower than the threshold voltage (VIT) or the MR pin is set to a logic low). RESET remains low (asserted) for the reset period after both SENSE is above VIT and MR is set to a logic high. A pullup resistor from 10 kΩ to 1 MΩ should be used on this pin, and allows the reset pin to attain voltages higher than VDD. GND 2 Ground MR 3 Driving the manual reset pin (MR) low asserts RESET. MR is internally tied to VDD by a 90kΩ pullup resistor. CT 4 Reset period programming pin. Connecting this pin to VDD through a 40-kΩ to 200-kΩ resistor or leaving it open results in fixed delay times (see Electrical Characteristics). Connecting this pin to a ground referenced capacitor ≥ 100 pF gives a user-programmable delay time. See the Selecting the Reset Delay Time section for more information. SENSE 5 This pin is connected to the voltage to be monitored. If the voltage at this terminal drops below the threshold voltage VIT, then RESET is asserted. VDD 6 Supply voltage. It is good analog design practice to place a 0.1-µF ceramic capacitor close to this pin. DESCRIPTION Submit Documentation Feedback Copyright © 2008, Texas Instruments Incorporated Product Folder Link(s): TPS3808-EP TPS3808-EP www.ti.com ................................................................................................................................................. SBVS103C – APRIL 2008 – REVISED NOVEMBER 2008 TIMING DIAGRAM VDD 0.8V 0.0V RESET tD = Reset Delay tD tD tD = Undefined State SENSE VIT + VHYS VIT MR 0.7VDD 0.3VDD Time Figure 2. TPS3808 Timing Diagram Showing MR and SENSE Reset Timing TRUTH TABLE MR SENSE > VIT RESET L 0 L L 1 L H 0 L H 1 H Submit Documentation Feedback Copyright © 2008, Texas Instruments Incorporated Product Folder Link(s): TPS3808-EP 5 TPS3808-EP SBVS103C – APRIL 2008 – REVISED NOVEMBER 2008 ................................................................................................................................................. www.ti.com TYPICAL CHARACTERISTICS At TJ = +25°C, VDD = 3.3 V, RLRESET = 100kΩ, and CLRESET = 50pF, unless otherwise noted. SUPPLY CURRENT vs SUPPLY VOLTAGE RESET TIMEOUT PERIOD vs CT 4.0 100 3.5 IDD (µA) RESET Timeout (sec) +125_ C 3.0 +85_ C 2.5 2.0 +25_C 1.5 1.0 10 −40°C, +25°C, +125°C 1 0.1 0.01 − 40_ C 0.5 0 0 1 2 3 4 5 6 0.001 0.0001 7 0.001 0.01 VDD (V) NORMALIZED RESET TIMEOUT PERIOD vs TEMPERATURE (CT = OPEN, CT = VDD, CT = Any) MAXIMUM TRANSIENT DURATION AT SENSE vs SENSE THRESHOLD OVERDRIVE VOLTAGE 100 Transient Duration below VIT (µs) Normalized RESET Timeout Period (%) 8 6 4 2 0 −2 −4 −6 −8 RESET OCCURS ABOVE THE CURVE 10 1 −10 −30 −10 10 30 50 70 90 110 0 130 5 10 15 25 30 35 40 Figure 6. NORMALIZED SENSE THRESHOLD VOLTAGE (VIT) vs TEMPERATURE LOW-LEVEL RESET VOLTAGE vs RESET CURRENT 45 50 4.5 VOL Low−Level RESET Voltage (V) 1.0 0.8 0.6 Normalized VIT (%) 20 Overdrive (%VIT) Figure 5. 0.4 0.2 0 −0.2 −0.4 −0.6 −0.8 −1.0 −50 10 Figure 4. Temperature (°C) 4.0 3.5 3.0 2.5 2.0 VDD = 1.8V 1.5 1.0 0.5 0 −30 −10 10 30 50 70 90 110 130 0 0.5 Temperature (°C) Figure 7. 6 1 Figure 3. 10 −50 0.1 CT (µF) 1.0 1.5 2.0 2.5 RESET Current (mA) 3.0 3.5 4.0 Figure 8. Submit Documentation Feedback Copyright © 2008, Texas Instruments Incorporated Product Folder Link(s): TPS3808-EP TPS3808-EP www.ti.com ................................................................................................................................................. SBVS103C – APRIL 2008 – REVISED NOVEMBER 2008 TYPICAL CHARACTERISTICS (continued) At TJ = +25°C, VDD = 3.3 V, RLRESET = 100kΩ, and CLRESET = 50pF, unless otherwise noted. LOW-LEVEL RESET VOLTAGE vs RESET CURRENT VOL Low−Level RESET Voltage (V) 0.8 0.7 0.6 0.5 0.4 VDD = 3.3V 0.3 0.2 0.1 VDD = 6.5V 0 0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 RESET Current (mA) Figure 9. Submit Documentation Feedback Copyright © 2008, Texas Instruments Incorporated Product Folder Link(s): TPS3808-EP 7 TPS3808-EP SBVS103C – APRIL 2008 – REVISED NOVEMBER 2008 ................................................................................................................................................. www.ti.com DEVICE OPERATION The TPS3808 microprocessor supervisory product family is designed to assert a RESET signal when either the SENSE pin voltage drops below VIT or the manual reset (MR) is driven low. The RESET output remains asserted for a user-adjustable time after both the manual reset (MR) and SENSE voltages return above the respective thresholds. A broad range of voltage threshold and reset delay time adjustments are available, allowing these devices to be used in a wide array of applications. Reset threshold voltages can be factory-set from 0.82 V to 3.3 V or from 4.4 V to 5.0 V, while the TPS3808G01 can be set to any voltage above 0.405 V using an external resistor divider. Two preset delay times are also user-selectable: connecting the CT pin to VDD results in a 300ms reset delay, while leaving the CT pin open yields a 20-ms reset delay. In addition, connecting a capacitor between CT and GND allows the designer to select any reset delay period from 1.25 ms to 10 s. supply line can be used to allow the reset signal for the microprocessor to have a voltage higher than VDD (up to 6.5 V). The pullup resistor should be no smaller than 10 kΩ as a result of the finite impedance of the RESET line. SENSE INPUT The SENSE input provides a terminal at which any system voltage can be monitored. If the voltage on this pin drops below VIT, then RESET is asserted. The comparator has a built-in hysteresis to ensure smooth RESET assertions and de-assertions. It is good analog design practice to put a 1-nF to 10-nF bypass capacitor on the SENSE input to reduce sensitivity to transients and layout parasitics. The TPS3808G01 can be used to monitor any voltage rail down to 0.405 V using the circuit shown in Figure 11. VIN RESET OUTPUT A typical application of the TPS3808G25 used with the OMAP1510 processor is shown in Figure 10. The open-drain RESET output is typically connected to the RESET input of a microprocessor. A pullup resistor must be used to hold this line high when RESET is not asserted. The RESET output is undefined for voltage below 0.8 V, but this is normally not a problem since most microprocessors do not function below this voltage. RESET remains high (unasserted) as long as SENSE is above its threshold (VIT) and the manual reset (MR) is logic high. If either SENSE falls below VIT or MR is driven low, RESET is asserted, driving the RESET pin to a low impedance. 2.5V V DDSHV 1, 3, 6, 7, 9 SENSE VDD T PS 380 8G 25 MR CT 1MΩ RESET GND O M AP 1510 RESPWRON GND Figure 10. Typical Application of the TPS3808 with an OMAP Processor Once MR is again logic high and SENSE is above VIT + VHYS (the threshold hysteresis), a delay circuit is enabled which holds RESET low for a specified reset delay period. Once the reset delay has expired, the RESET pin goes to a high impedance state. The pullup resistor from the open-drain RESET to the 8 VOUT VDD VIT¢ = (1 + R1 R1 ) 0.405 R2 TPS3808G01 SENSE RESET 1nF R2 GND Figure 11. Using the TPS3808G01 to Monitor a User-Defined Threshold Voltage MANUAL RESET (MR) INPUT The manual reset (MR) input allows a processor or other logic circuits to initiate a reset. A logic low (0.3 VDD) on MR causes RESET to assert. After MR returns to a logic high and SENSE is above its reset threshold, RESET is de-asserted after the user defined reset delay expires. Note that MR is internally tied to VDD using a 90-kΩ resistor so this pin can be left unconnected if MR will not be used. See Figure 12 for how MR can be used to monitor multiple system voltages. Note that if the logic signal driving MR does not go fully to VDD, there will be some additional current draw into VDD as a result of the internal pullup resistor on MR. To minimize current draw, a logic-level FET can be used as illustrated in Figure 13. Submit Documentation Feedback Copyright © 2008, Texas Instruments Incorporated Product Folder Link(s): TPS3808-EP TPS3808-EP www.ti.com ................................................................................................................................................. SBVS103C – APRIL 2008 – REVISED NOVEMBER 2008 1.2V affected by the choice of resistor. Figure 14b shows a fixed 20-ms delay time by leaving the CT pin open. Figure 14c shows a ground referenced capacitor connected to CT for a user-defined program time between 1.25 ms and 10 s. 3.3V SENSE TPS3808G12 TPS3808G33 RESET CT V I/O SENSE V DD V DD MR CT GND V CORE The capacitor CT should be ≥ 100 pF nominal value in order for the TPS3808xxx to recognize that the capacitor is present. The capacitor value for a given delay time can be calculated using the following equation: DSP RESET GPIO GND GND C T (nF) + ƪt D (s)*0.5 10*3 (s)ƫ 175 (1) The reset delay time is determined by the time it takes an on-chip precision 220-nA current source to charge the external capacitor to 1.23 V. When a RESET is asserted the capacitor is discharged. When the RESET conditions are cleared, the internal current source is enabled and begins to charge the external capacitor. When the voltage on this capacitor reaches 1.23 V, RESET is deasserted. Note that a low-leakage type capacitor such as a ceramic should be used, and that stray capacitance around this pin may cause errors in the reset delay time. Figure 12. Using MR to Monitor Multiple System Voltages 3.3V V DD SENSE 90kW MR TPS3808xxx IMMUNITY TO SENSE PIN VOLTAGE TRANSIENTS GND The TPS3808 is relatively immune to short negative transients on the SENSE pin. Sensitivity to transients is dependent on threshold overdrive, as shown in the Maximum Transient Duration at Sense vs Sense Threshold Overdrive Voltage graph (Figure 6) in the Typical Characteristics section. Figure 13. Using an External MOSFET to Minimize IDD When MR Signal Does Not Go to VDD SELECTING THE RESET DELAY TIME The TPS3808 has three options for setting the RESET delay time as shown in Figure 14. Figure 14a shows the configuration for a fixed 300-ms typical delay time by tying CT to VDD; a resistor from 40 kΩ to 200 kΩ must be used. Supply current is not 3.3V 3.3V 50kΩ 3.3V SENSE VDD SENSE VDD SENSE VDD TPS3808G33 TPS3808G33 TPS3808G33 CT CT RESET RESET CT RESET CT 300ms Delay 20ms Delay Delay (s) = CT (nF) + 0.5 x 10−3 (s) 175 (c) (b) (a) Figure 14. Configuration Used to Set the RESET Delay Time Submit Documentation Feedback Copyright © 2008, Texas Instruments Incorporated Product Folder Link(s): TPS3808-EP 9 PACKAGE OPTION ADDENDUM www.ti.com 2-Feb-2009 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Drawing Pins Package Eco Plan (2) Qty TPS3808G01MDBVTEP ACTIVE SOT-23 DBV 6 250 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM TPS3808G33MDBVREP ACTIVE SOT-23 DBV 6 3000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM V62/08607-01XE ACTIVE SOT-23 DBV 6 250 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM V62/08607-09XE ACTIVE SOT-23 DBV 6 3000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM Lead/Ball Finish MSL Peak Temp (3) (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) (3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. 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Addendum-Page 1 PACKAGE MATERIALS INFORMATION www.ti.com 20-Jul-2010 TAPE AND REEL INFORMATION *All dimensions are nominal Device Package Package Pins Type Drawing SPQ Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) TPS3808G01MDBVTEP SOT-23 DBV 6 250 179.0 8.4 TPS3808G33MDBVREP SOT-23 DBV 6 3000 179.0 8.4 Pack Materials-Page 1 B0 (mm) K0 (mm) P1 (mm) W Pin1 (mm) Quadrant 3.2 3.2 1.4 4.0 8.0 Q3 3.2 3.2 1.4 4.0 8.0 Q3 PACKAGE MATERIALS INFORMATION www.ti.com 20-Jul-2010 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) TPS3808G01MDBVTEP SOT-23 DBV TPS3808G33MDBVREP SOT-23 DBV 6 250 203.0 203.0 35.0 6 3000 203.0 203.0 35.0 Pack Materials-Page 2 IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, modifications, enhancements, improvements, and other changes to its products and services at any time and to discontinue any product or service without notice. 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