KSZ8895MLU
Integrated 5-Port 10/100 Managed Switch
Rev.1.1
General Description
The KSZ8895MLU is a highly-integrated Layer 2managed 5-port switch with an optimized design and
plentiful features, qualified to meet AEC-Q100 standard
for automotive applications. It is designed for costsensitive 10/100Mbps 5-port switch systems with on-chip
termination, lowest power consumption and internal core
power controller. These features will save more system
cost. It has 1.4Gbps high-performance
memory
bandwidth, shared memory based switch fabric with full
non-blocking configuration. It also provides an extensive
feature set such as power management, programmble
rate limit and priority ratio, tag/port-based VLAN, packets
filtering, quality of service (QoS) four-queues
prioritization, management interface, and MIB counters.
Port 5 is a MAC 5 MII interface with PHY mode. The
SW5-MII interface can be connected to a processor with
a MAC MII interface.
The KSZ8895MLU consists of 10/100 PHYs with
patented and enhanced mixed-signal technology, media
access control (MAC) units, a high-speed non-blocking
switch fabric, a dedicated address lookup engine, and an
on-chip frame buffer memory. The KSZ8895MLU
contains five MACs and four intergrated PHYs. All PHYs
support 10/100Base-T/TX.
All registers of MACs and PHYs units can be managed
by the SPI interface or the SMI interface. MIIM registers
of the PHYs can be accessed through the MDC/MDIO
interface. EEPROM can set all control registers for the
unmanaged mode.
Datasheets and support documentation can be found on
feature set such as power management, programmble
rate limit and priority ratio, tag/port-based VLAN, packets
filtering, quality of service (QoS) four-queues
prioritization, management interface, and MIB counters.
Port 5 is a MAC 5 MII interface with PHY mode. The
SW5-MII interface can be connected to a processor with
a MAC MII interface.
The KSZ8895MLU provides multiple CPU control/data
interfaces to effectively address both current and
emerging fast Ethernet applications. Micrel’s web site at:
www.micrel.com.
Functional Diagram
Micrel Inc. • 2180 Fortune Drive • San Jose, CA 95131 • USA • tel +1 (408) 944-0800 • fax + 1 (408) 474-1000 • http://www.micrel.com
October 2011
M9999-100311-1.1
Micrel, Inc.
Features
Advanced Switch Features
IEEE 802.1q VLAN support for up to 128 VLAN groups
(full-range 4096 of VLAN IDs).
Static MAC table supports up to 32 entries.
VLAN ID tag/untag options, per port basis.
IEEE 802.1p/q tag insertion or removal on a per port
basis based on ingress port (egress).
Programmable rate limiting at the ingress and egress on
a per port basis.
Jitter-free per packet based rate-limiting support.
Broadcast storm protection with percentage control
(global and per port basis).
IEEE 802.1d rapid spanning tree protocol RSTP
support.
Tail tag mode (1byte added before FCS) support at Port
5 to inform the processor which ingress port receives
the packet.
1.4Gbps high-performance memory bandwidth and
shared memory-based switch fabric with fully nonblocking configuration.
MII with MAC 5 on Port 5, SW5-MII for MAC 5 MII
interface.
Enable/Disable option for huge frame size up to 2000
bytes per frame.
IGMP v1/v2 snooping (Ipv4) support for multicast packet
filtering.
IPv4/IPv6 QoS support.
Support unknown unicast/multicast address and
unknown VID packet filtering.
Self-address filtering.
Comprehensive Configuration Register Access
Serial management interface (MDC/MDIO) to all PHYs
registers and SMI interface (MDC/MDIO) to all registers.
2
High-speed SPI (up to 25MHz) and I C master Interface
to all internal registers.
I/0 pins strapping and EEPROM to program selective
registers in unmanaged switch mode.
Control registers configurable on the fly (port-priority,
802.1p/d/q, AN…).
QoS/CoS Packet Prioritization Support
Per port, 802.1p and DiffServ-based.
1/2/4-queue QoS prioritization selection.
Programmable weighted fair queuing for ratio control.
Re-mapping of 802.1p priority field per port basis.
Integrated 5-Port 10/100 Ethernet Switch
New generation switch with five MACs and five PHYs
fully compliant with IEEE 802.3u standard.
Non-blocking switch fabric assures fast packet delivery
by utilizing a 1K MAC address lookup table and a storeand-forward architecture.
October 2011
KSZ8895MLU
On-chip 64Kbyte memory for frame buffering (not shared with
1K unicast address table).
Full duplex IEEE 802.3x flow control (PAUSE) with force mode
option.
Half-duplex back pressure flow control.
HP Auto MDI/MDI-X and IEEE Auto crossover support.
Port 5 MAC5 SW5-MII interface supports PHY mode and MAC
mode.
7-wire serial network interface (SNI) support for legacy MAC.
Per port LED Indicators for link, activity, and 10/100 speed.
Register port status support for link, activity, full/half duplex
and 10/100 speed.
On-chip terminations and internal biasing technology for cost
down and lowest power consumption.
Switch Monitoring Features
Port mirroring/monitoring/sniffing: ingress and/or egress traffic
to any port or MII.
MIB counters for fully-compliant statistics gathering 34 MIB
counters per port.
Loop-back support for MAC, PHY, and remote diagnostic of
failure.
Interrupt for the link change on any ports.
Low Power Dissipation
Full-chip hardware power-down.
Full-chip software power-down/per port software power down.
Energy-detect mode support < 100mW full-chip power
consumption when all ports have no activity.
Very-low, full-chip power consumption (<0.5W), without extra
power consumption on transformers.
Dynamic clock-tree shutdown feature.
Voltages: Single 3.3V supply with 3.3V VDDIO and Internal
1.2V LDO controller enabled or external 1.2V LDO solution:
Analog VDDAT 3.3V only
VDDIO support 3.3V, 2.5V and 1.8V
Low 1.2V core power
0.13um CMOS technology.
o
o
Industrial Temperature Range: –40 C to +85 C.
Available in 128-pin LQFP, lead-free package.
Applications
2
In-vehicle Diagnostics (OBD)
High speed software download
Gateway Switch
Head Unit
Rear Seat Entertainment
M9999-100311-1.1
Micrel, Inc.
KSZ8895MLU
Ordering Information
Part Number
KSZ8895MLU
(Automotive Grade)
Temperature Range
Package
Lead Finish/Grade
40C to +85C
128-Pin LQFP
Pb-Free/Automotive
Revision History
Revision
Date
Summary of Changes
1.0
03/16/11
Initial
1.1
09/27/11
Update some descriptions, updates for descriptions of SMI mode and IGMP mode, update register
default values, pins type and some parameters.
October 2011
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KSZ8895MLU
Contents
Pin Configuration .................................................................................................................................................................. 8
Pin Description ...................................................................................................................................................................... 9
Pin for Strap-In Options...................................................................................................................................................... 15
Introduction ......................................................................................................................................................................... 18
Physical Layer Transceiver................................................................................................................................................ 18
100BASE-TX Transmit ..................................................................................................................................................... 18
10BASE-T Transmit .......................................................................................................................................................... 19
10BASE-T Receive ........................................................................................................................................................... 19
MDI/MDI-X Auto Crossover .............................................................................................................................................. 19
Auto-Negotiation ............................................................................................................................................................... 21
On-Chip Termination Resistors ........................................................................................................................................ 22
Internal 1.2V LDO Controller ............................................................................................................................................ 22
Power Management ............................................................................................................................................................ 23
Normal Operation Mode ................................................................................................................................................... 23
Energy Detect Mode ......................................................................................................................................................... 23
Soft Power-Down Mode.................................................................................................................................................... 24
Power-Saving Mode ......................................................................................................................................................... 24
Port-Based Power-Down Mode ........................................................................................................................................ 24
Switch Core....................................................................................................................................................................... 24
Address Look-Up .............................................................................................................................................................. 24
Learning ............................................................................................................................................................................ 24
Migration ........................................................................................................................................................................... 24
Aging................................................................................................................................................................................. 24
Forwarding ........................................................................................................................................................................ 25
Switching Engine .............................................................................................................................................................. 25
Media Access Controller (MAC) Operation ...................................................................................................................... 25
MII Interface Operation ..................................................................................................................................................... 28
Port 5 MAC 5 SW5-MII Interface ...................................................................................................................................... 28
SNI Interface Operation .................................................................................................................................................... 29
Advanced Functionality...................................................................................................................................................... 31
QoS Priority Support......................................................................................................................................................... 31
Port-Based Priority............................................................................................................................................................ 31
802.1p-Based Priority ....................................................................................................................................................... 31
Spanning Tree Support..................................................................................................................................................... 32
Rapid Spanning Tree Support .......................................................................................................................................... 33
Tail Tagging Mode ............................................................................................................................................................ 33
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KSZ8895MLU
IGMP Support ................................................................................................................................................................... 34
Port Mirroring Support ...................................................................................................................................................... 35
VLAN Support ................................................................................................................................................................... 35
Rate Limiting Support ....................................................................................................................................................... 36
Ingress Rate Limit ............................................................................................................................................................. 36
Egress Rate Limit.............................................................................................................................................................. 36
Transmit Queue Ratio Programming ................................................................................................................................ 37
Filtering for Self-Address, Unknown Unicast/Multicast Address and Unknown VID Packet/IP Multicast ........................ 37
Configuration Interface ..................................................................................................................................................... 37
Register Description ........................................................................................................................................................... 43
Global Registers.................................................................................................................................................................. 45
Port Registers...................................................................................................................................................................... 55
Advanced Control Registers.............................................................................................................................................. 65
Data Rate Selection Table in 100BT .................................................................................................................................. 82
Data Rate Selection Table in 10BT .................................................................................................................................... 82
Static MAC Address Table ................................................................................................................................................. 84
VLAN Table .......................................................................................................................................................................... 86
Dynamic MAC Address Table ............................................................................................................................................ 89
Management Information Base (MIB) Counters............................................................................................................... 91
MIIM Registers ..................................................................................................................................................................... 95
Absolute Maximum Ratings(1) ............................................................................................................................................ 99
Operating Ratings(2) ............................................................................................................................................................ 99
Electrical Characteristics(4, 5) .............................................................................................................................................. 99
Timing Diagrams ............................................................................................................................................................... 101
EEPROM Timing............................................................................................................................................................. 101
SNI Timing ...................................................................................................................................................................... 102
MII Timing ....................................................................................................................................................................... 103
SPI Timing ...................................................................................................................................................................... 104
Auto-Negotiation Timing ................................................................................................................................................. 106
Reset Timing................................................................................................................................................................... 107
Reset Circuit Diagram..................................................................................................................................................... 108
Isolation Transformer Selection ...................................................................................................................................... 109
Reference Crystal Selection............................................................................................................................................. 109
Package Information......................................................................................................................................................... 110
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KSZ8895MLU
List of Figures
Figure 1.
Figure 2.
Figure 3.
Figure 4.
Figure 5.
Figure 6.
Figure 7.
Figure 8.
Figure 9.
Figure 10.
Figure 11.
Figure 12.
Figure 13.
Figure 14.
Figure 15.
Figure 16.
Figure 19.
Figure 20.
Figure 21.
Figure 22.
Figure 23.
Figure 24.
Figure 25.
Figure 26.
Typical Straight Cable Connection ..................................................................................................................... 20
Typical Crossover Cable Connection ................................................................................................................. 20
Auto-Negotiation ................................................................................................................................................. 22
Destination Address Look-Up Flow Chart (Stage 1)........................................................................................... 26
Destination Address Resolution Flow Chart (Stage 2) ....................................................................................... 27
802.1p Priority Field Format ............................................................................................................................... 31
Tail Tag Frame Format ....................................................................................................................................... 33
KSZ8895MLU EEPROM Configuration Timing Diagram.................................................................................... 37
SPI Write Data Cycle .......................................................................................................................................... 39
SPI Read Data Cycle .......................................................................................................................................... 39
SPI Multiple Write ............................................................................................................................................... 40
SPI Multiple Read ............................................................................................................................................... 40
EEPROM Interface Input Receive Timing Diagram.......................................................................................... 101
EEPROM Interface Output Transmit Timing Diagram...................................................................................... 101
SNI Input Timing ............................................................................................................................................... 102
SNI Output Timing ............................................................................................................................................ 102
MAC Mode MII Timing Data Received from MII ............................................................................................ 103
MAC Mode MII Timing Parameters .................................................................................................................. 103
SPI Input Timing ............................................................................................................................................... 104
SPI Output Timing............................................................................................................................................. 105
Auto-Negotiation Timing ................................................................................................................................... 106
Reset Timing..................................................................................................................................................... 107
Recommended Reset Circuit............................................................................................................................ 108
Recommended Circuit for Interfacing with CPU/FPGA Reset.......................................................................... 108
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KSZ8895MLU
List of Tables
Table 1.
Table 2.
Table 3.
Table 4.
Table 5.
Table 6.
Table 7.
Table 8.
Table 9.
Table 10.
Table 11.
Table 12.
Table 13.
Table 14.
Table 15.
Table 16.
Table 17.
Table 18.
Table 19.
Table 20.
Table 21.
Table 22.
Table 23.
Table 24.
Table 24.
Table 25.
Table 26.
Table 27.
Table 28.
MDI/MDI-X Pin Definitions ................................................................................................................................... 19
Internal Function Block Status ............................................................................................................................. 23
Switch MAC 5 MII/Turbo MII Signals ................................................................................................................... 29
SNI Signals .......................................................................................................................................................... 30
Tail Tag Rules ...................................................................................................................................................... 34
FID+DA Look-Up in the VLAN Mode ................................................................................................................... 35
FID+SA Look-Up in the VLAN Mode ................................................................................................................... 36
SPI Connections .................................................................................................................................................. 38
MII Management Interface Frame Format ........................................................................................................... 41
Serial Management Interface (SMI) Frame Format ............................................................................................. 41
Format of Static MAC Table for Read (32 Entries) .............................................................................................. 84
Format of Static MAC Table for Writes (32 Entries) ............................................................................................ 85
Format of Static VLAN Table (Support Max 4096 VLAN ID Entries and 128 Active VLANs).............................. 86
VLAN ID and Indirect Registers ........................................................................................................................... 88
Format of Dynamic MAC Address Table (1K Entries) ......................................................................................... 89
Port 1 MIB Counter Indirect Memory Offsets ....................................................................................................... 91
Format of “Per port” MIB Counter ........................................................................................................................ 92
All Port Dropped Packet MIB Counters................................................................................................................ 92
Format of All Dropped Packet MIB Counters....................................................................................................... 93
EEPROM Timing Parameters ............................................................................................................................ 101
SNI Timing Parameters...................................................................................................................................... 102
MAC Mode Timing Parameters.......................................................................................................................... 103
SPI Input Timing Parameters............................................................................................................................. 104
SPI Output Timing Parameters .......................................................................................................................... 105
Auto-Negotiation Timing Parameters................................................................................................................. 106
Reset Timing Parameters .................................................................................................................................. 107
Qualified Magnetic Vendors............................................................................................................................... 109
Qualified Magnetic Vendors............................................................................................................................... 109
Typical Reference Crystal Characteristics ......................................................................................................... 109
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KSZ8895MLU
Pin Configuration
128-Pin LQFP
October 2011
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M9999-100311-1.1
Micrel, Inc.
KSZ8895MLU
Pin Description
Pin Number
Pin Name
Type(1)
Port
Pin Function(2)
1
MDI-XDIS
Ipd
15
2
GNDA
GND
3
VDDAR
P
4
RXP1
I
1
Physical receive signal + (differential).
5
RXM1
I
1
Physical receive signal – (differential).
6
GNDA
GND
7
TXP1
O
1
Physical transmit signal + (differential).
8
TXM1
O
1
Physical transmit signal – (differential).
Disable auto MDI/MDI-X.
PD (default) = normal operation.
PU = disable auto MDI/MDI-X on all ports.
Analog ground.
1.2V analog VDD.
Analog ground.
9
VDDAT
P
10
RXP2
I
2
3.3V analog VDD.
Physical receive signal + (differential).
11
RXM2
I
2
Physical receive signal – (differential).
12
GNDA
GND
Analog ground.
13
TXP2
O
2
Physical transmit signal + (differential).
14
TXM2
O
2
Physical transmit signal – (differential).
15
VDDAR
P
16
GNDA
GND
17
ISET
18
VDDAT
P
19
RXP3
I
3
Physical receive signal + (differential).
20
RXM3
I
3
Physical receive signal - (differential).
21
GNDA
GND
1.2V analog VDD.
Analog ground.
Set physical transmit output current. Pull-down with a
12.4kΩ1% resistor.
3.3V analog VDD.
Analog ground.
22
TXP3
O
3
Physical transmit signal + (differential).
23
TXM3
O
3
Physical transmit signal – (differential).
24
VDDAT
P
25
RXP4
I
3.3V analog VDD.
4
Physical receive signal + (differential).
Notes:
1. P = Power supply.
I = Input.
O = Output.
I/O = Bidirectional.
GND = Ground.
IPU = Input w/internal pull-up.
IPD = Input w/internal pull-down.
IPD/O = Input w/internal pull-down during reset, output pin otherwise.
IPU/O = Input w/internal pull-up during reset, output pin otherwise.
NC = No connect.
2. PU = Strap pin pull-up.
PD = Strap pull-down.
OTRI = Output tristated.
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KSZ8895MLU
Pin Description (Continued)
Pin Number
Pin Name
Type(1)
Port
26
RXM4
I
4
27
GNDA
GND
Pin Function(2)
Physical receive signal - (differential).
Analog ground.
28
TXP4
O
4
Physical transmit signal + (differential).
29
TXM4
O
4
Physical transmit signal – (differential).
30
GNDA
GND
31
VDDAR
P
32
RXP5
I
5
Reserved for MLU. No connect.
33
RXM5
I
5
Reserved for MLU. No connect.
34
GNDA
GND
Analog ground.
1.2V analog VDD.
Analog ground.
35
TXP5
O
5
Reserved for MLU. No connect.
36
TXM5
O
5
Reserved for MLU. No connect.
37
VDDAT
P
38
NC
NC
No connect.
39
NC
NC
No connect.
40
NC
NC
No connect.
41
NC
NC
No connect.
42
NC
NC
No connect.
43
NC
NC
No connect.
44
NC
NC
No connect.
45
NC
NC
No connect.
46
NC
NC
No connect.
47
PWRDN_N
Ipu
Full-chip power down. Active low.
48
INTR_N
Opu
Interrupt. This pin is Open-Drain output pin.
49
GNDD
GND
Digital ground.
3.3V analog VDD.
50
VDDC
P
51
PMTXEN
Ipd
5
Reserved for MLU. No connect.
52
PMTXD3
Ipd
5
Reserved for MLU. No connect.
53
PMTXD2
Ipd
5
Reserved for MLU. No connect.
54
PMTXD1
Ipd
5
Reserved for MLU. No connect.
55
PMTXD0
Ipd
5
Reserved for MLU. No connect.
56
PMTXER
Ipd
5
Reserved for MLU. No connect.
57
PMTXC
I/O
5
Reserved for MLU. No connect.
58
GNDD
GND
59
VDDIO
P
60
PMRXC
I/O
5
Reserved for MLU. No connect.
61
PMRXDV
Ipd/O
5
62
PMRXD3
Ipd/O
5
Reserved for MLU. No connect.
Reserved for MLU.
Strap option:
PD (default) = enable flow control.
PU = disable flow control.
October 2011
1.2V digital core VDD.
Digital ground.
3.3V, 2.5V or 1.8V digital VDD for digital I/O circuitry.
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M9999-100311-1.1
Micrel, Inc.
KSZ8895MLU
Pin Description (Continued)
Pin Number
Pin Name
Type(1)
Port
63
PMRXD2
Ipd/O
5
64
PMRXD1
Ipd/O
5
65
PMRXD0
Ipd/O
5
66
PMRXER
Ipd/O
5
67
PCRS
Ipd/O
5
68
PCOL
Ipd/O
5
69
SMTXEN
Ipd
Pin Function(2)
Reserved for MLU.
Strap option:
PD (default) = disable back pressure.
PU = enable back pressure.
Reserved for MLU.
Strap option:
PD (default) = drop excessive collision packets.
PU = does not drop excessive collision packets.
Reserved for MLU.
Strap option:
PD (default) = disable aggressive back-off algorithm in half-duplex mode.
PU = enable for performance enhancement.
Reserved for MLU.
Strap option:
PD (default) = 1522/1518 bytes;
PU = packet size up to 1536 bytes.
Reserved for MLU.
Strap option for port 4 only.
PD (default) = force half-duplex if auto-negotiation is disabled or fails.
PU = force full-duplex if auto negotiation is disabled or fails. Refer to Register
76.
Reserved for MLU.
Strap option for port 4 only.
PD (default) = no force flow control, normal operation.
PU = force flow control. Refer to Register 66.
Port 5 Switch MII transmit enable.
70
SMTXD3
Ipd
Port 5 Switch MII transmit bit 3.
71
SMTXD2
Ipd
Port 5 Switch MII transmit bit 2.
72
SMTXD1
Ipd
Port 5 Switch MII transmit bit 1.
73
SMTXD0
Ipd
Port 5 Switch MII transmit bit 0.
74
SMTXER
Ipd
75
SMTXC
I/O
76
GNDD
GND
Port 5 Switch MII transmit error.
Port 5 Switch MII transmit clock:
Input: SW5-MII MAC mode.
Output: SW5-MII PHY modes.
Digital ground.
77
VDDIO
P
78
SMRXC
I/O
79
SMRXDV
Ipd/O
80
SMRXD3
Ipd/O
October 2011
3.3V, 2.5V or 1.8V digital VDD for digital I/O circuitry.
Port 5 Switch MII receive clock:
Input: SW5-MII MAC mode.
Output: SW5-MII PHY mode.
Switch MII receive data valid.
Port 5 Switch MII receive bit 3.
Strap option:
PD (default) = Disable Switch SW5-MII full-duplex flow control
PU = Enable Switch SW5-MII full-duplex flow control.
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Micrel, Inc.
KSZ8895MLU
Pin Description (Continued)
Pin Number
Pin Name
Type(1)
81
SMRXD2
Ipd/O
82
SMRXD1
Ipd/O
83
SMRXD0
Ipd/O
84
SCOL
Ipd/O
85
SCRS
Ipd/O
86
SCONF1
Ipd
Port
Pin Function(2)
Port 5 Switch MII receive bit 2.
Strap option:
PD (default) = Switch SW5-MII in full-duplex mode;
PU = Switch SW5-MII in half-duplex mode.
Port 5 Switch MII receive bit 1.
Strap option:
PD (default) =Port 5 Switch SW5-MII in 100Mbps mode; SW5-TMII in
200Mbps mode.
PU = Switch SW5-MII in 10Mbps mode.
Port 5 Switch MII receive bit 0.
Strap option: LED mode
PD (default) = mode 0; PU = mode 1. See “Register 11.”
Mode 0, link at
100/Full LEDx[2,1,0]=0,0,0
100/Half LEDx[2,1,0]=0,1,0
10/Full LEDx[2,1,0]=0,0,1
10/Half LEDx[2,1,0]=0,1,1
Mode 1, link at
100/Full LEDx[2,1,0]=0,1,0
100/Half LEDx[2,1,0]=0,1,1
10/Full LEDx[2,1,0]=1,0,0
10/Half LEDx[2,1,0]=1,0,1
Mode 0
Mode 1
LEDX_2
Lnk/Act
100Lnk/Act
LEDX_1
Fulld/Col
10Lnk/Act
LEDX_0
Speed
Full duplex
Port 5 Switch MII collision detect:
Input: SW5-MII MAC modes.
Output: SW5-MII PHY modes.
Port 5 Switch MII modes carrier sense:
Input: SW5-MII MAC modes.
Output: SW5-MII PHY modes.
Pin 91,86,87 are dual MII configuration pins for the Port5 MAC5 MII. SW5-MII
supports both MAC mode and PHY modes.
Pin#: (91, 86, 87)
Port5 Switch MAC5 SW5- MII
000
87
SCONF0
Ipd
88
GNDD
GND
89
VDDC
P
90
LED5-2
Ipd/O
October 2011
Disable, Otri
001
PHY Mode MII
010
MAC Mode MII
011
PHY Mode SNI
100
Disable (Default)
101
PHY Mode MII
110
MAC Mode MII
111
PHY Mode SNI
Dual MII configuration pin. See pin 86 descriptions.
Digital ground.
5
1.2V digital core VDD.
Reserved for MLU
Strap option: aging setup. See “Aging” section.
PU (default) = aging enable
PD = aging disable.
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KSZ8895MLU
Pin Description (Continued)
Pin Number
Pin Name
Type(1)
Port
91
LED5-1
Ipu/O
5
92
LED5-0
Ipu/O
5
93
LED4-2
Ipu/O
4
94
LED4-1
Ipu/O
4
95
LED4-0
Ipu/O
4
96
LED3-2
Ipu/O
3
97
LED3-1
Ipu/O
3
98
LED3-0
Ipu/O
3
99
GNDD
GND
100
VDDIO
P
101
LED2-2
Ipu/O
2
102
LED2-1
Ipu/O
2
103
LED2-0
Ipu/O
2
104
LED1-2
Ipu/O
1
105
LED1-1
Ipu/O
1
106
LED1-0
Ipu/O
1
107
MDC
Ipu
All
108
MDIO
Ipu/O
All
109
SPIQ
Ipu/O
All
110
SPIC/SCL
Ipu/O
All
October 2011
Pin Function(2)
Reserved for MLU
Strap option:
PU (default): enable PHY[5] MII I/F.
PD: tristate and disable all PHY[5] MII output. (Design should pull this pin
down as default for MLU.
Reserved for MLU
Strap option for port 4 only.
PU (default) = Enable auto-negotiation.
PD = Disable auto-negotiation. Strap to register76 bit[7].
LED indicator 2.
LED indicator 1.
LED indicator 0.
Strap option:
PU (default) = Normal mode.
PD = Energy Detection mode (EDPD mode).
Strap to register 14 bits[4:3]
LED indicator 2.
LED indicator 1.
LED indicator 0.
Strap option:
PU (default) = Select I/O drive strength (8mA);
PD = Select I/O drive strength (12mA).
Strap to register132 bit[7-6].
Digital ground.
3.3V, 2.5V or 1.8V digital VDD for digital I/O circuitry.
LED indicator 2.
LED indicator 1.
Strap option: for port 3 only.
PU (default) = Enable auto-negotiation.
PD = Disable auto-negotiation. Strap to register60 bit[7].
LED indicator 0.
LED indicator 2.
LED indicator 1.
Strap option: for port 3 only.
PU (default) = no force flow control, normal operation.
PD = force flow control. Strap to register60 bit[4].
LED indicator 0.
Strap option for port 3 only.
PU (default) = force half-duplex if auto-negotiation is disabled or fails.
PD = force full-duplex if auto negotiation is disabled or fails.
Strap to register60 bit[5].
Switch MII management data clock. Or SMI interface clock.
Switch MII management data I/O. Or SMI interface data I/O.
Features internal pull down to define pin state when not driven.
Need an external pull-up when driven.
SPI serial data output in SPI slave mode.
SPI slave mode: clock input
(1) Input clock up to 25MHz in SPI slave mode,
2
(2) output clock at 61kHz in I C master mode. See “Pin 113.”
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KSZ8895MLU
Pin Description (Continued)
Pin Number
Pin Name
Type(1)
Port
111
SSPID/SDA
Ipu/O
All
112
SPIS_N
Ipu
All
113
PS1
Ipd
Pin Function(2)
SPI slave mode: serial data input.
(1) Serial data input in SPI slave mode;
2
(2) Serial data input/output in I C master mode. See “Pin 113.”
SPI slave mode: chip select (active low).
(1) SPI data transfer start in SPI slave mode. When SPIS_N is high, the
KSZ8895MLU is deselected and SPIQ is held in high impedance state, a
high-to-low transition to initiate the SPI data transfer.
2
(2) not used in I C master mode.
Serial bus configuration pin.
For this case, if the EEPROM is not present, the KSZ8895MLU will start itself
with the PS[1.0] = 00 default register values.
Pin Configuration
Serial Bus Configuration
PS[1.0]=00
I2C Master Mode for EEPROM
PS[1.0]=01
SMI Interface Mode
PS[1.0]=10
SPI Slave Mode for CPU Interface
PS[1.0]=11
Factory Test Mode (BIST)
114
PS0
Ipd
Serial bus configuration pin. See “Pin 113.”
115
RST_N
Ipu
Reset the KSZ8895MLU device. Active low.
116
GNDD
GND
117
VDDC
P
118
TESTEN
Ipd
NC for normal operation. Factory test pin.
119
SCANEN
Ipd
NC for normal operation. Factory test pin.
120
NC
NC
No connect.
121
X1
I
25MHz crystal clock connection/or 3.3V Oscillator input. Crystal/Oscillator
should be ±50ppm tolerance.
122
X2
O
25MHz crystal clock connection.
123
NC
NC
No connect.
124
NC
NC
125
LDO_O
P
126
IN_PWR_SEL
Ipd
No connect.
When pin126 is pull-up, the Internal 1.2V LDO controller is enabled and
creates 1.2V output with using an external FET.
When pin126 is pull-down (default), the pin 125 is tristated.
Pull-up to enable LDO_O of pin 125. Pull-down to disable LDO_0.
127
GNDA
GND
128
TEST2
NC
Digital ground.
1.2V digital core VDD.
Analog ground.
NC for normal operation. Factory test pin.
Notes:
1.
P = Power supply.
I = Input.
O = Output.
I/O = Bidirectional.
GND = Ground.
Ipu = Input w/internal pull-up.
Ipd = Input w/internal pull-down.
Ipd/O = Input w/internal pull-down during reset, output pin otherwise.
Ipu/O = Input w/internal pull-up during reset, output pin otherwise.
NC = No connect.
2.
PU = Strap pin pull-up.
PD = Strap pull-down.
OTRI = Output tristated.
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KSZ8895MLU
Pin for Strap-In Options
The KSZ8895MLU can function as a managed switch or unmanaged switch. If no EEPROM or micro-controller exists, the
KSZ8895MLU will operate from its default setting. The strap-in option pins can be configures by external pull-up/down
resistors and take the effect after power-down reset or warm reset, the functions are described in the following tables.
Pin Number
Pin Name
PU/PD(1)
1
MDI-XDIS
Ipd
62
PMRXD3
Ipd/O
63
PMRXD2
Ipd/O
64
PMRXD1
Ipd/O
65
PMRXD0
Ipd/O
66
PMRXER
Ipd/O
67
PCRS
Ipd/O
68
PCOL
Ipd/O
80
SMRXD3
Ipd/O
81
SMRXD2
Ipd/O
82
SMRXD1
Ipd/O
83
SMRXD0
Ipd/O
October 2011
Description(1)
Disable auto MDI/MDI-X.
PD = (default) = normal operation
PU = disable auto MDI/MDI-X on all ports.
Strap option:
PD (default) = enable flow control;
PU = disable flow control.
Strap option:
PD (default) = disable back pressure;
PU = enable back pressure.
Strap option:
PD (default) = drop excessive collision packets;
PU = does not drop excessive collision packets.
Strap option:
PD (default) = disable aggressive back-off algorithm in half-duplex mode;
PU = enable for performance enhancement.
Strap option:
PD (default) = 1522/1518 bytes;
PU = packet size up to 1536 bytes.
Strap option for port 4 only.
PD (default) = force half-duplex if auto-negotiation is disabled or fails.
PU = force full-duplex if auto-negotiation is disabled or fails. Refer to register 76.
Strap option for port 4 only.
PD (default) = no force flow control.
PU = force flow control. Refer to register 66.
Switch MII receive bit 3. Strap option:
PD (default) = disable switch SW5-MII full-duplex flow control;
PU = enable switch SW5-MII full-duplex flow control.
Switch MII receive bit 2. Strap option:
PD (default) = switch SW5-MII in full-duplex mode;
PU = switch SW5-MII in half-duplex mode.
Switch MII receive bit 1. Strap option:
PD (default) = switch SW5-MII in 100Mbps mode and SW5-TMII in 200Mbps
PU = switch MII in 10Mbps mode.
Switch MII receive bit 0. Strap option: LED mode PD (default) = mode 0; PU = mode 1.
See “Register 11.”
Mode 0
Mode 1
LEDX_2
Lnk/Act
100Lnk/Act
LEDX_1
Fulld/Col
10Lnk/Act
LEDX_0
Speed
Fulld
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KSZ8895MLU
Pin for Strap-In Options (Continued)
Pin Number
Pin Name
PU/PD(1)
86
SCONF1
Ipd
87
SCONF0
Ipd
Description(1)
Pins 91, 86, 87 are dual MII configuration pins for the Port5 MAC5 MII. SW5-MII supports
both MAC mode and PHY modes.
Pin#: (91, 86, 87)
Port5 Switch MAC5 SW5- MII
000
Disable, Otri
001
PHY Mode MII
010
MAC Mode MII
011
PHY Mode SNI
100
Disable
101
PHY Mode MII
110
MAC Mode MII
111
PHY Mode SNI
Dual MII configuration pin. See pin 86 descriptions.
Strap option: Aging setup. See “Aging” section
PU (default) = aging enable;
PD = aging disable.
Strap option:
PU (default): enable PHY[5] MII I/F.
PD: tristate all PHY[5] MII output. See “Pin 86 SCONF1.”
Strap option for port 4 only.
PU (default) = Enable auto-negotiation.
PD = Disable auto-negotiation. Strap to register76 bit[7]
LED indicator 0.
Strap option:
PU (default) = Normal mode.
PD = Energy Detection mode (EDPD mode).
Strap to register 14 bits[4:3]
LED3 indicator 0.
Strap option:
PU (default) = Select I/O current drive strength (8mA);
PD = Select I/O current drive strength (12mA).
Strap to register132 bit[7:6].
90
LED5-2
Ipu/O
91
LED5-1
Ipu/O
92
LED5-0
Ipu/O
95
LED4-0
Ipu/O
98
LED3-0
Ipu/O
101
LED2-2
Ipu/O
LED2 indicator 2.
102
LED2-1
Ipu/O
LED2 indicator 1.
Strap option for port 3 only.
PU (default) = Enable auto-negotiation.
PD = Disable auto-negotiation.
Strap to register60 bit[7]
103
LED2-0
Ipu/O
LED2 indicator 0.
104
LED1-2
Ipu/O
LED1 indicator 2.
Ipu/O
LED1 indicator 1.
Strap option for port 3 only.
PU (default) = no force flow control, normal operation.
PD = force flow control. Strap to register50 bit[4]
105
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KSZ8895MLU
Pin for Strap-In Options (Continued)
Pin Number
106
Pin Name
LED1-0
PU/PD(2)
Ipu/O
Description(2)
LED1 indicator 0.
Strap option for port 3 only.
PU (default) = force half-duplex if auto-negotiation is disabled or fails.
PD = force full-duplex if auto negotiation is disabled or fails.
Strap to register60 bit[5].
Serial bus configuration pin. For this case, if the EEPROM is not present, the
KSZ8895MLU will start itself with the PS[1:0] =00 default register values.
Pin Configuration
113
PS1
Ipd
Serial Bus Configuration
2
PS[1:0]=00
I C Master Mode for EEPROM
PS[1:0]=01
SMI Interface Mode
PS[1:0]=10
SPI Slave Mode for CPU Interface
PS[1:0]=11
Factory Test Mode (BIST)
114
PS0
Ipd
Serial bus configuration pin. See “Pin 113.”
128
TEST2
NC
NC for normal operation. Factory test pin.
Notes:
NC = No connect.
Ipd = Input w/internal pull-down.
Ipd/O = Input w/internal pull-down during reset, output pin otherwise.
Ipu/O = Input w/internal pull-up during reset, output pin otherwise.
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KSZ8895MLU
Introduction
The KSZ8895MLU contains four 10/100 physical layer transceivers and five media access control (MAC) units with an
integrated Layer 2 managed switch. The device runs in two modes. The first mode is as a 4-port integrated switch. The
second is as a 4-port switch with the fifth MAC. In this mode, access to the fifth MAC is provided through a media
independent interface (MII).
The KSZ8895MLU has the flexibility to reside in a managed or unmanaged design. In a managed design, a host
processor has complete control of the KSZ8895MLU via the SPI bus, or via the MDC/MDIO interface with SMI mode. An
unmanaged design is achieved through I/O strapping or EEPROM programming at system reset time.
On the media side, the KSZ8895MLU supports IEEE 802.3 10BASE-T, 100BASE-TX on all ports with Auto MDI/MDIX.
The KSZ8895MLU can be used as fully-managed 4-port stand alone switch or hook up to microprocessor by its SW-MII
interface for an application solution.
Physical signal transmission and reception are enhanced through the use of patented analog circuitry that makes the
design more efficient and allows for lower power consumption and smaller chip die size.
There are a number of major enhancements from the KS8995MA to the KSZ8895MLU. These include: more host
interface options, four queues prioritization, tag as well as port based VLAN, rapid spanning tree support, IGMP snooping
support, port mirroring support and more flexible rate limiting and filtering functionality.
Physical Layer Transceiver
100BASE-TX Transmit
The 100BASE-TX transmit function performs parallel-to-serial conversion, 4B/5B coding, scrambling, NRZ-to-NRZI
conversion, MLT3 encoding and transmission. The circuit starts with a parallel-to-serial conversion, which converts the MII
data from the MAC into a 125MHz serial bit stream. The data and control stream is then converted into 4B/5B coding
followed by a scrambler. The serialized data is further converted from NRZ-to-NRZI format, and then transmitted in MLT3
current output. The output current is set by an external 1% 12.4kΩ resistor for the 1:1 transformer ratio. It has a typical
rise/fall time of 4ns and complies with the ANSI TP-PMD standard regarding amplitude balance, overshoot, and timing
jitter. The wave-shaped 10BASE-T output is also incorporated into the 100BASE-TX transmitter.
100BASE-TX Receive
The 100BASE-TX receiver function performs adaptive equalization, DC restoration, MLT3-to-NRZI conversion, data and
clock recovery, NRZI-to-NRZ conversion, de-scrambling, 4B/5B decoding, and serial-to-parallel conversion. The receiving
side starts with the equalization filter to compensate for inter-symbol interference (ISI) over the twisted pair cable. Since
the amplitude loss and phase distortion is a function of the length of the cable, the equalizer has to adjust its
characteristics to optimize the performance. In this design, the variable equalizer will make an initial estimation based on
comparisons of incoming signal strength against some known cable characteristics, then tunes itself for optimization. This
is an ongoing process and can self-adjust against environmental changes such as temperature variations.
The equalized signal then goes through a DC restoration and data conversion block. The DC restoration circuit is used to
compensate for the effect of baseline wander and improve the dynamic range. The differential data conversion circuit
converts the MLT3 format back to NRZI. The slicing threshold is also adaptive.
The clock recovery circuit extracts the 125MHz clock from the edges of the NRZI signal. This recovered clock is then used
to convert the NRZI signal into the NRZ format. The signal is then sent through the de-scrambler followed by the 4B/5B
decoder. Finally, the NRZ serial data is converted to the MII format and provided as the input data to the MAC.
PLL Clock Synthesizer
The KSZ8895MLU generates 125MHz, 83MHz, 41MHz, 25MHz and 10MHz clocks for system timing. Internal clocks are
generated from an external 25MHz crystal or oscillator.
Scrambler/De-Scrambler (100BASE-TX Only)
The purpose of the scrambler is to spread the power spectrum of the signal in order to reduce EMI and baseline wander.
The data is scrambled through the use of an 11-bit wide linear feedback shift register (LFSR). This can generate a 2047bit non-repetitive sequence. The receiver will then de-scramble the incoming data stream with the same sequence at the
transmitter.
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KSZ8895MLU
10BASE-T Transmit
The output 10BASE-T driver is incorporated into the 100BASE-T driver to allow transmission with the same magnetics.
They are internally wave-shaped and pre-emphasized into outputs with typical 2.3V amplitude. The harmonic contents are
at least 27dB below the fundamental when driven by an all-ones Manchester-encoded signal.
10BASE-T Receive
On the receive side, input buffer and level detecting squelch circuits are employed. A differential input receiver circuit and
a PLL perform the decoding function. The Manchester-encoded data stream is separated into clock signal and NRZ data.
A squelch circuit rejects signals with levels less than 400mV or with short pulse widths in order to prevent noises at the
RXP or RXM input from falsely triggering the decoder. When the input exceeds the squelch limit, the PLL locks onto the
incoming signal and the KSZ8895MLU decodes a data frame. The receiver clock is maintained active during idle periods
in between data reception.
MDI/MDI-X Auto Crossover
To eliminate the need for crossover cables between similar devices, the KSZ8895MLU supports HP Auto MDI/MDI-X and
IEEE 802.3u standard MDI/MDI-X auto crossover. HP Auto MDI/MDI-X is the default.
The auto-sense function detects remote transmit and receive pairs and correctly assigns transmit and receive pairs for the
KSZ8895MLU device. This feature is extremely useful when end users are unaware of cable types, and also, saves on an
additional uplink configuration connection. The auto-crossover feature can be disabled through the port control registers,
or MIIM PHY registers. The IEEE 802.3u standard MDI and MDI-X definitions are highlighted in Table 1:
MDI
MDI-X
RJ-45 Pins
Signals
RJ-45 Pins
Signals
1
TD+
1
RD+
2
TD-
2
RD-
3
RD+
3
TD+
6
RD-
6
TD-
Table 1. MDI/MDI-X Pin Definitions
Straight Cable
A straight cable connects an MDI device to an MDI-X device, or an MDI-X device to an MDI device. Figure 1 depicts a
typical straight cable connection between a NIC card (MDI) and a switch, or hub (MDI-X).
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KSZ8895MLU
Figure 1. Typical Straight Cable Connection
Crossover Cable
A crossover cable connects an MDI device to another MDI device, or an MDI-X device to another MDI-X device. Figure 2
shows a typical crossover cable connection between two switches or hubs (two MDI-X devices).
Figure 2. Typical Crossover Cable Connection
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KSZ8895MLU
Auto-Negotiation
The KSZ8895MLU conforms to the auto-negotiation protocol as described by the 802.3 committee. Auto-negotiation
allows unshielded twisted pair (UTP) link partners to select the highest common mode of operation. Link partners
advertise their capabilities to each other, and then compare their own capabilities with those they received from their link
partners. The highest speed and duplex setting that is common to the two link partners is selected as the mode of
operation.
The following list shows the speed and duplex operation mode from highest to lowest.
Highest:
100Base-TX, full-duplex
High:
100Base-TX, half-duplex
Low:
10Base-T, full-duplex
Lowest:
10Base-T, half-duplex
If auto-negotiation is not supported or the KSZ8895MLU link partner is forced to bypass auto-negotiation, the
KSZ8895MLU sets its operating mode by observing the signal at its receiver. This is known as parallel detection, and
allows the KSZ8895MLU to establish link by listening for a fixed signal protocol in the absence of auto-negotiation
advertisement protocol. The auto-negotiation link-up process is shown in Figure 3.
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KSZ8895MLU
Figure 3. Auto-Negotiation
On-Chip Termination Resistors
The KSZ8895MLU reduces board cost and simplifies board layout by using on-chip termination resistors for all ports and
the RX/TX differential pairs without the external termination resistors. The solution of the on chip termination and internal
biasing will save about 50% power consumption compare with using external biasing and termination resistors, and the
transformer will not consume power any more.
Internal 1.2V LDO Controller
The KSZ8895MLU reduces board cost and simplifies board layout by integrating an internal 1.2V LDO controller to drive a
low cost MOSFET to supply the 1.2V core power voltage for a single 3.3V power supply solution.
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KSZ8895MLU
Power Management
The KSZ8895MLU supports a full-chip hardware power-down mode. When PWRDN Pin 47 (Pin PWRDN =0) is activated
low, the entire chip is powered down. If this pin is de-asserted, the chip will be internally reset.
The KSZ8895MLU can also use multiple power level of 3.3V, 2.5V or 1.8V for VDDIO to support different I/O voltage.
The KSZ8895MLU supports enhanced power management feature in low power state with energy detection to ensure
low-power dissipation during device idle periods. There are five operation modes under the power management function
which is controlled by the register 14 bit [4:3] and the port register control 13 bit 3 as shown below:
Register 14 bit [4:3] = 00 normal operation mode
Register 14 bit [4:3] = 01 energy detect mode
Register 14 bit [4:3] = 10 soft power down mode
Register 14 bit [4:3] = 11 power saving mode
Port register 29, 45, 61, 77, 93 Control 13 bit 3 =1 are for the port based power-down mode
Table 2 indicates all internal function blocks status under four different power management operation modes.
Power Management Operation Modes
KSZ8895MLU
Function Blocks
Normal Mode
Power-Saving Mode
Energy Detect Mode
Soft Power-Down Mode
Internal PLL Clock
Enabled
Enabled
Disabled
Disabled
Tx/Rx PHY
Enabled
Rx unused block disabled
Energy detect at Rx
Disabled
MAC
Enabled
Enabled
Disabled
Disabled
Host Interface
Enabled
Enabled
Disabled
Disabled
Table 2. Internal Function Block Status
Normal Operation Mode
This is the default setting bit [4:3] =00 in register 14 after the chip power-up or hardware reset. When KSZ8895MLU is in
this normal operation mode, all PLL clocks are running, PHY and MAC are on and the host interface is ready for CPU
read or write.
During the normal operation mode, the host CPU can set the bit [4:3] in register 14 to transit the current normal operation
mode to any one of the other three power management operation modes.
Energy Detect Mode
The energy detect mode provides a mechanism to save more power than in the normal operation mode when the
KSZ8895MLU is not connected to an active link partner. In this mode, the device will save more power based on the
regular less power consumption. If the cable is not plugged, the KSZ8895MLU can automatically enter to a low power
state, otherwise known as the energy detect mode. In this mode, KSZ8895MLU will keep transmitting 120ns width pulses
at 1 pulse/s rate. Once activity resumes due to plugging a cable or attempting by the far end to establish link, the
KSZ8895MLU can automatically power up to normal power state in energy detect mode.
Energy detect mode consists of two states, normal power state and low power state. While in low power state, the
KSZ8895MLU reduces power consumption by disabling all circuitry except the energy detect circuitry of the receiver. The
energy detect mode is entered by setting bit [4:3] =01 in register 14. When the KSZ8895MLU is in this mode, it will
monitor the cable energy. If there is no energy on the cable for a time longer than pre-configured value at bit [7:0] GoSleep time in register 15, KSZ8895MLU will go into a low power state. When KSZ8895MLU is in low power state, it will
keep monitoring the cable energy. Once the energy is detected from the cable, KSZ8895MLU will enter normal power
state. When KSZ8895MLU is at normal power state, it is able to transmit or receive packet from the cable.
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KSZ8895MLU
Soft Power-Down Mode
The soft power-down mode is entered by setting bit [4:3] =10 in register 14. When KSZ8895MLU is in this mode, all PLL
clocks are disabled, also all of PHYs and the MACs are off. Any dummy host access will wake-up this device from current
soft power-down mode to normal operation mode and internal reset will be issued to make all internal registers go to the
default values.
Power-Saving Mode
The power saving mode is entered when auto-negotiation mode is enabled, cable is disconnected, and by setting bit [4:3]
=11 in register 14. When KSZ8895MLU is in this mode, all PLL clocks are enabled, MAC is on, all internal registers value
will not change, and host interface is ready for CPU read or write. In this mode, it mainly controls the PHY transceiver on
or off based on line status to achieve power saving. The PHY remains transmitting and only turns off the unused receiver
block. Once activity resumes due to plugging a cable or attempting by the far end to establish link, the KSZ8895MLU can
automatically enabled the PHY power up to normal power state from power saving mode.
During this power-saving mode, the host CPU can set bit [4:3] in register 14 to transit the current power saving mode to
any one of the other three power management operation modes.
Port-Based Power-Down Mode
In addition, the KSZ8895MLU features a per-port power down mode. To save power, a PHY port that is not in use can be
powered down via the port registers control 13 bit3, or MIIM PHY registers 0 bit11.
Switch Core
Address Look-Up
The internal look-up table stores MAC addresses and their associated information. It contains a 1K unicast address table
plus switching information. The KSZ8895MLU is guaranteed to learn 1K addresses and distinguishes itself from a hashbased look-up table, which depending on the operating environment and probabilities, may not guarantee the absolute
number of addresses it can learn.
Learning
The internal look-up engine updates its table with a new entry if the following conditions are met:
The received packet’s source address (SA) does not exist in the look-up table.
The received packet is good; the packet has no receiving errors and is of legal length.
The look-up engine inserts the qualified SA into the table, along with the port number and time stamp. If the table is full,
the last entry of the table is deleted first to make room for the new entry.
Migration
The internal look-up engine also monitors whether a station is moved. If this occurs, it updates the table accordingly.
Migration happens when the following conditions are met:
The received packet’s SA is in the table but the associated source port information is different.
The received packet is good; the packet has no receiving errors and is of legal length.
The look-up engine will update the existing record in the table with the new source port information.
Aging
The look-up engine will update the time stamp information of a record whenever the corresponding SA appears. The time
stamp is used in the aging process. If a record is not updated for a period of time, the look-up engine will remove the
record from the table. The look-up engine constantly performs the aging process and will continuously remove aging
records. The aging period is 300 75 seconds. This feature can be enabled or disabled through Register 3 or by external
pull-up or pull-down resistors on LED[5][2]. See “Register 3” section.
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KSZ8895MLU
Forwarding
The KSZ8895MLU will forward packets using an algorithm that is depicted in the following flowcharts. Figure 6 shows
stage one of the forwarding algorithm where the search engine looks up the VLAN ID, static table, and dynamic table for
the destination address, and comes up with “port to forward 1” (PTF1). PTF1 is then further modified by the spanning tree,
IGMP snooping, port mirroring, and port VLAN processes to come up with “port to forward 2” (PTF2), as shown in Figure
7. This is where the packet will be sent.
KSZ8895MLU Will Not Forward the Following Packets:
Error packets. These include framing errors, FCS errors, alignment errors, and illegal size packet errors.
802.3x pause frames. The KSZ8895MLU will intercept these packets and perform the appropriate actions.
“Local” packets. Based on destination address (DA) look-up. If the destination port from the look-up table matches the
port where the packet was from, the packet is defined as “local.”
Switching Engine
The KSZ8895MLU features a high-performance switching engine to move data to and from the MAC’s, packet buffers. It
operates in store and forward mode, while the efficient switching mechanism reduces overall latency. The KSZ8895MLU
has a 64kB internal frame buffer. This resource is shared between all five ports. There are a total of 512 buffers available.
Each buffer is sized at 128B.
Media Access Controller (MAC) Operation
The KSZ8895MLU strictly abides by IEEE 802.3 standards to maximize compatibility.
Inter-Packet Gap (IPG)
If a frame is successfully transmitted, the 96-bit time IPG is measured between the two consecutive MTXEN. If the current
packet is experiencing collision, the 96-bit time IPG is measured from MCRS and the next MTXEN.
Backoff Algorithm
The KSZ8895MLU implements the IEEE Std. 802.3 binary exponential back-off algorithm, and optional “aggressive mode”
back off. After 16 collisions, the packet will be optionally dropped depending on the chip configuration in Register 3. See
“Register 3.”
Late Collision
If a transmit packet experiences collisions after 512-bit times of the transmission, the packet will be dropped.
Illegal Frames
The KSZ8895MLU discards frames less than 64 bytes and can be programmed to accept frames up to 1536 bytes in
Register 4. For special applications, the KSZ8895MLU can also be programmed to accept frames up to 1916 bytes in
Register 4. Since the KSZ8895MLU supports VLAN tags, the maximum sizing is adjusted when these tags are present.
Flow Control
The KSZ8895MLU supports standard 802.3x flow control frames on both transmit and receive sides.
On the receive side, if the KSZ8895MLU receives a pause control frame, the KSZ8895MLU will not transmit the next
normal frame until the timer, specified in the pause control frame, expires. If another pause frame is received before the
current timer expires, the timer will be updated with the new value in the second pause frame. During this period (being
flow controlled), only flow control packets from the KSZ8895MLU will be transmitted.
On the transmit side, the KSZ8895MLU has intelligent and efficient ways to determine when to invoke flow control. The
flow control is based on availability of the system resources, including available buffers, available transmit queues and
available receive queues.
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The KSZ8895MLU flow controls a port that has just received a packet if the destination port resource is busy. The
KSZ8895MLU issues a flow control frame (XOFF), containing the maximum pause time defined in IEEE standard 802.3x.
Once the resource is freed up, the KSZ8895MLU sends out the other flow control frame (XON) with zero pause time to
turn off the flow control (turn on transmission to the port). A hysteresis feature is also provided to prevent over-activation
and deactivation of the flow control mechanism.
The KSZ8895MLU flow controls all ports if the receive queue becomes full.
Figure 4. Destination Address Look-Up Flow Chart (Stage 1)
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Figure 5. Destination Address Resolution Flow Chart (Stage 2)
The KSZ8895MLU will not forward the following packets:
1.
Error packets
2.
These include framing errors, Frame Check Sequence (FCS) errors, alignment errors, and illegal size packet
errors.
IEEE802.3x PAUSE frames
3.
KSZ8895MLU intercepts these packets and performs full duplex flow control accordingly.
"Local" packets
Based on destination address (DA) lookup, if the destination port from the lookup table matches the port from
which the packet originated, the packet is defined as "local."
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Half-Duplex Back Pressure
The KSZ8895MLU also provides a half-duplex back pressure option (note: this is not in IEEE 802.3 standards). The
activation and deactivation conditions are the same as the ones given for full-duplex mode. If back pressure is required,
the KSZ8895MLU sends preambles to defer the other station's transmission (carrier sense deference). To avoid jabber
and excessive deference as defined in IEEE 802.3 standard, after a certain period of time, the KSZ8895MLU discontinues
carrier sense but raises it quickly after it drops packets to inhibit other transmissions. This short silent time (no carrier
sense) is to prevent other stations from sending out packets and keeps other stations in a carrier sense deferred state. If
the port has packets to send during a back pressure situation, the carrier-sense-type back pressure is interrupted and
those packets are transmitted instead. If there areno more packets to send, carrier-sense-type back pressure becomes
active again until switch resources are free. If a collisionoccurs, the binary exponential backoff algorithm is skipped and
carrier sense is generated immediately, reducing the chanceof further colliding and maintaining carrier sense to prevent
reception of packets.To ensure no packet loss in 10BASE-T or 100BASE-TX half-duplex modes, the user must enable the
following:
Aggressive backoff (Register 3, bit 0)
No excessive collision drop (Register 4, bit 3)
Back pressure (Register 4, bit 5)
These bits are not set as the default because this is not the IEEE standard.
Broadcast Storm Protection
The KSZ8895MLU has an intelligent option to protect the switch system from receiving too many broadcast packets.
Broadcast packets are normally forwarded to all ports except the source port and thus use too many switch resources
(bandwidth and available space in transmit queues). The KSZ8895MLU has the option to include “multicast packets” for
storm control. The broadcast storm rate parameters are programmed globally and can be enabled or disabled on a per
port basis. The rate is based on a 50ms interval for 100BT and a 500ms interval for 10BT. At the beginning of each
interval, the counter is cleared to zero and the rate-limit mechanism starts to count the number of bytes during the interval.
The rate definition is described in Registers 6 and 7. The default setting for Registers 6 and 7 is 0x4A (74 decimal). This is
equal to a rate of 1%, calculated as follows:
148,800 frames/sec ¥ 50ms/interval ¥ 1% = 74 frames/interval (approx.) = 0x4A
MII Interface Operation
The media independent interface (MII) is specified by the IEEE 802.3 committee and provides a common interface
between physical layer and MAC layer devices. The KSZ8895MLU provides such interfaces on port 5. The SW5-MII
interface is used to connect to the fifth MAC. The MII interfaces contains two distinct groups of signals, one for
transmission and the other for receiving.
Port 5 MAC 5 SW5-MII Interface
Table 3 shows two connection manners:
1.
The first is an external MAC connects to SW5-MII PHY mode.
2.
The second is an external PHY connects to SW5-MII MAC mode.
Please see the pins [91, 86, and 87] description for detail configuration for the MAC mode and PHY mode, SW5-MII works
with 25MHz and 2.5MHz clock for 100Base-TX and 10Base-T.
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KSZ8895MLU PHY Mode Connection
KSZ8895MLU MAC Mode Connection
Description
External
PHY
KSZ8895MLU SW5-MII
Signals
Type
Transmit enable
MTXEN
SMRXDV
Output
Input
Transmit error
MTXER
Not used
Not used
SMTXD[3]
Input
Transmit data bit 3
MTXD3
SMRXD[3]
Output
MTXD2
SMTXD[2]
Input
Transmit data bit 2
MTXD2
SMRXD[2]
Output
MTXD1
SMTXD[1]
Input
Transmit data bit 1
MTXD1
SMRXD[1]
Output
MTXD0
SMTXD[0]
Input
Transmit data bit 0
MTXD0
SMRXD[0]
Output
MTXC
SMTXC
Output
Transmit clock
MTXC
SMRXC
Input
MCOL
SCOL
Output
Collision detection
MCOL
SCOL
Input
MCRS
SCRS
Output
Carrier sense
MCRS
SCRS
Input
MRXDV
SMRXDV
Output
Receive data valid
MRXDV
SMTXEN
Input
MRXER
Not used
Output
Receive error
MRXER
SMTXER
Input
MRXD3
SMRXD[3]
Output
Receive data bit 3
MRXD3
SMTXD[3]
Input
MRXD2
SMRXD[2]
Output
Receive data bit 2
MRXD2
SMTXD[2]
Input
MRXD1
SMRXD[1]
Output
Receive data bit 1
MRXD1
SMTXD[1]
Input
MRXD0
SMRXD[0]
Output
Receive data bit 0
MRXD0
SMTXD[0]
Input
MRXC
SMRXC
Output
Receive clock
MRXC
SMTXC
Input
External
MAC
KSZ8895MLU SW5-MII
Signals
Type
MTXEN
SMTXEN
Input
MTXER
SMTXER
MTXD3
Table 3. Switch MAC 5 MII/Turbo MII Signals
The switch MII interface operates in either MAC mode or PHY mode for KSZ8895MLU. These interfaces are nibble-wide
data interfaces and therefore run at 1/4 the network bit rate (not encoded). Additional signals on the transmit side indicate
when data is valid or when an error occurs during transmission. Likewise, the receive side has indicators that convey
when the data is valid and without physical layer errors. For half-duplex operation there is a signal that indicates a
collision has occurred during transmission.
Note that the signal MRXER is not provided on the MII-SW interface for PHY mode operation and the signal MTXER is
not provided on the MII-SW interface for MAC mode operation. Normally MRXER would indicate a receive error coming
from the physical layer device. MTXER would indicate a transmit error from the MAC device. These signals are not
appropriate for this configuration. For PHY mode operation, if the device interfacing with the KSZ8895MLU has an
MRXER pin, it should be tied low. For MAC mode operation, if the device interfacing with the KSZ8895MLU has an
MTXER pin, it should be tied low.
SNI Interface Operation
The serial network interface (SNI) is compatible with some controllers used for network layer protocol processing. This
interface can be directly connected to these types of devices. The signals are divided into two groups, one for
transmission and the other for reception. The signals involved are described in Table 4.
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SNI Signal
Description
KSZ8895MLU Signal
TXEN
Transmit Enable
SMTXEN
TXD
Serial Transmit Data
SMTXD[0]
TXC
Transmit Clock
SMTXC
COL
Collision Detection
SCOL
CRS
Carrier Sense
SMRXDV
RXD
Serial Receive Data
SMRXD[0]
RXC
Receive Clock
SMRXC
Table 4. SNI Signals
This interface is a bit-wide data interface and therefore runs at the network bit rate (not encoded). An additional signal on
the transmit side indicates when data is valid. Likewise, the receive side has an indicator that conveys when the data is
valid.
For half-duplex operation there is a signal that indicates a collision has occurred during transmission.
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Advanced Functionality
QoS Priority Support
The KSZ8895MLU provides Quality of Service (QoS) for applications such as VoIP and video conferencing. The
KSZ8895MLU offer 1/2/4 priority queues option per port by setting the port registers xxx control 9 bit1 and the port
registers xxx control 0 bit0, the 1/2/4 queues split as follows,
[Port registers xxx control 9 bit1, control 0 bit0]=00 single output queue as default.
[Port registers xxx control 9 bit1, control 0 bit0]=01 egress port can be split into two priority transmit queues.
[Port registers xxx control 9 bit1, control 0 bit0]=10 egress port can be split into four priority transmit queues.
The four priority transmit queues is a new feature in the KSZ8895MLU. The queue 3 is the highest priority queue and
Queue 0 is the lowest priority queue. The port registers xxx control 7 bit1 and the port registers xxx control 0 bit0 are used
to enable split transmit queues for ports 1, 2, 3, 4 and 5, respectively. If a port's transmit queue is not split, high priority
and low priority packets have equal priority in the transmit queue.
There is an additional option to either always deliver high priority packets first or use programmable weighted fair queuing
for the four priority queues scale by the port registers control 10, 11, 12 and 13 (default value are 8, 4, 2, 1 by their
bit[6:0].
Register 130 bit[7:6] Prio_2Q[1:0] is used when the 2 Queue configuration is selected, these bits are used to map the 2-bit
result of IEEE 802.1p from the registers 128, 129 or TOS/DiffServ mapping from registers 144-159 (for 4 Queues) into two
queues mode with priority high or low.
Please see the descriptions of the register 130 bits [7:6] for detail.
Port-Based Priority
With port-based priority, each ingress port is individually classified as a priority 0-3 receiving port. All packets received at
the priority 3 receiving port are marked as high priority and are sent to the high-priority transmit queue if the corresponding
transmit queue is split. The Port Registers Control 0 Bits [4:3] is used to enable port-based priority for ports 1, 2, 3, 4 and
5, respectively.
802.1p-Based Priority
For 802.1p-based priority, the KSZ8895MLU examines the ingress (incoming) packets to determine whether they are
tagged. If tagged, the 3-bit priority field in the VLAN tag is retrieved and compared against the “priority mapping” value, as
specified by the registers 128 and 129, both register 128/129 can map 3-bit priority field of 0-7 value to 2-bit result of 0-3
priority levels. The “priority mapping” value is programmable.
The following figure illustrates how the 802.1p priority field is embedded in the 802.1Q VLAN tag.
Figure 6. 802.1p Priority Field Format
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802.1p-based priority is enabled by bit [5] of the port registers control 0 for ports 1, 2, 3, 4 and 5, respectively.
The KSZ8895MLU provides the option to insert or remove the priority tagged frame's header at each individual egress
port. This header, consisting of the 2 bytes VLAN Protocol ID (VPID) and the 2-byte Tag Control Information field (TCI), is
also referred to as the IEEE 802.1Q VLAN tag.
Tag Insertion is enabled by bit [2] of the port registers control 0 and the port register control 8 to select which source port
(ingress port) PVID can be inserted on the egress port for ports 1, 2, 3, 4 and 5, respectively. At the egress port, untagged
packets are tagged with the ingress port’s default tag. The default tags are programmed in the port registers control 3 and
control 4 for ports 1, 2, 3, 4 and 5, respectively. The KSZ8895MLU will not add tags to already tagged packets.
Tag Removal is enabled by bit [1] of the port registers control 0 for ports 1, 2, 3, 4 and 5, respectively. At the egress port,
tagged packets will have their 802.1Q VLAN Tags removed. The KSZ8895MLU will not modify untagged packets.
The CRC is recalculated for both tag insertion and tag removal.
802.1p Priority Field Re-mapping is a QoS feature that allows the KSZ8895MLU to set the “User Priority Ceiling” at any
ingress port by the port register control 2 bit 7. If the ingress packet’s priority field has a higher priority value than the
default tag’s priority field of the ingress port, the packet’s priority field is replaced with the default tag’s priority field.
DiffServ-Based Priority
DiffServ-based priority uses the ToS registers (registers 144 to 159) in the Advanced Control Registers section. The ToS
priority control registers implement a fully decoded, 128-bit Differentiated Services Code Point (DSCP) register to
determine packet priority from the 6-bit ToS field in the IP header. When the most significant 6 bits of the ToS field are
fully decoded, the resultant of the 64 possibilities of DSCP decoded is compared with the corresponding bits in the DSCP
register to determine priority.
Spanning Tree Support
Port 5 is the designated port for spanning tree support.
The other ports (port 1 – port 4) can be configured in one of the five spanning tree states via “transmit enable,” “receive
enable,” and “learning disable” register settings in Registers 18, 34, 50, and 66 for ports 1, 2, 3, and 4, respectively. The
following description shows the port setting and software actions taken for each of the five spanning tree states.
Disable state: the port should not forward or receive any packets. Learning is disabled.
Port setting: "transmit enable = 0, receive enable = 0, learning disable = 1."
Software action: the processor should not send any packets to the port. The switch may still send specific packets to the
processor (packets that match some entries in the static table with “overriding bit” set) and the processor should discard
those packets.
Note: Processor is connected to port 5 via MII interface. Address learning is disabled on the port in this state.
Blocking state: only packets to the processor are forwarded. Learning is disabled.
Port setting: "transmit enable = 0, receive enable = 0, learning disable = 1"
Software action: the processor should not send any packets to the port(s) in this state. The processor should program the
“Static MAC table” with the entries that it needs to receive (e.g., BPDU packets). The “overriding” bit should also be set so
that the switch will forward those specific packets to the processor. Address learning is disabled on the port in this state.
Listening state: only packets to and from the processor are forwarded. Learning is disabled.
Port setting: "transmit enable = 0, receive enable = 0, learning disable = 1.
"Software action: The processor should program the static MAC table with the entries that it needs to receive (e.g., BPDU
packets). The “overriding” bit should be set so that the switch will forward those specific packets to the processor. The
processor may send packets to the port(s) in this state, see “Tail Tagging Mode” section for details. Address learning is
disabled on the port in this state.
Learning state: only packets to and from the processor are forwarded. Learning is enabled.
Port setting: “transmit enable = 0, receive enable = 0, learning disable = 0.”
Software action: The processor should program the static MAC table with the entries that it needs to receive (e.g., BPDU
packets). The “overriding” bit should be set so that the switch will forward those specific packets to the processor. The
processor may send packets to the port(s) in this state, see “Tail Tagging Mode” section for details. Address learning is
enabled on the port in this state.
Forwarding state: Packets are forwarded and received normally. Learning is enabled.
Port setting: “transmit enable = 1, receive enable = 1, learning disable = 0.”
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Software action: The processor should program the static MAC table with the entries that it needs to receive (e.g., BPDU
packets). The “overriding” bit should be set so that the switch will forward those specific packets to the processor. The
processor may send packets to the port(s) in this state, see “Tail Tagging Mode” section for details. Address learning is
enabled on the port in this state.
Rapid Spanning Tree Support
There are three operational states of the Discarding, Learning, and Forwarding assigned to each port for RSTP:
Discarding ports do not participate in the active topology and do not learn MAC addresses.
Discarding state: the state includs three states of the disable, blocking and listening of STP.
Port setting: "transmit enable = 0, receive enable = 0, learning disable = 1."
Software action: the processor should not send any packets to the port. The switch may still send specific packets to the
processor (packets that match some entries in the static table with “overriding bit” set) and the processor should discard
those packets. When disable the port’s learning capability (learning disable=’1’), set the register 1 bit5 and bi4 will flush
rapidly with the port related entries in the dynamic MAC table and static MAC table.
Note: Processor is connected to port 5 via MII interface. Address learning is disabled on the port in this state.
Ports in Learning states learn MAC addresses, but do not forward user traffic.
Learning state: only packets to and from the processor are forwarded. Learning is enabled.
Port setting: “transmit enable = 0, receive enable = 0, learning disable = 0.”
Software action: The processor should program the static MAC table with the entries that it needs to receive (e.g., BPDU
packets). The “overriding” bit should be set so that the switch will forward those specific packets to the processor. The
processor may send packets to the port(s) in this state, see “Tail Tagging Mode” section for details. Address learning is
enabled on the port in this state.
Ports in Forwarding states fully participate in both data forwarding and MAC learning.
Forwarding state: packets are forwarded and received normally. Learning is enabled.
Port setting: “transmit enable = 1, receive enable = 1, learning disable = 0.”
Software action: The processor should program the static MAC table with the entries that it needs to receive (e.g., BPDU
packets). The “overriding” bit should be set so that the switch will forward those specific packets to the processor. The
processor may send packets to the port(s) in this state, see “Tail Tagging Mode” section for details. Address learning is
enabled on the port in this state.
RSTP uses only one type of BPDU called RSTP BPDUs. They are similar to STP Configuration BPDUs with the exception
of a type field set to “version 2” for RSTP and “version 0” for STP, and a flag field carrying additional information.
Tail Tagging Mode
The Tail Tag is only seen and used by the port 5 interface, which should be connected to a processor by SW5-MII
interface. The one byte tail tagging is used to indicate the source/destination port in port 5. Only bit [3-0] are used for the
destination in the tail tagging byte. Other bits are not used. The Tail Tag feature is enabled by setting register 12.
Figure 7. Tail Tag Frame Format
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Ingress to Port 5 (Host > KSZ8895MLU)
Bit [3:0]
Destination
0,0,0,0
Normal (Address Look up for destination)
0,0,0,1
Port 1 (direct forward to port1)
0,0,1,0
Port 2 (direct forward to port2)
0,1,0,0
Port 3 (direct forward to port3)
1,0,0,0
Port 4 (direct forward to port4)
1,1,1,1
Port 1, 2,3 and 4 (direct forward to port 1,2,3,4,)
Bit [7:4]
0,0,0,0
Queue 0 is used at destination port
0,0,0,1
Queue 1 is used at destination port
0,0,1,0
Queue 2 is used at destination port
0,0,1,1
Queue 3 is used at destination port
x, 1,x,x
Whatever send packets to specified port in bit[3:0]
1, x,x,x
Bit[6:0] will be ignored
Egress from Port 5 (KSZ8895MLU > Host)
Bit [1:0]
Source
0,0
Port 1 (packets from port 1)
0,1
Port 2 (packets from port 2)
1,0
Port 3 (packets from port 3)
1,1
Port 4 (packets from port 4)
Table 5. Tail Tag Rules
IGMP Support
There are two parts involved to support the Internet Group Management Protocol (IGMP) in Layer 2. The first part is IGMP
snooping, the second part is this IGMP packet to be sent back to the subscribed port. Describe them as follows.
IGMP Snooping
The KSZ8895MLU traps IGMP packets and forwards them only to the processor (Port 5 SW5-MII/RMII). The IGMP
packets are identified as IP packets (either Ethernet IP packets, or IEEE 802.3 SNAP IP packets) with IP version = 0x4
and protocol version number = 0x2. Set register 5 bit [6] to ‘1’ to enable IGMP snooping.
IGMP Send Back to the Subscribed Port
Once the host responds the received IGMP packet, the host should knows the original IGMP ingress port and send
back the IGMP packet to this port only, otherwise this IGMP packet will be broadcasted to all port to downgrade the
performance.
Enable the tail tag mode, the host will know the IGMP packet received port from tail tag bits [1:0] and can send back
the response IGMP packet to this subscribed port by setting the bits [3:0] in the tail tag. Enable “Tail tag mode” by
setting Register 12 bit 1.
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Port Mirroring Support
KSZ8895MLU supports “port mirror” comprehensively as:
“Receive Only” Mirror on a Port
All the packets received on the port will be mirrored on the sniffer port. For example, port 1 is programmed to be “rx
sniff,” and port 5 is programmed to be the “sniffer port.” A packet, received on port 1, is destined to port 4 after the
internal look-up. The KSZ8895MLU will forward the packet to both port 4 and port 5. KSZ8895MLU can optionally
forward even “bad” received packets to port 5.
“Transmit Only” Mirror on a Port
All the packets transmitted on the port will be mirrored on the sniffer port. For example, port 1 is programmed to be “tx
sniff,” and port 5 is programmed to be the “sniffer port.” A packet, received on any of the ports, is destined to port 1
after the internal look-up. The KSZ8895MLU will forward the packet to both ports 1 and 5.
“Receive and Transmit” Mirror on Two Ports
All the packets received on port A AND transmitted on port B will be mirrored on the sniffer port. To turn on the “AND”
feature, set Register 5 bit 0 to 1. For example, port 1 is programmed to be “rx sniff,” port 2 is programmed to be
“transmit sniff,” and port 5 is programmed to be the “sniffer port.” A packet, received on port 1, is destined to port 4
after the internal look-up. The KSZ8895MLU will forward the packet to port 4 only, since it does not meet the “AND”
condition. A packet, received on port 1, is destined to port 2 after the internal look-up. The KSZ8895MLU will forward
the packet to both port 2 and port 5.
Multiple ports can be selected to be “rx sniffed” or “tx sniffed.” And any port can be selected to be the “sniffer port.” All
these per port features can be selected through Register 17.
VLAN Support
KSZ8895MLU supports 128 active VLANs and 4096 possible VIDs specified in IEEE 802.1q. KSZ8895MLU provides a
128-entry VLAN table, which correspond to 4096 possible VIDs and converts to FID (7 bits) for address look-up max 128
active VLANs. If a non-tagged or null-VID-tagged packet is received, the ingress port VID is used for look-up when 802.1q
is enabled by the global register 5 control 3 bit 7. In the VLAN mode, the look-up process starts from VLAN table look-up
to determine whether the VID is valid. If the VID is not valid, the packet will be dropped and its address will not be learned.
If the VID is valid, FID is retrieved for further look-up by the static MAC table or dynamic MAC table. FID+DA is used to
determine the destination port. The followed table describes the difference actions at different situations of DA and
FID+DA in the static MAC table and dynamic MAC table after the VLAN table finish a look-up action. FID+SA is used for
learning purposes. The followed table also describes how to learning in the dynamic MAC table when VLAN table has
done a look-up and the static MAC table without a valid entry.
DA Found in
Static MAC
Table
Use FID Flag?
FID Match?
DA+FID Found in
Dynamic MAC
Table
No
Don’t care
Don’t care
No
No
Don’t care
Don’t care
Yes
Yes
0
Don’t care
Don’t care
Yes
1
No
No
Yes
1
No
Yes
Yes
1
Yes
Don’t care
Action
Broadcast to the membership ports defined in the
VLAN table bit [11:7].
Send to the destination port defined in the dynamic
MAC table bit [57:55].
Send to the destination port(s) defined in the static
MAC table bit [52:48].
Broadcast to the membership ports defined in the
VLAN table bit [11:7].
Send to the destination port defined in the dynamic
MAC table bit [57:55].
Send to the destination port(s) defined in the static
MAC table bit [52:48].
Table 6. FID+DA Look-Up in the VLAN Mode
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SA+FID Found in
Dynamic MAC Table
KSZ8895MLU
Action
No
The SA+FID will be learned into the dynamic table.
Yes
Time stamp will be updated.
Table 7. FID+SA Look-Up in the VLAN Mode
Advanced VLAN features are also supported in KSZ8895MLU, such as “VLAN ingress filtering” and “discard non PVID”
defined in bits [6:5] of the port Register Control 2. These features can be controlled on a port basis.
Rate Limiting Support
The KSZ8895MLU provides a fine resolution hardware rate limiting. The rate step is 64Kbps when the rate limit is less
than 1Mbps rate for 100BT or 10BT. The rate step is 1Mbps when the rate limit is more than 1Mbps rate for 100BT or
10BT (refer to Data Rate Selection Table which follow the end of the Port Register Queue 0 3 Ingress/Egress Limit
Control section). The rate limit is independently on the “receive side” and on the “transmit side” on a per port basis. For
10BASE-T, a rate setting above 10 Mbps means the rate is not limited. On the receive side, the data receive rate for each
priority at each port can be limited by setting up Ingress Rate Control Registers. On the transmit side, the data transmit
rate for each priority queue at each port can be limited by setting up Egress Rate Control Registers. The size of each
frame has options to include minimum IFG (Inter Frame Gap) or Preamble byte, in addition to the data field (from packet
DA to FCS).
Ingress Rate Limit
For ingress rate limiting, KSZ8895MLU provides options to selectively choose frames from all types, multicast, broadcast,
and flooded unicast frames by bits [3 2] of the port rate limit control register. The KSZ8895MLU counts the data rate
from those selected type of frames. Packets are dropped at the ingress port when the data rate exceeds the specified
rate limit or the flow control takes effect without packet dropped when the ingress rate limit flow control is enabled by the
port rate limit control register bit 4. The ingress rate limiting supports the port-based, 802.1p and DiffServ-based priorities,
the port-based priority is fixed priority 0 3 selection by bits [4 3] of the port register control 0. The 802.1p and DiffServbased priority can be mapped to priority 0 3 by default of the register 128 and 129. In the ingress rate limit, set register
135 global control 19 bit3 for queue-based rate limit to be enabled if use two queues or four queues mode, all related
ingress ports and egress port should be spitted to two queues or four queues mode by the port registers control 9 and
control 0. The four queues mode will use Q0-Q3 for priority 0-3 by bit [6-0] of the port register ingress limit control 1 4.
The two queues mode will use Q0-Q1 for priority 0-1by bit [6-0] of the port register ingress limit control 1 2. The priority
levels in the packets of the 802.1p and DiffServ can be programmed to priority 0-3 by the register 128 and 129 for a remapping.
Egress Rate Limit
For egress rate limiting, the Leaky Bucket algorithm is applied to each output priority queue for shaping output traffic. Inter
frame gap is stretched on a per frame base to generate smooth, non-burst egress traffic. The throughput of each output
priority queue is limited by the egress rate specified by the data rate selection table followed the egress rate limit control
registers.
If any egress queue receives more traffic than the specified egress rate throughput, packets may be accumulated in the
output queue and packet memory. After the memory of the queue or the port is used up, packet dropping or flow control
will be triggered. As a result of congestion, the actual egress rate may be dominated by flow control/dropping at the
ingress end, and may be therefore slightly less than the specified egress rate. The egress rate limiting supports the portbased, 802.1p and DiffServ-based priorities, the port-based priority is fixed priority 0 3 selection by bits [4 3] of the port
register control 0. The 802.1p and DiffServ-based priority can be mapped to priority 0 3 by default of the register 128
and 129. In the egress rate limit, set register 135 global control 19 bit3 for queue-based rate limit to be enabled if use two
queues or four queues mode, all related ingress ports and egress port should be spitted to two queues or four queues
mode by the port registers control 9 and control 0. The four queues mode will use Q0-Q3 for priority 0 3 by bit [6 0] of
the port register egress limit control 1 4. The two queues mode will use Q0 Q1 for priority 0 1by bit [6 0] of the port
register egress limit control 1 2.
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The priority levels in the packets of the 802.1p and DiffServ can be programmed to priority 0 3 by the register 128 and
129 for a re-mapping.
When egress rate limit just use one queue per port for the egress port rate limit, the priority packets will be based on the
data rate selection table with the rate limit exact number. If egress rate limit use more than one queue per port for the
egress port rate limit, the highest priority packets will be based on the data rate selection table for the rate limit exact
number, other lower priority packet rate will be limited based on 8:4:2:1 (default) priority ratio based on the highest priority
rate. The transmit queue priority ratio is programmable.
To reduce congestion, it is a good practice to make sure the egress bandwidth exceeds the ingress bandwidth.
Transmit Queue Ratio Programming
In transmit queues 0 3 of the egress port, the default priority ratio is 8:4:2:1, the priority ratio can be programmed by the
port registers control 10, 11, 12 and 13. When the transmit rate exceed the ratio limit in the transmit queue, the transmit
rate will be limited by the transmit queue 0 3 ratio of the port register control 10, 11, 12 and 13. The highest priority
queue will be no limited, other lower priority queues will be limited based on the transmit queue ratio.
Filtering for Self-Address, Unknown Unicast/Multicast Address and Unknown VID Packet/IP Multicast
Enable Self-address filtering, the unknown unicast packet filtering and forwarding by the Register 131 Global Control 15.
Enable Unknown multicast packet filtering and forwarding by the Register 132 Global Control 16.
Enable Unknown VID packet filtering and forwarding by the Register 133 Global Control 17.
Enable Unknown IP multicast packet filtering and forwarding by the Register 134 Global Control 18.
This function is very useful in preventing those kinds of packets that could degrade the quality of the port in applications
such as voice over Internet Protocol (VoIP) and the daisy chain connection to prevent packets into endless loop.
Configuration Interface
I2C Master Serial Bus Configuration
If a 2-wire EEPROM exists, the KSZ8895MLU can perform more advanced features like broadcast storm protection and
rate control. The EEPROM should have the entire valid configuration data from Register 0 to Register 255 defined in the
“Memory Map,” except the status registers. After reset, the KSZ8895MLU will start to read all 255 registers sequentially
from the EEPROM. The configuration access time (tprgm) is less than 30ms as shown in Figure 12.
Figure 8. KSZ8895MLU EEPROM Configuration Timing Diagram
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To configure the KSZ8895MLU with a pre-configured EEPROM use the following steps:
1.
At the board level, connect pin 110 on the KSZ8895MLU to the SCL pin on the EEPROM. Connect pin 111 on the
KSZ8895MLU to the SDA pin on the EEPROM.
2.
Set the input signals PS[1:0] (pins 113 and 114, respectively) to “00.” This puts the KSZ8895MLU serial bus
configuration into I2C master mode.
3.
Be sure the board-level reset signal is connected to the KSZ8895MLU reset signal on pin 115 (RST_N).
4.
Program the contents of the EEPROM before placing it on the board with the desired configuration data. Note that
the first byte in the EEPROM must be “95” and second byte of chip ID must be “00” for the loading to occur
properly. If this value is not correct, all other data will be ignored.
5.
Place EEPROM on the board and power up the board. Assert the active-low board level reset to RST_N on the
KSZ8895MLU. After the reset is de-asserted, the KSZ8895MLU will begin reading configuration data from the
EEPROM. The configuration access time (tprgm) is less than 30ms.
Note: For proper operation, make sure that pin 47 (PWRDN_N) is not asserted during the reset operation.
SPI Slave Serial Bus Configuration
The KSZ8895MLU can also act as an SPI slave device. Through the SPI, the entire feature set can be enabled, including
“VLAN,” “IGMP snooping,” “MIB counters,” etc. The external master device can access any register from Register 0 to
Register 127 randomly. The system should configure all the desired settings before enabling the switch in the
KSZ8895MLU. To enable the switch, write a "1" to Register 1 bit 0.
Two standard SPI commands are supported (00000011 for “READ DATA,” and 00000010 for “WRITE DATA”). To speed
configuration time, the KSZ8895MLU also supports multiple reads or writes. After a byte is written to or read from the
KSZ8895MLU, the internal address counter automatically increments if the SPI Slave Select Signal (SPIS_N) continues to
be driven low. If SPIS_N is kept low after the first byte is read, the next byte at the next address will be shifted out on
SPIQ. If SPIS_N is kept low after the first byte is written, bits on the Master Out Slave Input (SPID) line will be written to
the next address. Asserting SPIS_N high terminates a read or write operation. This means that the SPIS_N signal must
be asserted high and then low again before issuing another command and address. The address counter wraps back to
zero once it reaches the highest address. Therefore the entire register set can be written to or read from by issuing a
single command and address.
The default SPI clock speed is 12.5MHz. The KSZ8895MLU is able to support a SPI bus up to 25MHz (set register 12 bit
[5:4]=0x10). A high performance SPI master is recommended to prevent internal counter overflow.
To use the KSZ8895MLU SPI:
1.
At the board level, connect KSZ8895MLU pins as noted in Table 8:
KSZ8895MLU Pin
Number
KSZ8895MLU Signal
Name
112
SPIS_N
110
SPIC
SPI Clock
111
SPID
Master Out Slave Input
109
SPIQ
Master In Slave Output
Microprocessor Signal Description
SPI Slave Select
Table 8. SPI Connections
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2.
3.
4.
5.
6.
KSZ8895MLU
Set the input signals PS[1:0] (pins 113 and 114, respectively) to “10” to set the serial configuration to SPI slave
mode.
Power up the board and assert a reset signal. After reset wait 100µs, the start switch bit in Register 1 will be set to
‘0’. Configure the desired settings in the KSZ8895MLU before setting the start register to ‘1.'
Write configuration to registers using a typical SPI write data cycle as shown in Figure 9 or SPI multiple write as
shown in Figure 11. Note that data input on SPID is registered on the rising edge of SPIC.
Registers can be read and configuration can be verified with a typical SPI read data cycle as shown in Figure 10
or a multiple read as shown in Figure 12. Note that read data is registered out of SPIQ on the falling edge of
SPIC.
After configuration is written and verified, write a ‘1’ to Register 1 bit 0 to begin KSZ8895MLU switch operation.
Figure 9. SPI Write Data Cycle
Figure 10. SPI Read Data Cycle
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Figure 11. SPI Multiple Write
Figure 12. SPI Multiple Read
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MII Management Interface (MIIM)
The KSZ8895MLU supports the standard IEEE 802.3 MII Management Interface, also known as the Management Data
Input/Output (MDIO) Interface. This interface allows upper-layer devices to monitor and control the states of the
KSZ8895MLU. An external device with MDC/MDIO capability is used to read the PHY status or configure the PHY
settings. Further detail on the MIIM interface is found in Clause 22.2.4.5 of the IEEE 802.3u Specification.
The MIIM interface consists of the following:
A physical connection that incorporates the data line (pin 108 MDIO) and the clock line (pin 107 MDC).
A specific protocol that operates across the aforementioned physical connection that allows an external controller to
communicate with the KSZ8895MLU device.
Access to a set of eight 16-bit registers, consisting of 8 standard MIIM registers [0:5h], 1d and 1f MIIM registers per
port.
The MIIM Interface can operate up to a maximum clock speed of 10MHz MDC clock.
Table 9 depicts the MII Management Interface frame format.
Preamble
Start of Frame
Read/Write
OP Code
PHY
Address
Bits [4:0]
REG
Address
Bits [4:0]
TA
Data Bits [15:0]
Idle
Read
32 1’s
01
10
AAAAA
RRRRR
Z0
DDDDDDDD_DDDDDDDD
Z
Write
32 1’s
01
01
AAAAA
RRRRR
10
DDDDDDDD_DDDDDDDD
Z
Table 9. MII Management Interface Frame Format
The MIIM interface does not have access to all the configuration registers in the KSZ8895MLU. It can only access the
standard MIIM registers. See “MIIM Registers”. The SPI interface and MDC/MDIO SMI mode, on the other hand, can be
used to access the entire KSZ8895MLU feature set.
Serial Management Interface (SMI)
The SMI is the KSZ8895MLU non-standard MIIM interface that provides access to all KSZ8895MLU configuration
registers. This interface allows an external device with MDC/MDIO interface to completely monitor and control the states
of the KSZ8895MLU.
The SMI interface consists of the following:
A physical connection that incorporates the data line (MDIO) and the clock line (MDC).
A specific protocol that operates across the aforementioned physical connection that allows an external controller to
communicate with the KSZ8895MLU device.
Access all KSZ8895MLU configuration registers. Register access includes the Global, Port and Advanced Control
Registers 0 255 (0x00 – 0xFF), and indirect access to the standard MIIM registers [0:5] and custom MIIM registers [29,
31].
The SMI Interface can operate up to a maximum clock speed of 10MHz MDC clock.
Table 10 depicts the SMI frame format.
Read/Write
OP Code
PHYAD
Address
Bits [4:0]
REG
Address
Bits [4:0]
TA
Data Bits [15:0]
Idle
01
10
RR11R
RRRRR
Z0
0000_0000_DDDD_DDDD
Z
01
01
RR11R
RRRRR
10
xxxx_xxxx_DDDD_DDDD
Z
Preamble
Start of Frame
Read
32 1’s
Write
32 1’s
Table 10. Serial Management Interface (SMI) Frame Format
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SMI register Read access is selected when OP Code is set to “10” and bits [2:1] of the PHY address is set to ‘11’. The
8-bit register address is the concatenation of {PHY address bits [4:3], PHY address bits [0], REG address bit [4:0]}. TA is
turn-around bits. TA bits [1:0] are ’Z0’ means the processor MDIO pin is changed to input Hi-Z from output mode and the
followed ‘0’ is the read response from device, as the switch configuration registers are 8-bit wide, only the lower 8 bits of
data bits [15:0] are used
SMI register Write access is selected when OP Code is set to “01” and bits [2:1] of the PHY address is set to ‘11’. The
8-bit register address is the concatenation of {PHY address bits [4:3], PHY address bits [0], REG address bit [4:0]}. TA
bits [1:0] are set to ’10’, as the switch configuration registers are 8-bit wide, only the lower 8 bits of data bits [15:0] are
used.
To access the KSZ8895MLU registers 0-255 (0x00 - 0xFF), the following applies:
PHYAD [4, 3, 0] and REGAD [4:0] are concatenated to form the 8-bit address; that is, {PHYAD [4, 3, 0], REGAD [4:0]} =
bits [7:0] of the 8-bit address.
Registers are 8 data bits wide. For read operation, data bits [15:8] are read back as zeroes. For write operation, data bits
[15:8] are not defined, and hence can be set to either zeroes or ones.
SMI register access is the same as the MIIM register access, except for the register access requirements presented in
this section.
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Register Description
Offset
Description
Decimal
Hex
01
0x00-0x01
Chip ID Registers
2 13
0x02-0x0D
Global Control Registers
14 15
0x0E-0x0F
Power Down Management Control Registers
16 20
0x10-0x14
Port 1 Control Registers
21 23
0x15-0x17
Port 1 Reserved (Factory Test Registers)
24 31
0x18-0x1F
Port 1 Control/Status Registers
32 36
0x20-0x24
Port 2 Control Registers
37 39
0x25-0x27
Port 2 Reserved (Factory Test Registers)
40 47
0x28-0x2F
Port 2 Control/Status Registers
48 52
0x30-0x34
Port 3 Control Registers
53 55
0x35-0x37
Port 3 Reserved (Factory Test Registers)
56 63
0x38-0x3F
Port 3 Control/Status Registers
64 68
0x40-0x44
Port 4 Control Registers
69 71
0x45-0x47
Port 4 Reserved (Factory Test Registers)
72 79
0x48-0x4F
Port 4 Control/Status Registers
80 84
0x50-0x54
Port 5 Control Registers
85 87
0x55-0x57
Port 5 Reserved (Factory Test Registers)
88 95
0x58-0x5F
Port 5 Control/Status Registers
96 103
0x60-0x67
Reserved (Factory Testing Registers)
104 109
0x68-0x6D
MAC Address Registers
110 111
0x6E-0x6F
Indirect Access Control Registers
112 120
0x70-0x78
Indirect Data Registers
121 123
0x79-0x7B
Reserved (Factory Testing Registers)
124 125
0x7C-0x7D
Port Interrupt Registers
126 127
0x7E-0x7F
Reserved (Factory Testing Registers)
128 135
0x80-0x87
Global Control Registers
136
0x88
137 143
0x89-0x8F
QM Global Control Registers
144 145
0x90-0x91
TOS Priority Control Registers
146 159
0x92-0x9F
TOS Priority Control Registers
160 175
0xA0-0xAF
Reserved (Factory Testing Registers)
176 190
0xB0-0xBE
Port 1 Control Registers
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Switch Self Test Control Register
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Register Description (Continued)
Offset
Description
Decimal
Hex
191
0xBF
192 206
0xC0-0xCE
207
0xCF
208 222
0xD0-0xDE
223
0xDF
224 238
0xE0-0xEE
239
0xEF
240 254
0xF0-0xFE
255
0xFF
October 2011
Reserved (Factory Testing Register): Transmit Queue Remap Base Register
Port 2 Control Registers
Reserved (Factory Testing Register)
Port 3 Control Registers
Reserved (Factory Testing Register)
Port 4 Control Registers
Reserved (Factory Testing Register)
Port 5 Control Registers
Reserved (Factory Testing Register)
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Global Registers
Register 0 (000): Chip ID0
Address
Name
Description
Mode
Default
Family ID
Chip family.
RO
0 95
Name
Description
Mode
Default
74
Chip ID
Based on each part number in KSZ8895 family
RO
04
31
Revision ID
Revision ID
RO
00
R/W
0
Mode
Default
70
Register 1 (001): Chip ID1 / Start Switch
Address
1, start the chip when external pins (PS1, PS0) =
(01) or (1,0)
Note: in (PS1, PS0) = (0,0) mode, the chip will
start automatically, after trying to read the external
EEPROM. If EEPROM does not exist, the chip will
use default values for all internal registers. If
EEPROM is present, the contents in the EEPROM
will be checked.
The switch will check:
0
Start Switch
Register 0 = 0 95
Register 1 [7:4] chip ID = 00
If this check is OK, the contents in the EEPROM
will override chip register default values.
Chip will not start when external pins (PS1, PS0)
= (1, 0) or (0, 1).
Note: (PS1, PS0) = (1, 1) for Factory test only.
0, stop the switch function of the chip.
Register 2 (002): Global Control 0
Address
Name
Description
7
New Back-off Enable
New back-off algorithm designed for UNH
1 = Enable
0 = Disable
R/W
0
6
Reserved
Reserved.
RO
0
R/W
(SC)
0
Flush the entire dynamic MAC table for RSTP
1 = Trigger the flush dynamic MAC table
operation. This bit is self clear.
0 = Normal operation
5
Flush Dynamic MAC Table
Note: All the entries associated with a port that
has its learning capability being turned off
(Learning Disable) will be flushed. If you want to
flush the entire Table, all ports learning capability
must be turned off.
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Global Registers (Continued)
Register 2 (002): Global Control 0
Address
Name
Description
Flush the matched entries in static MAC table for
RSTP
1 = Trigger the flush static MAC table operation.
This bit is self clear
0 = Normal operation
4
Flush Static MAC Table
Note: The matched entry is defined as the entry
whose Forwarding Ports field contains a single
port and MAC address with unicast. This port, in
turn, has its learning capability being turned off
(Learning Disable). Per port, multiple entries can
be qualified as matched entries.
Mode
Default
R/W
(SC)
0
3
Reserved
N/A Don’t change
RO
1
2
Reserved
N/A Don’t change
RO
1
UNH Mode
1, the switch will drop packets with 0x8808 in T/L
filed, or DA = 01-80-C2-00-00-01.
0, the switch will drop packets qualified as “flow
control” packets.
R/W
0
Link Change Age
1, link change from “link” to “no link” will cause
fast aging (800µs) to age address table faster.
After an age cycle is complete, the age logic will
return to normal (300 75 seconds). Note: If any
port is unplugged, all addresses will be
automatically aged out.
R/W
0
Mode
Default
1
0
Register 3 (003): Global Control 1
Address
Name
Description
7
Pass All Frames
1, switch all packets including bad ones. Used
solely for debugging purpose. Works in
conjunction with sniffer mode.
R/W
0
6
2K Byte Packet Support
1 = Enable support 2K Byte packet
0 = Disable support 2K Byte packet
R/W
0
0
5
IEEE 802.3x Transmit
Flow Control Disable
October 2011
0, will enable transmit flow control based on AN
result.
1, will not enable transmit flow control regardless
of AN result.
46
R/W
Pin PMRXD3
strap option.
PD(0): Enable Tx
flow control
(default).
PU(1): Disable
Tx/Rx flow
control.
Note: SPFLC
has internal pulldown.
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KSZ8895MLU
Global Registers (Continued)
Register 3 (003): Global Control 1
Address
Name
Description
Mode
Default
0
4
3
IEEE 802.3x Receive
Flow Control Disable
0, will enable receive flow control based on AN
result.
1, will not enable receive flow control regardless
of AN result.
Note: Bit 5 and bit 4 default values are controlled
by the same pin, but they can be programmed
independently.
R/W
Frame Length Field Check
1, will check frame length field in the IEEE
packets.
If the actual length does not match, the packet will
be dropped (for L/T <1500).
R/W
Pin PMRXD3
strap option.
PD (0): Enable
Rx flow control
(default).
PU(1): Disable
Tx/Rx flow
control.
Note: SPFLC
has internal pulldown.
0
1
2
Aging Enable
1, enable age function in the chip.
0, disable aging function.
R/W
1
Fast Age Enable
1 = Turn on fast age (800µs).
R/W
Pin LED[5][2]
strap option.
PD(0): Aging
disable.
PU(1): Aging
enable (default).
Note: LED[5][2]
has internal pull
up.
0
0
0
Aggressive Back Off Enable
October 2011
1 = Enable more aggressive back-off algorithm in
half duplex mode to enhance performance. This is
not an IEEE standard.
47
R/W
Pin PMRXD0
strap option.
PD(0): Disable
aggressive back
off (default).
PU(1):
Aggressive back
off.
Note: SPPE has
internal pull
down.
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Global Registers (Continued)
Register 4 (004): Global Control 2
Address
Mode
Default
Unicast Port-VLAN Mismatch
Discard
This feature is used for port VLAN (described in
Register 17, Register 33...).
1, all packets can not cross VLAN boundary.
0, unicast packets (excluding unknown/
multicast/broadcast) can cross VLAN boundary.
R/W
1
6
Multicast Storm Protection
Disable
1, “Broadcast Storm Protection” does not include
multicast packets. Only DA=FFFFFFFFFFFF
packets will be regulated.
0, “Broadcast Storm Protection” includes
DA = FFFFFFFFFFFF and DA[40] = 1 packets.
R/W
1
5
Back Pressure Mode
1, carrier sense based backpressure is selected.
0, collision based backpressure is selected.
R/W
1
Flow Control and Back
Pressure fair Mode
1, fair mode is selected. In this mode, if a flow
control port and a non-flow control port talk to the
same destination port, packets from the non-flow
control port may be dropped. This is to prevent
the flow control port from being flow controlled for
an extended period of time.
0, in this mode, if a flow control port and a nonflow control port talk to the same destination port,
the flow control port will be flow controlled. This
may not be “fair” to the flow control port.
R/W
1
7
4
Name
Description
0
3
2
No Excessive Collision Drop
1, the switch will not drop packets when 16 or
more collisions occur.
0, the switch will drop packets when 16 or more
collisions occur.
R/W
Huge Packet Support
1, will accept packet sizes up to 1916 bytes
(inclusive). This bit setting will override setting
from bit 1 of the same register.
0, the maximum packet size will be determined by
bit 1 of this register.
R/W
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48
Pin PMRXD1
strap option.
PD(0): (default )
Drop excessive
collision packets.
PU(1): Don’t
drop excessive
collision packets.
Note: SPDECP
has internal pull
down.
0
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Global Registers (Continued)
Register 4 (004): Global Control 2
Address
Name
Description
Mode
Default
0
1
Legal Maximum Packet
Size Check Disable
1, will accept packet sizes up to 1536 bytes
(inclusive).
0, 1522 bytes for tagged packets (not including
packets with STPID from CPU to ports 1-4), 1518
bytes for untagged packets. Any packets larger
than the specified value will be dropped.
0
Reserved
N/A
Pin PMRXER
strap option.
PD(0): (default)
1518/1522 byte
packets.
PU(1): 1536 byte
packets.
Note: SPPSZ
has internal pulldown.
R/W
RO
0
Register 5 (005): Global Control 3
Address
Name
Description
Mode
Default
7
802.1q VLAN Enable
1, 802.1q VLAN mode is turned on. VLAN table
needs to set up before the operation.
0, 802.1q VLAN is disabled.
R/W
0
6
IGMP Snoop Enable on
Switch SW5-MII Interface
1, IGMP snoop enabled. All the IGMP packets will
be forwarded to Switch MII port.
0, IGMP snoop disabled.
R/W
0
5
Enable Direct Mode on
Switch SW5-MII Interface
1, direct mode on port 5. This is a special mode
for the Switch MII interface. Using preamble
before MRXDV to direct switch to forward
packets, bypassing internal look-up.
0, normal operation.
R/W
0
4
Enable Pre-Tag on
Switch SW5-MII Interface
1, packets forwarded to Switch MII interface will
be pre-tagged with the source port number
(preamble before MRXDV).
0, normal operation.
R/W
0
Reserved
N/A
RO
00
Enable “Tag” Mask
1, the last 5 digits in the VID field are used as a
mask to determine which port(s) the packet
should be forwarded to.
0, no tag masks.
R/W
0
R/W
0
32
1
Note: Turn off the 802.1q VLAN mode (reg0x5, bit
7 = 0) for this bit to work.
0
Sniff Mode Select
October 2011
1, will do Rx AND Tx sniff (both source port and
destination port need to match).
0, will do Rx OR Tx sniff (Either source port or
destination port needs to match).
This is the mode used to implement Rx only sniff.
49
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KSZ8895MLU
Global Registers (Continued)
Register 6 (007): Global Control 4
Address
7
6
5
Name
Description
Switch SW5-MII Back Pressure
Enable
1, enable half-duplex back pressure on switch MII
interface.
0, disable back pressure on switch MII interface.
Switch SW5-MII Half-Duplex
Mode
Switch SW5-MII Flow Control
Enable
1, enable MII interface half-duplex mode.
0, enable MII interface full-duplex mode.
1, enable full-duplex flow control on switch MII
interface.
0, disable full-duplex flow control on switch MII
interface.
Mode
Default
R/W
0
R/W
Pin SMRXD2
strap option.
PD(0): (default)
Full-duplex
mode.
PU(1): Halfduplex mode.
Note: SMRXD2
has internal pulldown.
R/W
Pin SMRXD3
strap option.
PD(0): (default)
Disable flow
control.
PU(1): enable
flow control.
Note: SMRXD3
has internal pulldown.
4
Switch SW5-MII Speed
1, the switch SW5-MII is in 10Mbps mode.
0, the switch SW5-MII is in 100Mbps mode.
R/W
Pin SMRXD1
strap option.
PD(0): (default)
Enable
100Mbps.
PU(1): Enable
10Mbps.
Note: SMRXD1
has internal pulldown.
3
Null VID Replacement
1, will replace null VID with port VID (12 bits).
0, no replacement for null VID.
R/W
0
Broadcast Storm
Protection Rate Bit [10:8]
This along with the next register determines how
many
“64 byte blocks” of packet data allowed on an
input port in a preset period. The period is 50ms
for 100BT or 500ms for 10BT. The default is 1%.
R/W
000
20
October 2011
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KSZ8895MLU
Global Registers (Continued)
Register 7 (007): Global Control 5
Address
70
Name
Description
Mode
Broadcast Storm
Protection Rate Bit [7:0]
This along with the previous register determines
how many “64 byte blocks” of packet data are
allowed on an input port in a preset period. The
period is 50ms for
100BT or 500ms for 10BT. The default is 1%.
R/W
Default
0x4A
(1)
Note:
1. 148,800 frames/sec 1% = 74 frames/interval (approx.) = 0 4A.
Register 8 (008): Global Control 6
Address
70
Name
Description
Factory Testing
Reserved
Mode
Default
R/W
0 24
Mode
Default
R/W
0 28
Mode
Default
R/W
0 00
Mode
Default
Register 9 (009): Global Control 7
Address
70
Name
Description
Factory Testing
Reserved
Register 10 (00A): Global Control 8
Address
70
Name
Description
Factory Testing
Reserved
Register 11 (00B): Global Control 9
Address
Name
Description
7
Reversed
N/A Don’t change
RO
0
6
Reserved
N/A Don’t change
RO
0
5
Reserved
N/A Don’t change
RO
0
4
Reserved
N/A Don’t change
RO
0
3
PHY Power Save
1 = disable PHY power-save mode.
0 = enable PHY power-save mode.
R/W
0
2
Reserved
N/A Don’t change
RO
0
October 2011
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Global Registers (Continued)
Register 11 (00B): Global Control 9
Address
Name
Description
Mode
Default
R/W
Pin SMRXD0 strap option. Pulldown(0):
Enabled led
mode 0. Pullup(1): Enabled
led mode 1.
Note: SMRXD0
has internal pulldown 0.
R/W
0
0 = led mode 0.
1 = led mode 1.
Mode 0, link at
100/Full LEDx[2,1,0]=0,0,0
LEDx[2,1,0]=0,1,0
100/Half
10/Full LEDx[2,1,0]=0,0,1
LEDx[2,1,0]=0,1,1
10/Half
Mode 1, link at
1
LED Mode
100/Full LEDx[2,1,0]=0,1,0
LEDx[2,1,0]=0,1,1
100/Half
10/Full LEDx[2,1,0]=1,0,0
LEDx[2,1,0]=1,0,1
(0=LED on, 1=LED off)
10/Half
Mode 0
Mode 1
LEDX_2
Lnk/Act
100Lnk/Act
LEDX_1
Fulld/Col
10Lnk/Act
LEDX_0
Speed
Fulld
Select the SPI/SMI clock edge for sampling
SPI/SMI read data
0
SPI/SMI Read Sampling Clock
Edge Select
October 2011
1 = trigger by rising edge of SPI/SMI clock (for
high speed SPI about 25MHz and SMI about
10MHz)
0 = trigger by falling edge of SPI/SMI clock
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KSZ8895MLU
Global Registers (Continued)
Register 12 (00C): Global Control 10
Address
Name
Description
7
Reserved
6
Reserved
54
CPU interface clock select
Mode
Default
N/A Don’t change
RO
0
N/A Don’t change
RO
1
R/W
01
Select the internal clock speed for SPI, MDI
interface:
00 = 41.67MHz (SPI up to 6.25MHz, MDC up to
6MHz)
01 = 83.33MHz Default (SPI SCL up to 12.5MHz,
MDC up to 12MHz)
10 = 125MHz (for high-speed SPI about 25MHz)
11 = Reserved
Note: The internal clock speeds of 83.33 or
125MHz must be selected when the chip is set in
Turbo-MII mode.
3
Reserved
N/A
RO
00
2
Reserved
N/A Don’t change
RO
1
1
Tail Tag Enable
Tail Tag feature is applied for Port 5 only.
1 = Insert 1 Byte of data right before FCS
0 = Do not insert
R/W
0
0
Pass Flow Control Packet
1 = Switch will not filter 802.1x “flow control”
packets
0 = Switch will filter 802.1x “flow control” packets
R/W
0
Mode
Default
RO
00000000
Register 13 (00D): Global Control 11
Address
70
Name
Description
Factory Testing
N/A Don’t change
October 2011
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Micrel, Inc.
KSZ8895MLU
Global Registers (Continued)
Register 14 (00E): Power-Down Management Control 1
Address
Name
Description
7
Reserved
6
Reserved
5
PLL Power Down
Mode
Default
N/A Don’t change
RO
0
N/A Don’t change
RO
0
R/W
0
Pll power down:
1 = Disable
0 = Enable
Note: It takes the effect in the Energy Detect
mode (EDPD mode).
00
43
Power Management Mode
Power management mode:
00 = Normal mode (D0)
01 = Energy Detection mode (D2)
10 = soft Power Down mode (D3)
11 = Power Saving mode (D1)
R/W
Pin LED[4][0]
strap option.
PD(0): Select
Energy detection
mode
PU(1): (default)
Normal mode
Note: LED[4][0]
has internal pullup.
Register 14 (00E): Power-Down Management Control 1
Address
Name
Description
Mode
Default
21
Reserved
N/A Don’t change
R/W
00
0
Reserved
N/A Don’t change
RO
0
Mode
Default
R/W
01010000
Register 15 (00F): Power-Down Management Control 2
Address
7-0
Name
Description
Go_sleep_time[7:0]
When the Energy Detect mode is on, this value is
used to control the minimum period that the no
energy event has to be detected consecutively
before the device enters the low power state. The
unit is 20 ms. The default of go_sleep time is 1.6
seconds (80Dec x 20ms).
October 2011
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KSZ8895MLU
Port Registers
The following registers are used to enable features that are assigned on a per port basis. The register bit assignments are
the same for all ports, but the address for each port is different, as indicated:
Register 16 (010): Port 1 Control 0
Register 32 (020): Port 2 Control 0
Register 48 (030): Port 3 Control 0
Register 64 (040): Port 4 Control 0
Register 80 (050): Port 5 Control 0
Address
Name
Description
7
Broadcast Storm Protection
Enable
6
5
43
2
1
Mode
Default
1, enable broadcast storm protection for ingress
packets on the port.
0, disable broadcast storm protection.
R/W
0
DiffServ Priority Classification
Enable
1, enable DiffServ priority classification for ingress
packets on port.
0, disable DiffServ function.
R/W
0
802.1p Priority Classification
Enable
1, enable 802.1p priority classification for ingress
packets on port.
0, disable 802.1p.
R/W
0
Port-Based Priority
Classification Enable
= 00, ingress packets on port will be classified as
priority 0 queue if “Diffserv” or “802.1p” classification
is not enabled or fails to classify.
= 01, ingress packets on port will be classified as
priority 1 queue if “Diffserv” or “802.1p” classification
is not enabled or fails to classify.
= 10, ingress packets on port will be classified as
priority 2 queue if “Diffserv” or “802.1p” classification
is not enabled or fails to classify.
= 11, ingress packets on port will be classified as
priority 3 queue if “Diffserv” or “802.1p” classification
is not enabled or fails to classify.
Note: “DiffServ”, “802.1p” and port priority can be
enabled at the same time. The OR’d result of
802.1p and DSCP overwrites the port priority.
R/W
00
Tag Insertion
1, when packets are output on the port, the switch
will add 802.1q tags to packets without 802.1q tags
when received. The switch will not add tags to
packets already tagged. The tag inserted is the
ingress port’s “port VID.”
0, disable tag insertion.
R/W
0
Tag Removal
1, when packets are output on the port, the switch
will remove 802.1q tags from packets with 802.1q
tags when received. The switch will not modify
packets received without tags.
0, disable tag removal.
R/W
0
October 2011
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Micrel, Inc.
KSZ8895MLU
Port Registers (Continued)
Register 16 (010): Port 1 Control 0
Register 32 (020): Port 2 Control 0
Register 48 (030): Port 3 Control 0
Register 64 (040): Port 4 Control 0
Register 80 (050): Port 5 Control 0
Address
0
Name
Description
Two Queues Split Enable
This bit0 in the register16/32/48/64/80 should be
combination with Register177/193/209/225/241 bit 1
for port 1-5 will select the split of 1/2/4 queues:
For port 1, [Register177 bit 1, Register16 bit 0] =
[11], Reserved
[10], the port output queue is split into four priority
queues or if map 802.1p to priority 0-3 mode.
[01], the port output queue is split into two priority
queues or if map 802.1p to priority 0-3 mode.
[00], single output queue on the port. There is no
priority differentiation even though packets are
classified into high or low priority.
Mode
Default
R/W
0
Register 17 (011): Port 1 Control 1
Register 33 (021): Port 2 Control 1
Register 49 (031): Port 3 Control 1
Register 65 (041): Port 4 Control 1
Register 81 (051): Port 5 Control 1
Address
Name
7
Sniffer Port
6
Receive Sniff
5
Transmit Sniff
40
Port VLAN Membership
October 2011
Description
1, port is designated as sniffer port and will transmit packets that are
monitored.
0, port is a normal port.
1, all the packets received on the port will be marked as “monitored
packets” and forwarded to the designated “sniffer port.”
0, no receive monitoring.
1, all the packets transmitted on the port will be marked as “monitored
packets” and forwarded to the designated “sniffer port.”
0, no transmit monitoring.
Define the port’s Port VLAN membership. Bit 4 stands for port 5, bit 3
for port 4...bit 0 for port 1. The port can only communicate within the
membership. A ‘1’ includes a port in the membership; a ‘0’ excludes a
port from membership.
56
Mode
Default
R/W
0
R/W
0
R/W
0
R/W
0x1f
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Micrel, Inc.
KSZ8895MLU
Port Registers (Continued)
Register 18 (012): Port 1 Control 2
Register 34 (022): Port 2 Control 2
Register 50 (032): Port 3 Control 2
Register 66 (042): Port 4 Control 2
Register 82 (052): Port 5 Control 2
Address
Name
7
User Priority Ceiling
6
Ingress VLAN Filtering.
5
Discard Non-PVID
packets
October 2011
Description
1, If packet ‘s “user priority field” is greater than the “user
priority field” in the port default tag register, replace the
packet’s “user priority field” with the “user priority field” in
the port default tag register control 3.
0, no replace packet’s priority filed with port default tag
priority filed of the port register control 3 bit [7:5].
1, the switch will discard packets whose VID port
membership in VLAN table bit[20:16] does not include
the ingress port.
0, no ingress VLAN filtering.
1, the switch will discard packets whose VID does not
match ingress port default VID.
0, no packets will be discarded.
57
Mode
Default
R/W
0
R/W
0
R/W
0
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Micrel, Inc.
KSZ8895MLU
Port Registers (Continued)
Register 18 (012): Port 1 Control 2
Register 34 (022): Port 2 Control 2
Register 50 (032): Port 3 Control 2
Register 66 (042): Port 4 Control 2
Register 82 (052): Port 5 Control 2
Address
Name
Description
Mode
Default
0
4
Force Flow Control
1, will always enable Rx and Tx flow control on the port,
regardless of AN result.
0, the flow control is enabled based on AN result
(Default)
R/W
Strap-in option
LED1_1/PCOL For
port 3/port 4
LED1_1 default
Pull up (1): Not
force flow control;
PCOL default Pulldown (0): Not force
flow control.
LED1_1 Pull down
(0): Force flow
control; PCOL Pullup (1): Force flow
control.
Note: LED1_1 has
internal pull-up;
PCOL have internal
pull-down.
0
Pin PMRXD2 strap
option.
Pull-down (0):
disable back
pressure.
Pull-up(1): enable
back pressure.
Note: PMRXD2
has internal pulldown.
3
Back Pressure Enable
1, enable port half-duplex back pressure.
0, disable port half-duplex back pressure.
R/W
2
Transmit Enable
1, enable packet transmission on the port.
0, disable packet transmission on the port.
R/W
1
1
Receive Enable
1, enable packet reception on the port.
0, disable packet reception on the port.
R/W
1
0
Learning Disable
1, disable switch address learning capability.
0, enable switch address learning.
R/W
0
October 2011
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KSZ8895MLU
Port Registers (Continued)
Register 19 (013): Port 1 Control 3
Register 35 (023): Port 2 Control 3
Register 51 (033): Port 3 Control 3
Register 67 (043): Port 4 Control 3
Register 83 (053): Port 5 Control 3
Address
70
Name
Description
Default Tag [15:8]
Port’s default tag, containing:
7 5: user priority bits
4: CFI bit
3 0 : VID[11:8]
Mode
Default
R/W
0
Mode
Default
R/W
1
Register 20 (014): Port 1 Control 4
Register 36 (024): Port 2 Control 4
Register 52 (034): Port 3 Control 4
Register 68 (044): Port 4 Control 4
Register 84 (054): Port 5 Control 4
Address
70
Name
Description
Default Tag [7:0]
Default port 1’s tag, containing:
7 0: VID[7:0]
Note:
Registers 19 and 20 (and those corresponding to other ports) serve two purposes: (1) Associated with the ingress untagged packets, and used for
egress tagging; (2) Default VID for the ingress untagged or null-VID-tagged packets, and used for address look up.
Register 87 (057): Reserved Control Register
Address
70
Name
Description
Reserved
N/A Don’t change
October 2011
59
Mode
Default
RO
0 00
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Micrel, Inc.
KSZ8895MLU
Port Registers (Continued)
Register 25 (019): Port 1 Status 0
Register 41 (029): Port 2 Status 0
Register 57 (039): Port 3 Status 0
Register 73 (049): Port 4 Status 0
Register 89 (059): Reserved
Address
Name
Description
Mode
Default
7
Hp_mdix
1 = HP Auto MDI/MDI-X mode
0 = Micrel Auto MDI/MDI-X mode
R/W
1
6
Factory Testing
Reserved
RO
0
5
Polrvs
1 = Polarity is reversed
0 = Polarity is not reversed
RO
0
4
Transmit Flow Control
Enable
1 = Transmit flow control feature is active
0 = Transmit flow control feature is inactive
RO
0
3
Receive Flow Control
Enable
1 = Receive flow control feature is active
0 = Receive flow control feature is inactive
RO
0
2
Operation Speed
1 = Link speed is 100Mbps
0 = Link speed is 10Mbps
RO
0
1
Operation Duplex
1 = Link duplex is full
0 = Link duplex is half
RO
0
0
Reserved
N/A
RO
0
Mode
Default
Register 26 (01A): Port 1 PHY Special Control/Status
Register 42 (02A): Port 2 PHY Special Control/Status
Register 58 (03A): Port 3 PHY Special Control/Status
Register 74 (04A): Port 4 PHY Special Control/Status
Register 90 (05A): Reserved
Address
74
Name
Description
Reserved
N/A Don’t change
RO
0000
3
Force_lnk
1 = Force link pass
0 = Normal Operation
R/W
0
2
Pwrsave
1 = Enable power saving
0 = Disable power saving
R/W
0
1
Remote Loopback
1 = Perform Remote loopback, loopback on port 1 as
follows:
Port 1 (reg. 26, bit 1 = ‘1’)
Start: RXP1/RXM1 (port 1)
Loopback: PMD/PMA of port 1’s PHY
End: TXP1/TXM1 (port 1)
Setting reg. 42, 58, 74, 90, bit 1 = ‘1’ will perform
remote loopback on port 2, 3, 4, 5.
0 = Normal Operation.
R/W
0
0
Reserved
N/A Don’t change
RO
0
October 2011
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KSZ8895MLU
Port Registers (Continued)
Register 27 (01B): Reserved
Register 43 (02B): Reserved
Register 59 (03B): Reserved
Register 75 (04B): Reserved
Register 91 (05B): Reserved
Address
70
Name
Description
Reserved
N/A Don’t change
Mode
Default
RO
0x00
Register 28 (01C): Port 1 Control 5
Register 44 (02C): Port 2 Control 5
Register 60 (03C): Port 3 Control 5
Register 76 (04C): Port 4 Control 5
Register 92 (05C): Reserved
Address
Name
Description
Mode
Default
0
7
Disable AutoNegotiation
1, disable auto-negotiation, speed and duplex are
decided by bit 6 and 5 of the same register.
0, auto-negotiation is on.
R/W
Note: The register bit value is the INVERT of the
strap value at the pin.
6
Forced Speed
1, forced 100BT if AN is disabled (bit 7).
0, forced 10BT if AN is disabled (bit 7).
R/W
For port 3/port 4 only.
INVERT of pins
LED[2][1]/LED[5][0]
strap option.
PD(0): Disable AutoNegotiation.
PU(1): Enable AutoNegotiation.
Note:LED[2][1]/LED[5][0]
have internal pull up.
1
0
5
Forced Duplex
October 2011
1, forced full-duplex if (1) AN is disabled or (2) AN
is enabled but failed.
0, forced half-duplex if (1) AN is disabled or (2) AN
is enabled but failed (Default).
61
R/W
For port 3/port 4 only.
Pins LED1_0/PCRS
strap option.
1. For force half-duplex:
LED1_0 pin Pull-up(1)
(default)
PCRS pin Pull-down (0)
(default). 2. For force
full-duplex: LED1_0 pin
Pull-down(0).
PCRS Pull-up (1):
Note: LED1_0 has
internal pull-up; PCRS
have internal pull down.
M9999-100311-1.1
Micrel, Inc.
KSZ8895MLU
Port Registers (Continued)
Register 28 (01C): Port 1 Control 5
Register 44 (02C): Port 2 Control 5
Register 60 (03C): Port 3 Control 5
Register 76 (04C): Port 4 Control 5
Register 92 (05C): Reserved
Address
Name
Description
Mode
Default
4
Advertised Flow Control
Capability
1, advertise flow control capability.
0, suppress flow control capability from transmission to
link partner.
R/W
1
3
Advertised 100BT FullDuplex Capability
1, advertise 100BT full-duplex capability.
0, suppress 100BT full-duplex capability from
transmission to link partner.
R/W
1
2
Advertised 100BT HalfDuplex Capability
1, advertise 100BT half-duplex capability.
0, suppress 100BT half-duplex capability from
transmission to link partner.
R/W
1
1
Advertised 10BT FullDuplex Capability
1, advertise 10BT full-duplex capability.
0, suppress 10BT full-duplex capability from
transmission to link partner.
R/W
1
0
Advertised 10BT HalfDuplex Capability
1, advertise 10BT half-duplex capability.
0, suppress 10BT half-duplex capability from
transmission to link partner.
R/W
1
Mode
Default
Register 29 (01D): Port 1 Control 6
Register 45 (02D): Port 2 Control 6
Register 61 (03D): Port 3 Control 6
Register 77 (04D): Port 4 Control 6
Register 93 (05D): Reserved
Address
Name
Description
7
LED Off
1, turn off all port’s LEDs (LEDx_2, LEDx_1, LEDx_0,
where “x” is the port number). These pins will be
driven high if this bit is set to one.
0, normal operation.
R/W
0
6
Txids
1, disable port’s transmitter.
0, normal operation.
R/W
0
5
Restart AN
1, restart auto-negotiation.
0, normal operation.
R/W
(SC)
0
4
FX reserved
N/A
RO
0
3
Power Down
1, power down.
0, normal operation.
R/W
0
2
Disable Auto MDI/MDI-X
1, disable auto MDI/MDI-X function.
0, enable auto MDI/MDI-X function.
R/W
0
1
Forced MDI
1, if auto MDI/MDI-X is disabled, force PHY into MDIX
mode.
0, MDI mode.
R/W
0
October 2011
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Micrel, Inc.
KSZ8895MLU
Port Registers (Continued)
Register 29 (01D): Port 1 Control 6
Register 45 (02D): Port 2 Control 6
Register 61 (03D): Port 3 Control 6
Register 77 (04D): Port 4 Control 6
Register 93 (05D): Reserved
Address
Mode
Default
1 = Perform MAC loopback, loop back path as follows:
E.g. set port 1 MAC Loopback (reg. 29, bit 0 = ‘1’), use
port 2 as monitor port. The packets will transfer
Start: Port 2 receiving (also can start to receive
packets from port 3, 4, 5).
Loop-back: Port 1’s MAC.
End: Port 2 transmitting (also can end at port 3, 4,
5 respectively).
Setting reg. 45, 61, 77, 93, bit 0 = ‘1’ will perform MAC
loopback on port 2, 3, 4, 5 respectively.
0 = Normal Operation.
R/W
0
Name
Description
Mode
Default
7
MDIX Status
1, MDIX.
0, MDI.
RO
0
6
AN Done
1, AN done.
0, AN not done.
RO
0
5
Link Good
1, link good.
0, link not good.
RO
0
4
Partner Flow Control
Capability
1, link partner flow control capable.
0, link partner not flow control capable.
RO
0
3
Partner 100BT FullDuplex Capability
1, link partner 100BT full-duplex capable.
0, link partner not 100BT full-duplex capable.
RO
0
2
Partner 100BT HalfDuplex Capability
1, link partner 100BT half-duplex capable.
0, link partner not 100BT half-duplex capable.
RO
0
1
Partner 10BT Full-Duplex
Capability
1, link partner 10BT full-duplex capable.
0, link partner not 10BT full-duplex capable.
RO
0
0
Partner 10BT Half-Duplex
Capability
1, link partner 10BT half-duplex capable.
0, link partner not 10BT half-duplex capable.
RO
0
0
Name
Description
MAC Loopback
Register 30 (01E): Port 1 Status 1
Register 46 (02E): Port 2 Status 1
Register 62 (03E): Port 3 Status 1
Register 78 (04E): Port 4 Status 1
Register 94 (05E): Reserved
Address
October 2011
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Micrel, Inc.
KSZ8895MLU
Port Registers (Continued)
Register 31 (01F): Port 1 Control 7 and Status 2
Register 47 (02F): Port 2 Control 7 and Status 2
Register 63 (03F): Port 3 Control 7 and Status 2
Register 79 (04F): Port 4 Control 7 and Status 2
Register 95 (05F): Reserved
Address
Name
Description
7
PHY Loopback
1 = Perform PHY loopback, loop back path as follows:
E.g. set port 1 PHY Loopback (reg. 31, bit 7 = ‘1’)
Use the port 2 as monitor port. The packets will transfer
Start: Port 2 receiving (also can start from port 3, 4,
5).
Loopback: PMD/PMA of port 1’s PHY
End: Port 2 transmitting (also can end at port 3, 4,
5 respectively).
Setting reg. 47, 63, 79, 95, bit 7 = ‘1’ will perform PHY
loopback on port 2, 3, 4, 5 respectively.
0 = Normal Operation.
6
Reserved
5
PHY Isolate
4
3
20
Mode
Default
R/W
0
RO
0
1, electrical isolation of PHY from MII and TX+/TX-.
0, normal operation.
R/W
0
Soft Reset
1, PHY soft reset. This bit is self clear.
0, normal operation.
R/W
(SC)
0
Force Link
1, force link in the PHY.
0, normal operation
R/W
0
Port Operation Mode
Indication
Indicate the current state of port operation mode:
[000] = Reserved
[001] = Still in auto-negotiation
[010] = 10BASE-T half duplex
[011] = 100BASE-TX/FX half duplex
[100] = Reserved
[101] = 10BASE-T full duplex
[110] = 100BASE-TX/FX full duplex
[111] = Reserved
RO
001
Note:
Port Control 12 and 13, 14 and Port Status 1, 2 contents can be accessed by MIIM (MDC/MDIO) interface via the standard MIIM register definition.
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Advanced Control Registers
Registers 104 to 109 define the switching engine’s MAC address. This 48-bit address is used as the source address in
MAC pause control frames.
Register 104 (068): MAC Address Register 0
Address
70
Name
Description
MACA[47:40]
Mode
Default
R/W
0x00
Mode
Default
R/W
0x10
Mode
Default
R/W
0xA1
Mode
Default
R/W
0xff
Mode
Default
R/W
0xff
Mode
Default
R/W
0xff
Register 105 (069): MAC Address Register 1
Address
70
Name
Description
MACA[39:32]
Register 106 (06A): MAC Address Register 2
Address
70
Name
Description
MACA[31:24]
Register 107 (06B): MAC Address Register 3
Address
70
Name
Description
MACA[23:16]
Register 108 (06C): MAC Address Register 4
Address
70
Name
Description
MACA[15:8]
Register 109 (06D): MAC Address Register 5
Address
70
Name
Description
MACA[7:0]
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Advanced Control Registers (Continued)
Use registers 110 and 111 to read or write data to the static MAC address table, VLAN table, dynamic address table, or
the MIB counters.
Register 110 (06E): Indirect Access Control 0
Address
75
Name
Description
Mode
Default
Reserved
Reserved.
R/W
000
Read High Write Low
1, read cycle.
0, write cycle.
R/W
0
32
Table Select
00 = Static MAC address table selected.
01 = VLAN table selected.
10 = Dynamic address table selected.
11 = MIB counter selected.
R/W
0
10
Indirect Address High
Bit 9 8 of indirect address.
R/W
00
Mode
Default
R/W
00000000
Mode
Default
R/W
00000
Mode
Default
R/W
00000000
Mode
Default
R/W
00000000
Mode
Default
R/W
00000000
Mode
Default
R/W
00000000
4
Register 111 (06F): Indirect Access Control 1
Address
70
Name
Description
Indirect Address Low
Bit 7 0 of indirect address.
Note:
Write to Register 111 will actually trigger a command. Read or write access will be decided by bit 4 of Register 110.
Register 112 (070): Indirect Data Register 8
Address
Name
Description
68 64
Indirect Data
Bit 68 64 of indirect data.
Register 113 (071): Indirect Data Register 7
Address
Name
Description
63 56
Indirect Data
Bit 63 56 of indirect data.
Register 114 (072): Indirect Data Register 6
Address
Name
Description
55 48
Indirect Data
Bit 55 48 of indirect data.
Register 115 (073): Indirect Data Register 5
Address
Name
Description
47 40
Indirect Data
Bit 47 40 of indirect data.
Register 116 (074): Indirect Data Register 4
Address
Name
Description
39 32
Indirect Data
Bit 39 32 of indirect data.
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Advanced Control Registers (Continued)
Use registers 110 and 111 to read or write data to the static MAC address table, VLAN table, dynamic address table, or
the MIB counters.
Register 117 (075): Indirect Data Register 3
Address
Name
Description
31 24
Indirect Data
Bit of 31 24 of indirect data
Mode
Default
R/W
00000000
Mode
Default
R/W
00000000
Mode
Default
R/W
00000000
Mode
Default
R/W
00000000
Mode
Default
Register 118 (076): Indirect Data Register 2
Address
Name
Description
23 16
Indirect Data
Bit 23 16 of indirect data.
Register 119 (077): Indirect Data Register 1
Address
Name
Description
15 8
Indirect Data
Bit 15 8 of indirect data.
Register 120 (078): Indirect Data Register 0
Address
70
Name
Description
Indirect Data
Bit 7 0 of indirect data.
Register 124 (0x7C): Interrupt Status Register
Address
Name
Description
75
Reserved
Reserved
RO
000
4
Reserved
Reserved
RO
0
RO
0
RO
0
RO
0
RO
0
1, Port 4 interrupt request
0, normal
3
Port 4 Interrupt Status
Note: This bit is set by port 4 link change. Write a “1”
to clear this bit
1, Port 3 interrupt request
0, normal
2
Port 3 Interrupt Status
Note: This bit is set by port 3 link change. Write a “1”
to clear this bit
1, Port 2 interrupt request
0, normal
1
Port 2 Interrupt Status
Note: This bit is set by port 2 link change. Write a “1”
to clear this bit
1, Port 1 interrupt request
0, normal
0
Port 1 Interrupt Status
Note: This bit is set by port 1 link change. Write a “1”
to clear this bit
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Advanced Control Registers (Continued)
Use registers 110 and 111 to read or write data to the static MAC address table, VLAN table, dynamic address table, or
the MIB counters.
Register 125 (0x7D): Interrupt Mask Register
Address
Name
Description
Mode
Default
75
Reserved
Reserved.
RO
000
4
Reserved
Reserved
RO
0
3
Port 4 Interrupt Mask
1, Port 4 interrupt mask
0, normal
R/W
0
2
Port 3 Interrupt Mask
1, Port 3 interrupt mask
0, normal
R/W
0
1
Port 2 Interrupt Mask
1, Port 2 interrupt mask
0, normal
R/W
0
0
Port 1 Interrupt Mask
1, Port 1 interrupt mask
0, normal
R/W
0
The registers 128, 129 can be used to map from 802.1p priority field 0-7 to switch’s four priority queues 0-3, 0x3 is highest
priority queues as priority 3, 0x0 is lowest priority queues as priority 0.
Register 128 (0x80): Global Control 12
Address
Name
Description
Mode
Default
7-6
Tag_0x3
IEEE 802.1p mapping. The value in this field is
used as the frame’s priority when its IEEE 802.1p
tag has a value of 0x3
R/W
0x1
5-4
Tag_0x2
IEEE 802.1p mapping. The value in this field is
used as the frame’s priority when its IEEE 802.1p
tag has a value of 0x2
R/W
0x1
3-2
Tag_0x1
IEEE 802.1p mapping. The value in this field is
used as the frame’s priority when its IEEE 802.1p
tag has a value of 0x1
R/W
0x0
1-0
Tag_0x0
IEEE 802.1p mapping. The value in this field is
used as the frame’s priority when its IEEE 802.1p
tag has a value of 0x0
R/W
0x0
Mode
Default
Register 129 (0x81): Global Control 13
Address
Name
Description
7-6
Tag_0x7
IEEE 802.1p mapping. The value in this field is
used as the frame’s priority when its IEEE 802.1p
tag has a value of 0x7
R/W
0x3
5-4
Tag_0x6
IEEE 802.1p mapping. The value in this field is
used as the frame’s priority when its IEEE 802.1p
tag has a value of 0x6
R/W
0x3
3-2
Tag_0x5
IEEE 802.1p mapping. The value in this field is
used as the frame’s priority when its IEEE 802.1p
tag has a value of 0x5
R/W
0x2
1-0
Tag_0x4
IEEE 802.1p mapping. The value in this field is
used as the frame’s priority when its IEEE 802.1p
tag has a value of 0x4
R/W
0x2
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Advanced Control Registers (Continued)
Register 130 (0x82): Global Control 14
Address
Name
Description
Mode
Default
R/W
10
When the 2 Queue configuration is selected, these
Pri_2Q[1:0] bits are used to map the 2-bit result of
IEEE 802.1p from register 128/129 or TOS/DiffServ
from register 144- 159 mapping (for 4 Queues) into
two queues low/high priorities.
Pri_2Q[1:0]
76
(Note that program
Prio_2Q[1:0] = 01 is not
supported and should be
avoided)
2-bit result of IEEE 802.1p or TOS/DiffServ
00 (0) = map to Low priority queue
01 (1) = Prio_2Q[0] map to Low/High priority queue
10 (2) = Prio_2Q[1] map to Low/High priority queue
11 (3) = map to High priority queue
Pri_2Q[1:0] =
00: Result 0, 1, 2 are low priority. 3 is high priority.
10: Result 0, 1 are low priority. 2, 3 are high priority
(default).
11: Result 0 is low priority. 1, 2, 3 are high priority.
5
Reserved
N/A Don’t change
RO
0
4
Reserved
N/A Don’t change
RO
0
32
Reserved
N/A Don’t change
RO
01
1
Reserved
N/A Don’t change
RO
0
0
Reserved
N/A Don’t change
RO
0.
Mode
Default
Register 131 (0x83): Global Control 15
Address
Name
Description
7
Reserved
N/A
RO
0
6
Reserved
N/A
RO
0
5
Unknown unicast packet
forward
1 = enable supporting unknown unicast packet
forward
0 = disable
R/W
0
Unknown unicast packet
forward port map
00000 = filter unknown unicast packet
00001 = forward unknown unicast packet to port 1
00011 = forward unknown unicast packet to port 1,
port 2
…
11111 = broadcast unknown unicast packet to all
ports
R/W
00000
40
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Advanced Control Registers (Continued)
Register 132 (0x84): Global Control 16
Address
76
Name
Chip I/O output drive strength
select[1:0]
Description
Output drive strength select[1:0] =
00 = 4mA drive strength
01 = 8mA drive strength (default)
10 = 12mA drive strength
11 = 16mA drive strength
Mode
Default
R/W
Pin LED[3][0]
strap option. Pulldown (0): Select
12mA drive
strength. Pull-up
(1): Select 8mA
drive strength.
Note: LED[3][0]
has internal pullup.
Note:
bit[1] value is the INVERT of the strap value at the
pin.
bit[0] value is the SAME of the strap value at the pin
5
40
Unknown multicast packet
forward (not including IP
multicast packet)
1 = enable supporting unknown multicast packet
forward
0 = disable
R/W
0
Unknown multicast packet
forward port map
00000 = filter unknown multicast packet
00001 = forward unknown multicast packet to port 1
00011 = forward unknown multicast packet to port 1,
port 2
…
11111 = broadcast unknown multicast packet to all
ports
R/W
00000
Register 133(0x85): Global Control 17
Address
7-6
5
4-0
Name
Description
Reserved
Mode
Default
RO
00
Unknown VID packet forward
1 = enable supporting unknown VID packet forward
0 = disable
R/W
0
Unknown VID packet forward
port map
00000 = filter unknown VID packet
00001 = forward unknown VID packet to port 1
00011 = forward unknown VID packet to port 1, port
2
…
11111 = broadcast unknown VID packet to all ports
R/W
00000
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Advanced Control Registers (Continued)
Register 134 (0x86): Global Control 18
Address
7
Name
Description
Reserved
N/A
Mode
Default
RO
0
R/W
0
1 = Enable filtering of self-address unicast and
multicast packet
0 = Do not filter self-address packet
6
Self Address Filter Enable
Note: The self-address filtering will filter packets on
the egress port, self MAC address is assigned in the
register 104 109.
5
40
Unknown IP multicast packet
forward
1 = enable supporting unknown IP multicast packet
forward
0 = disable
R/W
0
Unknown IP multicast packet
forward port map
00000 = filter unknown IP multicast packet
00001 = forward unknown IP multicast packet to port 1
00011 = forward unknown IP multicast packet to port
1, port 2
…
11111 = broadcast unknown IP multicast packet to all
ports
R/W
00000
Mode
Default
Register 135 (0x87): Global Control 19
Address
Name
Description
7
Reserved
N/A Don’t change
RO
0
6
Reserved
N/A Don’t change
RO
0
Ingress Rate Limit Period
The unit period for calculating Ingress Rate Limit
00 = 16 ms
01 = 64 ms
1x = 256 ms
R/W
01
Queue-based Egress Rate
Limit Enabled
Enable Queue-based Egress Rate Limit
0 = port-base Egress Rate Limit (default)
1 = queue-based Egress Rate Limit
R/W
0
Insertion Source Port PVID
Tag Selection Enable
1 = enable source port PVID tag insertion or noninsertion option on the egress port for each source port
PVID based on the ports registers control 8.
0 = disable, all packets from any ingress port will be
inserted PVID based on port register control 0 bit 2.
R/W
0
Reserved
N/A Don’t change
RO
00
54
3
2
10
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Advanced Control Registers (Continued)
Register 144 (0x90): TOS Priority Control Register 0
The IPv4/IPv6 TOS priority control registers implement a fully decoded 64 bit differentiated services code point (DSCP) register used to determine
priority from the 6 bit TOS field in the IP header. The most significant 6 bits of the TOS field are fully decoded into 64 possibilities, and the singular
code that results is mapped to the value in the corresponding bit in the DSCP register.
Address
76
54
32
10
Name
Description
Mode
Default
DSCP[7:6]
IPv4 and IPv6 mapping
The value in this field is used as the frame’s priority
when bits[7:2] of the frame’s IP TOS/DiffServ/Traffic
Class value is 0x0C
R/W
00
DSCP[5:4]
IPv4 and IPv6 mapping
The value in this field is used as the frame’s priority
when bits[7:2] of the frame’s IP TOS/DiffServ/Traffic
Class value is 0x08
R/W
00
DSCP[3:2]
IPv4 and IPv6 mapping
The value in this field is used as the frame’s priority
when bits[7:2] of the frame’s IP TOS/DiffServ/Traffic
Class value is 0x04
R/W
00
DSCP[1:0]
IPv4 and IPv6 mapping
The value in this field is used as the frame’s priority
when bits[7:2] of the frame’s IP TOS/DiffServ/Traffic
Class value is 0x00
R/W
00
Mode
Default
Register 145 (0x91): TOS Priority Control Register 1
Address
Name
Description
7 6
DSCP[15:14]
IPv4 and IPv6 mapping _ for value 0x1C
R/W
00
5 4
DSCP[13:12]
IPv4 and IPv6 mapping _ for value 0x18
R/W
00
3 2
DSCP[11:10]
IPv4 and IPv6 mapping _ for value 0x14
R/W
00
1 0
DSCP[9:8]
IPv4 and IPv6 mapping _ for value 0x10
R/W
00
Mode
Default
Register 146 (0x92): TOS Priority Control Register 2
Address
Name
Description
76
DSCP[23:22]
IPv4 and IPv6 mapping _ for value 0x2C
R/W
00
54
DSCP[21:20]
IPv4 and IPv6 mapping _ for value 0x28
R/W
00
32
DSCP[19:18]
IPv4 and IPv6 mapping _ for value 0x24
R/W
00
10
DSCP[17:16]
IPv4 and IPv6 mapping _ for value 0x20
R/W
00
Mode
Default
Register 147 (0x93): TOS Priority Control Register 3
Address
Name
Description
76
DSCP[31:30]
IPv4 and IPv6 mapping _ for value 0x3C
R/W
00
54
DSCP[29:28]
IPv4 and IPv6 mapping _ for value 0x38
R/W
00
32
DSCP[27:26]
IPv4 and IPv6 mapping _ for value 0x34
R/W
00
10
DSCP[25:24]
IPv4 and IPv6 mapping _ for value 0x30
R/W
00
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Advanced Control Registers (Continued)
Register 148 (0x94): TOS Priority Control Register 4
Address
Name
Description
Mode
Default
76
DSCP[39:38]
IPv4 and IPv6 mapping _ for value 0x4C
R/W
00
54
DSCP[37:36]
IPv4 and IPv6 mapping _ for value 0x48
R/W
00
32
DSCP[35:34]
IPv4 and IPv6 mapping _ for value 0x44
R/W
00
10
DSCP[33:32]
IPv4 and IPv6 mapping _ for value 0x40
R/W
00
Mode
Default
Register 149 (0x95): TOS Priority Control Register 5
Address
Name
Description
76
DSCP[47:46]
IPv4 and IPv6 mapping _ for value 0x5C
R/W
00
54
DSCP[45:44]
IPv4 and IPv6 mapping _ for value 0x58
R/W
00
32
DSCP[43:42]
IPv4 and IPv6 mapping _ for value 0x54
R/W
00
10
DSCP[41:40]
IPv4 and IPv6 mapping _ for value 0x50
R/W
00
Mode
Default
Register 150 (0x96): TOS Priority Control Register 6
Address
Name
Description
7 6
DSCP[55:54]
IPv4 and IPv6 mapping _ for value 0x6C
R/W
00
5 4
DSCP[53:52]
IPv4 and IPv6 mapping _ for value 0x68
R/W
00
3 2
DSCP[51:50]
IPv4 and IPv6 mapping _ for value 0x64
R/W
00
1 0
DSCP[49:48]
IPv4 and IPv6 mapping _ for value 0x60
R/W
00
Mode
Default
Register 151 (0x97): TOS Priority Control Register 7
Address
Name
Description
76
DSCP[63:62]
IPv4 and IPv6 mapping _ for value 0x7C
R/W
00
54
DSCP[61:60]
IPv4 and IPv6 mapping _ for value 0x78
R/W
00
32
DSCP[59:58]
IPv4 and IPv6 mapping _ for value 0x74
R/W
00
10
DSCP[57:56]
IPv4 and IPv6 mapping _ for value 0x70
R/W
00
Mode
Default
Register 152 (0x98): TOS Priority Control Register 8
Address
Name
Description
76
DSCP[71:70]
IPv4 and IPv6 mapping _ for value 0x8C
R/W
00
54
DSCP[69:68]
IPv4 and IPv6 mapping _ for value 0x88
R/W
00
32
DSCP[67:66]
IPv4 and IPv6 mapping _ for value 0x84
R/W
00
10
DSCP[65:64]
IPv4 and IPv6 mapping _ for value 0x80
R/W
00
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Advanced Control Registers (Continued)
Register 153 (0x99): TOS Priority Control Register 9
Address
Name
Description
Mode
Default
76
DSCP[79:78]
IPv4 and IPv6 mapping _ for value 0x9C
R/W
00
5 4
DSCP[77:76]
IPv4 and IPv6 mapping _ for value 0x98
R/W
00
32
DSCP[75:74]
IPv4 and IPv6 mapping _ for value 0x94
R/W
00
10
DSCP[73:72]
IPv4 and IPv6 mapping _ for value 0x90
R/W
00
Mode
Default
Register 154 (0x9A): TOS Priority Control Register 10
Address
Name
Description
76
DSCP[87:86]
IPv4 and IPv6 mapping _ for value 0xAC
R/W
00
54
DSCP[85:84]
IPv4 and IPv6 mapping _ for value 0xA8
R/W
00
32
DSCP[83:82]
IPv4 and IPv6 mapping _ for value 0xA4
R/W
00
10
DSCP[81:80]
IPv4 and IPv6 mapping _ for value 0xA0
R/W
00
Mode
Default
Register 155 (0x9B): TOS Priority Control Register 11
Address
Name
Description
76
DSCP[95:94]
IPv4 and IPv6 mapping _ for value 0xBC
R/W
00
54
DSCP[93:92]
IPv4 and IPv6 mapping _ for value 0xB8
R/W
00
32
DSCP[91:90]
IPv4 and IPv6 mapping _ for value 0xB4
R/W
00
10
DSCP[89:88]
IPv4 and IPv6 mapping _ for value 0xB0
R/W
00
Mode
Default
Register 156 (0x9C): TOS Priority Control Register 12
Address
Name
Description
76
DSCP[103:102]
IPv4 and IPv6 mapping _ for value 0xCC
R/W
00
54
DSCP[101:100]
IPv4 and IPv6 mapping _ for value 0xC8
R/W
00
32
DSCP[99:98]
IPv4 and IPv6 mapping _ for value 0xC4
R/W
00
10
DSCP[97:96]
IPv4 and IPv6 mapping _ for value 0xC0
R/W
00
Mode
Default
Register 157 (0x9D): TOS Priority Control Register 13
Address
Name
Description
76
DSCP[111:110]
IPv4 and IPv6 mapping _ for value 0xDC
R/W
00
54
DSCP[109:108]
IPv4 and IPv6 mapping _ for value 0xD8
R/W
00
32
DSCP[107:106]
IPv4 and IPv6 mapping _ for value 0xD4
R/W
00
10
DSCP[105:104]
IPv4 and IPv6 mapping _ for value 0xD0
R/W
00
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Advanced Control Registers (Continued)
Register 158 (0x9E): TOS Priority Control Register 14
Address
Name
Description
Mode
Default
76
DSCP[119:118]
IPv4 and IPv6 mapping _ for value 0xEC
R/W
00
5 4
DSCP[117:116]
IPv4 and IPv6 mapping _ for value 0xE8
R/W
00
32
DSCP[115:114]
IPv4 and IPv6 mapping _ for value 0xE4
R/W
00
10
DSCP[113:112]
IPv4 and IPv6 mapping _ for value 0xE0
R/W
00
Mode
Default
Register 159 (0x9F): TOS Priority Control Register 15
Address
Name
Description
76
DSCP[127:126]
IPv4 and IPv6 mapping _ for value 0xFC
R/W
00
54
DSCP[125:124]
IPv4 and IPv6 mapping _ for value 0xF8
R/W
00
32
DSCP[123:122]
IPv4 and IPv6 mapping _ for value 0xF4
R/W
00
10
DSCP[121:120]
IPv4 and IPv6 mapping _ for value 0xF0
R/W
00
Mode
Default
RO
0000
R/W
0
R/W
0
Register 176 (0xB0): Port 1 Control 8
Register 192 (0xC0): Port 2 Control 8
Register 208 (0xD0): Port 3 Control 8
Register 224 (0xE0): Port 4 Control 8
Register 240 (0xF0): Port 5 Control 8
Address
74
Name
Description
Reserved
Insert Source Port PVID for
Untagged Packet Destination
to Highest Egress Port
3
Note: Enabled by the register
135 bit 2
Insert Source Port PVID for
Untagged Packet Destination
to Second Highest Egress Port
2
Note: Enabled by the register
135 bit 2
October 2011
Register 176: insert source
frame at egress port 5
Register 192: insert source
frame at egress port 5
Register 208: insert source
frame at egress port 5
Register 224: insert source
frame at egress port 5
Register 240: insert source
frame at egress port 4
port 1 PVID for untagged
Register 176: insert source
frame at egress port 4
Register 192: insert source
frame at egress port 4
Register 208: insert source
frame at egress port 4
Register 224: insert source
frame at egress port 3
Register 240: insert source
frame at egress port 3
port 1 PVID for untagged
75
port 2 PVID for untagged
port 3 PVID for untagged
port 4 PVID for untagged
port 5 PVID for untagged
port 2 PVID for untagged
port 3 PVID for untagged
port 4 PVID for untagged
port 5 PVID for untagged
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KSZ8895MLU
Advanced Control Registers (Continued)
Register 176 (0xB0): Port 1 Control 8
Register 192 (0xC0): Port 2 Control 8
Register 208 (0xD0): Port 3 Control 8
Register 224 (0xE0): Port 4 Control 8
Register 240 (0xF0): Port 5 Control 8
Address
Name
Insert Source Port PVID for
Untagged Packet Destination
to Second Lowest Egress Port
1
Note: Enabled by the register
135 bit 2
Insert Source Port PVID for
Untagged Packet Destination
to Lowest Egress Port
0
Note: Enabled by the register
135 bit 2
Description
Mode
Default
Register 176: insert source port 1 PVID for untagged
frame at egress port 3
Register 192: insert source port 2 PVID for untagged
frame at egress port 3
Register 208: insert source port 3 PVID for untagged
frame at egress port 2
Register 224: insert source port 4 PVID for untagged
frame at egress port 2
Register 240: insert source port 5 PVID for untagged
frame at egress port 2
R/W
0
Register 176: insert source port 1 PVID for untagged
frame at egress port 2
Register 192: insert source port 2 PVID for untagged
frame at egress port 1
Register 208: insert source port 3 PVID for untagged
frame at egress port 1
Register 224: insert source port 4 PVID for untagged
frame at egress port 1
Register 240: insert source port 5 PVID for untagged
frame at egress port 1
R/W
0
Mode
Default
RO
0000000
R/W
0
R/W
0
Register 177 (0xB1): Port 1 Control 9
Register 193 (0xC1): Port 2 Control 9
Register 209 (0xD1): Port 3 Control 9
Register 225 (0xE1): Port 4 Control 9
Register 241 (0xF1): Port 5 Control 9
Address
72
Name
Description
Reserved
1
4 Queue Split Enable
This bit in combination with Register16/32/48/64/80 bit
0 will select the split of 1/2/4 queues:
{Register177 bit 1, Register16 bit 0}=
11, reserved.
10, the port output queue is split into four priority
queues or if map 802.1p to priority 0-3 mode.
01, the port output queue is split into two priority
queues or if map 802.1p to priority 0-3 mode.
00, single output queue on the port. There is no priority
differentiation even though packets are classified into
high and low priority
0
Enable Dropping Tag
0 = disable tag drop
1 = enable tag drop
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Advanced Control Registers (Continued)
Register 178 (0xB2): Port 1 Control 10
Register 194 (0xC2): Port 2 Control 10
Register 210 (0xD2): Port 3 Control 10
Register 226 (0xE2): Port 4 Control 10
Register 242 (0xF2): Port 5 Control 10
Address
7
6-0
Name
Description
Mode
Default
Enable Port Transmit Queue 3
Ratio
0, strict priority, will transmit all the packets from this
priority queue 3 before transmit lower priority queue.
1, bit[6:0] reflect the packet number allow to transmit
from this priority queue 3 within a certain time
R/W
1
Port Transmit Queue 3
Ratio[6:0]
Packet number for Transmit Queue 3 for highest
priority packets in four queues mode
R/W
0001000
Register 179 (0xB3): Port 1 Control 11
Register 195 (0xC3): Port 2 Control 11
Register 211 (0xD3): Port 3 Control 11
Register 227 (0xE3): Port 4 Control 11
Register 243 (0xF3): Port 5 Control 11
Address
7
60
Name
Description
Mode
Default
Enable Port Transmit Queue 2
Ratio
0, strict priority, will transmit all the packets from this
priority queue 2 before transmit lower priority queue.
1, bit[6:0] reflect the packet number allow to transmit
from this priority queue 1 within a certain time
R/W
1
Port Transmit Queue 2
Ratio[6:0]
Packet number for Transmit Queue 2 for high/low
priority packets in high/low priority packets in four
queues mode
R/W
0000100
Mode
Default
Register 180 (0xB4): Port 1 Control 12
Register 196 (0xC4): Port 2 Control 12
Register 212 (0xD4): Port 3 Control 12
Register 228 (0xE4): Port 4 Control 12
Register 244 (0xF4): Port 5 Control 12
Address
7
60
Name
Description
Enable Port Transmit Queue 1
Rate
0, strict priority, will transmit all the packets from this
priority queue 1 before transmit lower priority queue.
1, bit[6:0] reflect the packet number allow to transmit
from this priority queue 1 within a certain time
R/W
1
Port Transmit Queue 1
Ratio[6:0]
Packet number for Transmit Queue 1 for low/high
priority packets in four queues mode and high priority
packets in two queues mode
R/W
0000010
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Advanced Control Registers (Continued)
Register 181 (0xB5): Port 1 Control 13
Register 197 (0xC5): Port 2 Control 13
Register 213 (0xD5): Port 3 Control 13
Register 229 (0xE5): Port 4 Control 13
Register 245 (0xF5): Port 5 Control 13
Address
7
60
Name
Description
Mode
Default
Enable Port Transmit Queue 0
Rate
0, strict priority, will transmit all the packets from this
priority queue 0 before transmit lower priority queue.
1, bit[6:0] reflect the packet number allow to transmit
from this priority queue 0 within a certain time
R/W
1
Port Transmit Queue 0
Ratio[6:0]
packet number for Transmit Queue 0 for lowest priority
packets in four queues mode and low priority packets
in two queues mode
R/W
0000001
Mode
Default
RO
000
Register 182 (0xB6): Port 1 Rate Limit Control
Register 198 (0xC6): Port 2 Rate Limit Control
Register 214 (0xD6): Port 3 Rate Limit Control
Register 230 (0xE6): Port 4 Rate Limit Control
Register 246 (0xF6): Port 5 Rate Limit Control
Address
75
4
32
1
0
Name
Description
Reserved
Ingress Rate Limit Flow
Control Enable
1 = Flow Control is asserted if the port’s receive rate is
exceeded
0 = Flow Control is not asserted if the port’s receive
rate is exceeded
R/W
0
Limit Mode
Ingress Limit Mode
These bits determine what kinds of frames are limited
and counted against ingress rate limiting.
= 00, limit and count all frames
= 01, limit and count Broadcast, Multicast, and flooded
unicast frames
= 10, limit and count Broadcast and Multicast frames
only
= 11, limit and count Broadcast frames only
R/W
00
Count IFG
Count IFG bytes
= 1, each frame’s minimum inter frame gap
(IFG) bytes (12 per frame) are included in Ingress and
Egress rate limiting calculations.
= 0, IFG bytes are not counted.
R/W
0
Count Pre
Count Preamble bytes
= 1, each frame’s preamble bytes (8 per
frame) are included in Ingress and Egress rate limiting
calculations.
= 0, preamble bytes are not counted.
R/W
0
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Advanced Control Registers (Continued)
Register 183 (0xB7): Port 1 Priority 0 Ingress Limit Control 1
Register 199 (0xC7): Port 2 Priority 0 Ingress Limit Control 1
Register 215 (0xD7): Port 3 Priority 0 Ingress Limit Control 1
Register 231 (0xE7): Port 4 Priority 0 Ingress Limit Control 1
Register 247 (0xF7): Port 5 Priority 0 Ingress Limit Control 1
Address
7
60
Name
Description
Reserved
Port-Based Priority 0 Ingress
Limit
Ingress data rate limit for priority 0 frames
Ingress traffic from this port is shaped according to the
Data Rate Selected Table. See the table follow the
end of Egress limit control registers
Mode
Default
RO
0
R/W
0000000
Mode
Default
RO
0
R/W
0000000
Mode
Default
RO
0
R/W
0000000
Register 184 (0xB8): Port 1 Priority 1 Ingress Limit Control 2
Register 200 (0xC8): Port 2 Priority 1 Ingress Limit Control 2
Register 216 (0xD8): Port 3 Priority 1 Ingress Limit Control 2
Register 232 (0xE8): Port 4 Priority 1 Ingress Limit Control 2
Register 248 (0xF8): Port 5 Priority 1 Ingress Limit Control 2
Address
7
60
Name
Description
Reserved
Port-Based Priority 1 Ingress
Limit
Ingress data rate limit for priority 1 frames
Ingress traffic from this port is shaped according to the
Data Rate Selected Table. See the table follow the
end of Egress limit control registers
Register 185 (0xB9): Port 1 Priority 2 Ingress Limit Control 3
Register 201 (0xC9): Port 2 Priority 2 Ingress Limit Control 3
Register 217 (0xD9): Port 3 Priority 2 Ingress Limit Control 3
Register 233 (0xE9): Port 4 Priority 2 Ingress Limit Control 3
Register 249 (0xF9): Port 5 Priority 2 Ingress Limit Control 3
Address
7
60
Name
Description
Reserved
Port-Based Priority 2 Ingress
Limit
October 2011
Ingress data rate limit for priority 2 frames
Ingress traffic from this port is shaped according to the
Data Rate Selected Table. See the table follow the
end of Egress limit control registers
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Advanced Control Registers (Continued)
Register 186 (0xBA): Port 1 Priority 3 Ingress Limit Control 4
Register 202 (0xCA): Port 2 Priority 3 Ingress Limit Control 4
Register 218 (0xDA): Port 3 Priority 3 Ingress Limit Control 4
Register 234 (0xEA): Port 4 Priority 3 Ingress Limit Control 4
Register 250 (0xFA): Port 5 Priority 3 Ingress Limit Control 4
Address
7
60
Name
Description
Reserved
Port-Based Priority 3 Ingress
Limit
Ingress data rate limit for priority 3 frames
Ingress traffic from this port is shaped according to the
Data Rate Selected Table. See the table follow the
end of Egress limit control registers
Mode
Default
RO
0
R/W
0000000
Mode
Default
RO
0
R/W
0000000
Mode
Default
RO
0
R/W
0000000
Register 187 (0xBB): Port 1 Queue 0 Egress Limit Control 1
Register 203 (0xCB): Port 2 Queue 0 Egress Limit Control 1
Register 219 (0xDB): Port 3 Queue 0 Egress Limit Control 1
Register 235 (0xEB): Port 4 Queue 0 Egress Limit Control 1
Register 251 (0xFB): Port 5 Queue 0 Egress Limit Control 1
Address
7
60
Name
Description
Reserved
Port Queue 0 Egress Limit
Egress data rate limit for priority 0 frames
Egress traffic from this priority queue is shaped
according to the Data Rate Selected Table. See the
table follow the end of Egress limit control registers.
In four queues mode, it is lowest priority.
In two queues mode, it is low priority.
Register 188 (0xBC): Port 1 Queue 1 Egress Limit Control 2
Register 204 (0xCC): Port 2 Queue 1 Egress Limit Control 2
Register 220 (0xDC): Port 3 Queue 1 Egress Limit Control 2
Register 236 (0xEC): Port 4 Queue 1 Egress Limit Control 2
Register 252 (0xFC): Port 5 Queue 1 Egress Limit Control 2
Address
7
60
Name
Description
Reserved
Port Queue 1 Egress Limit
October 2011
Egress data rate limit for priority 1 frames
Egress traffic from this priority queue is shaped
according to the Data Rate Selected Table. See the
table follow the end of Egress limit control registers.
In four queues mode, it is low/high priority.
In two queues mode, it is high priority.
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Advanced Control Registers (Continued)
Register 189 (0xBD): Port 1 Queue 2 Egress Limit Control 3
Register 205 (0xCD): Port 2 Queue 2 Egress Limit Control 3
Register 221 (0xDD): Port 3 Queue 2 Egress Limit Control 3
Register 237 (0xED): Port 4 Queue 2 Egress Limit Control 3
Register 253 (0xFD): Port 5 Queue 2 Egress Limit Control 3
Address
7
60
Name
Description
Reserved
Port Queue 2 Egress Limit
Egress data rate limit for priority 2 frames
Egress traffic from this priority queue is shaped
according to the Data Rate Selected Table. See the
table follow the end of Egress limit control registers.
In four queues mode, it is high/low priority.
Mode
Default
RO
0
R/W
0000000
Mode
Default
RO
0
R/W
0000000
Register 190 (0xBE): Port 1 Queue 3 Egress Limit Control 4
Register 206 (0xCE): Port 2 Queue 3 Egress Limit Control 4
Register 222 (0xDE): Port 3 Queue 3 Egress Limit Control 4
Register 238 (0xEE): Port 4 Queue 3 Egress Limit Control 4
Register 254 (0xFE): Port 5 Queue 3 Egress Limit Control 4
Address
7
60
Name
Description
Reserved
Port Queue 3 Egress Limit
Egress data rate limit for priority 3 frames
Egress traffic from this priority queue is shaped
according to the Data Rate Selected Table. See the
table follow the end of Egress limit control registers.
In four queues mode, it is highest priority.
Note:
1. In the port priority 0-3 ingress rate limit mode, need to set all related ingress/egress ports to two queues or four queues mode.
2. In the port queue 0-3 egress rate limit mode, the highest priority get exact rate limit based on the rate select table, other priorities packets rate are
based on the ratio of the port register control 10/11/12/13 when use more than one egress queue per port.
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Data Rate Selection Table in 100BT
Rate for 100BT Mode
1Mbps <= rate <= 99Mbps
Rate = 100 Mbps
Less than 1Mbps (see as below)
Priority/Queue 0-3 Ingress/egress
Limit Control Register bit[6:0] = decimal rate(decimal integer 1-99)
0 or 100 (decimal), ‘0’ is default value
Decimal
64 Kbps
7’d101
128 Kbps
7’d102
192 Kbps
7’d103
256 Kbps
7’d104
320 Kbps
7’d105
384 Kbps
7’d106
448 Kbps
7’d107
512 Kbps
7’d108
576 Kbps
7’d109
640 Kbps
7’d110
704 Kbps
7’d111
768 Kbps
7’d112
832 Kbps
7’d113
896 Kbps
7’d114
960 Kbps
7’d115
Data Rate Selection Table in 10BT
Rate for 10BT mode
1Mbps <= rate <= 9Mbps
Rate = 10 Mbps
Less than 1Mbps (see as below)
Priority/Queue 0-3 Ingress/egress
Limit Control Register bit[6:0]= decimal rate(decimal integer 1-9)
0 or 10 (decimal), ‘0’ is default value
Decimal
64 Kbps
7’d101
128 Kbps
7’d102
192 Kbps
7’d103
256 Kbps
7’d104
320 Kbps
7’d105
384 Kbps
7’d106
448 Kbps
7’d107
512 Kbps
7’d108
576 Kbps
7’d109
640 Kbps
7’d110
704 Kbps
7’d111
768 Kbps
7’d112
832 Kbps
7’d113
896 Kbps
7’d114
960 Kbps
7’d115
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Advanced Control Registers (Continued)
Register 191(0xBF): Testing Register
Address
70
Name
Description
Reserved
N/A
Mode
Default
RO
00000000
Mode
Default
RO
0x15
Mode
Default
R/W
00000000
Register 207(0xCF): Reserved Control Register
Address
70
Name
Description
Reserved
N/A Don’t change
Register 223(0xDF): Test Register 2
Address
70
Name
Description
Reserved
Register 239(0xEF): Test Register 3
Address
Name
Description
Mode
Default
7
Reserved
N/A Don’t change
RO
0
6
Reserved
N/A Don’t change
RO
0
5
Reserved
N/A Don’t change
RO
1
40
Reserved
N/A Don’t change
RO
0x12
Mode
Default
RO
0x00
Register 255(0xFF): Testing Register4
Address
70
Name
Description
Reserved
N/A Don’t change
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Static MAC Address Table
KSZ8895MLU has a static and a dynamic address table. When a DA look-up is requested, both tables will be searched to
make a packet forwarding decision. When an SA look-up is requested, only the dynamic table is searched for aging,
migration, and learning purposes. The static DA look-up result will have precedence over the dynamic DA look-up result. If
there are DA matches in both tables, the result from the static table will be used. The static table can only be accessed
and controlled by an external SPI master (usually a processor). The entries in the static table will not be aged out by
KSZ8895MLU. An external device does all addition, modification and deletion. Register bit assignments are different for
static MAC table reads and static MAC table write, as shown in Table 11 and Table 12.
Address
Name
Description
Mode
Default
63 57
FID
Filter VLAN ID, representing one of the 128 active
VLANs
RO
0000000
56
Use FID
1, use (FID+MAC) to look-up in static table.
0, use MAC only to look-up in static table.
RO
0
55
Reserved
Reserved.
RO
N/A
54
Override
1, override spanning tree “transmit enable = 0” or
“receive enable = 0* setting. This bit is used for
spanning tree implementation.
0, no override.
RO
0
53
Valid
1, this entry is valid, the look-up result will be used.
0, this entry is not valid.
RO
0
52 48
Forwarding Ports
The 5 bits control the forward ports, example:
00001, forward to port 1
00010, forward to port 2
…..
10000, forward to port 5
00110, forward to port 2 and port 3
11111, broadcasting (excluding the ingress port)
RO
00000
47 0
MAC Address
48-bit MAC address.
RO
0x0
Table 11. Format of Static MAC Table for Read (32 Entries)
Examples:
(1) Static Address Table Read (read the 2nd entry)
Write to Register 110 with 0x10 (read static table selected)
Write to Register 111 with 0x1 (trigger the read operation)
Then
Read Register 113 (63 56)
Read Register 114 (55 48)
Read Register 115 (47 40)
Read Register 116 (39 32)
Read Register 117 (31 24)
Read Register 118 (23 16)
Read Register 119 (15 8)
Read Register 120 (7 0)
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Address
Name
Description
Mode
Default
62 56
FID
Filter VLAN ID, representing one of the 128 active
VLANs.
W
0000000
55
Use FID
1, use (FID+MAC) to look-up in static table.
0, use MAC only to look-up in static table.
W
0
54
Override
1, override spanning tree “transmit enable = 0” or
“receive enable = 0” setting. This bit is used for
spanning tree implementation.
0, no override.
W
0
53
Valid
1, this entry is valid, the look-up result will be used.
0, this entry is not valid.
W
0
52 48
Forwarding Ports
The 5 bits control the forward ports, example:
00001, forward to port 1
00010, forward to port 2
.....
10000, forward to port 5
00110, forward to port 2 and port 3
11111, broadcasting (excluding the ingress port)
W
00000
47 0
MAC Address
48-bit MAC address.
W
0x0
Table 12. Format of Static MAC Table for Writes (32 Entries)
Examples:
(2) Static Address Table Write (write the 8th entry)
Write to Register 110 with 0x10 (read static table selected)
Write Register 113 (62 56)
Write Register 114 (55 48)
Write Register 115 (47 40)
Write Register 116 (39 32)
Write Register 117 (31 24)
Write Register 118 (23 16)
Write Register 119 (15 8)
Write Register 120 (7 0)
Write to Register 110 with 0x00 (write static table selected)
Write to Register 111 with 0x7 (trigger the write operation)
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VLAN Table
The VLAN table is used for VLAN table look-up. If 802.1q VLAN mode is enabled (Register 5 bit 7 = 1), this table is used
to retrieve VLAN information that is associated with the ingress packet. The fields includes FID (filter ID), Valid and VLAN
membership need initializtion, due to provide 4K spacing for the VLAN table, there is no VID filed bits, VID is used as
address index to input up to 4096 entries with bits [12:0] information.
Mode
Initial Value
suggestion
1, the entry is valid.
0, entry is invalid.
R/W
0
Membership
Specify which ports are members of the VLAN.
If a DA look-up fails (no match in both static and
dynamic tables), the packet associated with this VLAN
will be forwarded to ports specified in this field.
E.g., 11001 means port 5, port 4 and port 1.
R/W
11111
FID
Filter ID. KSZ8895MLU supports 128 active VLANs
represented by these seven bit fields. FID is the
mapped ID. If 802.1q VLAN is enabled, the look-up in
MAC table will be based on FID+DA and FID+SA.
R/W
0
Address
Name
12
Valid
11 7
60
Description
Table 13. Format of Static VLAN Table (Support Max 4096 VLAN ID Entries and 128 Active VLANs)
If 802.1q VLAN mode is enabled, KSZ8895MLU assigns a VID to every ingress packet when the packet is untagged or
tagged with a null VID, the packet is assigned with the default port VID of the ingress port. If the packet is tagged with
non-null VID, the VID in the tag is used. The look-up process starts from the VLAN table look-up based on VID number. If
the entry is not valid in VLAN table, the packet is dropped and no address learning occurs. If the entry is valid, the FID is
retrieved. The FID+DA and FID+SA lookups in MAC tables are performed. The FID+DA look-up determines the
forwarding ports. If FID+DA fails for look-up in MAC table, the packet is broadcast to all the members or specified
members (excluding the ingress port) based on the VLAN table. If FID+SA fails, the FID+SA is learned. If want to
communicate between different active VLANs, set same FID, otherwise set different FID.
The VLAN table configuration is organized as 1024 VLAN sets, each VLAN set consists of 4 VLAN entries, to support up
to 4096 VLAN entries. Each VLAN set has 52 bits and should be read or written at the same time specified by the indirect
address.
The VLAN entries in the VLAN set is mapped to indirect data registers as follow:
Entry0[12:0] maps to the VLAN set bits[12 0] {register119[4:0], register120[7:0]}
Entry1[12:0] maps to the VLAN set bits[25 13]{register117[1:0], register118[7:0], register119[7:5]}
Entry2[12:0] maps to the VLAN set bits[38 26]{register116[6:0], register117[7:2]}
Entry3[12:0] maps to the VLAN set bits[51 39]{register114[3:0], register115[7:0], register116[7]}
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In order to read one VLAN entry, the VLAN set is read first and the specific VLAN entry information can be extracted. To
update any VLAN entry, the VLAN set is read first then only the desired VLAN entry is updated and the whole VLAN set is
written back. Due to FID in VLAN table is 7-bit, so the VLAN table supports unique 128 flow VLAN groups. Each VLAN set
address is 10 bits long (Maximum is 1024) in the indirect address register 110 and 111, the bit [9 8] of VLAN set
address is at bit [1 0] of register 110, and the bit [7 0] of VLAN set address is at bit [7-0] of register 111. Each Write
and Read can access to four consecutive VLAN entries.
Examples:
(1) VLAN Table Read (read the VID=2 entry)
Write the indirect control and address registers first
Write to Register 110 (0x6E) with 0x14 (read VLAN table selected)
Write to Register 111 (0x6F) with 0x0 (trigger the read operation for VID=0, 1, 2, 3 entries)
Then read the indirect data registers bits [38-26] for VID=2 entry
Read Register 116 (0x74), (register116[6:0] are bits 12 6 of VLAN VID=2 entry)
Read Register 117 (0x75), (register117[7:2] are bits 5 0 of VLAN VID=2 entry)
(2) VLAN Table Write (write the VID=10 entry)
Read the VLAN set that contains VID=8, 9, 10, 11.
Write to Register 110 (0x6E) with 0x14 (read VLAN table selected)
Write to Register 111 (0x6F) with 0x02 (trigger the read operation and VID=8, 9, 10, 11 indirect address)
Read the VLAN set first by the indirect data registers 114, 115, 116, 117, 118, 119, 120.
Modify the indirect data registers bits [38 26] by the register 116 bit [6-0] and register 117 bit [7 2] as follows:
Write to Register 116 (0x74), (register116[6:0] are bits 12 6 of VLAN VID=10 entry)
Write to Register 117 (0x75), (register117[7:2] are bits 5 0 of VLAN VID=10 entry)
Then write the indirect control and address registers
Write to Register 110 (0x6E) with 0x04 (write VLAN table selected)
Write to Register 111 (0x6F) with 0x02 (trigger the write operation and VID=8, 9, 10, 11 indirect address)
Table 14 shows the relationship of the indirect address/data registers and VLAN ID.
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Indirect Address
High/Low Bit[9-0]
for VLAN Sets
Indirect Data
Registers Bits for
Each VLAN Entry
VID
Numbers
VID bit[12-2] in VLAN Tag
VID bit[1-0] in VLAN Tag
0
Bits[12 0]
0
0
0
0
Bits[25 13]
1
0
1
0
Bits[38 26]
2
0
2
0
Bits[51 39]
3
0
3
1
Bits[12 0]
4
1
0
1
Bits[25 13]
5
1
1
1
Bits[38 26]
6
1
2
1
Bits[51 39]
7
1
3
2
Bits[12 0]
8
2
0
2
Bits[25 13]
9
2
1
2
Bits[38 26]
10
2
2
2
Bits[51 39]
11
2
3
:
:
:
:
:
:
:
:
:
:
:
:
:
:
:
1023
Bits[12 0]
4092
1023
0
1023
Bits[25 13]
4093
1023
1
1023
Bits[38 26]
4094
1023
2
1023
Bits[51 39]
4095
1023
3
Table 14. VLAN ID and Indirect Registers
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Dynamic MAC Address Table
Table 15 is read only. The contents are maintained by the KSZ8895MLU only.
Address
Name
Description
Mode
Default
MAC Empty
1, there is no valid entry in the table.
0, there are valid entries in the table.
RO
1
70 61
No of Valid Entries
Indicates how many valid entries in the table.
0x3ff means 1K entries
0x1 and bit 71 = 0: means 2 entries
0x0 and bit 71 = 0: means 1 entry
0x0 and bit 71 = 1: means 0 entry
RO
0
60 59
Time Stamp
2-bit counters for internal aging
RO
58 56
Source Port
The source port where FID+MAC is learned.
000 Port 1
001 Port 2
010 Port 3
011 Port 4
100 Port 5
RO
55
Data Ready
1, The entry is not ready, retry until this bit is set to 0.
0, The entry is ready.
RO
54 48
FID
Filter ID.
RO
0x0
47 0
MAC Address
48-bit MAC address.
RO
0x0
71
0x0
Table 15. Format of Dynamic MAC Address Table (1K Entries)
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Dynamic MAC Address Table Read/Write Examples:
(1) Dynamic MAC Address Table Read (read the 1st entry), and retrieve the MAC table size:
Write to Register 110 with 0x18 (read dynamic table selected)
Write to Register 111 with 0x0 (trigger the read operation) and then
Read Register 112 (71 64)
Read Register 113 (63 56); // the above two registers show # of entries
Read Register 114 (55 48) // if bit 55 is 1, restart (reread) from this register
Read Register 115 (47 40)
Read Register 116 (39 32)
Read Register 117 (31 24)
Read Register 118 (23 16)
Read Register 119 (15 8)
Read Register 120 (7 0)
(2) Dynamic MAC Address Table Read (read the 257th entry), without retrieving # of entries information:
Write to Register 110 with 0x19 (read dynamic table selected)
Write to Register 111 with 0x1 (trigger the read operation) and then
Read Register 112 (71 64)
Read Register 113 (63 56)
Read Register 114 (55 48) // if bit 55 is 1, restart (reread) from this register
Read Register 115 (47 40)
Read Register 116 (39 32)
Read Register 117 (31 24)
Read Register 118 (23 16)
Read Register 119 (15 8)
Read Register 120 (7 0)
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Management Information Base (MIB) Counters
The Management Information Base (MIB) counters are provided on per port basis. These counters are read using indirect
memory access as noted in the following tables:
For Port 1
Offset
Counter Name
Description
0x0
RxLoPriorityByte
Rx lo-priority (default) octet count including bad packets.
0x1
RxHiPriorityByte
Rx hi-priority octet count including bad packets.
0x2
RxUndersizePkt
Rx undersize packets w/good CRC.
0x3
RxFragments
Rx fragment packets w/bad CRC, symbol errors or alignment errors.
0x4
RxOversize
Rx oversize packets w/good CRC (max: 1536 or 1522 bytes).
0x5
RxJabbers
Rx packets longer than 1522B w/either CRC errors, alignment errors, or symbol errors (depends
on max packet size setting) or Rx packets longer than 1916B only.
0x6
RxSymbolError
Rx packets w/ invalid data symbol and legal preamble, packet size.
0x7
RxCRCerror
Rx packets within (64,1522) bytes w/an integral number of bytes and a bad CRC (upper limit
depends on max packet size setting).
0x8
RxAlignmentError
Rx packets within (64,1522) bytes w/a non-integral number of bytes and a bad CRC (upper limit
depends on max packet size setting).
0x9
RxControl8808Pkts
The number of MAC control frames received by a port with 88-08h in EtherType field.
0xA
RxPausePkts
The number of PAUSE frames received by a port. PAUSE frame is qualified with EtherType (8808h), DA, control opcode (00 01), data length (64B min), and a valid CRC.
0xB
RxBroadcast
Rx good broadcast packets (not including errored broadcast packets or valid multicast packets).
0xC
RxMulticast
Rx good multicast packets (not including MAC control frames, errored multicast packets or valid
broadcast packets).
0xD
RxUnicast
Rx good unicast packets.
0xE
Rx64Octets
Total Rx packets (bad packets included) that were 64 octets in length.
0xF
Rx65to127Octets
Total Rx packets (bad packets included) that are between 65 and 127 octets in length.
0x10
Rx128to255Octets
Total Rx packets (bad packets included) that are between 128 and 255 octets in length.
0x11
Rx256to511Octets
Total Rx packets (bad packets included) that are between 256 and 511 octets in length.
0x12
Rx512to1023Octets
Total Rx packets (bad packets included) that are between 512 and 1023 octets in length.
0x13
Rx1024to1522Octets
Total Rx packets (bad packets included) that are between 1024 and 1522 octets in length (upper
limit depends on max packet size setting).
0x14
TxLoPriorityByte
Tx lo-priority good octet count, including PAUSE packets.
0x15
TxHiPriorityByte
Tx hi-priority good octet count, including PAUSE packets.
0x16
TxLateCollision
The number of times a collision is detected later than 512 bit-times into the Tx of a packet.
0x17
TxPausePkts
The number of PAUSE frames transmitted by a port.
0x18
TxBroadcastPkts
Tx good broadcast packets (not including errored broadcast or valid multicast packets).
Table 16. Port 1 MIB Counter Indirect Memory Offsets
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For Port 1 (Continued)
Offset
Counter Name
Description
0x19
TxMulticastPkts
Tx good multicast packets (not including errored multicast packets or valid broadcast packets).
0x1A
TxUnicastPkts
Tx good unicast packets.
0x1B
TxDeferred
Tx packets by a port for which the 1st Tx attempt is delayed due to the busy medium.
0x1C
TxTotalCollision
Tx total collision, half-duplex only.
0x1D
TxExcessiveCollision
A count of frames for which Tx fails due to excessive collisions.
0x1E
TxSingleCollision
Successfully Tx frames on a port for which Tx is inhibited by exactly one collision.
0x1F
TxMultipleCollision
Successfully Tx frames on a port for which Tx is inhibited by more than one collision.
Table 16. Port 1 MIB Counter Indirect Memory Offsets (Continued)
For Port 2, the Base is 0x20, Same Offset Definition (0x20-0x3f)
For Port 3, the Base is 0x40, Same Offset Definition (0x40-0x5f)
For Port 4, the Base is 0x60, Same Offset Definition (0x60-0x7f)
For Port 5, the Base is 0x80, Same Offset Definition (0x80-0x9f)
Address
Name
Description
Mode
Default
Format of Per Port MIB Counters (16 entries)
31
Overflow
1, Counter overflow.
0, No Counter overflow.
RO
0
30
Count Valid
1, Counter value is valid.
0, Counter value is not valid.
RO
0
29 0
Counter Values
Counter value.
RO
0
Table 17. Format of “Per port” MIB Counter
Offset
Counter Name
Description
0x100
Port1 Tx Drop Packets
Tx packets dropped due to lack of resources.
0x101
Port2 Tx Drop Packets
Tx packets dropped due to lack of resources.
0x102
Port3 Tx Drop Packets
Tx packets dropped due to lack of resources.
0x103
Port4 Tx Drop Packets
Tx packets dropped due to lack of resources.
0x104
Port5 Tx Drop Packets
Tx packets dropped due to lack of resources.
0x105
Port1 Rx Drop Packets
Rx packets dropped due to lack of resources.
0x106
Port2 Rx Drop Packets
Rx packets dropped due to lack of resources.
0x107
Port3 Rx Drop Packets
Rx packets dropped due to lack of resources.
0x108
Port4 Rx Drop Packets
Rx packets dropped due to lack of resources.
0x109
Port5 Rx Drop Packets
Rx packets dropped due to lack of resources.
Table 18. All Port Dropped Packet MIB Counters
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Address
Name
Description
Mode
Default
30 16
Reserved
Reserved.
N/A
N/A
15 0
Counter Values
Counter value.
RO
0
Table 19. Format of All Dropped Packet MIB Counters
Note that all port dropped packet MIB counters do not indicate overflow or validity; therefore the application must keep
track of overflow and valid conditions.
The KSZ8895MLU provides total 34 MIB counter per port. These counter are used to monitor the port detail activity for
network management and maintenance. These MIB counters are read using indirect memory access as as noted in the
following examples:
Programming Examples:
(1) MIB counter read (read port 1 Rx64Octets counter)
Write to Register 110 with 0x1c (read MIB counters selected)
Write to Register 111 with 0xe (trigger the read operation)
Then
Read Register 117 (counter value 31 24)
// If bit 31 = 1, there was a counter overflow
// If bit 30 = 0, restart (reread) from this register
Read Register 118 (counter value 23 16)
Read Register 119 (counter value 15 8)
Read Register 120 (counter value 7 0)
(2) MIB counter read (read port 2 Rx64Octets counter)
Write to Register 110 with 0x1c (read MIB counter selected)
Write to Register 111 with 0x2e (trigger the read operation)
Then
Read Register 117 (counter value 31 24)
//If bit 31 = 1, there was a counter overflow
//If bit 30 = 0, restart (reread) from this register
Read Register 118 (counter value 23 16)
Read Register 119 (counter value 15 8)
Read Register 120 (counter value 7 0)
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Programming Examples (Continued):
(3) MIB counter read (read port 1 tx drop packets)
Write to Register 110 with 0x1d
Write to Register 111 with 0x00
Then
Read Register 119 (counter value 15 8)
Read Register 120 (counter value 7 0)
Note that to read out all the counters, the best performance over the SPI bus is (160+3) × 8 × 80 = 104us, where there are
160 registers, 3 overhead, 8 clocks per access, at 12.5MHz. In the heaviest condition, the byte counter will overflow in 2
minutes. It is recommended that the software read all the counters at least every 30 seconds. The per port MIB counters
are designed as “read clear.” A per port MIB counter will be cleared after it is accessed. All port dropped packet MIB
counters are not cleared after they are accessed. The application needs to keep track of overflow and valid conditions on
these counters.
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MIIM Registers
All the registers defined in this section can be also accessed via the SPI interface. Note that different mapping
mechanisms are used for MIIM and SPI. The “PHYAD” defined in IEEE is assigned as “0x1” for port 1, “0x2” for port 2,
“0x3” for port 3 and “0x4” for port 4.. The “REGAD” supported are 0x0-0x5 (0h-5h), 0x1D (1dh) and 0x1F (1fh).
Register 0h: MII Control
Address
Name
Description
Mode
Default
15
Soft Reset
1, PHY soft reset.
0, Normal operation.
R/W
(SC)
0
14
Loop Back
1 = Perform MAC loopback, loop back path as follows:
Assume the loop-back is at port 1 MAC, port 2 is the
monitor port.
Port 1 MAC Loopback (port 1 reg. 0, bit 14 = ‘1’)
Start: RXP2/RXM2 (port 2). Can also start from
port 3, 4, 5
Loopback: MAC/PHY interface of port 1’s MAC
End: TXP2/TXM2 (port 2). Can also end at port 3,
4, 5 respectively
Setting address ox3,4,5 reg. 0, bit 14 = ‘1’ will
perform MAC loopback on port 3, 4, 5 respectively.
0 = Normal Operation.
R/W
0
13
Force 100
1, 100Mbps.
0, 10Mbps.
R/W
1
12
AN Enable
1, Auto-negotiation enabled.
0, Auto-negotiation disabled.
R/W
1
11
Power Down
1, Power down.
0, Normal operation.
R/W
0
10
PHY Isolate
1, Electrical PHY isolation of PHY from Tx+/Tx-.
0, Normal operation.
R/W
0
9
Restart AN
1, Restart Auto-negotiation.
0, Normal operation.
R/W
0
8
Force Full Duplex
1, Full duplex.
0, Half duplex.
R/W
0
7
Collision Test
Not supported.
RO
0
6
Reserved
RO
0
5
Hp_mdix
1 = HP Auto MDI/MDI-X mode
0 = Micrel Auto MDI/MDI-X mode
R/W
1
4
Force MDI
1, Force MDI.
0, Normal operation.
R/W
0
3
Disable Auto MDI/MDI-X
1, Disable auto MDI/MDI-X.
0, Normal operation.
R/W
0
2
Disable far End fault
1, Disable far end fault detection.
0, Normal operation.
R/W
0
1
Disable Transmit
1, Disable transmit.
0, Normal operation.
R/W
0
0
Disable LED
1, Disable LED.
0, Normal operation.
R/W
0
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MIIM Registers (Continued)
Register 1h: MII Status
Address
Name
Description
Mode
Default
15
T4 Capable
0, Not 100 BASET4 capable.
RO
0
14
100 Full Capable
1, 100BASE-TX full-duplex capable.
0, Not capable of 100BASE-TX full-duplex.
RO
1
13
100 Half Capable
1, 100BASE-TX half-duplex capable.
0, Not 100BASE-TX half-duplex capable.
RO
1
12
10 Full Capable
1, 10BASE-T full-duplex capable.
0, Not 10BASE-T full-duplex capable.
RO
1
11
10 Half Capable
1, 10BASE-T half-duplex capable.
0, 10BASE-T half-duplex capable.
RO
1
10 7
Reserved
RO
0
6
Preamble Suppressed
Not supported.
RO
0
5
AN Complete
1, Auto-negotiation complete.
0, Auto-negotiation not completed.
RO
0
4
far End fault
1, far end fault detected.
0, No far end fault detected.
RO
0
3
AN Capable
1, Auto-negotiation capable.
0, Not auto-negotiation capable.
RO
1
2
Link Status
1, Link is up.
0, Link is down.
RO
0
1
Jabber Test
Not supported.
RO
0
0
Extended Capable
0, Not extended register capable.
RO
0
Mode
Default
RO
0x0022
Mode
Default
RO
0x1450
Register 2h: PHYID HIGH
Address
Name
Description
15 0
Phyid High
High order PHYID bits.
Register 3h: PHYID LOW
Address
Name
Description
15 0
Phyid Low
Low order PHYID bits.
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MIIM Registers (Continued)
Register 4h: Advertisement Ability
Address
Name
Description
Mode
Default
15
Next Page
Not supported.
RO
0
14
Reserved
RO
0
13
Remote fault
RO
0
12 11
Reserved
RO
0
10
Pause
R/W
1
9
Reserved
R/W
0
8
Adv 100 Full
1, Advertise 100 full-duplex ability.
0, Do not advertise 100 full-duplex ability.
R/W
1
7
Adv 100 Half
1, Advertise 100 half-duplex ability.
0, Do not advertise 100 half-duplex ability.
R/W
1
6
Adv 10 Full
1, Advertise 10 full-duplex ability.
0, Do not advertise 10 full-duplex ability.
R/W
1
5
Adv 10 Half
1, Advertise 10 half-duplex ability.
0, Do not advertise 10 half-duplex ability.
R/W
1
40
Selector Field
802.3
RO
00001
Mode
Default
Not supported.
1, Advertise pause ability.
0, Do not advertise pause ability.
Register 5h: Link Partner Ability
Address
Name
Description
15
Next Page
Not supported.
RO
0
14
LP ACK
Not supported.
RO
0
13
Remote fault
Not supported.
RO
0
12 11
Reserved
RO
0
10
Pause
RO
0
9
Reserved
RO
0
8
Adv 100 Full
Link partner 100 full capability.
RO
0
7
Adv 100 Half
Link partner 100 half capability.
RO
0
6
Adv 10 Full
Link partner 10 full capability.
RO
0
5
Adv 10 Half
Link partner 10 half capability.
RO
0
4-0
Reserved
RO
00001
October 2011
Link partner pause capability.
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MIIM Registers (Continued)
Register 1dh: Reserved
Address
Name
15 0
Reserved
Description
Mode
Default
RO
0x0000
Mode
Default
RO
0000000000
RO
000
R/W
xx
Register 1fh: PHY Special Control/Status
Address
Name
15 11
Reserved
Description
Indicate the current state of port operation mode:
[000] = reserved
[001] = still in auto-negotiation
[010] = 10BASE-T half duplex
[011] = 100BASE-TX half duplex
[100] = reserved
[101] = 10BASE-T full duplex
[110] = 100BASE-TX full duplex
[111] = PHY/MII isolate
10-8
Port Operation Mode
Indication
7-6
Reserved
5
Polrvs
1 = Polarity is reversed
0 = Polarity is not reversed
RO
0
4
MDI-X status
1 = MDI
0 = MDI-X
RO
0
3
Force_lnk
1 = Force link pass
0 = Normal operation
R/W
0
2
Pwrsave
1 = Enable power save
0 = Disable power save
R/W
0
1
Remote Loopback
1 = Perform Remote loopback, loop back path as
follows:
Port 1 (PHY ID address 0x1 reg. 1f, bit 1 = ‘1’)
Start: RXP1/RXM1 (port 1)
Loopback: PMD/PMA of port 1’s PHY
End: TXP1/TXM1 (port 1)
Setting PHY ID address 0x2,3,4,5 reg. 1fh, bit 1 = ‘1’
will perform remote loopback on port 2, 3, 4, 5.
0 = Normal Operation.
R/W
0
0
Reserved
RO
0
October 2011
N/A, don’t change
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Absolute Maximum Ratings(1)
Operating Ratings(2)
Supply Voltage
(VDDAR, VDDAP, VDDC) .........................–0.5V to +2.4V
(VDDAT, VDDIO) ...................................–0.5V to +4.0V
Input Voltage ..........................................–0.5V to +4.0V
Output Voltage .......................................–0.5V to +4.0V
Lead Temperature (soldering, 10 sec.)............... 260°C
Storage Temperature (TS).................. –55°C to +150°C
HBM ESD Rating .................................................1.5KV
Supply Voltage
(VDDAR, VDDAP, VDDC)........................ +1.15V to +1.25V
(VDDAT) ............................................ +3.15V to +3.45V
(VDDIO) .. 3.15 to 3.45V or 2.4 to 2.6V or 1.71 to 1.89V
Ambient Temperature (TA)
Industrial ............................................–40°C to +85°C
Package Thermal Resistance(3)
LQFP (θJA) No Air Flow .............................41.54°C/W
LQFP (θJC) No Air Flow..............................19.78°C/W
Electrical Characteristics(4, 5)
VIN = 1.2V/3.3V (typ.); TA = 25°C.
Symbol
Parameter
Condition
Min.
Typ.
Max.
Units
100BASE-TX Operation—All Ports 100% Utilization
IDX
100BASE-TX (Transmitter) 3.3V Analog
VDDAT
129
mA
IDda
100BASE-TX 1.2V Analog
VDDAR
40
mA
IDDc
100BASE-TX 1.2V Digital
VDDC
45
mA
IDDIO
100BASE-TX (Digital IO) 3.3V Digital
VDDIO
2.5
mA
10BASE-T Operation —All Ports 100% Utilization
IDX
10BASE-T (Transmitter) 3.3V Analog
VDDAT
124
mA
IDda
10BASE-T 1.2V Analog
VDDAR
15
mA
IDDc
10BASE-T 1.2V Digital
VDDC
56
mA
IDDIO
10BASE-T (Digital IO) 3.3V Digital
VDDIO
2
mA
Auto-Negotiation Mode
IDX
10BASE-T (Transmitter) 3.3V Analog
VDDAT
75
mA
IDda
10BASE-T 1.2V Analog
VDDAR
39
mA
IEDM
10BASE-T 1.2V Digital
VDDC
58
mA
IDDIO
10BASE-T (Digital IO) 3.3V Digital
VDDIO
1.6
mA
38
mA
Power Management Mode
IPSM1
Power Saving Mode 3.3V
VDDAT + VDDIO
IPSM2
Power Saving Mode 1.2V
VDDAR + VDDC
73
mA
ISPDM1
Soft Power Down Mode 3.3V
VDDAT + VDDIO
1.6
mA
ISPDM2
Soft Power Down Mode 1.2V
VDDAR + VDDC
0.8
mA
IEDM1
Energy Detect Mode 3.3V
VDDAT + VDDIO
7.5
mA
IEDM2
Energy Detect Mode 1.2V
VDDAR + VDDC
46
mA
Notes:
1. Exceeding the absolute maximum rating may damage the device.
2. The device is not guaranteed to function outside its operating rating. Unused inputs must always be tied to an appropriate logic voltage level (ground
or VDD).
3. No heat spreader in package. The thermal junction to ambient (θJA) and the thermal junction to case (θJC) are under air velocity 0m/s.
4. Specification for packaged product only. There is no an additional transformer consumption due to use on chip termination technology with internal
biasing for 10Bese-T and 100Base-TX.
5. Measurements were taken with operating ratings.
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Electrical Characteristics(4, 5) (Continued)
VIN = 1.2V/3.3V (typ.); TA = 25°C.
Symbol
Parameter
Condition
Min.
Typ.
Max.
Units
0.8/0.6/0.3
V
10
µA
0.4/0.4/0.2
V
10
µA
1.05
V
2
%
3
5
ns
0
0.5
ns
±0.5
ns
5
%
TTL Inputs
VIH
Input High Voltage
2.0/2.0/1.3
Input Low Voltage
Input Current
IIN
(Excluding Pull-up/Pull-down)
TTL Outputs
VIN = GND ~ VDDIO
VOH
Output High Voltage
IOH = –8mA
VOL
Output Low Voltage
IOL = 8mA
IOZ
Output Tri-State Leakage
VIN = GND ~ VDDIO
V
VIL
–10
2.4/1.9/1.5
100BASE-TX Transmit (measured differentially after 1:1 transformer)
100Ω termination on the differential
VO
Peak Differential Output Voltage
output
100Ω termination on the differential
VIMB
Output Voltage Imbalance
output
Rise/fall Time
tr tt
Rise/fall Time Imbalance
V
0.95
Duty Cycle Distortion
Overshoot
Output Jitters
Peak-to-Peak
0
0.75
1.4
ns
300
400
585
mV
2.2
2.5
2.8
V
1.4
3.5
ns
28
30
ns
10BASE-T Receive
VSQ
Squelch Threshold
5MHz square wave
10BASE-T Transmit (measured differentially after 1:1 transformer) VDDAT = 3.3V
100Ω termination on the differential
VP
Peak Differential Output Voltage
output
Output Jitters
Peak-to-Peak
Rise/fall Times
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Timing Diagrams
EEPROM Timing
Figure 13. EEPROM Interface Input Receive Timing Diagram
Figure 14. EEPROM Interface Output Transmit Timing Diagram
Symbol
Parameter
Min.
Typ.
Max.
tCYC1
Clock Cycle
tS1
Set-Up Time
20
ns
tH1
Hold Time
20
ns
tOV1
Output Valid
16384
4096
4112
Units
ns
4128
ns
Table 20. EEPROM Timing Parameters
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Timing Diagrams (Continued)
SNI Timing
Figure 15. SNI Input Timing
Figure 16. SNI Output Timing
Symbol
Parameter
Min.
Typ.
Max.
tCYC2
Clock Cycle
tS2
Set-Up Time
10
ns
tH2
Hold Time
0
ns
tO2
Output Valid
0
100
3
Units
ns
6
ns
Table 21. SNI Timing Parameters
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Timing Diagrams (Continued)
MII Timing
Figure 19. MAC Mode MII Timing Data Received from MII
Figure 20. MAC Mode MII Timing Parameters
Symbol
10Base-T/100-Base-TX
Parameter
Min.
Typ.
Max.
400/40
Units
tCYC3
Clock Cycle
tS3
Set-Up Time
10
ns
tH3
Hold Time
5
ns
tO3
Output Valid
3
9
ns
25
ns
Table 22. MAC Mode Timing Parameters
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Timing Diagrams (Continued)
SPI Timing
Figure 21. SPI Input Timing
Symbol
Parameter
Min.
Typ.
Max.
Units
fC
Clock Frequency
25
MHz
tCHSL
SPIS_N Inactive Hold Time
10
ns
tSLCH
SPIS_N Active Set-Up Time
10
ns
tCHSH
SPIS_N Active Hold Time
10
ns
tSHCH
SPIS_N Inactive Set-Up Time
10
ns
tSHSL
SPIS_N Deselect Time
200
ns
tDVCH
Data Input Set-Up Time
5
ns
tCHDX
Data Input Hold Time
5
ns
tCLCH
Clock Rise Time
1
µs
tCHCL
Clock fall Time
1
µs
tDLDH
Data Input Rise Time
1
µs
tDHDL
Data Input fall Time
1
µs
Table 23. SPI Input Timing Parameters
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Timing Diagrams (Continued)
SPI Timing (Continued)
Figure 22. SPI Output Timing
Symbol
Parameter
Min.
fC
Clock Frequency
tCLQX
SPIQ Hold Time
tCLQV
Clock Low to SPIQ Valid
tCH
Clock High Time
18
ns
tCL
Clock Low Time
18
ns
tQLQH
SPIQ Rise Time
50
ns
tQHQL
SPIQ fall Time
50
ns
tSHQZ
SPIQ Disable Time
15
ns
0
Typ.
Max.
Units
25
MHz
0
ns
15
ns
Table 24. SPI Output Timing Parameters
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Timing Diagrams (Continued)
Auto-Negotiation Timing
Figure 23. Auto-Negotiation Timing
Symbols
Parameters
Min.
Typ.
Max.
Units
tBTB
FLP Burst to FLP Burst
8
16
24
ms
tFLPW
FLP Burst Width
tPW
Clock/Data Pulse Width
tCTD
Clock Pulse to Data Pulse
55.5
64
69.5
µs
tCTC
Clock Pulse to Clock Pulse
111
128
139
µs
Number of Clock/Data Pulse per Burst
17
2
ms
100
ns
33
Table 24. Auto-Negotiation Timing Parameters
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Timing Diagrams (Continued)
Reset Timing
Figure 24. Reset Timing
Symbol
Parameter
Min.
Typ.
Max.
Units
tSR
Stable Supply Voltages to Reset High
10
ms
tCS
Configuration Set-Up Time
50
ns
tCH
Configuration Hold Time
50
ns
tRC
Reset to Strap-In Pin Output
50
ns
tvr
3.3V rise time
100
µs
Table 25. Reset Timing Parameters
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Reset Circuit Diagram
Micrel recommends the following discrete reset circuit as shown in Figure 25 when powering up the KS8895MQ device.
For the application where the reset circuit signal comes from another device (e.g., CPU, FPGA, etc), we recommend the
reset circuit as shown in Figure 26.
Figure 25. Recommended Reset Circuit
Figure 26. Recommended Circuit for Interfacing with CPU/FPGA Reset
At power-on-reset, R, C, and D1 provide the necessary ramp rise time to reset the Micrel device. The reset out
RST_OUT_n from CPU/FPGA provides the warm reset after power up.
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Isolation Transformer Selection
One simple 1:1 isolation transformer is needed at the line interface. An isolation transformer with integrated commonmode choke is recommended for exceeding FCC requirements at line side. Request to separate the center taps of RX/TX
at chip side. Table 26 gives recommended transformer characteristics.
Characteristics Name
Value
Test Condition
Turns Ratio
1 CT : 1 CT
Open-Circuit Inductance (min.)
350µH
100mV, 100kHz, 8mA
Leakage Inductance (max.)
0.4µH
1MHz (min.)
Inter-Winding Capacitance (max.)
12pF
D.C. Resistance (max.)
0.9Ω
Insertion Loss (max.)
1.0dB
HIPOT (min.)
1500Vrms
0MHz to 65MHz
Note:
1. The IEEE 802.3u standard for 100BASE-TX assumes a transformer loss of 0.5dB. For the transmit line transformer, insertion loss of up to 1.3dB can
be compensated by increasing the line drive current by means of reducing the ISET resistor value.
2. The center taps of RX and TX should be isolated for the low power consumption.
Table 26. Qualified Magnetic Vendors
Table 27 provide transformer vendors provide compatible magnetic parts for Micrel’s device.
Vendors and Parts
Auto MDIX
# of Ports
Vendors and Parts
Auto MDIX
# of Ports
Pulse
H1664NL
Yes
4
Pulse
H1102
Yes
1
YCL
PH406082
Yes
4
Bel Fuse
S558-5999-U7
Yes
1
TDK
TLA-6T718A
Yes
1
YCL
PT163020
Yes
1
LanKom
LF-H41S
Yes
1
Transpower
HB726
Yes
1
Datatronic
NT79075
Yes
1
Delta
LF8505
Yes
1
Table 27. Qualified Magnetic Vendors
Reference Crystal Selection
Chacteristics
Value
Units
25.00000
MHz
Frequency tolerance (max.)
= 50
ppm
Load capacitance (max.)
18 27
pF
40
Frequency
Series resistance
Table 28. Typical Reference Crystal Characteristics
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Package Information
128-Pin LQFP
MICREL, INC. 2180 FORTUNE DRIVE SAN JOSE, CA 95131 USA
TEL +1 (408) 944-0800 FAX +1 (408) 474-1000 WEB http://www.micrel.com
Micrel makes no representations or warranties with respect to the accuracy or completeness of the information furnished in this data sheet. This
information is not intended as a warranty and Micrel does not assume responsibility for its use. Micrel reserves the right to change circuitry,
specifications and descriptions at any time without notice. No license, whether express, implied, arising by estoppel or otherwise, to any intellectual
property rights is granted by this document. Except as provided in Micrel’s terms and conditions of sale for such products, Micrel assumes no liability
whatsoever, and Micrel disclaims any express or implied warranty relating to the sale and/or use of Micrel products including liability or warranties
relating to fitness for a particular purpose, merchantability, or infringement of any patent, copyright or other intellectual property right.
Micrel Products are not designed or authorized for use as components in life support appliances, devices or systems where malfunction of a product
can reasonably be expected to result in personal injury. Life support devices or systems are devices or systems that (a) are intended for surgical implant
into the body or (b) support or sustain life, and whose failure to perform can be reasonably expected to result in a significant injury to the user. A
Purchaser’s use or sale of Micrel Products for use in life support appliances, devices or systems is a Purchaser’s own risk and Purchaser agrees to fully
indemnify Micrel for any damages resulting from such use or sale.
© 2011 Micrel, Incorporated.
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