8-BIT SHIFT REGISTER Micrel, Inc. FEATURES ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ SY100S341 SY100S341 DESCRIPTION The SY100S341 offer eight D-type, edge-triggered flipflops with both individual inputs for parallel operation as well as serial inputs for bidirectional shifting, and are designed for use in high-performance ECL systems. Data is clocked into the flip-flops on the rising edge of the clock. The mode of operation is selected by two Select inputs (S0, S1) which determine if the device performs a shift, hold or parallel entry function, as described in the Truth Table. The inputs on these devices have 75kΩ pull-down resistors. Max. shift frequency of 600MHz Max. Clock to Q delay of 1200ps IEE min. of –150mA Industry standard 100K ECL levels Extended supply voltage option: VEE = –4.2V to –5.5V Voltage and temperature compensation for improved noise immunity Internal 75kΩ input pull-down resistors 70% faster than Fairchild 300K at lower power Function and pinout compatible with Fairchild F100K Available in 28-pin PLCC package PIN NAMES Label Function CP Clock Pulse Input S0 — S1 Select Inputs D0 — D7 Serial Inputs P0 — P7 Parallel Inputs Q0 — Q7 Data Outputs VEES VEE Substrate VCCA VCCO for ECL Outputs M9999-042307 [email protected] or (408) 955-1690 Rev.: I 1 Amendment: /0 Issue Date: April 2007 SY100S341 Micrel, Inc. D7 Ordering Information Q7 Q6 P6 P7 VEES P5 PACKAGE/ORDERING INFORMATION 11 10 9 8 7 6 5 Part Number Package Type Operating Range Package Marking Lead Finish P4 CP 12 4 Q5 13 SY100S341JC J28-1 Commercial SY100S341JC Sn-Pb VEE VEES S0 14 3 2 1 Q4 VCCA SY100S341JCTR(1) J28-1 Commercial SY100S341JC Sn-Pb SY100S341JZ(2) J28-1 Commercial SY100S341JZ with Pb-Free bar-line indicator Matte-Sn SY100S341JZTR(1, 2) J28-1 Commercial SY100S341JZ with Pb-Free bar-line indicator Matte-Sn S1 P3 15 16 17 Top View PLCC J28-1 28 27 26 18 VCC VCC Q3 Q2 19 20 21 22 23 24 25 Q1 D0 Q0 VEES P2 P1 P0 Notes: 1. Tape and Reel. 2. Pb-Free package is recommended for new designs. 28-Pin PLCC (J28-1) M9999-042307 [email protected] or (408) 955-1690 2 SY100S341 Micrel, Inc. BLOCK DIAGRAM D7 Q7 D Q C P7 Q6 Q D C P6 Q1 Q D C P1 PARALLEL LOAD Q0 SHIFT LEFT Q D SHIFT RIGHT HOLD C P0 DECODE S0 S1 M9999-042307 [email protected] or (408) 955-1690 D0 CP 3 SY100S341 Micrel, Inc. TRUTH TABLE Inputs Function Outputs D7 D0 S1 S0 CP Q7 Q6 Q5 Q4 Q3 Q2 Q1 Q0 Load Register X X L L u P7 P6 P5 P4 P3 P2 P1 P0 Shift Left Shift Left X X L H L L H H u u Q6 Q6 Q5 Q5 Q4 Q4 Q3 Q3 Q2 Q2 Q1 Q1 Q0 Q0 L H Shift Right Shift Right L H X X H H L L u u L H Q7 Q7 Q6 Q6 Q5 Q5 Q4 Q4 Q3 Q3 Q2 Q2 Q1 Q1 Hold Hold Hold X X X X X X H X X H X X X H L No Change NOTE: 1. H = HIGH Voltage Level L = LOW Voltage Level X = Don't Care u = LOW-to-HIGH Transition DC ELECTRICAL CHARACTERISTICS VEE = –4.2V to –5.5V unless otherwise specified; VCC = VCCA = GND Symbol Parameter IIH Input HIGH Current, All Inputs IEE Power Supply Current Min. Typ. Max. Unit Condition — — 200 µA VIN = VIH (Max.) –150 –102 –71 mA Inputs Open AC ELECTRICAL CHARACTERISTICS VEE = –4.2V to –5.5V unless otherwise specified; VCC = VCCA = GND TA = 0°C Symbol Parameter TA = +25°C TA = +85°C Min. Max. Min. Max. Min. Max. Unit fshift Shift Frequency 600 — 600 — 600 — MHz tPLH tPHL Propagation Delay CP to Output 450 1200 450 1200 450 1200 ps tTLH tTHL Transition Time 20% to 80%, 80% to 20% 300 900 300 900 300 900 ps tS Set-up Time Dn, Pn Sn 300 600 — — 300 600 — — 300 600 — — Hold Time Dn, Pn Sn 300 0 — — 300 0 — — 300 0 — — — 600 — 600 — 600 tH tpw (H) Pulse Width HIGH, CP M9999-042307 [email protected] or (408) 955-1690 ps ps 4 ps Condition SY100S341 Micrel, Inc. TIMING DIAGRAMS 0.7 ± 0.1 ns 0.7 ± 0.1 ns –0.95V 80% 50% 20% CLOCK –1.69V tpw (H) 1/fshift –0.95V PARALLEL –1.69V tPLH tPHL OUTPUT tTLH tTHL Propagation Delay and Transition Times –0.95V Pn, Sn, Dn 50% –1.69V tH tS –0.95V CLOCK 50% –1.69V Set-up and Hold Times Notes: 1. VEE = –4.2V to –5.5V unless otherwise specified; VCC = VCCA = GND. 2. tS is the minimum time before the transition of the clock that information must be present at the data input. 3. tH is the minimum time after the transition of the clock that information must remain unchanged at the data input. M9999-042307 [email protected] or (408) 955-1690 5 SY100S341 Micrel, Inc. 28-PIN PLCC (J28-1) Rev. A MICREL, INC. 2180 FORTUNE DRIVE SAN JOSE, CA 95131 TEL + 1 (408) 944-0800 FAX + 1 (408) 474-1000 WEB USA http://www.micrel.com The information furnished by Micrel in this data sheet is believed to be accurate and reliable. However, no responsibility is assumed by Micrel for its use. Micrel reserves the right to change circuitry and specifications at any time without notification to the customer. Micrel Products are not designed or authorized for use as components in life support appliances, devices or systems where malfunction of a product can reasonably be expected to result in personal injury. Life support devices or systems are devices or systems that (a) are intended for surgical implant into the body or (b) support or sustain life, and whose failure to perform can be reasonably expected to result in a significant injury to the user. A Purchaser’s use or sale of Micrel Products for use in life support appliances, devices or systems is at Purchaser’s own risk and Purchaser agrees to fully indemnify Micrel for any damages resulting from such use or sale. © 2006 Micrel, Incorporated. M9999-042307 [email protected] or (408) 955-1690 6