SY89809AL 3.3V LVPECL/HSTL to HSTL 1:9 HighPerformance Clock Driver with LVTTL Clock Select and Enable General Description The SY89809AL is a high-performance bus clock driver with nine differential High-Speed Transceiver Logic (HSTL) output pairs. The part is designed for use in low-voltage (3.3V/1.8V) applications, which require a large number of outputs to drive precisely aligned, ultra-low skew signals to their destination. The input is multiplexed from either HSTL or Low-Voltage Positive-Emitter-Coupled Logic (LVPECL) by the CLK_SEL pin. The Output Enable (OE) is synchronous so that the outputs will only be enabled/disabled when they are already in the LOW state. This avoids any chance of generating a runt clock pulse when the device is enabled/disabled as can happen with an asynchronous control. The SY89809AL features low pin-to-pin skew (15ps typical) and low part-to-part skew (100ps typical). The SY89809AL is available in a single space-saving package, enabling a lower overall cost solution. Datasheets and support documentation can be found on Micrel’s web site at: www.micrel.com. Precision Edge® Features • • • • • • • • 3.3V core supply, 1.8V output supply for reduced power LVPECL and HSTL inputs Nine differential HSTL (low-voltage swing) output pairs HSTL outputs drive 50Ω-to-ground with no offset voltage 750MHz maximum clock frequency Low part-to-part skew (100ps typical) Low pin-to-pin skew (15ps typical) Available in 32-pin TQFP Applications • • • • • High-performance PCs Workstations Parallel processor-based systems Other high-performance computing Communications Block Diagram Level Direction Signal HSTL Input HSTL_CLK, /HSTL_CLK HSTL Output Q0 – Q8, /Q0 – /Q8 LVPECL Input LVPECL_CLK, /LVPECL_CLK LVCMOS/LVTTL Input CLK_SEL, OE OE(1) CLK_SEL 0 0 Table 1. Signal Groups Q0 – Q8 /Q0 – /Q8 LOW HIGH 0 1 LOW HIGH 1 0 HSTL_CLK /HSTL_CLK 1 1 LVPECL_CLK /LVPECL_CLK Table 2. Truth Table Note: 1. The OE (output enable) signal is synchronized with the low level of the HSTL_CLK and LVPECL_CLK signal. Precision Edge is a registered trademark of Micrel, Inc. Micrel Inc. • 2180 Fortune Drive • San Jose, CA 95131 • USA • tel +1 (408) 944-0800 • fax + 1 (408) 474-1000 • http://www.micrel.com July 2010 M9999-070110 [email protected] or (408) 955-1690 Micrel, Inc. SY89809AL Ordering Information(1) Part Number Package Type Operating Range Package Marking Lead Finish T32-1 Commercial SY89809ALTZ with Pb-Free bar-line indicator Matte-Sn Pb-Free T32-1 Commercial SY89809ALTZ with Pb-Free bar-line indicator Matte-Sn Pb-Free SY89809ALTZ(3) SY89809ALTZTR (2, 3) Notes: 1. Contact factory for die availability. Dice are guaranteed at TA = 25°C, DC Electricals only. 2. Tape and Reel. 3. Pb-Free package is recommended for new designs. Pin Configuration 32-Pin TQFP (T32-1) Pin Description Pin Number Pin Name Type 2, 3 HSTL_CLK, /HSTL_CLK HSTL Input Differential clock input selected by CLK_SEL. Can be left floating if not selected. Floating input, if selected, produces a LOW at HSTL_CLK and a HIGH at /HSTL_CLK. HSTL input signal requires external termination 50Ω-toground. 5, 6 LVPECL_CLK, /LVPECL_CLK LVPECL Input Differential clock input selected by CLK_SEL. Can be left floating if not selected. Floating input, if selected, produces a LOW at LVPECL_CLK and a HIGH at /LVPECL_CLK. Non-inverted input has a 75kΩ pull-down. Inverted input has a 75kΩ pull-down and a 37.5kΩ pull-up. 4 CLK_SEL LVTTL Input Selected HSTL_CLK input when LOW and LVPECL_CLK output when HIGH. 37.5kΩ pull-up. LVTTL Input Enable input synchronized internally to prevent glitching of the Q0-Q8 and /Q0-/Q8 outputs. OE high-to-low transition ensures outputs remain disabled during the next clock cycle. OE low-to-high transition enables normal operation of the next input clock. 37.5kΩ pull-up. HSTL Output Differential clock outputs from HSTL_CLK when CLK_SEL = LOW and and from LVPECL outputs when CLK_SEL = HIGH. HSTL outputs must be terminated with 50Ω to GND. Q0-Q8 outputs are static LOW when OE = LOW. Unused output pairs may be left floating. 8 31, 29, 27, 23, 21, 19, 15, 13, 11 July 2010 OE Q0 – Q8 Pin Function 2 M9999-070110 [email protected] or (408) 955-1690 Micrel, Inc. SY89809AL Pin Description (Continued) Pin Number Pin Name Type Pin Function 30, 28, 26, 22, 20, 18, 14, 12, 10 /Q0 – /Q8 HSTL Output Differential clock outputs from HSTL_CLK when CLK_SEL = LOW and from LVPECL outputs when CLK_SEL = HIGH. HSTL outputs must be terminated with 50Ω to GND. /Q0-/Q8 outputs are static HIGH when OE = LOW. Unused output pairs may be left floating. 1 VCCI VCC Core Power Core VCC connected to 3.3V supply. Bypass with 0.1µF in parallel with 0.01µF low ESR capacitors as close to VCCI pin as possible. 9, 16, 17, 24, 25, 32 VCCO VCC Output Power 7 GND Ground July 2010 Output Buffer VCC connected to 1.8V supply. Bypass with 0.1µF in parallel with 0.01µF low ESR capacitors as close to VCCO pins as possible. All VCCO pins should be connected together on the PCB. Ground. 3 M9999-070110 [email protected] or (408) 955-1690 Micrel, Inc. SY89809AL Absolute Maximum Ratings(1) Operating Ratings(2) Input Voltage (VIN) ........................................... –0.5V to VCCI VCC Pin Potential to Ground Pin (VCCI, VCCO) ............................................ –0.5V to +4.0V Output Current (IOUT) ............................................................ Continuous............................................................50mA Surge ..................................................................100mA Lead Temperature (soldering, 20sec.)....................... 260°C Storage Temperature (Ts) .........................–65°C to +150°C Supply Voltage (VCCI) ...................................................... +3.0V to +3.6V (VCCO)..................................................... +1.6V to +2.0V Ambient Temperature (TA) .............................. 0°C to +85°C Package Thermal Resistance TQFP (θJA) –Still-Air.......................................................50°C/W –500lfpm .....................................................42°C/W TQFP (θJC) .........................................................20°C/W DC Electrical Characteristics TA = 0°C to +85°C, unless otherwise noted. Symbol Parameter Condition Min. Typ. Max. Units Power Supply VCCI VCC Core 3.0 3.3 3.6 V VCCO VCC Output 1.6 1.8 2.0 V ICCI ICC Core 65 90 mA 1.0 1.2 V 0.4 V HSTL VOH Output HIGH Voltage(3) (3) VOL Output LOW Voltage 0.1 VIH Input HIGH Voltage VX +0.1 1.6 V VIL Input LOW Voltage –0.3 VX – 0.1 V VX Input Crossover Voltage 0.68 0.9 V IIH Input HIGH Current –350 20 µA IIL Input LOW Current –500 VIHCMR Input HIGH Voltage Common Mode Range( Differential Configuration) µA 0.6 1.6 V LVPECL VIH Input HIGH Voltage VCCI – 1.145 VCCI – 0.895 V VIL Input LOW Voltage VCCI – 1.945 VCCI – 1.695 V IIH Input HIGH Current –150 150 µA IIL Input LOW Current –150 150 µA VIHCMR Input HIGH Voltage Common Mode Range( Differential (4) Configuration) 1.2 VCCI V Notes: 1. Exceeding the absolute maximum rating may damage the device. 2. The device is not guaranteed to function outside its operating rating. 3. Outputs loaded with 50Ω to ground. 4. VIHCMR max varies 1:1 with VCCI. The VIHCMR range is referenced to the most positive side of the differential input signal. July 2010 4 M9999-070110 [email protected] or (408) 955-1690 Micrel, Inc. SY89809AL DC Electrical Characteristics TA = 0°C to +85°C, unless otherwise noted. Symbol Parameter Condition Min. Typ. Max. Units LVCMOS/LVTTL VIH Input HIGH Voltage 2.0 V VIL Input LOW Voltage 0.8 V IIH Input HIGH Current –150 150 µA IIL Input LOW Current –300 300 µA AC Electrical Characteristics(5) TA = 0°C to +85°C, unless otherwise noted. 0 Symbol Parameters Min. Typ. FOUT < 100MHz 600 FOUT < 500MHz FOUT < 750MHz 25°C Max. Min. Typ. 800 600 600 700 450 510 LVPECL_CLK to Q 680 800 HSTL_CLK to Q 690 85°C Max. Min. Typ. Max. Units 800 600 800 600 700 600 700 450 510 450 510 930 700 820 950 780 920 1070 830 990 700 850 1000 790 950 1110 15 25 15 25 15 25 100 200 100 200 100 200 ps 1.4 3 1.4 3 1.4 3 ps Differential Output Voltage VOpp mV Propagation Delay tPLH tPHL tSkew tJITTER (Differential Configuration) Pin-to-Pin Skew(6) (7) Part-to-Part Skew Random Clock Jitter ( RMS) Input Voltage Swing VPP ps (8) LVPECL 200 HSTL 200 200 200 1900 200 1900 200 1900 mV OE Set-Up Time(9) 0.5 0.5 0.5 ns tH OE Hold Time 0.5 0.5 0.5 ns tr, tf Output Rise/Fall Times (20% to 80%) Q, /Q 350 tS 600 350 450 600 350 600 ps Notes: 5. Outputs loaded with 50Ω to ground. Airflow ≥ 500lfpm. 6. The Pin-to-Pin skew is defined as the worst-case difference between any two similar delay paths within a single device operating at the same voltage and temperature. 7. The Part-to-Part skew is defined as the absolute worst-case difference between any two delay paths on any two devices operating at the same voltage and temperature. 8. VPP is the Input Voltage swing required to maintain AC characteristics listed herein. It represents the input voltage swing for CLK or /CLK. 9. OE set-up time is defined with respect to the rising edge of the clock. OE HIGH-to-LOW transition ensures outputs remain disabled during the next clock cycle. July 2010 5 M9999-070110 [email protected] or (408) 955-1690 Micrel, Inc. SY89809AL Output Waveforms Figure 1. 100MHz Output Waveform Figure 2. 500MHz Output Waveform Frequency vs. Amplitude 900 800 AMPLITUDE (mV) 700 600 500 400 300 200 100 1000 900 800 700 600 500 400 300 200 100 0 0 FREQUENCY (MHz) July 2010 6 M9999-070110 [email protected] or (408) 955-1690 Micrel, Inc. SY89809AL Figure 3. Output Enable Timing Diagram July 2010 7 M9999-070110 [email protected] or (408) 955-1690 Micrel, Inc. SY89809AL Package Information 32-Pin TQFP (T32-1) MICREL, INC. 2180 FORTUNE DRIVE SAN JOSE, CA 95131 USA TEL +1 (408) 944-0800 FAX +1 (408) 474-1000 WEB http://www.micrel.com The information furnished by Micrel in this data sheet is believed to be accurate and reliable. However, no responsibility is assumed by Micrel for its use. Micrel reserves the right to change circuitry and specifications at any time without notification to the customer. Micrel Products are not designed or authorized for use as components in life support appliances, devices or systems where malfunction of a product can reasonably be expected to result in personal injury. Life support devices or systems are devices or systems that (a) are intended for surgical implant into the body or (b) support or sustain life, and whose failure to perform can be reasonably expected to result in a significant injury to the user. A Purchaser’s use or sale of Micrel Products for use in life support appliances, devices or systems is a Purchaser’s own risk and Purchaser agrees to fully indemnify Micrel for any damages resulting from such use or sale. © 2010 Micrel, Incorporated. July 2010 8 M9999-070110 [email protected] or (408) 955-1690