MICRON MT48H4M16LFB4-8ITH

64Mb: 4 Meg x 16 Mobile SDRAM
Features
Mobile SDRAM
MT48H4M16LF – 1 Meg x 16 x 4 banks
Features
Figure 1:
• 1.70–1.95V
• Fully synchronous; all signals registered on positive
edge of system clock
• Internal pipelined operation; column address can be
changed every clock cycle
• Internal banks for hiding row access/precharge
• Programmable burst lengths: 1, 2, 4, 8, or continuous
page1
• Auto precharge, includes concurrent auto precharge
• Self refresh mode
• 64ms, 4,096-cycle refresh
• LVTTL-compatible inputs and outputs
• Partial-array self refresh (PASR) power-saving mode
• On-die temperature-compensated self refresh
(TCSR)
• Deep power-down (DPD) mode
• Programmable output drive strength
• Operating temperature ranges
– Commercial (0°C to +70°C)
– Industrial (–40°C to +85°C)
Notes: 1. For continuous page burst, contact factory
for availability.
1
2
3
7
8
9
A
VSS
DQ15
VSSQ
VDDQ
DQ0
VDD
B
DQ14
DQ13
VDDQ
VSSQ
DQ2
DQ1
C
DQ12
DQ11
VSSQ
VDDQ
DQ4
DQ3
D
DQ10
DQ9
VDDQ
VSSQ
DQ6
DQ5
E
DQ8
NC
VSS
VDD
LDQM
DQ7
F
UDQM
CLK
CKE
CAS#
RAS#
WE#
G
NC
A11
A9
BA0
BA1
CS#
H
A8
A7
A6
A0
A1
A10
J
VSS
A5
A4
A3
A2
VDD
4
5
6
Top view
(Ball down)
Table 1:
Options
54-Ball VFBGA Ball Assignment
(Top View)
Address Table
Marking
• VDD/VDDQ
– 1.8V/1.8V
• Configurations
– 4 Meg x 16 (1 Meg x 16 x 4 banks)
• Plastic “green” package
– 54-ball VFBGA, 8mm x 8mm
• Timing (cycle time)
– 7.5ns @ CL = 3 (133 MHz)
– 8ns @ CL = 3 (125 MHz)
• Operating temperature
– Commercial (0°C to +70°C)
– Industrial (–40°C to +85°C)
• Die revision designator
4 Meg x 16
H
4M16
B4
-75
-8
Table 2:
None
IT
:H
Speed
Grade
Key Timing Parameters
CL = CAS (READ) latency
-75
-8
PDF: 09005aef8237ed98/Source: 09005aef8237ed68
64mb_x16_Mobile SDRAM_Y24L_1.fm - Rev. C 10/07 EN
1 Meg x 16 x 4 banks
4K
4K (A0–A11)
4 (BA0, BA1)
256 (A0–A7)
Configuration
Refresh count
Row addressing
Bank addressing
Column addressing
1
Clock Rate (MHz)
Access Time
CL = 2
CL = 3
CL = 2
CL = 3
104
83
133
125
8ns
8ns
6ns
6ns
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2006 Micron Technology, Inc. All rights reserved.
Products and specifications discussed herein are subject to change by Micron without notice.
64Mb: 4 Meg x 16 Mobile SDRAM
Table of Contents
Table of Contents
Options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1
Marking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1
General Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5
Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8
Initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8
Mode Register Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8
Burst Length (BL) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9
Burst Type . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10
CAS Latency (CL) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10
Operating Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11
Write Burst Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11
Extended Mode Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11
Temperature–Compensated Self Refresh (TCSR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12
Partial-Array Self Refresh . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12
Driver Strength . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13
Commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14
COMMAND INHIBIT. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15
NO OPERATION (NOP). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15
LOAD MODE REGISTER . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15
ACTIVE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15
READ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15
WRITE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15
PRECHARGE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16
BURST TERMINATE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16
Auto Precharge . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16
AUTO REFRESH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16
SELF REFRESH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16
Deep Power-Down. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17
Operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18
Bank/Row Activation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18
READs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19
WRITEs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .24
PRECHARGE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .28
Power-Down . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .28
Deep Power-Down. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .29
Clock Suspend. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .29
Burst Read/Single Write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .31
Concurrent Auto Precharge . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .31
READ with Auto Precharge . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .31
WRITE with Auto Precharge . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .32
Electrical Specifications. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .39
Notes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .43
Timing Diagrams. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .45
Package Dimensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .62
PDF: 09005aef8237ed98/Source: 09005aef8237ed68
64Mb_x16_Mobile SDRAM_Y24LTOC.fm - Rev. C 10/07 EN
2
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2006 Micron Technology, Inc. All rights reserved.
64Mb: 4 Meg x 16 Mobile SDRAM
List of Figures
List of Figures
Figure 1:
Figure 2:
Figure 3:
Figure 4:
Figure 5:
Figure 6:
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Figure 8:
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Figure 10:
Figure 11:
Figure 12:
Figure 13:
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Figure 22:
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Figure 24:
Figure 25:
Figure 26:
Figure 27:
Figure 28:
Figure 29:
Figure 30:
Figure 31:
Figure 32:
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Figure 36:
Figure 37:
Figure 38:
Figure 39:
Figure 40:
Figure 41:
Figure 42:
Figure 43:
Figure 44:
Figure 45:
Figure 46:
Figure 47:
Figure 48:
Figure 49:
54-Ball VFBGA Ball Assignment (Top View) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1
Part Numbering Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5
Functional Block Diagram – 4 Meg x 16 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6
Mode Register Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9
CAS Latency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11
Extended Mode Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12
Activating a Specific Row in a Specific Bank Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18
Meeting tRCD (MIN) when 2 < tRCD (MIN)/tCK < 3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19
READ Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20
Consecutive READ Bursts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20
Random READ Accesses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21
READ-to-WRITE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22
READ-to-WRITE with Extra Clock Cycle . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22
READ-to-PRECHARGE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23
Terminating a READ Burst . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23
WRITE Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .24
WRITE Burst . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .25
WRITE-to-WRITE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .25
Random WRITE Cycles . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .26
WRITE-to-READ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .26
WRITE-to-PRECHARGE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .27
Terminating a WRITE Burst . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .27
PRECHARGE Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .28
Power-Down . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .29
Clock Suspend During WRITE Burst . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .30
Clock Suspend During READ Burst . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .30
READ with Auto Precharge Interrupted by a READ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .31
READ with Auto Precharge Interrupted by a WRITE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .32
WRITE with Auto Precharge Interrupted by a READ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .33
WRITE with Auto Precharge Interrupted by a WRITE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .33
Typical Self Refresh Current vs. Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .42
Initialize and Load Mode Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .45
Power-Down Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .46
Clock Suspend Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .47
Auto Refresh Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .48
Self Refresh Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .49
READ – Without Auto Precharge . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .50
READ – with Auto Precharge . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .51
Single READ – Without Auto Precharge . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .52
Single READ – with Auto Precharge . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .53
Alternating Bank Read Accesses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .54
READ – DQM Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .55
WRITE – Without Auto Precharge . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .56
WRITE – with Auto Precharge . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .57
Single WRITE – Without Auto Precharge . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .58
Single WRITE – with Auto Precharge . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .59
Alternating Bank Write Accesses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .60
WRITE – DQM Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .61
54-Ball VFBGA (8mm x 8mm) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .62
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3
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2006 Micron Technology, Inc. All rights reserved.
64Mb: 4 Meg x 16 Mobile SDRAM
List of Tables
List of Tables
Table 1:
Table 2:
Table 3:
Table 4:
Table 5:
Table 6:
Table 7:
Table 8:
Table 9:
Table 10:
Table 11:
Table 12:
Table 13:
Table 14:
Table 15:
Table 16:
Address Table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1
Key Timing Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1
Ball Descriptions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7
Burst Definition. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10
Truth Table 1 – Commands and DQM Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14
Truth Table 2 – CKE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .34
Truth Table 3 – Current State Bank n, Command to Bank n . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .35
Truth Table 4 – Current State Bank n, Command to Bank m . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .37
Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .39
DC Electrical Characteristics and Operating Conditions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .39
AC Electrical Characteristics and Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .39
Electrical Characteristics and Recommended AC Operating Conditions . . . . . . . . . . . . . . . . . . . . . . .40
AC Functional Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .41
IDD Specifications and Conditions (x16) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .41
IDD7 - Self Refresh Current Options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .42
Capacitance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .42
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64Mb_x16_Mobile SDRAM_Y24LLOT.fm - Rev. C 10/07 EN
4
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2006 Micron Technology, Inc. All rights reserved.
64Mb: 4 Meg x 16 Mobile SDRAM
General Description
Figure 2:
Part Numbering Diagram
Example Part Number: MT48H4M16LFB4-8 IT :H
–
MT48
VDD/
VDDQ
Configuration
Package
Temp
Speed
Revision
VDD/VDDQ
1.8V/1.8V
:H Design revision
H
Operating Temp.
Configuration
4 Meg x16
4M16LF
Package
None
Commercial
IT
Industrial
Speed Grade
54-ball VFBGA (8mm x 8mm) ”green”
B4
-75
7.5ns
-8
8ns
General Description
The Micron® 64Mb SDRAM is a high-speed CMOS, dynamic random access memory
containing 67,108,864 bits. It is internally configured as a quad-bank DRAM with a
synchronous interface (all signals are registered on the positive edge of the clock signal,
CLK). Each of the x16’s 16,777,216-bit banks is organized as 4,096 rows by 256 columns
by 16 bits.
Read and write accesses to the SDRAM are burst oriented; accesses start at a selected
location and continue for a programmed number of locations in a programmed
sequence. Accesses begin with the registration of an ACTIVE command, which is then
followed by a READ or WRITE command. The address bits registered coincident with the
ACTIVE command are used to select the bank and row to be accessed (BA0, BA1 select
the bank; A0–A11 select the row). The address bits registered coincident with the READ
or WRITE command are used to select the starting column location for the burst access.
The SDRAM provides for programmable read or write burst lengths of 1, 2, 4, or 8 locations with a burst terminate option. An auto precharge function may be enabled to
provide a self-timed row precharge that is initiated at the end of the burst sequence.
The 64Mb SDRAM uses an internal pipelined architecture to achieve high-speed operation. This architecture is compatible with the 2n rule of prefetch architectures, but it also
enables the column address to be changed on every clock cycle to achieve a high-speed,
fully random access. Precharging one bank while accessing one of the other three banks
will hide the PRECHARGE cycles and provide seamless high-speed, random-access
operation.
The 64Mb SDRAM is designed to operate in 1.8V, low-power memory systems. An auto
refresh mode is provided, along with a power-saving, deep power-down mode. All inputs
and outputs are LVTTL-compatible.
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©2006 Micron Technology, Inc. All rights reserved.
64Mb: 4 Meg x 16 Mobile SDRAM
General Description
Self refresh mode offers temperature compensation through an on-die temperature
sensor and partial-array self refresh (PASR). PASR enables users to achieve additional
power savings from normal usage. The temperature sensor is enabled by default and the
PASR settings can be programmed through the extended mode register.
SDRAM offers substantial advances in DRAM operating performance, including the
ability to synchronously burst data at a high data rate with automatic column-address
generation, the ability to interleave between internal banks to hide precharge time, and
the capability to randomly change column addresses on each clock cycle during a burst
access.
Figure 3:
Functional Block Diagram – 4 Meg x 16
BA1
0
0
1
1
CKE
BA0
0
1
0
1
Bank
0
1
2
3
CLK
COMMAND
DECODE
CS#
WE#
CAS#
RAS#
CONTROL
LOGIC
BANK3
BANK2
BANK1
MODE REGISTER
REFRESH 12
COUNTER
12
ROWADDRESS
MUX
12
12
BANK0
ROWADDRESS
LATCH
&
DECODER
4096
BANK0
MEMORY
ARRAY
(4,096 x 256 x 16)
2
LDQM,
UDQM
SENSE AMPLIFIERS
16
4096
14
ADDRESS
REGISTER
2
DATA
OUTPUT
REGISTER
I/O GATING
DQM MASK LOGIC
READ DATA LATCH
WRITE DRIVERS
2
A0-A11,
BA0, BA1
2
BANK
CONTROL
LOGIC
16
16
256
(x16)
DQ0DQ15
DATA
INPUT
REGISTER
COLUMN
DECODER
8
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COLUMNADDRESS
COUNTER/
LATCH
8
6
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©2006 Micron Technology, Inc. All rights reserved.
64Mb: 4 Meg x 16 Mobile SDRAM
General Description
Table 3:
Ball Descriptions
54-Ball VFBGA
Symbol
Type
Description
F2
CLK
Input
F3
CKE
Input
G9
CS#
Input
F7, F8, F9
CAS#, RAS#,
WE#
LDQM,
UDQM
Input
G7, G8
BA0, BA1
Input
H7, H8, J8, J7, J3, J2, H3,
H2, H1, G3, H9, G2
A0–A11
Input
A8, B9, B8, C9, C8, D9,
D8, E9, E1, D2, D1, C2,
C1, B2, B1, A2
E2, G1
DQ0–DQ15
I/O
Clock: CLK is driven by the system clock. All SDRAM input signals are
sampled on the positive edge of CLK. CLK also increments the internal
burst counter and controls the output registers.
Clock enable: CKE activates (HIGH) and deactivates (LOW) the CLK signal.
Deactivating the clock provides precharge power-down and SELF REFRESH
operation (all banks idle), ACTIVE POWER-DOWN (row active in any
bank), deep power-down (all banks idle), or CLOCK SUSPEND operation
(burst/access in progress). CKE is synchronous except after the device
enters power-down and self refresh modes, where CKE becomes
asynchronous until after exiting the same mode. The input buffers,
including CLK, are disabled during power-down and self refresh modes,
providing low standby power. CKE may be tied HIGH.
Chip select: CS# enables (registered LOW) and disables (registered HIGH)
the command decoder. All commands are masked when CS# is registered
HIGH. CS# provides for external bank selection on systems with multiple
banks. CS# is considered part of the command code.
Command inputs: CAS#, RAS#, and WE# (along with CS#) define the
command being entered.
Input/output mask: DQM is sampled HIGH and is an input mask signal for
write accesses and an output enable signal for read accesses. Input data is
masked during a WRITE cycle. The output buffers are placed in a High-Z
state (two-clock latency) during a READ cycle. LDQM corresponds to DQ0–
DQ7, UDQM corresponds to DQ8–DQ15. LDQM and UDQM are considered
same state when referenced as DQM. DQM loading is designed to match
that of DQ balls.
Bank address input(s): BA0 and BA1 define to which bank the ACTIVE,
READ, WRITE, or PRECHARGE command is being applied. These pins also
select between the mode register and the extended mode register.
Address inputs: A0–A11 are sampled during the ACTIVE command (rowaddress A0–A11) and READ/WRITE command (column-address A0–A7;
with A10 defining auto precharge) to select one location out of the
memory array in the respective bank. A10 is sampled during a
PRECHARGE command to determine whether all banks are to be
precharged (A10 HIGH) or bank selected by BA0, BA1. The address inputs
also provide the op-code during a LOAD MODE REGISTER command.
Data input/output: Data bus.
NC
–
A7, B3, C7, D3
A3, B7, C3, D7
A9, E7, J9
A1, E3, J1
VDDQ
VSSQ
VDD
VSS
Supply
Supply
Supply
Supply
E8, F1
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Input
NC = no connect (internally unconnected): These may be left
unconnected, but it is recommended that they be connected to VSS.
DNU = do not use; must be left unconnected.
DQ power: Provides isolated power to DQ for improved noise immunity.
DQ ground: Provides isolated ground to DQ for improved noise immunity.
Core power supply.
Ground.
7
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2006 Micron Technology, Inc. All rights reserved.
64Mb: 4 Meg x 16 Mobile SDRAM
Functional Description
Functional Description
The 64Mb SDRAM (1 Meg x 16 x 4 banks) is a quad-bank DRAM that operates at 1.8V and
includes a synchronous interface (all signals are registered on the positive edge of the
clock signal, CLK). Each of the x16’s 16,777,216-bit banks is organized as 4,096 rows by
256 columns by 16 bits.
Read and write accesses to the SDRAM are burst oriented; accesses start at a selected
location and continue for a programmed number of locations in a programmed
sequence. Accesses begin with the registration of an ACTIVE command, which is then
followed by a READ or WRITE command. The address bits registered coincident with the
ACTIVE command are used to select the bank and row to be accessed (BA0 and BA1
select the bank; A0–A11 select the row). The address bits (A0–A7) registered coincident
with the READ or WRITE command are used to select the starting column location for
the burst access.
Prior to normal operation, the SDRAM must be initialized. The following sections
provide detailed information covering device initialization, register definition,
command descriptions, and device operation.
Initialization
SDRAM must be powered up and initialized in a predefined manner. Operational procedures other than those specified may result in undefined operation. Power should be
applied to VDD and VDDQ simultaneously. After the power is applied to VDD and VDDQ
and the clock is stable (stable clock is defined as a signal cycling within timing
constraints specified for the clock pin), the SDRAM requires a 100µs delay prior to
issuing any command other than a COMMAND INHIBIT or NOP. Starting at some point
during this 100µs period and continuing at least through the end of this period,
COMMAND INHIBIT or NOP commands should be applied.
After the 100µs delay has been satisfied with at least one COMMAND INHIBIT or NOP
command having been applied, a PRECHARGE command should be applied. All banks
must then be precharged, thereby placing the device in the all-banks-idle state.
When in the idle state, two AUTO REFRESH cycles must be performed. After the AUTO
REFRESH cycles are complete, the SDRAM is ready for mode register programming.
Because the mode register will power up in an unknown state, it should be loaded prior
to applying any operational command.
Mode Register Definition
Two mode registers exist in mobile SDRAM: the mode register and the extended mode
register. The mode register is illustrated in Figure 4 on page 9, and the extended mode
register is illustrated in Figure 6 on page 12.
The mode register defines the specific mode of operation of the SDRAM, including burst
length, burst type, CAS latency, operating mode, and write burst mode. The mode
register is programmed via the LOAD MODE REGISTER command and will retain the
stored information until it is programmed again or the device loses power.
Mode register bits M0–M2 specify the burst length, M3 specifies the type of burst
(sequential or interleaved), M4–M6 specify the CAS latency, M7 and M8 specify the operating mode, M9 specifies the write burst mode, and M10 and M11 are reserved for future
use and should be set to zero. M12 and M13 are set to zero to select the mode register.
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64Mb: 4 Meg x 16 Mobile SDRAM
Mode Register Definition
The mode register must be loaded when all banks are idle, and the controller must wait
t
MRD before initiating the subsequent operation. Violating either of these requirements
will result in unspecified operation.
Figure 4:
Mode Register Definition
BA1 BA0 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1
A0
Address bus
M13 M12 M11 M10 M9 M8 M7 M6 M5 M4 M3 M2 M1 M0
13
0
9
8
7
6 5
4
12 11 10
0 Reserved WB OP Mode CAS Latency
0
Mode
register (Mx)
Burst Length
M13 M12 Mode Register Definintion
0
0
Base mode register
1
0
3
2
1
BT Burst Length
M2 M1 M0
Extended mode register
M3 = 0
M3 = 1
0
0
0
1
1
0
0
1
2
2
0
1
0
4
4
Write Burst Mode
0
1
1
8
0
Programmed burst length
1
0
0
Reserved
8
Reserved
1
Single location access
1
0
1
Reserved
Reserved
1
1
0
Reserved
Reserved
1
1
1
Reserved
Reserved
M9
M8 M7
M6–M0
Operating Mode
Normal operation
0
0
Defined
–
–
–
All other states reserved
M3
M6 M5 M4
CAS Latency
0
0
0
Reserved
0
0
1
Reserved
0
1
0
2
0
1
1
3
1
0
0
Reserved
1
0
1
Reserved
1
1
0
Reserved
1
1
1
Reserved
Burst Type
0
Sequential
1
Interleaved
Burst Length (BL)
Read and write accesses to the SDRAM are burst oriented, with the burst length (BL)
being programmable, as shown in Figure 4 on page 9. The BL determines the maximum
number of column locations that can be accessed for a given READ or WRITE command.
BLs of 1, 2, 4, or 8 locations are available for both the sequential and the interleaved
burst types. Reserved states must not be used, as unknown operation or incompatibility
with future versions may result.
When a READ or WRITE command is issued, a block of columns equal to the BL is effectively selected. All accesses for that burst take place within this block, meaning that the
burst will wrap within the block if a boundary is reached. The block is uniquely selected
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64Mb: 4 Meg x 16 Mobile SDRAM
Mode Register Definition
by A1–A7 when BL = 2; by A2–A7 when BL = 4; and by A3–A7 when
BL = 8. The remaining (least significant) address bit(s) is (are) used to select the starting
location within the block.
Burst Type
Accesses within a given burst may be programmed to be sequential or interleaved; this is
referred to as the burst type and is selected via bit M3.
The ordering of accesses within a burst is determined by the BL, the burst type, and the
starting column address, as shown in Table 4.
Table 4:
Burst Definition
Burst
Length
Order of Accesses within a Burst
Starting Column Address
2
4
8
A1
0
0
1
1
A1
0
0
1
1
0
0
1
1
A2
0
0
0
0
1
1
1
1
A0
0
1
A0
0
1
0
1
A0
0
1
0
1
0
1
0
1
Type = Sequential
Type = Interleaved
0-1
1-0
0-1
1-0
0-1-2-3
1-2-3-0
2-3-0-1
3-0-1-2
0-1-2-3
1-0-3-2
2-3-0-1
3-2-1-0
0-1-2-3-4-5-6-7
1-2-3-4-5-6-7-0
2-3-4-5-6-7-0-1
3-4-5-6-7-0-1-2
4-5-6-7-0-1-2-3
5-6-7-0-1-2-3-4
6-7-0-1-2-3-4-5
7-0-1-2-3-4-5-6
0-1-2-3-4-5-6-7
1-0-3-2-5-4-7-6
2-3-0-1-6-7-4-5
3-2-1-0-7-6-5-4
4-5-6-7-0-1-2-3
5-4-7-6-1-0-3-2
6-7-4-5-2-3-0-1
7-6-5-4-3-2-1-0
CAS Latency (CL)
The CAS latency (CL) is the delay, in clock cycles, between the registration of a READ
command and the availability of the first piece of output data. The latency can be set to
two or three clocks.
If a READ command is registered at clock edge n, and the latency is m clocks, the data
will be available by clock edge n + m. The DQ will start driving as a result of the clock
edge one cycle earlier (n + m - 1), and provided that the relevant access times are met,
the data will be valid by clock edge n + m. For example, assuming that the clock cycle
time is such that all relevant access times are met, if a READ command is registered at T0
and the latency is programmed to two clocks, the DQ will start driving after T1 and the
data will be valid by T2, as shown in Figure 5 on page 11. Table 5 on page 14 indicates the
operating frequencies at which each CL setting can be used.
Reserved states should not be used because unknown operation or incompatibility with
future versions may result.
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©2006 Micron Technology, Inc. All rights reserved.
64Mb: 4 Meg x 16 Mobile SDRAM
Mode Register Definition
Figure 5:
CAS Latency
T0
T1
T2
T3
READ
NOP
NOP
CLK
Command
tLZ
tOH
DOUT
DQ
tAC
CL = 2
T0
T1
T2
T3
T4
READ
NOP
NOP
NOP
CLK
Command
tLZ
tOH
DOUT
DQ
tAC
CL = 3
Don’t Care
Undefined
Operating Mode
The normal operating mode is selected by setting M7 and M8 to zero; the other combinations of values for M7 and M8 are reserved for future use. The programmed burst
length applies to both read and write bursts.
Reserved states must not be used; unknown operation or incompatibility with future
versions may result.
Write Burst Mode
When M9 = 0, the burst length programmed via M0–M2 applies to both READ and
WRITE bursts; when M9 = 1, the programmed burst length applies to READ bursts, but
write accesses are single-location accesses.
Extended Mode Register
The extended mode register controls the functions beyond those controlled by the mode
register. These additional functions are special features of the mobile device. They
include temperature-compensated self refresh (TCSR) control, partial-array self refresh
(PASR), and output drive strength.
The extended mode register is programmed via the MODE REGISTER SET command
with BA = 1 and BA = 0 and retains the stored information until it is programmed again
or the device loses power.
The extended mode register must be loaded when all banks are idle and no bursts are in
progress, and the controller must wait tMRD before initiating any subsequent operation.
Violating any of these requirements will result in unspecified operation.
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64Mb: 4 Meg x 16 Mobile SDRAM
Mode Register Definition
Figure 6:
Extended Mode Register
BA1 BA0 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0
E13
13
1
E12 E11 E10 E9 E8 E7 E6 E5 E4 E3 E2 E1 E0
12 11 10
0
9
8
7
6
All must be set to “0”
E13 E12 Mode Register Definition
0 Base mode register
0
1 Reserved
0
0 Extended mode register
1
1 Reserved
1
E4
0
5
4
3
1
TCSR
DS
2
1
PASR
0
Extended mode
register (Ex)
E3 Maximum Case Temp.
1
1
85°C
0
0
70°C
0
1
45°C
1
0
15°C
E6 E5 Driver Strength
Notes:
Address bus
0 Full strength
E2
0
0
E1
0
0
E0
0
1
Self Refresh Coverage
Four banks
Two banks
0
1 Half strength
1
0 Quarter strength
0
1
0
One bank
1
1 Reserved
0
1
1
1
1
0
0
1
1
0
1
0
Reserved
Reserved
1/2 bank2
1/4 bank2
1
1
1
Reserved
1. The on-die temperature sensor is used in place of TCSR. Setting these bits has no effect.
2. 1/2- and 1/4-bank settings will default to one-bank PASR.
Temperature–Compensated Self Refresh (TCSR)
On this version of the Mobile SDR SDRAM, a temperature sensor is implemented for
automatic control of the self refresh oscillator on the device. Therefore, it is recommended not to program or use the TCSR control bits in the extended mode register.
Programming of the TCSR bits has no effect on the device. The self refresh oscillator will
continue refresh at the factory-programmed optimal rate for the device temperature.
Partial-Array Self Refresh
For further power savings during SELF REFRESH, the PASR feature enables the
controller to select the amount of memory that will be refreshed during SELF REFRESH.
The following refresh options are available:
• All banks (banks 0, 1, 2, and 3)
• Two banks (banks 0 and 1; BA1 = 0)
• One bank (bank 0; BA1 = BA0 = 0)
WRITE and READ commands occur to any bank selected during standard operation, but
only the selected banks in PASR will be refreshed during SELF REFRESH. Data in unused
banks, or portions of banks, is lost when PASR is used.
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Mode Register Definition
Driver Strength
Bits E5 and E6 of the extended mode register can be used to select the driver strength of
the DQ outputs. This value should be set according to the application’s requirements.
Full-drive strength is suitable to drive higher load systems. Half-drive strength is
intended for multi-drop systems with various loads. Quarter-drive strength is intended
for lighter loads or point-to-point systems.
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Commands
Commands
Table 5 provides a quick reference of available commands. This is followed by a written
description of each command. Three additional truth tables appear following “Operations” on page 18; these tables provide current state/next state information.
Table 5:
Truth Table 1 – Commands and DQM Operation
Note 1; notes appear below table
Name (Function)
CS# RAS# CAS# WE#
COMMAND INHIBIT (NOP)
NO OPERATION (NOP)
ACTIVE (Select bank and activate row)
READ (Select bank and column, and start READ burst)
WRITE (Select bank and column, and start WRITE burst)
BURST TERMINATE or deep power-down
(Enter deep power-down mode)
PRECHARGE (Deactivate row in bank or banks)
AUTO REFRESH or SELF REFRESH
(Enter self refresh mode)
LOAD MODE REGISTER/LOAD EXTENDED MODE
REGISTER
Write enable/output enable
Write inhibit/output High-Z
Notes:
1.
2.
3.
4.
5.
6.
7.
8.
9.
10.
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DQM
ADDR
DQ
Notes
H
L
L
L
L
L
X
H
L
H
H
H
X
H
H
L
L
H
X
H
H
H
L
L
X
X
X
L/H
L/H
X
X
X
Bank/Row
Bank/Col
Bank/Col
X
X
X
X
X
Valid
X
3
4
4
9, 10
L
L
L
L
H
L
L
H
X
X
Bank, A10
X
X
X
5
6, 7
L
L
L
L
X
Op-code
X
2
X
X
X
X
X
X
X
X
L
H
X
X
Active
High-Z
8
8
CKE is HIGH for all commands shown except SELF REFRESH and deep power-down.
A0–A11 define op-code written to mode register.
A0–A11 provide row address, and BA0, BA1 determine which bank is made active.
A0–A7 provide column address; A10 HIGH enables the auto precharge feature (nonpersistent), while A10 LOW disables the auto precharge feature; BA0, BA1 determine which bank
is being read from or written to.
A10 LOW: BA0, BA1 determine the bank being precharged. A10 HIGH: All banks precharged
and BA0, BA1 are “Don’t Care.”
This command is AUTO REFRESH if CKE is HIGH, SELF REFRESH if CKE is LOW.
Internal refresh counter controls row addressing; all inputs and I/Os are “Don’t Care” except
for CKE.
Activates or deactivates the DQ during WRITEs (zero-clock delay) and READs (two-clock
delay). LDQM controls DQ0–7, UDQM controls DQ8–15.
This command is BURST TERMINATE when CKE is HIGH and deep power-down when CKE is
LOW.
The purpose of the BURST TERMINATE command is to stop a data burst; thus, the command
could coincide with data on the bus. However, the DQ column reads a “Don’t Care” state to
illustrate that the BURST TERMINATE command can occur when there is no data present.
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Commands
COMMAND INHIBIT
The COMMAND INHIBIT function prevents new commands from being executed by the
SDRAM, regardless of whether the CLK signal is enabled. The SDRAM is effectively deselected. Operations already in progress are not affected.
NO OPERATION (NOP)
The NO OPERATION (NOP) command is used to perform a NOP to an SDRAM which is
selected (CS# is LOW). This prevents unwanted commands from being registered during
idle or wait states. Operations already in progress are not affected.
LOAD MODE REGISTER
The mode register is loaded via inputs A0–A11, BA0, BA1. See the “Mode Register”
heading in the Register Definition section. The LOAD MODE REGISTER and LOAD
EXTENDED MODE REGISTER commands can only be issued when all banks are idle,
and a subsequent executable command cannot be issued until tMRD is met.
ACTIVE
The ACTIVE command is used to open (or activate) a row in a particular bank for a
subsequent access. The value on the BA0, BA1 inputs selects the bank, and the address
provided on inputs A0–A11 selects the row. This row remains active (or open) for
accesses until a PRECHARGE command is issued to that bank. A PRECHARGE
command must be issued before opening a different row in the same bank.
READ
The READ command is used to initiate a burst read access to an active row. The value on
the BA0, BA1 inputs selects the bank, and the address provided on inputs A0–A7 selects
the starting column location. The value on input A10 determines whether auto
precharge is used. If auto precharge is selected, the row being accessed will be
precharged at the end of the read burst; if auto precharge is not selected, the row will
remain open for subsequent accesses. Read data appears on the DQ subject to the logic
level on the DQM inputs two clocks earlier. If a given DQM signal was registered HIGH,
the corresponding DQ will be High-Z two clocks later; if the DQM signal was registered
LOW, the DQ will provide valid data.
WRITE
The WRITE command is used to initiate a burst write access to an active row. The value
on the BA0, BA1 inputs selects the bank, and the address provided on inputs A0–A7
selects the starting column location. The value on input A10 determines whether auto
precharge is used. If auto precharge is selected, the row being accessed will be
precharged at the end of the write burst; if auto precharge is not selected, the row will
remain open for subsequent accesses. Input data appearing on the DQ is written to the
memory array subject to the DQM input logic level appearing coincident with the data.
If a given DQM signal is registered LOW, the corresponding data will be written to
memory; if the DQM signal is registered HIGH, the corresponding data inputs will be
ignored, and a write will not be executed to that byte/column location.
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Commands
PRECHARGE
The PRECHARGE command is used to deactivate the open row in a particular bank or
the open row in all banks. The bank(s) will be available for a subsequent row access a
specified time (tRP) after the PRECHARGE command is issued. Input A10 determines
whether one or all banks are to be precharged, and in the case where only one bank is to
be precharged, inputs BA0, BA1 select the bank. Otherwise BA0, BA1 are treated as
“Don’t Care.” After a bank has been precharged, it is in the idle state and must be activated prior to any READ or WRITE commands being issued to that bank.
BURST TERMINATE
The BURST TERMINATE command is used to truncate fixed-length bursts. The most
recently registered READ or WRITE command prior to the BURST TERMINATE
command will be truncated, as shown in “Operations” on page 18.
Auto Precharge
Auto precharge is a feature that performs the same individual-bank PRECHARGE function described above, without requiring an explicit command. This is accomplished by
using A10 to enable auto precharge in conjunction with a specific READ or WRITE
command. A precharge of the bank/row that is addressed with the READ or WRITE
command is automatically performed upon completion of the READ or WRITE burst.
Auto precharge is nonpersistent in that it is either enabled or disabled for each individual READ or WRITE command.
Auto precharge ensures that the precharge is initiated at the earliest valid stage within a
burst. The user must not issue another command to the same bank until the precharge
time (tRP) is completed. This is determined as if an explicit PRECHARGE command was
issued at the earliest possible time, as described for each burst type in “Operations” on
page 18.
AUTO REFRESH
AUTO REFRESH is used during normal operation of the SDRAM and is analogous to
CAS#-BEFORE-RAS# (CBR) refresh in conventional DRAM. This command is nonpersistent, so it must be issued each time a refresh is required. All active banks must be
PRECHARGED prior to issuing an AUTO REFRESH command. The AUTO REFRESH
command should not be issued until the minimum tRP has been met after the
PRECHARGE command, as shown in “Operations” on page 18.
The addressing is generated by the internal refresh controller. This makes the address
bits “Don’t Care” during an AUTO REFRESH command. The 64Mb SDRAM requires
4,096 AUTO REFRESH cycles every 64ms (tREF). Providing a distributed AUTO REFRESH
command every 15.625µs will meet the refresh requirement and ensure that each row is
refreshed. Alternatively, 4,096 AUTO REFRESH commands can be issued in a burst at the
minimum cycle rate (tRFC), once every 64ms.
SELF REFRESH
The SELF REFRESH command can be used to retain data in the SDRAM, even if the rest
of the system is powered down, as long as power is not completely removed from the
SDRAM. When in the self refresh mode, the SDRAM retains data without external
clocking. The SELF REFRESH command is initiated like an AUTO REFRESH command
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Commands
except CKE is disabled (LOW). When the SELF REFRESH command is registered, all the
inputs to the SDRAM become “Don’t Care” with the exception of CKE, which must
remain LOW.
During self refresh, the device is refreshed as identified in the extended mode register
PASR settings. After self refresh mode is engaged, the SDRAM provides its own internal
clocking, causing it to perform its own AUTO REFRESH cycles. The SDRAM must remain
in self refresh mode for a minimum period equal to tRAS and may remain in self refresh
mode for an indefinite period beyond that.
The procedure for exiting self refresh requires a sequence of commands. First, CLK must
be stable (stable clock is defined as a signal cycling within timing constraints specified
for the clock pin) prior to CKE going back HIGH. When CKE is HIGH, the SDRAM must
have NOP commands issued (a minimum of two clocks) for tXSR because time is
required for the completion of any internal refresh in progress.
Upon exiting the self refresh mode, AUTO REFRESH commands should be issued at
once and then every 15.625µs or less, because SELF REFRESH and AUTO REFRESH use
the row refresh counter.
Deep Power-Down
Deep power-down is an operating mode used to achieve maximum power reduction by
eliminating the power to the memory array. Data is not retained after the device enters
deep power-down mode.
This mode is entered by having all banks idle then CS# and WE# held LOW with RAS#
and CAS# held HIGH at the rising edge of the clock, while CKE is LOW. This mode is
exited by asserting CKE HIGH.
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Operations
Operations
Bank/Row Activation
Before any READ or WRITE commands can be issued to a bank within the SDRAM, a row
in that bank must be “opened.” This is accomplished via the ACTIVE command, which
selects both the bank and the row to be activated (see Figure 7).
After opening a row (issuing an ACTIVE command), a READ or WRITE command may be
issued to that row, subject to the tRCD specification. tRCD (MIN) should be divided by
the clock period and rounded up to the next whole number to determine the earliest
clock edge after the ACTIVE command on which a READ or WRITE command can be
entered. For example, a tRCD specification of 20ns with a 125 MHz clock (8ns period)
results in 2.5 clocks, rounded to 3. This is reflected in Figure 8 on page 19, which covers
any case where 2 < tRCD (MIN)/tCK ≤ 3. (The same procedure is used to convert other
specification limits from time units to clock cycles.)
A subsequent ACTIVE command to a different row in the same bank can only be issued
after the previous active row has been “closed” (precharged). The minimum time
interval between successive ACTIVE commands to the same bank is defined by tRC.
A subsequent ACTIVE command to another bank can be issued while the first bank is
being accessed, which results in a reduction of total row-access overhead. The minimum
time interval between successive ACTIVE commands to different banks is defined by
t
RRD.
Figure 7:
Activating a Specific Row in a Specific Bank Register
CLK
CKE
HIGH
CS#
RAS#
CAS#
WE#
Address
BA0, BA1
Row
Address
Bank
Address
Don’t Care
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Operations
Figure 8:
Meeting tRCD (MIN) when 2 < tRCD (MIN)/tCK < 3
T0
T1
T2
NOP
NOP
T3
T4
CLK
Command
ACTIVE
READ or
WRITE
tRCD
Don’t Care
READs
READ bursts are initiated with a READ command, as shown in Figure 8.
The starting column and bank addresses are provided with the READ command, and
auto precharge is either enabled or disabled for that burst access. If auto precharge is
enabled, the row being accessed is precharged at the completion of the burst.
Note:
For the generic READ commands used in the following illustrations, auto precharge is
disabled.
During READ bursts, the valid data-out element from the starting column address will
be available following the CL after the READ command. Each subsequent data-out
element will be valid by the next positive clock edge. Figure 5 on page 11 shows general
timing for each possible CL setting.
Upon completion of a burst, assuming no other commands have been initiated, the DQ
will go High-Z.
Data from any READ burst may be truncated with a subsequent READ command, and
data from a fixed-length READ burst may be immediately followed by data from a READ
command. In either case, a continuous flow of data can be maintained. The first data
element from the new burst follows either the last element of a completed burst or the
last desired data element of a longer burst that is being truncated. The new READ
command should be issued x cycles before the clock edge at which the last desired data
element is valid, where x = CL - 1.
This is shown in Figure 10 on page 20 for CL = 2 and CL = 3; data element n + 3 is either
the last of a burst of four or the last desired of a longer burst. The Mobile SDRAM uses a
pipelined architecture and therefore does not require the 2n rule associated with a
prefetch architecture. A READ command can be initiated on any clock cycle following a
previous READ command. Full-speed random read accesses can be performed to the
same bank, as shown in Figure 11 on page 21, or each subsequent READ may be
performed to a different bank.
Data from any READ burst may be truncated with a subsequent WRITE command, and
data from a fixed-length READ burst may be immediately followed by data from a
WRITE command (subject to bus turnaround limitations). The WRITE burst may be
initiated on the clock edge immediately following the last (or last desired) data element
from the READ burst, provided that I/O contention can be avoided. In a given system
design, there may be a possibility that the device driving the input data will go Low-Z
before the SDRAM DQ go High-Z. In this case, at least a single-cycle delay should occur
between the last read data and the WRITE command.
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Operations
Figure 9:
READ Command
CLK
CKE
HIGH
CS#
RAS#
CAS#
WE#
Column
Address
Address
Enable auto precharge
A10
Disable auto precharge
Bank
Address
BA0, BA1
Don’t Care
Figure 10:
Consecutive READ Bursts
T0
T1
T2
T3
T4
T5
T6
CLK
Command
READ
Address
Bank,
Col n
NOP
NOP
NOP
NOP
READ
NOP
X = 1 cycle
Bank,
Col b
DOUT
n
DQ
DOUT
n+2
DOUT
n+1
DOUT
n+3
DOUT
b
CL = 2
T0
T1
T2
T3
T4
T5
T6
T7
CLK
Command
READ
Address
Bank,
Col n
NOP
NOP
NOP
READ
NOP
NOP
NOP
X = 2 cycles
Bank,
Col b
DOUT
n
DQ
DOUT
n+1
DOUT
n+2
DOUT
n+3
DOUT
b
CL = 3
Transitioning Data
Note:
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Don’t Care
Each READ command may be issued to any bank. DQM is LOW.
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Operations
Figure 11:
Random READ Accesses
T0
T1
T2
T3
T4
T5
CLK
Command
Address
READ
READ
READ
READ
Bank,
Col n
Bank,
Col a
Bank,
Col x
Bank,
Col m
DOUT
n
DQ
NOP
NOP
DOUT
x
DOUT
a
DOUT
m
CL = 2
T0
T1
T2
T3
T4
T5
T6
CLK
Command
READ
READ
READ
READ
Address
Bank,
Col n
Bank,
Col a
Bank,
Col x
Bank,
Col m
DOUT
n
DQ
NOP
DOUT
a
NOP
DOUT
x
NOP
DOUT
m
CL = 3
Transitioning Data
Note:
Don’t Care
Each READ command may be issued to any bank. DQM is LOW.
The DQM input is used to avoid I/O contention, as shown in Figure 12 on page 22 and
Figure 13 on page 22. The DQM signal must be asserted (HIGH) at least two clocks prior
to the WRITE command (DQM latency is two clocks for output buffers) to suppress dataout from the READ. After the WRITE command is registered, the DQ will go High-Z (or
remain High-Z), regardless of the state of the DQM signal, provided the DQM was active
on the clock just prior to the WRITE command that truncated the READ command. If
not, the second WRITE will be an invalid WRITE. For example, if DQM was LOW during
T4 in Figure 14 on page 23, then the WRITEs at T5 and T7 would be valid, while the
WRITE at T6 would be invalid.
The DQM signal must be de-asserted prior to the WRITE command (DQM latency is
zero clocks for input buffers) to ensure that the written data is not masked. Figure 13 on
page 22 shows the case where the clock frequency allows for bus contention to be
avoided without adding a NOP cycle, and Figure 14 on page 23 shows the case where the
additional NOP is needed. A fixed-length READ burst may be followed by, or truncated
with, a PRECHARGE command to the same bank (provided that auto precharge was not
activated). The PRECHARGE command should be issued x cycles before the clock edge
at which the last desired data element is valid, where x equals the CL minus one. This is
shown in Figure 14 for each possible CL; data element n + 3 is either the last of a burst of
four or the last desired of a longer burst. Following the PRECHARGE command, a subsequent command to the same bank cannot be issued until tRP is met.
Note:
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Part of the row precharge time is hidden during the access of the last data element(s).
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Operations
In the case of a fixed-length burst being executed to completion, a PRECHARGE
command issued at the optimum time (as described above) provides the same operation
that would result from the same fixed-length burst with auto precharge. The disadvantage of the PRECHARGE command is that it requires that the command and address
buses be available at the appropriate time to issue the command; the advantage of the
PRECHARGE command is that it can be used to truncate fixed-length bursts.
Figure 12:
READ-to-WRITE
T0
T1
T2
T3
T4
CLK
DQM
Command
READ
Address
Bank,
Col n
NOP
NOP
NOP
WRITE
Bank,
Col b
tCK
tHZ
DOUT n
DQ
DIN b
tDS
Transitioning Data
Note:
Figure 13:
Don’t Care
A CL of three is used for illustration. The READ command may be issued to any bank, and
the WRITE command may be issued to any bank. If a burst of one is used, then DQM is not
required.
READ-to-WRITE with Extra Clock Cycle
T0
T1
T2
T3
T4
T5
CLK
DQM
Command
Address
READ
NOP
NOP
NOP
NOP
WRITE
Bank,
Col b
Bank,
Col n
tHZ
DOUT n
DQ
DIN b
tDS
Transitioning Data
Note:
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Don’t Care
A CL of three is used for illustration. The READ command may be issued to any bank, and
the WRITE command may be issued to any bank.
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Operations
Figure 14:
READ-to-PRECHARGE
T0
T1
T2
T3
T4
T5
T6
T7
CLK
t RP
Command
READ
NOP
NOP
NOP
PRECHARGE
NOP
NOP
ACTIVE
X = 1 cycle
Address
Bank
(a or all)
Bank a,
Col n
DOUT
n+2
DOUT
n+1
DOUT
n
DQ
Bank a,
Row
DOUT
n+3
CL = 2
T0
T1
T2
T3
T4
T5
T6
T7
CLK
t RP
Command
READ
Address
Bank a,
Col n
NOP
NOP
NOP
PRECHARGE
NOP
NOP
ACTIVE
X = 2 cycles
Bank
(a or all)
DOUT
n+2
DOUT
n+1
DOUT
n
DQ
Bank a,
Row
DOUT
n+3
CL = 3
Transitioning Data
Note:
Figure 15:
Don’t Care
DQM is LOW.
Terminating a READ Burst
T0
T1
T2
T3
T4
T5
T6
CLK
Command
READ
Address
Bank,
Col n
NOP
NOP
NOP
BURST
TERMINATE
NOP
NOP
X = 1 cycle
DOUT
n
DQ
DOUT
n+2
DOUT
n+1
DOUT
n+3
CL = 2
T0
T1
T2
T3
T4
T5
T6
T7
CLK
Command
READ
Address
Bank,
Col n
NOP
NOP
NOP
BURST
TERMINATE
NOP
NOP
NOP
X = 2 cycles
DOUT
n
DQ
DOUT
n+1
DOUT
n+2
DOUT
n+3
CL = 3
Transitioning Data
Note:
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Don’t Care
DQM is LOW.
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64Mb: 4 Meg x 16 Mobile SDRAM
Operations
Fixed-length READ bursts may be truncated with a BURST TERMINATE command,
provided that auto precharge was not activated. The BURST TERMINATE command
should be issued x cycles before the clock edge at which the last desired data element is
valid, where x equals the CL minus one. This is shown in Figure 15 on page 23 for each
possible CL; data element n + 3 is the last desired data element of a longer burst.
WRITEs
WRITE bursts are initiated with a WRITE command, as shown in Figure 16.
The starting column and bank addresses are provided with the WRITE command and
auto precharge is either enabled or disabled for that access. If auto precharge is enabled,
the row being accessed is precharged at the completion of the burst. For the generic
WRITE commands used in the following illustrations, auto precharge is disabled.
During WRITE bursts, the first valid data-in element will be registered coincident with
the WRITE command. Subsequent data elements will be registered on each successive
positive clock edge. Upon completion of a fixed-length burst, assuming no other
commands have been initiated, the DQ will remain High-Z and any additional input
data will be ignored (see Figure 18 on page 25).
Figure 16:
WRITE Command
CLK
CKE HIGH
CS#
RAS#
CAS#
WE#
Column
Address
Address
Enable auto precharge
A10
Disable auto precharge
Bank
Address
BA0, BA1
Don’t Care
Valid Address
Data for any WRITE burst may be truncated with a subsequent WRITE command, and
data for a fixed-length WRITE burst may be immediately followed by data for a WRITE
command. The new WRITE command can be issued on any clock following the previous
WRITE command, and the data provided coincident with the new command applies to
the new command. An example is shown in Figure 19 on page 26. Data n + 1 is either the
last of a burst of two or the last desired of a longer burst. The Mobile SDRAM uses a pipelined architecture and therefore does not require the 2n rule associated with a prefetch
architecture. A WRITE command can be initiated on any clock cycle following a previous
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64Mb: 4 Meg x 16 Mobile SDRAM
Operations
WRITE command. Full-speed random write accesses within a page can be performed to
the same bank, as shown in Figure 19 on page 26, or each subsequent WRITE may be
performed to a different bank.
Figure 17:
WRITE Burst
T0
T1
T2
T3
Command
WRITE
NOP
NOP
NOP
Address
Bank,
Col n
CLK
DQ
DIN
n
DIN
n+1
Transitioning Data
Note:
Figure 18:
Don’t Care
BL = 2. DQM is LOW.
WRITE-to-WRITE
T0
T1
T2
Command
WRITE
NOP
WRITE
Address
Bank,
Col n
CLK
DQ
DIN
n
Transitioning Data
Note:
Bank,
Col b
DIN
n+1
DIN
b
Don’t Care
DQM is LOW. Each WRITE command may be issued to any bank.
Data for any WRITE burst may be truncated with a subsequent READ command, and
data for a fixed-length WRITE burst may be immediately followed by a READ command.
After the READ command is registered, the data inputs will be ignored and writes will
not be executed. An example is shown in Figure 20 on page 26. Data n + 1 is either the
last of a burst of two or the last desired of a longer burst.
Data for a fixed-length WRITE burst may be followed by, or truncated with, a
PRECHARGE command to the same bank (provided that auto precharge was not activated). The PRECHARGE command should be issued tWR after the clock edge at which
the last desired input data element is registered. The auto precharge mode requires a
t
WR of at least one clock plus time, regardless of frequency.
In addition, when truncating a WRITE burst, the DQM signal must be used to mask
input data for the clock edge prior to, and the clock edge coincident with, the
PRECHARGE command. An example is shown in Figure 21 on page 27. Data n + 1 is
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64Mb: 4 Meg x 16 Mobile SDRAM
Operations
either the last of a burst of two or the last desired of a longer burst. Following the
PRECHARGE command, a subsequent command to the same bank cannot be issued
until tRP is met.
In the case of a fixed-length burst being executed to completion, a PRECHARGE
command issued at the optimum time (as described above) provides the same operation
that would result from the same fixed-length burst with auto precharge. The disadvantage of the PRECHARGE command is that it requires that the command and address
buses be available at the appropriate time to issue the command; the advantage of the
PRECHARGE command is that it can be used to truncate fixed-length bursts.
Fixed-length WRITE bursts can be truncated with the BURST TERMINATE command.
When truncating a WRITE burst, the input data applied coincident with the BURST
TERMINATE command will be ignored. The last data written (provided that DQM is
LOW at that time) will be the input data applied one clock previous to the BURST
TERMINATE command. This is shown in Figure 22 on page 27, where data n is the last
desired data element of a longer burst.
Figure 19:
Random WRITE Cycles
T0
T1
T2
T3
Command
WRITE
WRITE
WRITE
WRITE
Address
Bank,
Col n
Bank,
Col a
Bank,
Col x
Bank,
Col m
DIN
n
DIN
a
DIN
x
DIN
m
CLK
DQ
Don’t Care
Transitioning Data
Note:
Figure 20:
Each WRITE command may be issued to any bank. DQM is LOW.
WRITE-to-READ
T0
T1
T2
T3
T4
T5
Command
WRITE
NOP
READ
NOP
NOP
NOP
Address
Bank,
Col n
DOUT
b
DOUT
b+1
CLK
DQ
DIN
n
Bank,
Col b
DIN
n+1
Transitioning Data
Note:
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64mb_x16_Mobile SDRAM_Y24L_2.fm - Rev. C 10/07 EN
Don’t Care
The WRITE command may be issued to any bank, and the READ command may be issued
to any bank. DQM is LOW. CL = 2 for illustration.
26
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Operations
Figure 21:
WRITE-to-PRECHARGE
T0
T1
T2
T3
T4
T5
T6
NOP
ACTIVE
NOP
CLK
tWR @ tCLK ≥ 15ns
DQM
t RP
Command
Address
WRITE
NOP
NOP
PRECHARGE
Bank
(a or all)
Bank a,
Col n
Bank a,
Row
t WR
DQ
DIN
n+1
DIN
n
tWR = tCLK < 15ns
DQM
t RP
Command
Address
WRITE
NOP
NOP
PRECHARGE
NOP
Bank
(a or all)
Bank a,
Col n
NOP
ACTIVE
Bank a,
Row
t WR
DQ
DIN
n+1
DIN
n
Transitioning Data
Note:
Figure 22:
Don’t Care
DQM could remain LOW in this example if the WRITE burst is a fixed length of two.
Terminating a WRITE Burst
T0
T1
WRITE
BURST
TERMINATE
T2
CLK
Command
Address
DQ
Bank,
Col n
(Address)
DIN
n
(Data)
Transitioning Data
Note:
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NEXT
COMMAND
Don’t Care
DQM is LOW.
27
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Operations
PRECHARGE
The PRECHARGE command (see Figure 23 on page 28) is used to deactivate the open
row in a particular bank or the open row in all banks. The bank(s) will be available for a
subsequent row access some specified time (tRP) after the PRECHARGE command is
issued. Input A10 determines whether one or all banks are to be precharged, and in the
case where only one bank is to be precharged, inputs BA0, BA1 select the bank. When all
banks are to be precharged, inputs BA0, BA1 are treated as “Don’t Care.” After a bank has
been precharged, it is in the idle state and must be activated prior to any READ or WRITE
commands being issued to that bank.
Figure 23:
PRECHARGE Command
CLK
CKE
HIGH
CS#
RAS#
CAS#
WE#
Address
All Banks
A10
Bank Selected
BA0, BA1
BANK
ADDRESS
Valid Address
Don’t Care
Power-Down
Power-down occurs if CKE is registered LOW coincident with a NOP or COMMAND
INHIBIT when no accesses are in progress. If power-down occurs when all banks are
idle, this mode is referred to as precharge power-down; if power-down occurs when
there is a row active in any bank, this mode is referred to as active power-down. Entering
power-down deactivates the input and output buffers, excluding CKE, for maximum
power savings while in standby. The device must not remain in the power-down state
longer than the refresh period (64ms) since no refresh operations are performed in this
mode.
The power-down state is exited by registering an NOP or COMMAND INHIBIT and CKE
HIGH at the desired clock edge (meeting tCKS). See Figure 24 on page 29.
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Operations
Figure 24:
Power-Down
((
))
((
))
CLK
tCKS
CKE
> tCKS
((
))
Command
((
))
((
))
NOP
NOP
All banks idle
Input buffers gated off
Enter power-down mode
Exit power-down mode
ACTIVE
tRCD
tRAS
tRC
Deep Power-Down
Deep power-down mode is a maximum power savings feature achieved by shutting off
the power to the entire memory array of the device. Data on the memory array will not
be retained after deep power-down mode is executed. Deep power-down mode is
entered by having all banks idle then CS# and WE# held LOW with RAS# and CAS# HIGH
at the rising edge of the clock, while CKE is LOW. CKE must be held LOW during deep
power-down.
To exit deep power-down mode, CKE must be asserted HIGH. Upon exit of deep powerdown mode, a full Mobile SDRAM initialization sequence is required.
Clock Suspend
The clock suspend mode occurs when a column access/burst is in progress and CKE is
registered LOW. In the clock suspend mode, the internal clock is deactivated, “freezing”
the synchronous logic.
For each positive clock edge on which CKE is sampled LOW, the next internal positive
clock edge is suspended. Any command or data present on the input pins at the time of a
suspended internal clock edge is ignored; any data present on the DQ pins remains
driven; and burst counters are not incremented, as long as the clock is suspended. (See
examples in Figure 25 on page 30 and Figure 26 on page 30.)
Clock suspend mode is exited by registering CKE HIGH; the internal clock and related
operation will resume on the subsequent positive clock edge.
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Operations
Figure 25:
Clock Suspend During WRITE Burst
T0
T1
NOP
WRITE
T2
T3
T4
T5
CLK
CKE
Internal
Clock
Command
NOP
NOP
DIN
n+1
DIN
n+2
Bank,
Col n
Address
DIN
n
DIN
Transitioning Data
Note:
Figure 26:
Don’t Care
For this example, BL = 4 or greater, and DM is LOW.
Clock Suspend During READ Burst
T0
T1
T2
T3
T4
T5
T6
CLK
CKE
Internal
Clock
Command
READ
Address
Bank,
Col n
DQ
NOP
NOP
NOP
DOUT
n
DOUT
n+1
Transitioning Data
Note:
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NOP
DOUT
n+2
NOP
DOUT
n+3
Don’t Care
For this example, CL = 2, BL = 4 or greater, and DQM is LOW.
30
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Operations
Burst Read/Single Write
The burst read/single write mode is entered by programming the write burst mode bit
(M9) in the mode register to a logic 1. In this mode, all WRITE commands result in the
access of a single column location (burst of one), regardless of the programmed burst
length. READ commands access columns according to the programmed burst length
and sequence, just as in the normal mode of operation (M9 = 0).
Concurrent Auto Precharge
Micron SDRAM devices support concurrent auto precharge, which enables an access
command (READ or WRITE) to another bank while an access command with auto
precharge enabled is executing. Four cases where concurrent auto precharge occurs are
defined below.
READ with Auto Precharge
1. Interrupted by a READ (with or without auto precharge): A READ to bank m will interrupt a READ on bank n, two or three clocks later, depending on CL. The precharge to
bank n will begin when the READ to bank m is registered (see Figure 27).
2. Interrupted by a WRITE (with or without auto precharge): When a WRITE to bank m
registers, a READ on bank n will be interrupted. DQM should be used two clocks prior
to the WRITE command to prevent bus contention. The precharge to bank n will
begin when the WRITE to bank m is registered (see Figure 28 on page 32).
Figure 27:
READ with Auto Precharge Interrupted by a READ
T0
T1
T2
T3
T4
T5
T6
T7
CLK
Command
Bank n
Internal
States
NOP
Page active
READ - AP
Bank n
READ - AP
Bank m
NOP
READ with BL = 4
NOP
NOP
NOP
Idle
Interrupt burst, precharge
t RP - Bank n
Bank m
Page active
Address
Bank n,
Col a
NOP
tRP - Bank m
Precharge
READ with BL = 4
Bank m,
Col d
DOUT
a
DQ
DOUT
a+1
DOUT
d
DOUT
d+1
CL = 3 (Bank n)
CL = 3 (Bank m)
Transitioning Data
Note:
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Don’t Care
DQM is LOW.
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Operations
Figure 28:
READ with Auto Precharge Interrupted by a WRITE
T0
T1
T2
T3
T4
T5
T6
T7
CLK
Command
Bank n
READ - AP
Bank n
NOP
NOP
NOP
Page READ with BL = 4
Active
Internal
States
WRITE - AP
Bank m
NOP
NOP
Interrupt burst, precharge
Idle
tRP - Bank n
Page active
Bank m
Address
NOP
t WR - Bank m
Write-Bank
WRITE with BL = 4
Bank n,
Col a
Bank m,
Col d
DQM1
DOUT
a
DQ
CL = 3 (Bank n)
Note:
DIN
d
DIN
d+1
Transitioning Data
DIN
d+2
DIN
d+3
Don’t Care
DQM is HIGH at T2 to prevent DOUT a + 1 from contending with DIN d at T4.
WRITE with Auto Precharge
3. Interrupted by a READ (with or without auto precharge): When a READ to bank m registers, it will interrupt a WRITE on bank n, with the data-out appearing 2 or 3 clocks
later, depending on CL. The precharge to bank n will begin after tWR is met, where
t
WR begins when the READ to bank m is registered. The last valid WRITE to bank n
will be data-in registered one clock prior to the READ to bank m (see Figure 29 on
page 33).
4. Interrupted by a WRITE (with or without auto precharge): When a WRITE to bank m
registers, it will interrupt a WRITE on bank n. The precharge to bank n will begin after
t
WR is met, where tWR begins when the WRITE to bank m is registered. The last valid
data WRITE to bank n will be data registered one clock prior to a WRITE to bank m
(see Figure 30 on page 33).
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Operations
Figure 29:
WRITE with Auto Precharge Interrupted by a READ
T0
T1
T2
T3
T4
T5
T6
T7
CLK
Command
Bank n
Internal
States
NOP
Write - AP
Bank n
Page active
NOP
Read - AP
Bank m
WRITE with BL = 4
Bank m
Address
Bank n,
Col a
NOP
NOP
Precharge
tRP
- Bank n
- Bank n
tRP
- Bank m
READ with BL = 4
Bank m,
Col d
DOUT
d+ 1
DOUT
d
DIN
a+1
DIN
a
DQ
NOP
Interrupt burst, Write-back
tWR
Page active
NOP
CL = 3 (Bank m)
Transitioning Data
Note:
Figure 30:
Don’t Care
DQM is LOW.
WRITE with Auto Precharge Interrupted by a WRITE
T0
T1
T2
T3
T4
T5
T6
T7
CLK
Command
Bank n
Internal
States
NOP
WRITE - AP
Bank n
Page active
NOP
NOP
WRITE with BL = 4
WRITE - AP
Bank m
NOP
Interrupt Burst, write-back
tWR
Bank m
Page active
- Bank n
Address
Bank n,
Col a
DIN
a
- Bank m
Write-bank
WRITE with BL = 4
Bank m,
Col d
DIN
a+1
DIN
a+2
DIN
d
DIN
d+1
Transitioning Data
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Precharge
tRP
- Bank n
NOP
tWR
DQ
Note:
NOP
DIN
d+2
DIN
d+3
Don’t Care
DQM is LOW.
33
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Operations
Table 6:
Truth Table 2 – CKE
Notes: 1–4; notes appear below table
CKEn - 1
CKEn
Current State
Commandn
Actionn
L
L
Power-down
Self refresh
Clock suspend
Deep power-down
Power-down
Deep power-down
Self refresh
Clock suspend
All banks idle
All banks idle
All banks idle
Reading or writing
X
X
X
X
COMMAND INHIBIT or NOP
X
COMMAND INHIBIT or NOP
X
COMMAND INHIBIT or NOP
BURST TERMINATE
AUTO REFRESH
VALID
See Table 7 on page 35
Maintain power-down
Maintain self refresh
Maintain clock suspend
Maintain deep power-down
Exit power-down
Exit deep power-down
Exit self refresh
Exit clock suspend
Power-down entry
Deep power-down entry
Self refresh entry
Clock suspend entry
L
H
H
L
H
H
Notes:
Notes
8
5
8
6
7
8
1. CKEn is the logic state of CKE at clock edge n; CKEn - 1 was the state of CKE at the previous
clock edge.
2. Current state is the state of the SDRAM immediately prior to clock edge n.
3. COMMANDn is the command registered at clock edge n, and ACTIONn is a result of COMMANDn.
4. All states and sequences not shown are illegal or reserved.
5. Exiting power-down at clock edge n will put the device in the all banks idle state in time for
clock edge n + 1 (provided that tCKS is met).
6. Exiting self refresh at clock edge n will put the device in the all banks idle state when tXSR is
met. COMMAND INHIBIT or NOP commands should be issued on any clock edges occurring
during the tXSR period. A minimum of two NOP commands must be provided during tXSR
period.
7. After exiting clock suspend at clock edge n, the device will resume operation and recognize
the next command at clock edge n + 1.
8. Deep power-down is a power-saving feature of this Mobile SDRAM device. This command is
BURST TERMINATE when CKE is HIGH and deep power-down when CKE is LOW.
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Operations
Table 7:
Truth Table 3 – Current State Bank n, Command to Bank n
Notes: 1–5; notes appear below table and on next page
Current
State
Any
Idle
Row active
Read (auto
precharge
disabled)
Write (auto
precharge
disabled)
CS#
RAS# CAS#
H
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
Notes:
X
H
L
L
L
L
H
H
L
H
H
L
H
H
H
L
H
X
H
H
L
L
H
L
L
H
L
L
H
H
L
L
H
H
WE#
X
H
H
H
L
L
H
L
L
H
L
L
L
H
L
L
L
Command (Action)
Notes
COMMAND INHIBIT (NOP/Continue previous operation)
NO OPERATION (NOP/Continue previous operation)
ACTIVE (Select and activate row)
AUTO REFRESH
LOAD MODE REGISTER
PRECHARGE
READ (Select column and start READ burst)
WRITE (Select column and start WRITE burst)
PRECHARGE (Deactivate row in bank or banks)
READ (Select column and start new READ burst)
WRITE (Select column and start WRITE burst)
PRECHARGE (Truncate READ burst, start PRECHARGE)
BURST TERMINATE
READ (Select column and start READ burst)
WRITE (Select column and start new WRITE burst)
PRECHARGE (Truncate WRITE burst, start PRECHARGE)
BURST TERMINATE
6
6
10
9
9
7
9
9
7
8
9
9
7
8
1. This table applies when CKEn - 1 was HIGH and CKEn is HIGH (see Table 6 on page 34) and
after tXSR has been met (if the previous state was self refresh).
2. This table is bank-specific, except where noted; for example, the current state is for a specific bank and the commands shown are those allowed to be issued to that bank when in
that state. Exceptions are covered in the notes below.
3. Current state definitions:
Idle:
Row
active:
Read:
Write:
The bank has been precharged, and tRP has been met.
A row in the bank has been activated, and tRCD has been met. No data bursts/
accesses and no register accesses are in progress.
A READ burst has been initiated, with auto precharge disabled, and has not yet
terminated or been terminated.
A WRITE burst has been initiated, with auto precharge disabled, and has not yet
terminated or been terminated.
The following states must not be interrupted by a command issued to the same bank. COMMAND INHIBIT or NOP commands, or allowable commands to the other bank, should be
issued on any clock edge occurring during these states. Allowable commands to the other
bank are determined by its current state and Table 7, and according to Table 8.
Precharging:
Row activating:
Read with auto
precharge
enabled:
Write with auto
precharge
enabled:
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Starts with registration of a PRECHARGE command and ends when tRP is
met. After tRP is met, the bank will be in the idle state.
Starts with registration of an ACTIVE command and ends when tRCD is
met. After tRCD is met, the bank will be in the row active state.
Starts with registration of a READ command with auto precharge
enabled and ends when tRP has been met. After tRP is met, the bank will
be in the idle state.
Starts with registration of a WRITE command with auto precharge
enabled and ends when tRP has been met. After tRP is met, the bank will
be in the idle state.
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Operations
4. The following states must not be interrupted by any executable command; COMMAND
INHIBIT or NOP commands must be applied on each positive clock edge during these states.
Refreshing:
Accessing mode
register:
Precharging all:
Starts with registration of an AUTO REFRESH command and ends when
t
RFC is met. After tRFC is met, the SDRAM will be in the all banks idle
state.
Starts with registration of a LOAD MODE REGISTER command and ends
when tMRD has been met. After tMRD is met, the SDRAM will be in the
all banks idle state.
Starts with registration of a PRECHARGE ALL command and ends when
t
RP is met. After tRP is met, all banks will be in the idle state.
5. All states and sequences not shown are illegal or reserved.
6. Not bank specific; requires that all banks are idle.
7. May or may not be bank specific; if all banks are to be precharged, all must be in a valid
state for precharging.
8. Not bank specific; BURST TERMINATE affects the most recent WRITE or READ burst, regardless of bank.
9. READs or WRITEs listed in the Command (Action) column include READs or WRITEs with
auto precharge enabled and READs or WRITEs with auto precharge disabled.
10. Does not affect the state of the bank and acts as a NOP to that bank.
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64mb_x16_Mobile SDRAM_Y24L_2.fm - Rev. C 10/07 EN
36
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64Mb: 4 Meg x 16 Mobile SDRAM
Operations
Table 8:
Truth Table 4 – Current State Bank n, Command to Bank m
Notes: 1–6; notes appear below table and on next page
Current State
CS#
RAS#
CAS#
WE#
Any
H
L
X
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
X
H
X
L
H
H
L
L
H
H
L
L
H
H
L
L
H
H
L
L
H
H
L
X
H
X
H
L
L
H
H
L
L
H
H
L
L
H
H
L
L
H
H
L
L
H
X
H
X
H
H
L
L
H
H
L
L
H
H
L
L
H
H
L
L
H
H
L
L
Idle
Row
activating,
active, or
precharging
Read
(auto
precharge
disabled)
Write
(auto
precharge
disabled)
Read
(with auto
precharge)
Write
(with auto
precharge)
Notes:
Command (Action)
COMMAND INHIBIT (NOP/Continue previous operation)
NO OPERATION (NOP/Continue previous operation)
Any command otherwise allowed to bank m
ACTIVE (Select and activate row)
READ (Select column and start READ burst)
WRITE (Select column and start WRITE burst)
PRECHARGE
ACTIVE (Select and activate row)
READ (Select column and start new READ burst)
WRITE (Select column and start WRITE burst)
PRECHARGE
ACTIVE (Select and activate row)
READ (Select column and start READ burst)
WRITE (Select column and start new WRITE burst)
PRECHARGE
ACTIVE (Select and activate row)
READ (Select column and start new READ burst)
WRITE (Select column and start WRITE burst)
PRECHARGE
ACTIVE (Select and activate row)
READ (Select column and start READ burst)
WRITE (Select column and start new WRITE burst)
PRECHARGE
Notes
7
7
7, 10
7, 11
9
7, 12
7, 13
9
7, 8, 14
7, 8, 15
9
7, 8, 16
7, 8, 17
9
1. This table applies when CKEn-1 was HIGH and CKEn is HIGH (see Table 6 on page 34) and
after tXSR has been met (if the previous state was self refresh).
2. This table describes alternate bank operation, except where noted; i.e., the current state is
for bank n and the commands shown are those allowed to be issued to bank m (assuming
that bank m is in such a state that the given command is allowable). Exceptions are covered
in the notes below.
3. Current state definitions:
Idle:
Row active:
Read:
Write:
Read with auto
precharge
enabled:
Write with auto
precharge
enabled:
The bank has been precharged, and tRP has been met.
A row in the bank has been activated, and tRCD has been met. No data
bursts/accesses and no register accesses are in progress.
A READ burst has been initiated with auto precharge disabled and has
not yet terminated or been terminated.
A WRITE burst has been initiated with auto precharge disabled and has
not yet terminated or been terminated.
Starts with registration of a READ command with auto precharge
enabled and ends when tRP has been met. After tRP is met, the bank will
be in the idle state.
Starts with registration of a WRITE command with auto precharge
enabled and ends when tRP has been met. After tRP is met, the bank will
be in the idle state.
4. AUTO REFRESH, SELF REFRESH, and LOAD MODE REGISTER commands may only be issued
when all banks are idle.
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64Mb: 4 Meg x 16 Mobile SDRAM
Operations
5. A BURST TERMINATE command cannot be issued to another bank; it applies to the bank
represented by the current state only.
6. All states and sequences not shown are illegal or reserved.
7. READs or WRITEs to bank m listed in the Command (Action) column include READs or
WRITEs with auto precharge enabled and READs or WRITEs with auto precharge disabled.
8. Concurrent auto precharge: Bank n will initiate the auto precharge command when its
burst has been interrupted by bank m’s burst.
9. Burst in bank n continues as initiated.
10. For a READ without auto precharge interrupted by a READ (with or without auto precharge), the READ to bank m will interrupt the READ on bank n, CL later (see Figure 10 on
page 20).
11. For a READ without auto precharge interrupted by a WRITE (with or without auto precharge), the WRITE to bank m will interrupt the READ on bank n when registered (see
Figure 12 on page 22 and Figure 13 on page 22). DQM should be used one clock prior to the
WRITE command to prevent bus contention.
12. For a WRITE without auto precharge interrupted by a READ (with or without auto precharge), the READ to bank m will interrupt the WRITE on bank n when registered (see
Figure 20 on page 26), with the data-out appearing CL later. The last valid WRITE to bank n
will be data-in registered one clock prior to the READ to bank m.
13. For a WRITE without auto precharge interrupted by a WRITE (with or without auto precharge), the WRITE to bank m will interrupt the WRITE on bank n when registered (see
Figure 18 on page 25). The last valid WRITE to bank n will be data-in registered one clock
prior to the READ to bank m.
14. For a READ with auto precharge interrupted by a READ (with or without auto precharge),
the READ to bank m will interrupt the READ on bank n, CL later (see Figure 27 on page 31).
The PRECHARGE to bank n will begin when the READ to bank m is registered.
15. For a READ with auto precharge interrupted by a WRITE (with or without auto precharge),
the WRITE to bank m will interrupt the READ on bank n when registered (see Figure 28 on
page 32). DQM should be used two clocks prior to the WRITE command to prevent bus contention. The PRECHARGE to bank n will begin when the WRITE to bank m is registered.
16. For a WRITE with auto precharge interrupted by a READ (with or without auto precharge),
the READ to bank m will interrupt the WRITE on bank n when registered, with the data-out
appearing CL later (see Figure 29 on page 33). The PRECHARGE to bank n will begin after
tWR is met, where tWR begins when the READ to bank m is registered. The last valid WRITE
bank n will be data-in registered one clock prior to the READ to bank m.
17. For a WRITE with auto precharge interrupted by a WRITE (with or without auto precharge),
the WRITE to bank m will interrupt the WRITE on bank n when registered. The PRECHARGE
to bank n will begin after tWR is met, where tWR begins when the WRITE to bank m is registered (see Figure 30 on page 33). The last valid WRITE to bank n will be data registered
one clock to the WRITE to bank m.
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64Mb: 4 Meg x 16 Mobile SDRAM
Electrical Specifications
Electrical Specifications
Stresses greater than those listed may cause permanent damage to the device. This is a
stress rating only, and functional operation of the device at these or any other conditions
above those indicated in the operational sections of this specification is not implied.
Exposure to absolute maximum rating conditions for extended periods may affect reliability.
Table 9:
Absolute Maximum Ratings
Parameter
Voltage on VDD/VDDQ supply relative to VSS/VSSQ
Voltage on any ball relative to VSS
Storage temperature (plastic)
Table 10:
Symbol
Min
Max
Units
VDD/VDDQ
VIN
TSTG
–0.35
–0.35
–55
+2.8
+2.8
+150
V
V
°C
DC Electrical Characteristics and Operating Conditions
Notes: 1, 5, 6; notes appear on page 43 and 44; VDD/VDDQ = 1.7–1.95V
Parameter/Condition
Symbol
Supply voltage
I/O supply voltage
Input high voltage: Logic 1; All inputs
Input low voltage: Logic 0; All inputs
Output high voltage: all inputs: IOUT = -100µA
Input low voltage: all inputs: IOUT = 100µA
Input leakage current:
Any input 0V ≤ VIN ≤ VDD (All other pins not under test = 0V)
Output leakage current: DQ disabled; 0V ≤ VOUT ≤ VDDQ
Operating temperature
Commercial
Industrial
Table 11:
VDD
VDDQ
VIH
VIL
VOH
VOL
II
IOZ
TA
Min
Max
Units
1.7
1.95
1.7
1.95
0.8 × VDDQ VDDQ + 0.3
–0.3
+0.3
0.9 × VDDQ
–
–
0.2
–1.0
+1.0
–1.5
+1.5
0
–40
+70
+85
V
V
V
V
V
V
µA
Notes
22
22
µA
°C
AC Electrical Characteristics and Operating Conditions
VDD/VDDQ = 1.7–1.95V
Parameter/Condition
Input high voltage: Logic 1; All inputs
Input low voltage: Logic 0; All inputs
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64mb_x16_Mobile SDRAM_Y24L_2.fm - Rev. C 10/07 EN
39
Symbol
Min
Max
Units
VIH
VIL
1.4
–
–
0.4
V
V
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64Mb: 4 Meg x 16 Mobile SDRAM
Electrical Specifications
Table 12:
Electrical Characteristics and Recommended AC Operating Conditions
Notes: 5, 6, 8, 9, and 11; notes appear on page 43 and 44
AC Characteristics
-75
Parameter
Access time from CLK (positive edge)
Address hold time
Address setup time
CLK high-level width
CLK low-level width
Clock cycle time
CKE hold time
CKE setup time
CS#, RAS#, CAS#, WE#, DQM hold time
CS#, RAS#, CAS#, WE#, DQM setup time
Data-in hold time
Data-in setup time
Data-out High-Z time
Data-out Low-Z time
Data-out hold time (load)
Data-out hold time (no load)
ACTIVE-to-PRECHARGE command
ACTIVE-to-ACTIVE command period
ACTIVE-to-READ or WRITE delay
Refresh period (4,096 rows)
AUTO REFRESH period
PRECHARGE command period
ACTIVE bank a to ACTIVE bank b command
Transition time
WRITE recovery time
Exit SELF REFRESH-to-ACTIVE command
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64mb_x16_Mobile SDRAM_Y24L_2.fm - Rev. C 10/07 EN
Symbol
CL = 3
CL = 2
CL = 3
CL = 2
CL = 3
CL = 2
t
AC (3)
AC (2)
t
AH
tAS
t
CH
t
CL
tCK (3)
tCK (2)
t
CKH
tCKS
tCMH
tCMS
tDH
tDS
tHZ (3)
tHZ (2)
tLZ
tOH
t
OHN
tRAS
tRC
tRCD
tREF
tRFC
tRP
tRRD
tT
tWR
t
XSR
t
40
-8
Min
Max
Min
Max
Units
–
–
1
2.5
3
3
7.5
9.6
1
2.5
1
2.5
1
2.5
–
–
1
2.5
1.8
45
67.5
19.2
–
75
19.2
15
0.5
15
75
6
8
–
–
–
–
100
100
–
–
–
–
–
–
6
8
–
–
–
120,000
–
–
64
–
–
–
1.2
–
–
–
–
1
2.5
3
3
8
12
1
2.5
1
2.5
1
2.5
–
–
1
2.5
1.8
48
72
24
–
80
24
16
0.5
15
80
6
8
–
–
–
–
100
100
–
–
–
–
–
–
6
8
–
–
–
120,000
–
–
64
–
–
–
1.2
–
–
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ms
ns
ns
ns
ns
ns
ns
Notes
23
23
10
10
26
7
24
20
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64Mb: 4 Meg x 16 Mobile SDRAM
Electrical Specifications
Table 13:
AC Functional Characteristics
Notes: 5, 6, 8, 9, and 11; notes appear on page 43 and 44
Parameter
Symbol
READ/WRITE command to READ/WRITE command
CKE to clock disable or power-down entry mode
CKE to clock enable or power-down exit setup mode
DQM to input data delay
DQM to data mask during WRITEs
DQM to data High-Z during READs
WRITE command to input data delay
Data-in to ACTIVE command
Data-in to PRECHARGE command
Last data-in to burst STOP command
Last data-in to new READ/WRITE command
Last data-in to PRECHARGE command
LOAD MODE REGISTER command to ACTIVE or REFRESH
command
Data-out to High-Z from PRECHARGE command
Table 14:
-75
t
Units
Notes
CCD
CKED
t
PED
t
DQD
tDQM
t
DQZ
t
DWD
t
DAL
t
DPL
t
BDL
t
CDL
tRDL
tMRD
1
1
1
0
0
2
0
5
2
1
1
2
2
1
1
1
0
0
2
0
5
2
1
1
2
2
t
CK
CK
t
CK
t
CK
tCK
t
CK
t
CK
t
CK
t
CK
t
CK
t
CK
tCK
tCK
17
14
14
17
17
17
17
15, 21
16, 21
17
17
16, 21
24
tROH(3)
3
2
3
2
tCK
17
17
t
CL = 3
CL = 2
-8
tROH(2)
t
tCK
IDD Specifications and Conditions (x16)
Notes: 1, 5, 6, 11, and 13; notes appear on page 43 and 44; VDD = 1.7V–1.95V, VDDQ = 1.7V–1.95V
Max
Parameter/Condition
Operating current:
Active mode; Burst = 1; READ or WRITE; tRC = tRC (MIN)
Standby current:
Power-down mode; All banks idle; CKE = LOW
Standby current:
Nonpower-down mode; All banks idle; CKE = HIGH
Standby current:
Active mode; CKE = LOW; CS# = HIGH; All banks active; No
accesses in progress
Standby current:
Active mode; CKE = HIGH; CS# = HIGH; All banks active after
tRCD met; No accesses in progress
Operating current:
Burst mode; Continuous burst; READ or WRITE; All banks active,
half DQ toggling every cycle
tRFC = tRFC (MIN)
Auto refresh current:
CKE = HIGH; CS# = HIGH
tRFC = 15.625µs
Deep power-down
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64mb_x16_Mobile SDRAM_Y24L_2.fm - Rev. C 10/07 EN
41
Symbol
-75
-8
Units
Notes
IDD1
60
55
mA
IDD2P
150
150
µA
3, 18,
19
25
IDD2N
10
10
mA
IDD3P
5
5
mA
IDD3N
15
15
mA
3, 18,
19
IDD4
50
50
mA
3, 18,
19
IDD5
75
60
mA
IDD6
2
2
mA
IZZ
10
10
µA
3, 12,
18, 19
3, 12,
18, 19, 26
25, 27
3, 12,
19, 25
3, 18,
19
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64Mb: 4 Meg x 16 Mobile SDRAM
Electrical Specifications
Table 15:
IDD7 - Self Refresh Current Options
Notes: 4, 13, 25, and 28; notes appear on page 43 and 44; VDD/VDDQ = 1.7–1.95V
Temperature-Compensated Self Refresh
Parameter/Condition
Max Temperature
-75/-8
Units
85ºC
45ºC
85ºC
45ºC
85ºC
45ºC
85ºC
45ºC
85ºC
45ºC
180
120
130
80
100
80
100
80
100
80
µA
µA
µA
µA
µA
µA
µA
µA
µA
µA
Self refresh current:
CKE < 0.2V – 4 banks open
Self refresh current:
CKE < 0.2V – 2 banks open
Self refresh current:
CKE < 0.2V – 1 bank open
Self refresh current:
CKE < 0.2V – 1/2 bank open
Self refresh current:
CKE < 0.2V – 1/4 bank open
Figure 31:
Typical Self Refresh Current vs. Temperature
100
4-Banks
90
2-Banks
1-Bank, 1/2 Bank,
1/4 Bank
80
Current (µA)
70
60
50
40
30
20
10
0
-50
-40
-30
-20
-10
0
10
20
30
40
50
60
70
80
90
100
Temperature (C)
Table 16:
Capacitance
Note: 2; notes appear on page 43
Parameter
Input capacitance: CLK
Input capacitance: All other input-only pins
Input/output capacitance: DQ
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64mb_x16_Mobile SDRAM_Y24L_2.fm - Rev. C 10/07 EN
42
Symbol
Min
Max
Units
CI1
CI2
CIO
1.5
1.5
3.0
4.0
4.0
6.0
pF
pF
pF
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64Mb: 4 Meg x 16 Mobile SDRAM
Notes
Notes
1. All voltages referenced to VSS.
2. This parameter is sampled. VDD/VDDQ = 1.7–1.95V; TA = 25°C; pin under test biased at
1.4V. f = 1 MHz.
3. IDD is dependent on output loading and cycle rates. Specified values are obtained
with minimum cycle time and the outputs open.
4. Enables on-chip refresh and address counters.
5. The minimum specifications are used only to indicate cycle time at which proper
operation over the full temperature range (0°C ≤ TA ≤ +70°C for commercial parts;
–40°C ≤ TA ≤ +85°C for industrial parts) is ensured.
6. An initial pause of 100µs is required after power-up, followed by two AUTO REFRESH
commands, before proper device operation is ensured. (VDD and VDDQ must be powered up simultaneously. VSS and VSSQ must be at same potential.) The two AUTO
REFRESH command wake-ups should be repeated any time the tREF refresh requirement is exceeded.
7. AC characteristics assume tT = 1ns.
8. In addition to meeting the transition rate specification, the clock and CKE must transition between VIH and VIL (or between VIL and VIH) in a monotonic manner.
9. Outputs measured for 1.8V at 0.9V with equivalent load:
Q
20pF
10. tHZ defines the time at which the output achieves the open circuit condition; it is not
a reference to VOH or VOL. The last valid data element will meet tOH before going
High-Z.
11. AC timing and IDD tests have VIL and VIH, with timing referenced to VIH/2 = crossover
point. If the input transition time is longer than tT (MAX), then the timing is referenced at VIL (MAX) and VIH (MIN) and no longer at the VIH/2 crossover point.
12. Other input signals are allowed to transition no more than once every two clocks and
are otherwise at valid VIH or VIL levels.
13. IDD specifications are tested after the device is properly initialized.
14. Timing actually specified by tCKS; clock(s) specified as a reference only at minimum
cycle rate.
15. Timing actually specified by tWR plus tRP; clock(s) specified as a reference only at
minimum cycle rate.
16. Timing actually specified by tWR.
17. Required clocks are specified by JEDEC functionality and are not dependent on any
timing parameter.
18. The IDD current will increase or decrease proportionally according to the amount of
frequency alteration for the test condition.
19. Address transitions average one transition every two clocks.
20. CLK must be toggled a minimum of two times during this period.
21. Based on tCK = 7.5ns for -75 and tCK = 8.0ns for -8.
22. VIH overshoot: VIH (MAX) = VDDQ + 2V for a pulse width ≤3ns, and the pulse width
cannot be greater than one-third of the cycle rate. VIL undershoot: VIL (MIN) = -2V for
a pulse width ≤3ns.
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64Mb: 4 Meg x 16 Mobile SDRAM
Notes
23. The clock frequency must remain constant (stable clock is defined as a signal cycling
within timing constraints specified for the clock pin) during access or precharge
states (READ, WRITE, including tWR, and PRECHARGE commands). CKE may be
used to reduce the data rate.
24. For auto precharge mode, at least one clock cycle is required during tWR. During auto
precharge mode, the precharge timing budget (tRP) begins at 7.5ns for -75, and 7ns
for -8, after the first clock delay after the last WRITE is executed.
25. Measurement is taken 500ms after entering this operating mode to allow for tester
measurement settling time.
26. CKE is HIGH during REFRESH command period tRFC (MIN) else CKE is LOW. The
IDD6 limit is actually a nominal value and does not result in a fail value.
27. Deep power-down current is a nominal value at 25°C. The parameter is not tested.
28. Values for IDD7 85°C are guaranteed for the entire temperature range. All other IDD7
values are estimated.
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Timing Diagrams
Timing Diagrams
Figure 32:
Initialize and Load Mode Register
T0
CLK
((
))
((
))
Tn + 1
T1
tCK
To + 1
Tp + 1
Tq + 1
Tr + 1
((
))
((
))
((
))
((
))
((
))
((
))
((
))
((
))
((
))
((
))
((
))
((
))
((
))
((
))
((
))
((
))
((
))
((
))
((
))
((
))
((
))
((
))
((
))
((
))
tCKS tCKH
CKE
((
))
((
))
Command1
((
))
((
))
DQM
((
))
((
))
((
))
((
))
((
))
((
))
((
))
((
))
A0–A9, A11
((
))
((
))
((
))
((
))
((
))
((
))
((
))
((
))
Code
((
))
((
))
Code
((
))
((
))
Valid
((
))
((
))
A10
((
))
((
))
((
))
((
))
((
))
((
))
((
))
((
))
Code
((
))
((
))
Code
((
))
((
))
Valid
((
))
((
))
BA0, BA1
((
))
((
))
((
))
((
))
((
))
((
))
((
))
((
))
((
))
((
))
BA0
BA0 == L,
L,
BA1
BA1==HL
((
))
((
))
Valid
((
))
((
))
DQ
((
))
((
))
((
))
((
))
tRP
tRFC2
tCMS tCMH
NOP
((
))
((
))
PRE
AR
((
))
((
))
AR
((
))
((
))
LMR
((
))
((
))
LMR
((
))
((
))
((
))
((
))
VALID
((
))
((
))
((
))
((
))
((
))
((
))
tAS tAH
All Banks
t AS tAH
tAS tAH
High-Z
BA0 = L,
BA1 = L
((
))
((
))
((
))
T = 100µs
Power-up:
VDD and
CLK stable
Notes:
tRFC2
tMRD3
Load mode
register
Precharge
all banks
tMRD3
Load extended
mode register
1. PRE = PRECHARGE command, AR = AUTO REFRESH command, and LMR = LOAD MODE REGISTER command.
2. Only NOPs or COMMAND INHIBITs may be issued during tRFC time.
3. At least one NOP or COMMAND INHIBIT is required during tMRD time.
PDF: 09005aef8237ed98/Source: 09005aef8237ed68
64mb_x16_Mobile SDRAM_Y24L_2.fm - Rev. C 10/07 EN
45
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2006 Micron Technology, Inc. All rights reserved.
64Mb: 4 Meg x 16 Mobile SDRAM
Timing Diagrams
Figure 33:
Power-Down Mode
T0
T1
tCK
CLK
T2
((
))
((
))
tCL
tCKS
tCH
CKE
tCKS
Tn + 2
tCKS
((
))
tCKH
tCMS tCMH
Command
Tn + 1
PRECHARGE
NOP
((
))
((
))
NOP
NOP
ACTIVE
DQM
((
))
((
))
A0–A9, A11
((
))
((
))
Row
((
))
((
))
Row
((
))
((
))
Bank
All banks
A10
Single bank
tAS
BA0, BA1
tAH
Banks\S)
High-Z
((
))
DQ
Two clock cycles
Input buffers gated off while in
power-down mode
Precharge all
active banks
All banks idle
All banks idle, enter
power-down mode
Exit power-down mode
Don’t Care
Notes:
1. Violating refresh requirements during power-down may result in a loss of data.
PDF: 09005aef8237ed98/Source: 09005aef8237ed68
64mb_x16_Mobile SDRAM_Y24L_2.fm - Rev. C 10/07 EN
46
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2006 Micron Technology, Inc. All rights reserved.
64Mb: 4 Meg x 16 Mobile SDRAM
Timing Diagrams
Figure 34:
Clock Suspend Mode
T0
T1
T2
tCK
CLK
T3
T4
T5
T6
T7
T8
T9
tCL
tCH
tCKS tCKH
CKE
tCKS
tCKH
tCMS tCMH
Command
READ
NOP
NOP
NOP
NOP
NOP
WRITE
NOP
tCMS tCMH
DQM
tAS
A0–A9, A11
tAH
Column m 2
tAS
tAH
tAS
tAH
Column e 2
A10
BA0, BA1
Bank
Bank
tAC
tOH
tAC
DQ
tLZ
tHZ
DOUT m
DOUT m + 1
tDS
tDH
DOUT e
DOUT e + 1
Don’t Care
Undefined
Notes:
1. For this example, the BL = 2, the CL = 3, and auto precharge is disabled.
2. A8, A9, and A11 = “Don’t Care.”
PDF: 09005aef8237ed98/Source: 09005aef8237ed68
64mb_x16_Mobile SDRAM_Y24L_2.fm - Rev. C 10/07 EN
47
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2006 Micron Technology, Inc. All rights reserved.
64Mb: 4 Meg x 16 Mobile SDRAM
Timing Diagrams
Figure 35:
Auto Refresh Mode
T0
T1
CLK
tCK
T2
((
))
((
))
tCH
tCKS
tCKH
tCMS
tCMH
PRECHARGE
NOP
AUTO
REFRESH
NOP
A0–A9, A11
All banks
A10
Single bank
tAS
DQ
((
))
( ( NOP
))
To + 1
((
))
AUTO
REFRESH
NOP
((
))
((
))
DQM
BA0, BA1
((
))
((
))
((
))
CKE
Command
Tn + 1
tCL
((
))
( ( NOP
))
ACTIVE
((
))
((
))
((
))
((
))
((
))
((
))
Row
((
))
((
))
((
))
((
))
Row
tAH
Bank(S)
High-Z
tRP
tRFC1
((
))
((
))
((
))
((
))
((
))
((
))
Bank
tRFC1
Precharge all
active banks
Don’t Care
Note:
PDF: 09005aef8237ed98/Source: 09005aef8237ed68
64mb_x16_Mobile SDRAM_Y24L_2.fm - Rev. C 10/07 EN
tRFC must not be interrupted by any executable command; Command INHIBIT or NOP commands must be applied on any positive edge during tRFC.
48
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2006 Micron Technology, Inc. All rights reserved.
64Mb: 4 Meg x 16 Mobile SDRAM
Timing Diagrams
Figure 36:
Self Refresh Mode
T0
CLK
T1
tCK
tCL
tCH
T2
tCKS
CKE
Command
tCKS
tCKH
tCMS
tCMH
AUTO1
REFRESH
NOP
DQM
A0–A9, A11
All Banks
A10
Single Bank
BA0, BA1
DQ
> tRAS
((
))
((
))
To + 1
To + 2
((
))
((
))
((
))
PRECHARGE
tAS
Tn + 1
((
))
((
))
((
))
((
))
((
))
AUTO1
REFRESH
NOP ( (
))
((
))
((
))
((
))
((
))
((
))
((
))
((
))
((
))
((
))
((
))
((
))
((
))
((
))
((
))
((
))
((
))
tAH
Bank(s)
High-Z
((
))
((
))
tRP
Precharge all
active banks
tXSR
Enter self refresh mode
Exit self refresh mode
(Restart refresh time base)
CLK stable prior to exiting
self refresh mode
Note:
PDF: 09005aef8237ed98/Source: 09005aef8237ed68
64mb_x16_Mobile SDRAM_Y24L_2.fm - Rev. C 10/07 EN
tXSR
Don’t Care
requires a minimum of two clocks regardless of frequency or timing.
49
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2006 Micron Technology, Inc. All rights reserved.
64Mb: 4 Meg x 16 Mobile SDRAM
Timing Diagrams
Figure 37:
READ – Without Auto Precharge
T0
T1
T2
tCK
CLK
T3
T4
T5
NOP
NOP
T6
T7
T8
NOP
ACTIVE
tCL
tCH
tCKS
tCKH
CKE
tCMS tCMH
Command
ACTIVE
NOP
READ
NOP
PRECHARGE
tCMS tCMH
DQM
tAS
A0–A9, A11
tAS
Column m 2
Row
tAH
All banks
Row
A10
tAS
BA0, BA1
tAH
Row
Row
Single banks
Disable auto precharge
tAH
Bank
Bank
Bank(s)
tAC
DQ
tLZ
tRCD
tAC
tOH
DOUT m
tAC
tOH
DOUT m+1
Bank
tAC
tOH
tOH
DOUT m+2
DOUT m+3
tHZ
tRP
CAS latency
tRAS
tRC
Don’t Care
Undefined
Notes:
1. For this example, the BL = 4, the CL = 2, and the READ burst is followed by a “manual” PRECHARGE.
2. A8, A9, and A11 = “Don’t Care.”
PDF: 09005aef8237ed98/Source: 09005aef8237ed68
64mb_x16_Mobile SDRAM_Y24L_2.fm - Rev. C 10/07 EN
50
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2006 Micron Technology, Inc. All rights reserved.
64Mb: 4 Meg x 16 Mobile SDRAM
Timing Diagrams
Figure 38:
READ – with Auto Precharge
T0
T1
tCK
CLK
tCKS
T2
T3
T4
T5
NOP
NOP
T6
T7
T8
NOP
ACTIVE
tCL
tCH
tCKH
CKE
tCMS tCMH
Command
ACTIVE
NOP
READ
tCMS
NOP
NOP
tCMH
DQM
tAS
A0–A9, A11
tAH
tAS
A10
tAH
Row
Enable auto precharge
Row
tAS
BA0, BA1
Column m 2
Row
Row
tAH
Bank
Bank
Bank
tAC
tOH
tAC
DQ
tLZ
tRCD
DOUT m
tAC
tOH
DOUT m + 1
tAC
tOH
DOUT m + 2
tOH
DOUT m + 3
tHZ
tRP
CAS latency
tRAS
tRC
Don’t Care
Undefined
Notes:
1. For this example, the BL = 4, and the CL = 2.
2. A8, A9, and A11 = “Don’t Care.”
PDF: 09005aef8237ed98/Source: 09005aef8237ed68
64mb_x16_Mobile SDRAM_Y24L_2.fm - Rev. C 10/07 EN
51
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2006 Micron Technology, Inc. All rights reserved.
64Mb: 4 Meg x 16 Mobile SDRAM
Timing Diagrams
Figure 39:
Single READ – Without Auto Precharge
T0
T1
T2
tCK
CLK
T3
T4
T5
NOP 3
NOP 3
T6
T7
T8
tCL
tCH
tCKS
tCKH
CKE
tCMS tCMH
Command
ACTIVE
NOP
READ
PRECHARGE
NOP
ACTIVE
NOP
tCMS tCMH
DQM
tAS
A0–A9, A11
Column m2
Row
tAS
Row
tAH
All banks
Row
A10
tAS
BA0, BA1
tAH
Row
Disable auto precharge
tAH
Bank
Single banks
Bank
Bank(S)
tAC
DQ
t
LZ
tRCD
Bank
tOH
DOUT m
tHZ
tRP
CAS latency
tRAS
tRC
Don’t Care
Undefined
Notes:
1. For this example, the BL = 4, the CL = 2, and the READ burst is followed by a “manual” PRECHARGE.
2. A8, A9, and A11 = “Don’t Care.”
3. PRECHARGE command not allowed, or tRAS would be violated.
PDF: 09005aef8237ed98/Source: 09005aef8237ed68
64mb_x16_Mobile SDRAM_Y24L_2.fm - Rev. C 10/07 EN
52
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2006 Micron Technology, Inc. All rights reserved.
64Mb: 4 Meg x 16 Mobile SDRAM
Timing Diagrams
Figure 40:
Single READ – with Auto Precharge
T0
T1
tCK
CLK
tCKS
T2
T3
T4
T5
T6
T7
T8
tCL
tCH
tCKH
CKE
tCMS tCMH
Command
ACTIVE
NOP
NOP3
NOP3
READ
tCMS
NOP
NOP
ACTIVE
NOP
tCMH
DQM
tAS
A0–A9, A11
tAS
A10
Column m 2
tAH
Row
Enable auto precharge
Row
tAS
BA0, BA1
tAH
Row
Row
tAH
Bank
Bank
Bank
tAC
t OH
DOUT m
DQ
tRCD
CAS latency
tHZ
tRP
tRAS
tRC
Don’t Care
Undefined
Notes:
1. For this example, the BL = 4 and the CL = 2.
2. A8, A9, and A11 = “Don’t Care.”
3. PRECHARGE command not allowed, or tRAS would be violated.
PDF: 09005aef8237ed98/Source: 09005aef8237ed68
64mb_x16_Mobile SDRAM_Y24L_2.fm - Rev. C 10/07 EN
53
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2006 Micron Technology, Inc. All rights reserved.
64Mb: 4 Meg x 16 Mobile SDRAM
Timing Diagrams
Figure 41:
Alternating Bank Read Accesses
T0
T1
tCK
CLK
T2
T3
T4
T5
NOP
ACTIVE
T6
T7
T8
READ
NOP
ACTIVE
tCL
tCH
tCKS
tCKH
tCMS
tCMH
CKE
Command
ACTIVE
NOP
READ
tCMS
NOP
tCMH
DQM
tAS
A0–A9, A11
tAS
A10
2
Column m
tAH
Column b2
Row
Enable auto precharge
Row
Enable auto precharge
Row
tAS
BA0, BA1
tAH
Row
Row
Row
tAH
Bank 0
Bank 0
Bank 3
tAC
DQ
tLZ
tRCD - Bank 0
Bank 3
tAC
tOH
DOUT m
tAC
tOH
DOUT m + 1
Bank 0
tAC
tOH
DOUT m + 2
tAC
tOH
DOUT m + 3
tRP - Bank 0
CAS latency - Bank 0
tAC
tOH
DOUT b
tRCD - Bank 0
tRAS - Bank 0
tRC - Bank 0
tRCD - Bank 3
tRRD
CAS latency - Bank 3
Don’t Care
Undefined
Notes:
1. For this example, the BL = 4, and the CL = 2.
2. A8, A9, and A11 = “Don’t Care.”
PDF: 09005aef8237ed98/Source: 09005aef8237ed68
64mb_x16_Mobile SDRAM_Y24L_2.fm - Rev. C 10/07 EN
54
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2006 Micron Technology, Inc. All rights reserved.
64Mb: 4 Meg x 16 Mobile SDRAM
Timing Diagrams
Figure 42:
READ – DQM Operation
T0
T1
tCK
CLK
tCKS
tCKH
tCMS
tCMH
T2
T3
T4
T5
NOP
NOP
T6
T7
T8
NOP
NOP
NOP
tCL
tCH
CKE
Command
ACTIVE
NOP
READ
tCMS
NOP
tCMH
DQM
tAS
A0–A9, A11
tAH
Enable auto precharge
Row
tAS
BA0, BA1
Column m 2
Row
tAS
A10
tAH
Disable auto precharge
tAH
Bank
Bank
tAC
tOH
DQ
tAC
DOUT m
tLZ
tRCD
tHZ
tAC
tOH
DOUT m + 2
tLZ
tOH
DOUT m + 3
tHZ
CAS latency
Don’t Care
Undefined
Notes:
1. For this example, the CL = 2.
2. A8, A9, and A11 = “Don’t Care.”
PDF: 09005aef8237ed98/Source: 09005aef8237ed68
64mb_x16_Mobile SDRAM_Y24L_2.fm - Rev. C 10/07 EN
55
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2006 Micron Technology, Inc. All rights reserved.
64Mb: 4 Meg x 16 Mobile SDRAM
Timing Diagrams
Figure 43:
WRITE – Without Auto Precharge
T0
tCK
CLK
T1
T2
tCL
T3
T4
T5
T6
T7
T8
T9
NOP
NOP
NOP
NOP
PRECHARGE
NOP
ACTIVE
tCH
tCKS
tCKH
tCMS
tCMH
CKE
Command
ACTIVE
NOP
WRITE
tCMS tCMH
DQM
tAS
A0–A9, A11
tAS
A10
Column m 3
Row
tAH
All banks
Row
tAS
BA0, BA1
tAH
Row
Row
tAH
Disable auto precharge
Single bank
Bank
Bank
Bank
tDS
tDH
DIN m
DQ
tDS
tDH
DIN m + 1
tDS
tDH
tDS
DIN m + 2
Bank
tDH
DIN m + 3
t WR 2
tRCD
tRAS
tRP
tRC
Don’t Care
Notes:
1. For this example, the BL = 4, and the WRITE burst is followed by a “manual” PRECHARGE.
2. 15ns is required between <DIN m + 3> and the PRECHARGE command, regardless of frequency.
3. A8, A9, and A11 = “Don’t Care.”
PDF: 09005aef8237ed98/Source: 09005aef8237ed68
64mb_x16_Mobile SDRAM_Y24L_2.fm - Rev. C 10/07 EN
56
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2006 Micron Technology, Inc. All rights reserved.
64Mb: 4 Meg x 16 Mobile SDRAM
Timing Diagrams
Figure 44:
WRITE – with Auto Precharge
T0
tCK
CLK
tCKS
tCKH
tCMS
tCMH
T1
T2
tCL
T3
T4
T5
T6
T7
T8
T9
NOP
NOP
NOP
NOP
NOP
NOP
ACTIVE
tCH
CKE
Command
ACTIVE
NOP
WRITE
tCMS tCMH
DQM
tAS
A0–A9, A11
tAH
Row
Enable auto precharge
Row
tAS
BA0, BA1
Column m 2
Row
tAS
A10
tAH
Row
tAH
Bank
Bank
Bank
tDS
tDH
DIN m
DQ
tDS
tDH
DIN m + 1
tDS
tDH
DIN m + 2
tRCD
tRAS
tDS
tDH
DIN m + 3
tWR
tRP
tRC
Don’t Care
Notes:
1. For this example, the BL = 4.
2. A8, A9, and A11 = “Don’t Care.”
PDF: 09005aef8237ed98/Source: 09005aef8237ed68
64mb_x16_Mobile SDRAM_Y24L_2.fm - Rev. C 10/07 EN
57
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2006 Micron Technology, Inc. All rights reserved.
64Mb: 4 Meg x 16 Mobile SDRAM
Timing Diagrams
Figure 45:
Single WRITE – Without Auto Precharge
T0
tCK
CLK
T1
T2
tCL
T3
T4
NOP 4
NOP 4
T5
T6
T7
T8
ACTIVE
NOP
tCH
tCKS
tCKH
tCMS
tCMH
CKE
Command
ACTIVE
NOP
WRITE
PRECHARGE
NOP
tCMS tCMH
DQM
tAS
A0–A9, A11
tAH
All banks
Row
Row
tAS
BA0, BA1
Column m3
Row
tAS
A10
tAH
Disable auto precharge
tAH
Bank
Single bank
Bank
Bank
tDS
Bank
tDH
DIN m
DQ
tRCD
tRAS
tRP
t WR 2
tRC
Don’t Care
Notes:
1.
2.
3.
4.
PDF: 09005aef8237ed98/Source: 09005aef8237ed68
64mb_x16_Mobile SDRAM_Y24L_2.fm - Rev. C 10/07 EN
For this example, the BL = 1, and the WRITE burst is followed by a “manual” PRECHARGE.
15ns is required between <DIN m> and the PRECHARGE command, regardless of frequency.
A8, A9, and A11 = “Don’t Care.”
PRECHARGE command not allowed or tRAS would be violated.
58
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2006 Micron Technology, Inc. All rights reserved.
64Mb: 4 Meg x 16 Mobile SDRAM
Timing Diagrams
Figure 46:
Single WRITE – with Auto Precharge
T0
tCK
CLK
tCKS
tCKH
tCMS
tCMH
T1
tCL
T2
T3
T4
T5
T6
T7
NOP4
WRITE
NOP
NOP
NOP
T8
T9
tCH
CKE
Command
NOP4
ACTIVE
NOP4
tCMS
ACTIVE
NOP
tCMH
DQM
tAS
A0–A9, A11
tAS
Column m3
tAH
Row
Enable Auto Precharge
Row
A10
tAS
BA0, BA1
tAH
Row
Row
tAH
Bank
Bank
Bank
tDS
tDH
DIN m 2
DQ
tRCD
tRAS
tWR
tRP
tRC
Don’t Care
Notes:
1.
2.
3.
4.
PDF: 09005aef8237ed98/Source: 09005aef8237ed68
64mb_x16_Mobile SDRAM_Y24L_2.fm - Rev. C 10/07 EN
For this example, the BL = 1.
15ns is required between <DIN m> and the PRECHARGE command, regardless of frequency.
A8, A9, and A11 = “Don’t Care.”
WRITE command not allowed or tRAS would be violated.
59
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2006 Micron Technology, Inc. All rights reserved.
64Mb: 4 Meg x 16 Mobile SDRAM
Timing Diagrams
Figure 47:
Alternating Bank Write Accesses
T0
tCK
CLK
T1
T2
tCL
T3
T4
T5
T6
T7
T8
T9
NOP
NOP
ACTIVE
tCH
tCKS
tCKH
tCMS
tCMH
CKE
Command
ACTIVE
NOP
WRITE
tCMS
NOP
ACTIVE
NOP
WRITE
tCMH
DQM
tAS
A0–A9, A11
tAS
A10
Column m 2
tAH
Column b 2
Row
Enable auto precharge
Row
Enable auto precharge
Row
tAS
BA0, BA1
tAH
Row
Row
Row
tAH
Bank 0
Bank 0
tDS
tDH
DIN m
DQ
Bank 1
tDS
tDH
DIN m + 1
tDS
Bank 1
tDH
tDS
DIN m + 2
tDH
DIN m + 3
tDS
tDH
DIN b
tWR - Bank 0
tRCD - Bank 0
Bank 0
tDS
tDH
DIN b + 1
tRP - Bank 0
tDS
tDH
DIN b + 2
tDS
tDH
DIN b + 3
tRCD - Bank 0
tRAS - Bank 0
tRC - Bank 0
tRCD - Bank 1
tRRD
tWR - Bank 1
Don’t Care
Notes:
1. For this example, the BL = 4.
2. A8, A9, and A11 = “Don’t Care.”
PDF: 09005aef8237ed98/Source: 09005aef8237ed68
64mb_x16_Mobile SDRAM_Y24L_2.fm - Rev. C 10/07 EN
60
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2006 Micron Technology, Inc. All rights reserved.
64Mb: 4 Meg x 16 Mobile SDRAM
Timing Diagrams
Figure 48:
WRITE – DQM Operation
T0
T1
tCK
CLK
T2
T3
T4
T5
NOP
NOP
NOP
T6
T7
NOP
NOP
tCL
tCH
tCKS
tCKH
tCMS
tCMH
CKE
Command
ACTIVE
NOP
WRITE
tCMS tCMH
DQM
tAS
A0–A9, A11
tAH
Enable auto precharge
Row
tAS
BA0, BA1
Column m2
Row
tAS
A10
tAH
tAH
Disable auto precharge
Bank
Bank
tDS
tDH
tDS
DIN m
DQ
tDH
DIN m + 2
tDS
tDH
DIN m + 3
tRCD
Don’t Care
Notes:
1. For this example, the BL = 4.
2. A8, A9, and A11 = “Don’t Care.”
PDF: 09005aef8237ed98/Source: 09005aef8237ed68
64mb_x16_Mobile SDRAM_Y24L_2.fm - Rev. C 10/07 EN
61
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2006 Micron Technology, Inc. All rights reserved.
64Mb: 4 Meg x 16 Mobile SDRAM
Package Dimensions
Package Dimensions
Figure 49:
54-Ball VFBGA (8mm x 8mm)
0.65 ±0.05
Seating plane
C
0.10 C
Solder ball material: 96.5% Sn, 3% Ag, 0.5% CU
Solder mask defined ball pads: Ø0.40
Substrate material: Plastic laminate
Mold compound: Epoxy novolac
6.40
54X Ø0.45 ±0.05
Solder ball diameter
refers to post-reflow
condition. The pre-reflow
diameter is 0.42.
0.80
TYP
Ball A1 ID
Ball A1 ID
Ball A1
4.00 ±0.05
Ball A9
6.40
CL
8.00 ±0.10
3.20 ±0.05
0.80 TYP
CL
3.20 ±0.05
4.00 ±0.05
1.00 MAX
8.00 ±0.10
Notes:
1. All dimensions are in millimeters.
®
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This data sheet contains minimum and maximum limits specified over the complete power supply and temperature range
for production devices. Although considered final, these specifications are subject to change, as further product
development and data characterization sometimes occur.
PDF: 09005aef8237ed98/Source: 09005aef8237ed68
64mb_x16_Mobile SDRAM_Y24L_2.fm - Rev. C 10/07 EN
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