MICRON MT48LC64M4A2_99

256Mb: x4, x8, x16 SDRAM
Features
Synchronous DRAM
MT48LC64M4A2 – 16 Meg x 4 x 4 banks
MT48LC32M8A2 – 8 Meg x 8 x 4 banks
MT48LC16M16A2 – 4 Meg x 16 x 4 banks
For the latest data sheet, refer to Micron’s Web site: www.micron.com
Features
Options
• PC100- and PC133-compliant
• Fully synchronous; all signals registered on positive
edge of system clock
• Internal pipelined operation; column address can be
changed every clock cycle
• Internal banks for hiding row access/precharge
• Programmable burst lengths: 1, 2, 4, 8, or full page
• Auto precharge, includes concurrent auto precharge,
and auto refresh modes
• Self refresh mode
• 64ms, 8,192-cycle refresh
• LVTTL-compatible inputs and outputs
• Single +3.3V ±0.3V power supply
• Configurations
– 64 Meg x 4 (16 Meg x 4 x 4 banks)
– 32 Meg x 8 (8 Meg x 8 x 4 banks)
– 16 Meg x 16 (4 Meg x 16 x 4 banks)
• Write recovery (tWR)
– tWR = “2 CLK”1
• Plastic package – OCPL2
– 54-pin TSOP II OCPL2 (400 mil)
(standard)
– 54-pin TSOP II OCPL2 (400 mil)
Pb-free
– 60-ball FBGA (x4, x8) (8mm x 16mm)
– 60-ball FBGA (x4, x8) Pb-free
(8mm x 16mm)
– 54-ball VFBGA (x16) (8mm x 14 mm)
– 54-ball VFBGA (x16) Pb-free
(8mm x 14 mm)
• Timing (cycle time)
– 6.0ns @ CL = 3 (x8, x16 only)
– 7.5ns @ CL = 3 (PC133)
– 7.5ns @ CL = 2 (PC133)
• Self refresh
– Standard
– Low power
• Operating temperature range
– Commercial (0°C to +70°C)
– Industrial (–40°C to +85°C)
• Design revision
Table 1:
Address Table
Parameter
64 Meg x 4 32 Meg x 8 16 Meg x 16
16 Meg x 4
8 Meg x 8
4 Meg x 16
x 4 banks
x 4 banks
x 4 banks
8K
8K
8K
Refresh count
8K (A0–A12) 8K (A0–A12) 8K (A0–A12)
Row
addressing
4 (BA0, BA1) 4 (BA0, BA1) 4 (BA0, BA1)
Bank
addressing
2K (A0–A9, 1K (A0–A9) 512 (A0–A8)
Column
A11)
addressing
Configuration
Table 2:
Key Timing Parameters
CL = CAS (READ) latency
Speed
Grade
-6A
-7E
-75
-7E
-75
Access Time
Clock
Frequency CL = 2
167 MHz
143 MHz
133 MHz
133 MHz
100 MHz
–
–
–
5.4ns
6ns
CL = 3
Setup
Time
Hold
Time
5.4ns
5.4ns
5.4ns
–
–
1.5ns
1.5ns
1.5ns
1.5ns
1.5ns
0.8ns
0.8ns
0.8ns
0.8ns
0.8ns
Marking
64M4
32M8
16M16
A2
TG
P
FB
BB
FG
BG
-6A
-75
-7E
None
L3
None
IT
:D
Notes: 1. Refer to Micron technical note: TN-48-05.
2. Off-center parting line.
3. Contact Micron for availability.
Part Number Example:
MT48LC16M16A2TG-75:D
PDF: 09005aef8091e6d1/Source: 09005aef8091e6a8
256MSDRAM_1.fm - Rev. L 10/07 EN
1
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©1999 Micron Technology, Inc. All rights reserved.
Products and specifications discussed herein are subject to change by Micron without notice.
256Mb: x4, x8, x16 SDRAM
Table of Contents
Table of Contents
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1
Options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1
Marking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1
General Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6
Pin/Ball Assignments and Descriptions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10
Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15
Initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15
Register Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17
Mode Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17
Burst Length (BL). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17
Operating Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18
Write Burst Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18
Burst Type . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19
CAS Latency (CL) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19
Commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22
The COMMAND INHIBIT. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22
NO OPERATION (NOP). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22
LOAD MODE REGISTER . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23
ACTIVE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23
READ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23
WRITE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23
PRECHARGE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23
Auto Precharge . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .24
BURST TERMINATE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .24
AUTO REFRESH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .24
SELF REFRESH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .25
Operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .25
Bank/Row Activation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .25
READs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .26
WRITEs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .32
PRECHARGE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .36
Power-Down . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .36
Clock Suspend. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .37
Burst Read/Single Write Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .38
Concurrent Auto Precharge . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .38
READ with Auto Precharge . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .38
WRITE with Auto Precharge . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .38
Electrical Specifications. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .46
Temperature and Thermal Impedance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .46
Notes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .54
Timing Diagrams. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .56
Package Dimensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .75
PDF: 09005aef8091e6d1/Source: 09005aef8091e6a8
256MSDRAMTOC.fm - Rev. L 10/07 EN
2
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©1999 Micron Technology, Inc. All rights reserved.
256Mb: x4, x8, x16 SDRAM
List of Figures
List of Figures
Figure 1:
Figure 2:
Figure 3:
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Figure 5:
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Figure 47:
Figure 48:
Figure 49:
Figure 50:
Figure 51:
Figure 52:
Figure 53:
Figure 54:
Figure 55:
Figure 56:
64 Meg x 4 SDRAM Functional Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7
32 Meg x 8 SDRAM Functional Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8
16 Meg x 16 SDRAM Functional Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9
54-Pin TSOP Assignment (Top View) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10
60-Ball FBGA Assignment (Top View) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11
54-Ball FBGA Assignment (Top View) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12
Mode Register Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18
CAS Latency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20
Terminating a WRITE Burst . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .24
Activating a Specific Row in a Specific Bank . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .26
Example: Meeting tRCD (MIN) When 2 < tRCD (MIN)/tCK ≤ 3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .26
READ Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .27
Consecutive READ Bursts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .28
Random READ Accesses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .29
READ-to-WRITE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .30
READ-to-WRITE with Extra Clock Cycle . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .30
READ-to-PRECHARGE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .31
Terminating a READ Burst . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .32
WRITE Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .33
WRITE Burst . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .33
WRITE-to-WRITE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .34
Random WRITE Cycles . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .34
WRITE-to-READ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .34
WRITE-to-PRECHARGE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .35
PRECHARGE Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .36
Power-Down . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .37
Clock Suspend During WRITE Burst . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .37
Clock Suspend During READ Burst . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .38
READ With Auto Precharge Interrupted by a READ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .39
READ With Auto Precharge Interrupted by a WRITE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .39
WRITE With Auto Precharge Interrupted by a READ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .40
WRITE With Auto Precharge Interrupted by a WRITE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .40
Example Temperature Test Point Location, 54-Pin TSOP: Top View . . . . . . . . . . . . . . . . . . . . . . . . . . .48
Example Temperature Test Point Location, 54-Ball VFBGA: Top View . . . . . . . . . . . . . . . . . . . . . . . . .48
Example Temperature Test Point Location, 60-Ball FBGA: Top View . . . . . . . . . . . . . . . . . . . . . . . . . .48
Initialize and Load Mode Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .56
Power-Down Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .57
Clock Suspend Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .58
Auto Refresh Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .59
Self Refresh Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .60
Read – Without Auto Precharge . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .61
Read – With Auto Precharge . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .62
Single Read – Without Auto Precharge . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .63
Single Read – With Auto Precharge . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .64
Alternating Bank Read Accesses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .65
Read – Full-Page Burst . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .66
Read – DQM Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .67
Write – Without Auto Precharge . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .68
Write – With Auto Precharge . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .69
Single Write – Without Auto Precharge . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .70
Single Write – With Auto Precharge . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .71
Alternating Bank Write Accesses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .72
Write – Full-Page Burst . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .73
Write – DQM Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .74
54-Pin Plastic TSOP (400 mil) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .75
60-Ball FBGA “FB” Package, 8mm x 16mm (x4, x8) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .76
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3
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©1999 Micron Technology, Inc. All rights reserved.
256Mb: x4, x8, x16 SDRAM
List of Figures
Figure 57:
54-Ball VFBGA “FG” Package, 8mm x 14mm (x16) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .77
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256MSDRAMLOF.fm - Rev. L 10/07 EN
4
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©1999 Micron Technology, Inc. All rights reserved.
256Mb: x4, x8, x16 SDRAM
List of Tables
List of Tables
Table 1:
Table 2:
Table 3:
Table 4:
Table 5:
Table 6:
Table 7:
Table 8:
Table 9:
Table 10:
Table 11:
Table 12:
Table 13:
Table 14:
Table 15:
Table 16:
Table 17:
Table 18:
Table 19:
Table 20:
Table 21:
Table 22:
Address Table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1
Key Timing Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1
256Mb SDRAM Part Numbers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6
54-Pin TSOP Descriptions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13
54-Ball and 60-Ball FBGA Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14
Burst Definition. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19
CAS Latency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21
Truth Table 1 – Commands and DQM Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22
Truth Table 2 – CKE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .41
Truth Table 3 – Current State Bank n, Command to Bank n . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .42
Truth Table 4 – Current State Bank n, Command to Bank m . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .44
Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .46
Temperature Limits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .47
Thermal Impedance Simulated Values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .47
DC Electrical Characteristics and Operating Conditions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .49
IDD Specifications and Conditions (-6A) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .49
IDD Specifications and Conditions (-7E, -75) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .49
Capacitance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .50
Electrical Characteristics and Recommended AC Operating Conditions (-6A) . . . . . . . . . . . . . . . . . .51
Electrical Characteristics and Recommended AC Operating Conditions (-7E, -75) . . . . . . . . . . . . . .52
AC Functional Characteristics (-6A) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .53
AC Functional Characteristics (-7E, -75) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .53
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256MSDRAMLOT.fm - Rev. L 10/07 EN
5
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©1999 Micron Technology, Inc. All rights reserved.
256Mb: x4, x8, x16 SDRAM
General Description
Table 3:
256Mb SDRAM Part Numbers
Part Numbers
MT48LC64M4A2TG
MT48LC64M4A2P
MT48LC64M4A2FB1
MT48LC64M4A2BB1
MT48LC32M8A2TG
MT48LC32M8A2P
MT48LC32M8A2FB1
MT48LC32M8A2BB1
MT48LC16M16A2TG
MT48LC16M16A2P
MT48LC16M16A2FG
MT48LC16M16A2BG
Notes:
Architecture
Package
64 Meg x 4
64 Meg x 4
64 Meg x 4
64 Meg x 4
32 Meg x 8
32 Meg x 8
32 Meg x 8
32 Meg x 8
16 Meg x 16
16 Meg x 16
16 Meg x 16
16 Meg x 16
54-pin TSOP II
54-pin TSOP II
60-ball FBGA
60-ball FBGA
54-pin TSOP II
54-pin TSOP II
60-ball FBGA
60-ball FBGA
54-pin TSOP II
54-pin TSOP II
54-ball FBGA
54-ball FBGA
1. Actual FBGA part marking shown on pages 76 and 77.
General Description
The 256Mb SDRAM is a high-speed CMOS, dynamic random-access memory containing
268,435,456 bits. It is internally configured as a quad-bank DRAM with a synchronous
interface (all signals are registered on the positive edge of the clock signal, CLK). Each of
the x4’s 67,108,864-bit banks is organized as 8,192 rows by 2,048 columns by 4 bits. Each
of the x8’s 67,108,864-bit banks is organized as 8,192 rows by 1,024 columns by 8 bits.
Each of the x16’s 67,108,864-bit banks is organized as 8,192 rows by 512 columns by 16
bits.
Read and write accesses to the SDRAM are burst oriented; accesses start at a selected
location and continue for a programmed number of locations in a programmed
sequence. Accesses begin with the registration of an ACTIVE command, which is then
followed by a READ or WRITE command. The address bits registered coincident with the
ACTIVE command are used to select the bank and row to be accessed (BA0, BA1 select
the bank; A0–A12 select the row). The address bits registered coincident with the READ
or WRITE command are used to select the starting column location for the burst access.
The SDRAM provides for programmable read or write burst lengths (BL) of 1, 2, 4, or 8
locations, or the full page, with a burst terminate option. An auto precharge function
may be enabled to provide a self-timed row precharge that is initiated at the end of the
burst sequence.
The 256Mb SDRAM uses an internal pipelined architecture to achieve high-speed operation. This architecture is compatible with the 2n rule of prefetch architectures, but it also
allows the column address to be changed on every clock cycle to achieve a high-speed,
fully random access. Precharging one bank while accessing one of the other three banks
will hide the PRECHARGE cycles and provide seamless, high-speed, random-access
operation.
The 256Mb SDRAM is designed to operate in 3.3V memory systems. An auto refresh
mode is provided, along with a power-saving, power-down mode. All inputs and outputs
are LVTTL-compatible.
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Micron Technology, Inc., reserves the right to change products or specifications without notice.
©1999 Micron Technology, Inc. All rights reserved.
256Mb: x4, x8, x16 SDRAM
General Description
SDRAMs offer substantial advances in DRAM operating performance, including the
ability to synchronously burst data at a high data rate with automatic column-address
generation, the ability to interleave between internal banks to hide precharge time, and
the capability to randomly change column addresses on each clock cycle during a burst
access.
Figure 1:
64 Meg x 4 SDRAM Functional Block Diagram
CKE
CLK
COMMAND
DECODE
CS#
WE#
CAS#
RAS#
CONTROL
LOGIC
BANK3
BANK2
BANK1
MODE REGISTER
REFRESH 13
COUNTER
12
ROWADDRESS
MUX
13
13
BANK0
ROWADDRESS
8,192
LATCH
&
DECODER
BANK0
MEMORY
ARRAY
(8,192 x 2,048 x 4)
1
DQM
SENSE AMPLIFIERS
4
8,192
I/O GATING
DQM MASK LOGIC
READ DATA LATCH
WRITE DRIVERS
2
A0–A12,
BA0, BA1
15
ADDRESS
REGISTER
2
BANK
CONTROL
LOGIC
DATA
OUTPUT
REGISTER
4
4
2,048
(x4)
1
DQ0DQ3
DATA
INPUT
REGISTER
COLUMN
DECODER
11
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COLUMNADDRESS
COUNTER/
LATCH
11
7
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©1999 Micron Technology, Inc. All rights reserved.
256Mb: x4, x8, x16 SDRAM
General Description
Figure 2:
32 Meg x 8 SDRAM Functional Block Diagram
CKE
CLK
COMMAND
DECODE
CS#
WE#
CAS#
RAS#
CONTROL
LOGIC
BANK3
BANK2
BANK1
MODE REGISTER
REFRESH 13
COUNTER
12
ROWADDRESS
MUX
13
13
BANK0
ROWADDRESS
8,192
LATCH
&
DECODER
BANK0
MEMORY
ARRAY
(8,192 x 1,024 x 8)
1
DQM
SENSE AMPLIFIERS
8
8,192
I/O GATING
DQM MASK LOGIC
READ DATA LATCH
WRITE DRIVERS
2
A0–A12,
BA0, BA1
15
ADDRESS
REGISTER
2
BANK
CONTROL
LOGIC
DATA
OUTPUT
REGISTER
8
8
1,024
(x8)
1
DQ0–
DQ7
DATA
INPUT
REGISTER
COLUMN
DECODER
10
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COLUMNADDRESS
COUNTER/
LATCH
10
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Micron Technology, Inc., reserves the right to change products or specifications without notice.
©1999 Micron Technology, Inc. All rights reserved.
256Mb: x4, x8, x16 SDRAM
General Description
Figure 3:
16 Meg x 16 SDRAM Functional Block Diagram
CKE
CLK
COMMAND
DECODE
CS#
WE#
CAS#
RAS#
CONTROL
LOGIC
BANK3
BANK2
BANK1
MODE REGISTER
REFRESH 13
COUNTER
12
ROWADDRESS
MUX
13
13
BANK0
ROWADDRESS
8,192
LATCH
&
DECODER
BANK0
MEMORY
ARRAY
(8,192 x 512 x 16)
2
DQML,
DQMH
SENSE AMPLIFIERS
16
8,192
I/O GATING
DQM MASK LOGIC
READ DATA LATCH
WRITE DRIVERS
2
A0–A12,
BA0, BA1
15
ADDRESS
REGISTER
2
BANK
CONTROL
LOGIC
DATA
OUTPUT
REGISTER
16
16
512
(x16)
2
DQ0–
DQ15
DATA
INPUT
REGISTER
COLUMN
DECODER
9
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COLUMNADDRESS
COUNTER/
LATCH
9
9
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©1999 Micron Technology, Inc. All rights reserved.
256Mb: x4, x8, x16 SDRAM
Pin/Ball Assignments and Descriptions
Pin/Ball Assignments and Descriptions
Figure 4:
54-Pin TSOP Assignment (Top View)
x4 x8 x16
-
-
NC DQ0
-
-
NC NC
DQ0 DQ1
-
-
NC NC
NC DQ2
-
-
NC NC
DQ1 DQ3
Notes:
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256MSDRAM_2.fm - Rev. L 10/07 EN
-
-
NC
NC
-
-
NC
NC
-
-
VDD
DQ0
VDDQ
DQ1
DQ2
VssQ
DQ3
DQ4
VDDQ
DQ5
DQ6
VssQ
DQ7
VDD
DQML
WE#
CAS#
RAS#
CS#
BA0
BA1
A10
A0
A1
A2
A3
VDD
x16 x8 x4
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
Vss
DQ15 DQ7
VssQ DQ14 NC
DQ13 DQ6
VDDQ DQ12 NC
DQ11 DQ5
VssQ DQ10 NC
DQ9 DQ4
VDDQ DQ8 NC
Vss
NC
DQMH DQM
CLK
CKE A12 A11 A9
A8
A7
A6
A5
A4
Vss
-
NC
NC
DQ3
NC
NC
NC
DQ2
NC
DQM
-
1. The # symbol indicates signal is active LOW. A dash (-) indicates x8 and x4 pin function is
same as x16 pin function.
10
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©1999 Micron Technology, Inc. All rights reserved.
256Mb: x4, x8, x16 SDRAM
Pin/Ball Assignments and Descriptions
Figure 5:
60-Ball FBGA Assignment (Top View)
64 Meg x 4 SDRAM
8mm x 16mm “FB”
32 Meg x 8 SDRAM
8mm x 16mm “FB”
7
8
7
8
Vss
VDD
NC
Vss
VDD
DQ0
NC
VssQ
VDDQ
NC
VssQ
VDDQ
NC
C
VDDQ
DQ3
C
VDDQ
DQ6
DQ1
VssQ
D
NC
NC
D
DQ5
NC
NC
DQ2
E
VDDQ
NC
E
NC
VssQ
VDDQ
NC
DQ2
DQ1
VssQ
F
VDDQ
DQ4
DQ3
VssQ
NC
NC
NC
NC
G
NC
NC
NC
NC
H
NC
Vss
VDD
NC
H
NC
Vss
VDD
NC
J
NC
DQM
WE#
CAS#
J
NC
DQM
WE#
CAS#
K
NC
CK
RAS#
NC
K
NC
CK
RAS#
NC
L
A12
CKE
NC
CS#
L
A12
CKE
NC
CS#
M
A11
A9
BA1
BA0
M
A11
A9
BA1
BA0
N
A8
A7
A0
A10
N
A8
A7
A0
A10
P
A6
A5
A2
A1
P
A6
A5
A2
A1
R
A4
Vss
VDD
A3
R
A4
Vss
VDD
A3
1
2
A
NC
B
4
6
1
2
A
DQ7
NC
B
DQ0
VssQ
NC
NC
NC
VssQ
F
VDDQ
G
3
5
Depopulated Balls
Note:
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256MSDRAM_2.fm - Rev. L 10/07 EN
3
4
5
6
Depopulated Balls
FBGA pin symbol, type, and descriptions are identical to the listing in Table 4 on page 13.
11
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©1999 Micron Technology, Inc. All rights reserved.
256Mb: x4, x8, x16 SDRAM
Pin/Ball Assignments and Descriptions
Figure 6:
54-Ball FBGA Assignment (Top View)
7
8
9
VSSQ
VDDQ
DQ0
VDD
DQ13
VDDQ
VssQ
DQ2
DQ1
DQ12
DQ11
VSSQ
VDDQ
DQ4
DQ3
D
DQ10
DQ9
VDDQ
VSSQ
DQ6
DQ5
E
DQ8
NC
Vss
VDD
LDQM
DQ7
F
UDQM
CLK
CKE
CAS#
RAS#
WE#
G
A12
A11
A9
BA0
BA1
CS#
H
A8
A7
A6
A0
A1
A10
J
Vss
A5
A4
A3
A2
VDD
1
2
3
A
Vss
DQ15
B
DQ14
C
4
5
6
Depopulated Balls
Notes:
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256MSDRAM_2.fm - Rev. L 10/07 EN
1. The balls at A4, A5, and A6 are absent from the physical package. They are included to illustrate that rows 4, 5, and 6 exist, but contain no solder balls.
12
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©1999 Micron Technology, Inc. All rights reserved.
256Mb: x4, x8, x16 SDRAM
Pin/Ball Assignments and Descriptions
Table 4:
54-Pin TSOP Descriptions
Pin Numbers
Symbol
Type
Description
38
CLK
Input
37
CKE
Input
19
CS#
Input
16, 17, 18
WE#, CAS#,
RAS#
x4, x8: DQM
x16: DQML,
DQMH
Input
20, 21
BA0, BA1
Input
23–26, 29–34, 22,
35, 36
A0–A12
Input
2, 4, 5, 7, 8, 10, 11,
13, 42, 44, 45, 47,
48, 50, 51, 53
2, 5, 8, 11, 44, 47,
50, 53
5, 11, 44, 50
40
3, 9, 43, 49
6, 12, 46, 52
1, 14, 27
28, 41, 54
DQ0–DQ15
x16: I/O
DQ0–DQ7
x8: I/O
Clock: CLK is driven by the system clock. All SDRAM input signals are
sampled on the positive edge of CLK. CLK also increments the internal
burst counter and controls the output registers.
Clock enable: CKE activates (HIGH) and deactivates (LOW) the CLK signal.
Deactivating the clock provides PRECHARGE power-down and SELF
REFRESH operation (all banks idle), ACTIVE power-down (row active in
any bank), or CLOCK SUSPEND operation (burst/access in progress). CKE is
synchronous except after the device enters power-down and self refresh
modes, where CKE becomes asynchronous until after exiting the same
mode. The input buffers, including CLK, are disabled during power-down
and self refresh modes, providing low standby power. CKE may be tied
HIGH.
Chip select: CS# enables (registered LOW) and disables (registered HIGH)
the command decoder. All commands are masked when CS# is registered
HIGH, but READ/WRITE bursts already in progress will continue and DQM
operation will retain its DQ mask capability while CS# is HIGH. CS#
provides for external bank selection on systems with multiple banks. CS#
is considered part of the command code.
Command inputs: WE#, CAS#, and RAS# (along with CS#) define the
command being entered.
Input/output mask: DQM is an input mask signal for write accesses and
an output enable signal for read accesses. Input data is masked when
DQM is sampled HIGH during a WRITE cycle. The output buffers are
placed in a High-Z state (two-clock latency) when DQM is sampled HIGH
during a READ cycle. On the x4 and x8, DQML (Pin 15) is a NC and DQMH
is DQM. On the x16, DQML corresponds to DQ0–DQ7 and DQMH
corresponds to DQ8–DQ15. DQML and DQMH are considered same state
when referenced as DQM.
Bank address inputs: BA0 and BA1 define to which bank the ACTIVE,
READ, WRITE, or PRECHARGE command is being applied.
Address inputs: A0–A12 are sampled during the ACTIVE command (rowaddress A0–A12) and READ or WRITE command (column-address A0–A9,
A11 [x4]; A0–A9 [x8]; A0–A8 [x16]; with A10 defining auto precharge) to
select one location out of the memory array in the respective bank. A10
is sampled during a PRECHARGE command to determine whether all
banks are to be precharged (A10 [HIGH]) or bank selected by (A10
[LOW]). The address inputs also provide the op-code during a LOAD
MODE REGISTER command.
Data input/output: Data bus for x16 (pins 4, 7, 10, 13, 42, 45, 48, and 51
are NCs for x8; and pins 2, 4, 7, 8, 10, 13, 42, 45, 47, 48, 51, and 53 are NCs
for x4).
Data input/output: Data bus for x8 (pins 2, 8, 47, 53 are NCs for x4).
DQ0–DQ3
NC
VDDQ
VSSQ
VDD
VSS
x4: I/O
–
Supply
Supply
Supply
Supply
Data input/output: Data bus for x4.
No connect: This pin should be left unconnected.
DQ power: DQ power to the die for improved noise immunity.
DQ ground: DQ ground to the die for improved noise immunity.
Power supply: +3.3V ±0.3V.
Ground.
39
15, 39
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Input
13
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256Mb: x4, x8, x16 SDRAM
Pin/Ball Assignments and Descriptions
Table 5:
54-Ball and 60-Ball FBGA Descriptions
54-Ball
FBGA
60-Ball
FBGA
Symbol
Type
Description
F2
K2
CLK
Input
F3
L2
CKE
Input
G9
L8
CS#
Input
F7, F8, F9
J8, K7, J7
Input
E8, F1
J2
CAS#, RAS#,
WE#
DQM,
LDQM,
UDQM
G7, G8
M8, M7
BA0, BA1
Input
H7, H8, J8,
J7, J3, J2, H3,
H2, H1, G3,
H9, G2, G1
N7, P8, P7,
R8, R1, P2,
P1, N2, N1,
M2, N8, M1,
L1
A0–A12
Input
DQ0–DQ15
I/O
Clock: CLK is driven by the system clock. All SDRAM input signals are
sampled on the positive edge of CLK. CLK also increments the internal
burst counter and controls the output registers.
Clock enable: CKE activates (HIGH) and deactivates (LOW) the CLK
signal. Deactivating the clock provides PRECHARGE power-down and
SELF REFRESH operation (all banks idle), ACTIVE power-down (row
active in any bank), or CLOCK SUSPEND operation (burst/access in
progress). CKE is synchronous except after the device enters powerdown and self refresh modes, where CKE becomes asynchronous until
after exiting the same mode. The input buffers, including CLK, are
disabled during power-down and self refresh modes, providing low
standby power. CKE may be tied HIGH.
Chip select: CS# enables (registered LOW) and disables (registered
HIGH) the command decoder. All commands are masked when CS# is
registered HIGH, but READ/WRITE bursts already in progress will
continue and DQM operation will retain its DQ mask capability while
CS# is HIGH. CS# provides for external bank selection on systems with
multiple banks. CS# is considered part of the command code.
Command inputs: CAS#, RAS#, and WE# (along with CS#) define the
command being entered.
Input/output mask: DQM is sampled HIGH and is an input mask signal
for write accesses and an output enable signal for read accesses. Input
data is masked during a WRITE cycle. The output buffers are placed in
a High-Z state (two-clock latency) when during a READ cycle. LDQM
corresponds to DQ0–DQ7; UDQM corresponds to DQ8–DQ15. LDQM
and UDQM are considered same state when referenced as DQM.
Bank address input(s): BA0 and BA1 define to which bank the ACTIVE,
READ, WRITE, or PRECHARGE command is being applied. These balls
also provide the op-code during a LOAD MODE REGISTER command.
Address inputs: A0–A12 are sampled during the ACTIVE command
(row-address A0–A12) and READ or WRITE command (column-address
A0–A9, A11 [x4]; A0–A9 [x8]; A0–A8 [x16]; with A10 defining auto
precharge) to select one location out of the memory array in the
respective bank. A10 is sampled during a PRECHARGE command to
determine whether all banks are to be precharged (A10 HIGH) or bank
selected by BA0, BA1 (LOW). The address inputs also provide the opcode during a LOAD MODE REGISTER command.
Data input/output: Data bus.
A8, B9, B8,
C9, C8, D9,
D8, E9, E1,
D2, D1, C2,
C1, B2, B1,
A2
C7, F7, F2,
C2
A8, C7, D8,
F7, F2, D1,
C2, A1
E2
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Input
DQ0–DQ3
(x4) I/O Data input/output: Data bus.
DQ0–DQ7
(x8) I/O Data input/output: Data bus.
NC
–
No connect: These balls should be left unconnected.
14
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©1999 Micron Technology, Inc. All rights reserved.
256Mb: x4, x8, x16 SDRAM
Functional Description
Table 5:
54-Ball and 60-Ball FBGA Descriptions (continued)
54-Ball
FBGA
60-Ball
FBGA
A7, B3, C7,
D3
A3, B7, C3,
D7
A9, E7, J9
A1, E3, J1
A1, A8, B1,
B8, D1, D2,
D7, D8, E1,
E8, G1, G2,
G7, G8, H1,
H8, J1, K1,
K8, L7
B1, B8, D2,
D7, E1, E8,
G1, G2, G7,
G8, H1, H8,
J1, K1, K8,
L7
B7, C1, E7,
F1
B2, C8, E2,
F8
A7, R7
A2, H2, R2
Symbol
Type
NC
x4
Description
No connect: These balls should be left unconnected.
G1 is a no connect for this part, but may be used as A12 in future
designs.
NC
x8
No connect: These balls should be left unconnected.
G1 is a no connect for this part, but may be used as A12 in future
designs.
VDDQ
Supply DQ power: DQ power to the die for improved noise immunity.
VSSQ
Supply DQ ground: DQ ground to the die for improved noise immunity.
VDD
VSS
Supply Power supply: Voltage dependent on option.
Supply Ground.
Functional Description
In general, the 256Mb SDRAMs (16 Meg x 4 x 4 banks, 8 Meg x 8 x 4 banks, and 4 Meg x 16
x 4 banks) are quad-bank DRAMs that operate at 3.3V and include a synchronous interface (all signals are registered on the positive edge of the clock signal, CLK). Each of the
x4’s 67,108,864-bit banks is organized as 8,192 rows by 2,048 columns by 4 bits. Each of
the x8’s 67,108,864-bit banks is organized as 8,192 rows by 1,024 columns by 8 bits. Each
of the x16’s 67,108,864-bit banks is organized as 8,192 rows by 512 columns by 16 bits.
Read and write accesses to the SDRAM are burst oriented; accesses start at a selected
location and continue for a programmed number of locations in a programmed
sequence. Accesses begin with the registration of an ACTIVE command, which is then
followed by a READ or WRITE command. The address bits registered coincident with the
ACTIVE command are used to select the bank and row to be accessed (BA0 and BA1
select the bank, A0–A12 select the row). The address bits (x4: A0–A9, A11; x8: A0–A9; x16:
A0–A8) registered coincident with the READ or WRITE command are used to select the
starting column location for the burst access.
Prior to normal operation, the SDRAM must be initialized. The following sections
provide detailed information covering device initialization, register definition,
command descriptions, and device operation.
Initialization
SDRAMs must be powered up and initialized in a predefined manner. Operational
procedures other than those specified may result in undefined operation. After power is
applied to VDD and VDDQ (simultaneously) and the clock is stable (stable clock is
defined as a signal cycling within timing constraints specified for the clock pin), the
SDRAM requires a 100µs delay prior to issuing any command other than a COMMAND
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256Mb: x4, x8, x16 SDRAM
Functional Description
INHIBIT or NOP. Starting at some point during this 100µs period and continuing at least
through the end of this period, COMMAND INHIBIT or NOP commands must be
applied.
After the 100µs delay has been satisfied with at least one COMMAND INHIBIT or NOP
command having been applied, a PRECHARGE command should be applied. All banks
must then be precharged, thereby placing the device in the all banks idle state.
Once in the idle state, at least two AUTO REFRESH cycles must be performed. After the
AUTO REFRESH cycles are complete, the SDRAM is ready for mode register programming. Because the mode register will power up in an unknown state, it must be loaded
prior to applying any operational command. If desired, the two AUTO REFRESH
commands can be issued after the LMR command.
The recommended power-up sequence for SDRAMs:
1. Simultaneously apply power to VDD and VDDQ.
2. Assert and hold CKE at a LVTTL logic LOW since all inputs and outputs are LVTTLcompatible.
3. Provide stable CLOCK signal. Stable clock is defined as a signal cycling within timing
constraints specified for the clock pin.
4. Wait at least 100µs prior to issuing any command other than a COMMAND INHIBIT
or NOP.
5. Starting at some point during this 100µs period, bring CKE HIGH. Continuing at least
through the end of this period, 1 or more COMMAND INHIBIT or NOP commands
must be applied.
6. Perform a PRECHARGE ALL command.
7. Wait at least tRP time; during this time NOPs or DESELECT commands must be given.
All banks will complete their precharge, thereby placing the device in the all banks
idle state.
8. Issue an AUTO REFRESH command.
9. Wait at least tRFC time, during which only NOPs or COMMAND INHIBIT commands
are allowed.
10. Issue an AUTO REFRESH command.
11. Wait at least tRFC time, during which only NOPs or COMMAND INHIBIT commands
are allowed.
12. The SDRAM is now ready for mode register programming. Because the mode register
will power up in an unknown state, it should be loaded with desired bit values prior to
applying any operational command. Using the LMR command, program the mode
register. The mode register is programmed via the MODE REGISTER SET command
with BA1 = 0, BA0 = 0 and retains the stored information until it is programmed again
or the device loses power. Not programming the mode register upon initialization will
result in default settings which may not be desired. Outputs are guaranteed High-Z
after the LMR command is issued. Outputs should be High-Z already before the LMR
command is issued.
13. Wait at least tMRD time, during which only NOP or DESELECT commands are
allowed.
At this point the DRAM is ready for any valid command.
Note:
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If desired, more than two AUTO REFRESH commands can be issued in the sequence.
After steps 9 and 10 are complete, repeat them until the desired number of AUTO
REFRESH + tRFC loops is achieved.
16
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256Mb: x4, x8, x16 SDRAM
Functional Description
Register Definition
Mode Register
The mode register is used to define the specific mode of operation of the SDRAM. This
definition includes the selection of BL, a burst type, CL, an operating mode, and a write
burst mode, as shown in Figure 7 on page 18. The mode register is programmed via the
LOAD MODE REGISTER command and will retain the stored information until it is
programmed again or the device loses power.
Mode register bits M0–M2 specify BL, M3 specifies the type of burst (sequential or interleaved), M4–M6 specify CL, M7, and M8 specify the operating mode, M9 specifies the
write burst mode, and M10 and M11 are reserved for future use. Address A12 (M12) is
undefined but should be driven LOW during loading of the mode register.
The mode register must be loaded when all banks are idle, and the controller must wait
the specified time before initiating the subsequent operation. Violating either of these
requirements will result in unspecified operation.
Burst Length (BL)
Read and write accesses to the SDRAM are burst oriented, with BL being programmable,
as shown in Figure 7 on page 18. BL determines the maximum number of column locations that can be accessed for a given READ or WRITE command. Burst lengths of 1, 2, 4,
or 8 locations are available for both the sequential and the interleaved burst types, and a
full-page burst is available for the sequential mode. The full-page burst is used in
conjunction with the BURST TERMINATE command to generate arbitrary BLs.
Reserved states cannot be used, because unknown operation or incompatibility with
future versions may result.
When a READ or WRITE command is issued, a block of columns equal to BL is effectively
selected. All accesses for that burst take place within this block, meaning that the burst
will wrap within the block if a boundary is reached. The block is uniquely selected by A1–
A9, A11 (x4), A1–A9 (x8) or A1–A8 (x16) when BL = 2; by A2–A9, A11 (x4), A2–A9 (x8) or
A2–A8 (x16) when BL = 4; and by A3–A9, A11 (x4), A3–A9 (x8) or A3–A8 (x16) when BL = 8.
The remaining (least significant) address bit(s) is (are) used to select the starting location
within the block. Full-page bursts wrap within the page if the boundary is reached.
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256Mb: x4, x8, x16 SDRAM
Functional Description
Figure 7:
Mode Register Definition
A12 A11 A10
12
11
9
10
Reserved
A9
A8
8
A6
A7
6
7
WB Op Mode
A5
A4
5
A3
4
3
CAS Latency
BT
Program
BA1, BA0 = “0, 0”
to ensure compatibility
with future devices.
M3 = 0
M3 = 1
0
0
1
1
0
0
1
2
2
0
1
0
4
4
0
1
1
8
8
1
0
0
Reserved
Reserved
Operating Mode
1
0
1
Reserved
Reserved
Standard Operation
1
1
0
Reserved
Reserved
All other states reserved
1
1
1
Full Page
Reserved
1
Single Location Access
M6-M0
0
0
Defined
–
–
–
Mode Register (Mx)
0
Programmed Burst Length
M7
0
Burst Length
M2 M1 M0
0
M8
1
2
Address Bus
A0
Burst Length
Write Burst Mode
M9
A1
A2
M6 M5 M4
M3
Burst Type
0
Sequential
1
Interleaved
CAS Latency
0
0
0
Reserved
0
0
1
Reserved
0
1
0
2
0
1
1
3
1
0
0
Reserved
1
0
1
Reserved
1
1
0
Reserved
1
1
1
Reserved
Operating Mode
The normal operating mode is selected by setting M7 and M8 to zero; the other combinations of values for M7 and M8 are reserved for future use and/or test modes. The
programmed BL applies to both READ and WRITE bursts.
Test modes and reserved states should not be used because unknown operation or
incompatibility with future versions may result.
Write Burst Mode
When M9 = 0, BL programmed via M0–M2 applies to both READ and WRITE bursts;
when M9 = 1, the programmed BL applies to READ bursts, but write accesses are singlelocation (nonburst) accesses.
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256Mb: x4, x8, x16 SDRAM
Functional Description
Burst Type
Accesses within a given burst may be programmed either to be sequential or interleaved;
this is referred to as the burst type and is selected via bit M3.
The ordering of accesses within a burst is determined by BL, the burst type, and the
starting column address, as shown in Table 6.
Table 6:
Burst Definition
Burst
Length
Order of Accesses Within a Burst
Starting Column Address
2
4
8
Full page (y)
Notes:
A2
0
0
0
0
1
1
1
1
A0
0
1
A1
A0
0
0
0
1
1
0
1
1
A1
A0
0
0
0
1
1
0
1
1
0
0
0
1
1
0
1
1
n = A0–A11/9/8
(location 0–y)
Type = Sequential
Type = Interleaved
0-1
1-0
0-1
1-0
0-1-2-3
1-2-3-0
2-3-0-1
3-0-1-2
0-1-2-3
1-0-3-2
2-3-0-1
3-2-1-0
0-1-2-3-4-5-6-7
1-2-3-4-5-6-7-0
2-3-4-5-6-7-0-1
3-4-5-6-7-0-1-2
4-5-6-7-0-1-2-3
5-6-7-0-1-2-3-4
6-7-0-1-2-3-4-5
7-0-1-2-3-4-5-6
Cn, Cn + 1, Cn + 2
Cn + 3, Cn + 4...
…Cn - 1, Cn…
0-1-2-3-4-5-6-7
1-0-3-2-5-4-7-6
2-3-0-1-6-7-4-5
3-2-1-0-7-6-5-4
4-5-6-7-0-1-2-3
5-4-7-6-1-0-3-2
6-7-4-5-2-3-0-1
7-6-5-4-3-2-1-0
Not supported
1. For full-page accesses: y = 2,048 (x4); y = 1,024 (x8); y = 512 (x16).
2. For BL = 2, A1–A9, A11 (x4); A1–A9 (x8); or A1–A8 (x16) select the block-of-two burst; A0
selects the starting column within the block.
3. For BL = 4, A2–A9, A11 (x4); A2–A9 (x8); or A2–A8 (x16) select the block-of-four burst; A0–
A1 select the starting column within the block.
4. For BL = 8, A3–A9, A11 (x4); A3–A9 (x8); or A3–A8 (x16) select the block-of-eight burst; A0–
A2 select the starting column within the block.
5. For a full-page burst, the full row is selected and A0–A9, A11 (x4); A0–A9 (x8); or A0–A8
(x16) select the starting column.
6. Whenever a boundary of the block is reached within a given sequence above, the following
access wraps within the block.
7. For BL = 1, A0–A9, A11 (x4); A0–A9 (x8); or A0–A8 (x16) select the unique column to be
accessed, and mode register bit M3 is ignored.
CAS Latency (CL)
CL is the delay, in clock cycles, between the registration of a READ command and the
availability of the first piece of output data. The latency can be set to two or three clocks.
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256Mb: x4, x8, x16 SDRAM
Functional Description
If a READ command is registered at clock edge n and the latency is m clocks, the data will
be available by clock edge n + m. The DQs will start driving as a result of the clock edge
one cycle earlier (n + m - 1), and provided that the relevant access times are met, the data
will be valid by clock edge n + m. For example, assuming that the clock cycle time is such
that all relevant access times are met, if a READ command is registered at T0 and the
latency is programmed to two clocks, the DQs will start driving after T1 and the data will
be valid by T2, as shown in Figure 8. Table 7 on page 21 indicates the operating frequencies at which each CL setting can be used.
Reserved states cannot be used as unknown operation or incompatibility with future
versions may result.
Figure 8:
CAS Latency
T0
T1
T2
T3
READ
NOP
NOP
CLK
COMMAND
tLZ
tOH
DOUT
DQ
tAC
CL = 2
T0
T1
T2
T3
T4
READ
NOP
NOP
NOP
CLK
COMMAND
tLZ
tOH
DOUT
DQ
tAC
CL = 3
DON’T CARE
UNDEFINED
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Functional Description
Table 7:
CAS Latency
Allowable Operating Frequency (MHz)
Speed
CL = 2
CL = 3
≤133
≤167
-6A
2
≤133
≤143
-7E
-75
≤100
≤133
1. -6A speed grade supports latency of 3-3-3 cycles (CAS latency-tRCD-tRP) at 167 MHz (MAX).
2. -7E speed grade supports latency of 2-2-2 cycles at 133 MHz (MAX).
1
Notes:
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Commands
Commands
Truth Table 1 provides a quick reference of available commands. This is followed by a
written description of each command. Three additional Truth Tables appear following
“Operations” on page 25; these tables provide current state/next state information.
Table 8:
Truth Table 1 – Commands and DQM Operation
Note: 1 applies to the entire table
Name (Function)
COMMAND INHIBIT (NOP)
NO OPERATION (NOP)
ACTIVE (Select bank and activate row)
READ (Select bank and column, and start READ
burst)
WRITE (Select bank and column, and start WRITE
burst)
BURST TERMINATE
PRECHARGE (Deactivate row in bank or banks)
AUTO REFRESH or SELF REFRESH
(Enter self refresh mode)
LOAD MODE REGISTER
Write enable/output enable
Write inhibit/output High-Z
Notes:
1.
2.
3.
4.
5.
6.
7.
8.
CS#
RAS#
CAS#
WE#
DQM
ADDR
DQs
Notes
H
L
L
L
X
H
L
H
X
H
H
L
X
H
H
H
X
X
X
L/H8
X
X
Bank/row
Bank/col
X
X
X
X
3
4
L
H
L
L
L/H8
Bank/col
Valid
4
L
L
L
H
L
L
H
H
L
L
L
H
X
X
X
X
Code
X
Active
X
X
5
6, 7
L
–
–
L
–
–
L
–
–
L
–
–
X
L
H
Op-code
–
–
X
Active
High-Z
2
8
8
CKE is HIGH for all commands shown except SELF REFRESH.
A0–A11 define the op-code written to the mode register, and A12 should be driven LOW.
A0–A12 provide row address, and BA0, BA1 determine which bank is made active.
A0–A9, A11 (x4); A0–A9 (x8); or A0–A8 (x16) provide column address; A10 HIGH enables the
auto precharge feature (nonpersistent), while A10 LOW disables the auto precharge feature; BA0, BA1 determine which bank is being read from or written to.
A10 LOW: BA0, BA1 determine the bank being precharged. A10 HIGH: All banks precharged
and BA0, BA1 are “Don’t Care.”
This command is AUTO REFRESH if CKE is HIGH, SELF REFRESH if CKE is LOW.
Internal refresh counter controls row addressing; all inputs and I/Os are “Don’t Care” except
for CKE.
Activates or deactivates the DQs during WRITEs (zero-clock delay) and READs (two-clock
delay).
The COMMAND INHIBIT
The COMMAND INHIBIT function prevents new commands from being executed by the
SDRAM, regardless of whether the CLK signal is enabled. The SDRAM is effectively deselected. Operations already in progress are not affected.
NO OPERATION (NOP)
The NO OPERATION (NOP) command is used to perform a NOP to an SDRAM that is
selected (CS# is LOW). This prevents unwanted commands from being registered during
idle or wait states. Operations already in progress are not affected.
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Commands
LOAD MODE REGISTER
The mode register is loaded via inputs A0–A11 (A12 should be driven LOW.) See “Register
Definition” on page 17. The LOAD MODE REGISTER command can only be issued when
all banks are idle, and a subsequent executable command cannot be issued until tMRD
is met.
ACTIVE
The ACTIVE command is used to open (or activate) a row in a particular bank for a
subsequent access. The value on the BA0, BA1 inputs selects the bank, and the address
provided on inputs A0–A12 selects the row. This row remains active (or open) for
accesses until a PRECHARGE command is issued to that bank. A PRECHARGE
command must be issued before opening a different row in the same bank.
READ
The READ command is used to initiate a burst read access to an active row. The value on
the BA0, BA1 inputs selects the bank, and the address provided on inputs A0–A9, A11
(x4), A0–A9 (x8), or A0–A8 (x16) selects the starting column location. The value on input
A10 determines whether auto precharge is used. If auto precharge is selected, the row
being accessed will be precharged at the end of the READ burst; if auto precharge is not
selected, the row will remain open for subsequent accesses. Read data appears on the
DQs subject to the logic level on the DQM inputs two clocks earlier. If a given DQM
signal was registered HIGH, the corresponding DQs will be High-Z two clocks later; if the
DQM signal was registered LOW, the DQs will provide valid data.
WRITE
The WRITE command is used to initiate a burst write access to an active row. The value
on the BA0, BA1 inputs selects the bank, and the address provided on inputs A0–A9; A11
(x4); A0–A9 (x8); or A0–A8 (x16) selects the starting column location. The value on input
A10 determines whether auto precharge is used. If auto precharge is selected, the row
being accessed will be precharged at the end of the WRITE burst; if auto precharge is not
selected, the row will remain open for subsequent accesses. Input data appearing on the
DQs is written to the memory array subject to the DQM input logic level appearing coincident with the data. If a given DQM signal is registered LOW, the corresponding data
will be written to memory; if the DQM signal is registered HIGH, the corresponding data
inputs will be ignored, and a WRITE will not be executed to that byte/column
location.
PRECHARGE
The PRECHARGE command is used to deactivate the open row in a particular bank or
the open row in all banks. The bank(s) will be available for a subsequent row access a
specified time (tRP) after the PRECHARGE command is issued. Input A10 determines
whether one or all banks are to be precharged, and in the case where only one bank is to
be precharged, inputs BA0, BA1 select the bank. Otherwise BA0, BA1 are treated as
“Don’t Care.” After a bank has been precharged, it is in the idle state and must be activated prior to any READ or WRITE commands being issued to that bank.
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Commands
Auto Precharge
Auto precharge is a feature that performs the same individual-bank precharge function
described above, without requiring an explicit command. This is accomplished by using
A10 to enable auto precharge in conjunction with a specific READ or WRITE command.
A precharge of the bank/row that is addressed with the READ or WRITE command is
automatically performed upon completion of the READ or WRITE burst, except in the
full-page burst mode, where auto precharge does not apply. Auto precharge is nonpersistent in that it is either enabled or disabled for each individual READ or WRITE
command.
Auto precharge ensures that the precharge is initiated at the earliest valid stage within a
burst. The user must not issue another command to the same bank until the precharge
time (tRP) is completed. This is determined as if an explicit PRECHARGE command was
issued at the earliest possible time, as described for each burst type in “Operations” on
page 25.
BURST TERMINATE
The BURST TERMINATE command is used to truncate either fixed-length or full-page
bursts. The most recently registered READ or WRITE command prior to the BURST
TERMINATE command will be truncated, as shown in “Operations” on page 25. The
BURST TERMINATE command does not precharge the row; the row will remain open
until a PRECHARGE command is issued.
Figure 9:
Terminating a WRITE Burst
T0
T1
T2
COMMAND
WRITE
BURST
TERMINATE
ADDRESS
BANK,
COL n
(ADDRESS)
DIN
n
(DATA)
CLK
DQ
TRANSITIONING DATA
Note:
NEXT
COMMAND
DON’T CARE
DQM is LOW.
AUTO REFRESH
AUTO REFRESH is used during normal operation of the SDRAM and is analogous to
CAS#-BEFORE-RAS# (CBR) refresh in conventional DRAMs. This command is nonpersistent, so it must be issued each time a refresh is required. All active banks must be
precharged prior to issuing an AUTO REFRESH command. The AUTO REFRESH
command should not be issued until the minimum tRP has been met after the
PRECHARGE command, as shown in “Operations” on page 25.
The addressing is generated by the internal refresh controller. This makes the address
bits a “Don’t Care” during an AUTO REFRESH command. The 256Mb SDRAM requires
8,192 AUTO REFRESH cycles every 64ms (tREF), regardless of width option. Providing a
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Operations
distributed AUTO REFRESH command every 7.81µs will meet the refresh requirement
and ensure that each row is refreshed. Alternatively, 8,192 AUTO REFRESH commands
can be issued in a burst at the minimum cycle rate (tRFC), once every 64ms.
SELF REFRESH
The SELF REFRESH command can be used to retain data in the SDRAM, even if the rest
of the system is powered down. When in the self refresh mode, the SDRAM retains data
without external clocking.
The SELF REFRESH command is initiated like an AUTO REFRESH command except CKE
is disabled (LOW). After the SELF REFRESH command is registered, all the inputs to the
SDRAM become a “Don’t Care” with the exception of CKE, which must remain LOW.
After self refresh mode is engaged, the SDRAM provides its own internal clocking,
causing it to perform its own AUTO REFRESH cycles. The SDRAM must remain in self
refresh mode for a minimum period equal to tRAS and may remain in self refresh mode
for an indefinite period beyond that.
The procedure for exiting self refresh requires a sequence of commands. First, CLK must
be stable (stable clock is defined as a signal cycling within timing constraints specified
for the clock pin) prior to CKE going back HIGH. After CKE is HIGH, the SDRAM must
have NOP commands issued (a minimum of two clocks) for tXSR because time is
required for the completion of any internal refresh in progress.
Upon exiting the self refresh mode, AUTO REFRESH commands must be issued every
7.81µs or less as both SELF REFRESH and AUTO REFRESH utilize the row refresh
counter.
Operations
Bank/Row Activation
Before any READ or WRITE commands can be issued to a bank within the SDRAM, a row
in that bank must be “opened.” This is accomplished via the ACTIVE command, which
selects both the bank and the row to be activated (see Figure 10 on page 26).
After opening a row (issuing an ACTIVE command), a READ or WRITE command may be
issued to that row, subject to the tRCD specification. tRCD (MIN) should be divided by
the clock period and rounded up to the next whole number to determine the earliest
clock edge after the ACTIVE command on which a READ or WRITE command can be
entered. For example, a tRCD specification of 20ns with a 125 MHz clock (8ns period)
results in 2.5 clocks, rounded to 3. This is reflected in Figure 11 on page 26, which covers
any case where 2 < tRCD (MIN)/tCK ≤ 3. (The same procedure is used to convert other
specification limits from time units to clock cycles.)
A subsequent ACTIVE command to a different row in the same bank can only be issued
after the previous active row has been “closed” (precharged). The minimum time
interval between successive ACTIVE commands to the same bank is defined by tRC.
A subsequent ACTIVE command to another bank can be issued while the first bank is
being accessed, which results in a reduction of total row-access overhead. The minimum
time interval between successive ACTIVE commands to different banks is defined by
t
RRD.
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Operations
Figure 10:
Activating a Specific Row in a Specific Bank
CLK
CKE
HIGH
CS#
RAS#
CAS#
WE#
ROW
ADDRESS
A0–A12
BANK
ADDRESS
BA0, BA1
DON’T CARE
Figure 11:
Example: Meeting tRCD (MIN) When 2 < tRCD (MIN)/tCK ≤ 3
T0
T1
T2
NOP
NOP
T3
T4
CLK
COMMAND
ACTIVE
READ or
WRITE
tRCD
DON’T CARE
READs
READ bursts are initiated with a READ command, as shown in Figure 12 on page 27.
The starting column and bank addresses are provided with the READ command, and
auto precharge is either enabled or disabled for that burst access. If auto precharge is
enabled, the row being accessed is precharged at the completion of the burst. For the
generic READ commands used in the following illustrations, auto precharge is disabled.
During READ bursts, the valid data-out element from the starting column address will
be available following CL after the READ command. Each subsequent data-out element
will be valid by the next positive clock edge. Figure 13 on page 28 shows general timing
for each possible CL setting.
Upon completion of a burst, assuming no other commands have been initiated, the DQs
will go High-Z. A full-page burst will continue until terminated. (At the end of the page, it
will wrap to the start address and continue.)
Data from any READ burst may be truncated with a subsequent READ command, and
data from a fixed-length READ burst may be immediately followed by data from a READ
command. In either case, a continuous flow of data can be maintained. The first data
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Operations
element from the new burst follows either the last element of a completed burst or the
last desired data element of a longer burst that is being truncated. The new READ
command should be issued x cycles before the clock edge at which the last desired data
element is valid, where x = CL - 1.
This is shown in Figure 13 on page 28 for CL = 2 and CL = 3; data element n + 3 is either
the last of a burst of four or the last desired of a longer burst. The 256Mb SDRAM uses a
pipelined architecture and therefore does not require the 2n rule associated with a
prefetch architecture. A READ command can be initiated on any clock cycle following a
previous READ command. Full-speed random read accesses can be performed to the
same bank, as shown in Figure 14 on page 29, or each subsequent READ may be
performed to a different bank.
Figure 12:
READ Command
CLK
CKE
HIGH
CS#
RAS#
CAS#
WE#
A0–A9, A11: x4
A0–A9: x8
A0–A8: x16
COLUMN
ADDRESS
A12: x4
A11, A12: x8
A9, A11, A12: x16
ENABLE AUTO PRECHARGE
A10
DISABLE AUTO PRECHARGE
BA0, BA1
BANK
ADDRESS
DON’T CARE
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Operations
Figure 13:
Consecutive READ Bursts
T0
T1
T2
T3
T4
T5
T6
CLK
COMMAND
READ
ADDRESS
BANK,
COL n
NOP
NOP
NOP
READ
NOP
NOP
X = 1 cycle
BANK,
COL b
DOUT
n
DQ
DOUT
n+2
DOUT
n+1
DOUT
n+3
DOUT
b
CL = 2
T0
T1
T2
T3
T4
T5
T6
T7
CLK
COMMAND
READ
ADDRESS
BANK,
COL n
NOP
NOP
NOP
READ
NOP
NOP
NOP
X = 2 cycles
BANK,
COL b
DOUT
n
DQ
DOUT
n+1
DOUT
n+2
DOUT
n+3
DOUT
b
CL = 3
TRANSITIONING DATA
Note:
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DON’T CARE
Each READ command may be to any bank. DQM is LOW.
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Operations
Figure 14:
Random READ Accesses
T0
T1
T2
T3
T4
T5
CLK
COMMAND
READ
READ
READ
READ
ADDRESS
BANK,
COL n
BANK,
COL a
BANK,
COL x
BANK,
COL m
DOUT
n
DQ
NOP
NOP
DOUT
x
DOUT
a
DOUT
m
CL = 2
T0
T1
T2
T3
T4
T5
T6
CLK
COMMAND
READ
READ
READ
READ
ADDRESS
BANK,
COL n
BANK,
COL a
BANK,
COL x
BANK,
COL m
NOP
DOUT
n
DQ
DOUT
a
NOP
DOUT
x
NOP
DOUT
m
CL = 3
TRANSITIONING DATA
Note:
DON’T CARE
Each READ command may be to any bank. DQM is LOW.
Data from any READ burst may be truncated with a subsequent WRITE command, and
data from a fixed-length READ burst may be immediately followed by data from a
WRITE command (subject to bus turnaround limitations). The WRITE burst may be
initiated on the clock edge immediately following the last (or last desired) data element
from the READ burst, provided that I/O contention can be avoided. In a given system
design, there may be a possibility that the device driving the input data will go Low-Z
before the SDRAM DQs go High-Z. In this case, at least a single-cycle delay should occur
between the last read data and the WRITE command.
The DQM input is used to avoid I/O contention, as shown in Figure 15 and Figure 16 on
page 30. The DQM signal must be asserted (HIGH) at least two clocks prior to the WRITE
command (DQM latency is two clocks for output buffers) to suppress data-out from the
READ. Once the WRITE command is registered, the DQs will go High-Z (or remain
High-Z), regardless of the state of the DQM signal; provided the DQM was active on the
clock just prior to the WRITE command that truncated the READ command. If not, the
second WRITE will be an invalid WRITE. For example, if DQM was LOW during T4 in
Figure 11 on page 26, then the WRITEs at T5 and T7 would be valid, while the WRITE at
T6 would be invalid.
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Operations
The DQM signal must be de-asserted prior to the WRITE command (DQM latency is
zero clocks for input buffers) to ensure that the written data is not masked. Figure 10 on
page 26 shows the case where the clock frequency allows for bus contention to be
avoided without adding a NOP cycle, and Figure 16 shows the case where the additional
NOP is needed.
Figure 15:
READ-to-WRITE
T0
T1
T2
T3
T4
CLK
DQM
COMMAND
READ
ADDRESS
BANK,
COL n
NOP
NOP
NOP
WRITE
BANK,
COL b
tCK
tHZ
DOUT n
DQ
DIN b
tDS
Note:
Figure 16:
CL = 3 is used for illustration. The READ command may be to any bank, and the WRITE
command may be to any bank. If a burst of one is used, then DQM is not required.
READ-to-WRITE with Extra Clock Cycle
T0
T1
T2
T3
T4
T5
CLK
DQM
COMMAND
READ
ADDRESS
BANK,
COL n
NOP
NOP
NOP
NOP
WRITE
BANK,
COL b
tHZ
DOUT n
DQ
DIN b
tDS
TRANSITIONING DATA
Note:
DON’T CARE
CL = 3 is used for illustration. The READ command may be to any bank, and the WRITE
command may be to any bank.
A fixed-length READ burst may be followed by, or truncated with, a PRECHARGE
command to the same bank (provided that auto precharge was not activated), and a fullpage burst may be truncated with a PRECHARGE command to the same bank. The
PRECHARGE command should be issued x cycles before the clock edge at which the last
desired data element is valid, where x = CL - 1. This is shown in Figure 17 on page 31 for
each possible CL; data element n + 3 is either the last of a burst of four or the last desired
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Operations
of a longer burst. Following the PRECHARGE command, a subsequent command to the
same bank cannot be issued until tRP is met. Note that part of the row precharge time is
hidden during the access of the last data element(s).
In the case of a fixed-length burst being executed to completion, a PRECHARGE
command issued at the optimum time (as described above) provides the same operation
that would result from the same fixed-length burst with auto precharge. The disadvantage of the PRECHARGE command is that it requires command and address buses to be
available at the appropriate time to issue the command; the advantage of the
PRECHARGE command is that it can be used to truncate fixed-length or full-page bursts.
Full-page READ bursts can be truncated with the BURST TERMINATE command, and
fixed-length READ bursts may be truncated with a BURST TERMINATE command,
provided that auto precharge was not activated. The BURST TERMINATE command
should be issued x cycles before the clock edge at which the last desired data element is
valid, where x = CL - 1. This is shown in Figure 18 on page 32 for each possible CL; data
element n + 3 is the last desired data element of a longer burst.
Figure 17:
READ-to-PRECHARGE
T0
T1
T2
T3
T4
T5
T6
T7
CLK
t RP
COMMAND
READ
NOP
NOP
PRECHARGE
NOP
NOP
NOP
ACTIVE
X = 1 cycle
ADDRESS
BANK
(a or all)
BANK a,
COL n
DOUT
n
DQ
BANK a,
ROW
DOUT
n+2
DOUT
n+1
DOUT
n+3
CL = 2
T0
T1
T2
T3
T4
T5
T6
T7
CLK
t RP
COMMAND
READ
NOP
NOP
PRECHARGE
NOP
NOP
NOP
ACTIVE
X = 2 cycles
ADDRESS
BANK
(a or all)
BANK a,
COL n
DOUT
n
DQ
DOUT
n+1
BANK a,
ROW
DOUT
n+2
DOUT
n+3
CL = 3
TRANSITIONING DATA
Note:
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DQM is LOW.
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Operations
Figure 18:
Terminating a READ Burst
T0
T1
T2
T3
T4
T5
T6
CLK
COMMAND
READ
ADDRESS
BANK,
COL n
NOP
NOP
BURST
TERMINATE
NOP
NOP
NOP
X = 1 cycle
DOUT
n+2
DOUT
n+1
DOUT
n
DQ
DOUT
n+3
CL = 2
T0
T1
T2
T3
T4
T5
T6
T7
CLK
COMMAND
READ
ADDRESS
BANK,
COL n
NOP
NOP
BURST
TERMINATE
NOP
NOP
NOP
NOP
X = 2 cycles
DOUT
n
DQ
DOUT
n+1
DOUT
n+2
DOUT
n+3
CL = 3
TRANSITIONING DATA
Note:
DON’T CARE
DQM is LOW.
WRITEs
WRITE bursts are initiated with a WRITE command, as shown in Figure 19 on page 33.
The starting column and bank addresses are provided with the WRITE command, and
auto precharge is either enabled or disabled for that access. If auto precharge is enabled,
the row being accessed is precharged at the completion of the burst. For the generic
WRITE commands used in the following illustrations, auto precharge is disabled.
During WRITE bursts, the first valid data-in element will be registered coincident with
the WRITE command. Subsequent data elements will be registered on each successive
positive clock edge. Upon completion of a fixed-length burst, assuming no other
commands have been initiated, the DQs will remain High-Z, and any additional input
data will be ignored (see Figure 20 on page 33). A full-page burst will continue until
terminated. (At the end of the page, it will wrap to the start address and continue.)
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Operations
Figure 19:
WRITE Command
CLK
CKE
HIGH
CS#
RAS#
CAS#
WE#
A0–A9, A11: x4
A0–A9: x8
A0–A8: x16
COLUMN
ADDRESS
A12: x4
A11, A12: x8
A9, A11, A12: x16
ENABLE AUTO PRECHARGE
A10
DISABLE AUTO PRECHARGE
BANK
ADDRESS
BA0, BA1
Figure 20:
WRITE Burst
T0
T1
T2
T3
COMMAND
WRITE
NOP
NOP
NOP
ADDRESS
BANK,
COL n
CLK
DQ
DIN
n
DIN
n+1
TRANSITIONING DATA
Note:
DON’T CARE
BL = 2. DQM is LOW.
Data for any WRITE burst may be truncated with a subsequent WRITE command, and
data for a fixed-length WRITE burst may be immediately followed by data for a WRITE
command. The new WRITE command can be issued on any clock following the previous
WRITE command, and the data provided coincident with the new command applies to
the new command. An example is shown in Figure 21 on page 34. Data n + 1 is either the
last of a burst of two or the last desired of a longer burst. The 256Mb SDRAM uses a pipelined architecture and therefore does not require the 2n rule associated with a prefetch
architecture. A WRITE command can be initiated on any clock cycle following a previous
WRITE command. Full-speed random write accesses within a page can be performed to
the same bank, as shown in Figure 22 on page 34, or each subsequent WRITE may be
performed to a different bank.
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Operations
Data for any WRITE burst may be truncated with a subsequent READ command, and
data for a fixed-length WRITE burst may be immediately followed by a READ command.
After the READ command is registered, the data inputs will be ignored, and WRITEs will
not be executed. An example is shown in Figure 23. Data n + 1 is either the last of a burst
of two or the last desired of a longer burst.
Figure 21:
WRITE-to-WRITE
T0
T1
T2
COMMAND
WRITE
NOP
WRITE
ADDRESS
BANK,
COL n
CLK
DIN
n
DQ
Note:
Figure 22:
BANK,
COL b
DIN
n+1
DIN
b
DQM is LOW. Each WRITE command may be to any bank.
Random WRITE Cycles
T0
T1
T2
T3
COMMAND
WRITE
WRITE
WRITE
WRITE
ADDRESS
BANK,
COL n
BANK,
COL a
BANK,
COL x
BANK,
COL m
DIN
n
DIN
a
DIN
x
DIN
m
T0
T1
T2
T3
T4
T5
COMMAND
WRITE
NOP
READ
NOP
NOP
NOP
ADDRESS
BANK,
COL n
DOUT
b
DOUT
b+1
CLK
DQ
Figure 23:
WRITE-to-READ
CLK
DQ
DIN
n
BANK,
COL b
DIN
n+1
TRANSITIONING DATA
DON’T CARE
Data for a fixed-length WRITE burst may be followed by, or truncated with, a
PRECHARGE command to the same bank (provided that auto precharge was not activated), and a full-page WRITE burst may be truncated with a PRECHARGE command to
the same bank. The PRECHARGE command should be issued tWR after the clock edge at
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Operations
which the last desired input data element is registered. The auto precharge mode
requires a tWR of at least one clock plus time, regardless of frequency. In addition, when
truncating a WRITE burst, the DQM signal must be used to mask input data for the clock
edge prior to, and the clock edge coincident with, the PRECHARGE command. An
example is shown in Figure 24. Data n + 1 is either the last of a burst of two or the last
desired of a longer burst. Following the PRECHARGE command, a subsequent
command to the same bank cannot be issued until tRP is met. The PRECHARGE is issued
coincident with the second clock (see Figure 24).
In the case of a fixed-length burst being executed to completion, a PRECHARGE
command issued at the optimum time (as described above) provides the same operation
that would result from the same fixed-length burst with auto precharge. The disadvantage of the PRECHARGE command is that it requires that the command and address
buses be available at the appropriate time to issue the command; the advantage of the
PRECHARGE command is that it can be used to truncate fixed-length or full-page bursts.
Fixed-length or full-page WRITE bursts can be truncated with the BURST TERMINATE
command. When truncating a WRITE burst, the input data applied coincident with the
BURST TERMINATE command will be ignored. The last data written (provided that
DQM is LOW at that time) will be the input data applied one clock previous to the
BURST TERMINATE command. This is shown in Figure 9 on page 24, where data n is the
last desired data element of a longer burst.
Figure 24:
WRITE-to-PRECHARGE
T0
T1
T2
T3
T4
T5
T6
NOP
ACTIVE
NOP
CLK
tWR @ tCLK ≥ 15ns
DQM
t RP
COMMAND
ADDRESS
WRITE
NOP
NOP
PRECHARGE
BANK
(a or all)
BANK a,
COL n
BANK a,
ROW
t WR
DQ
DIN
n
DIN
n+1
tWR = tCLK < 15ns
DQM
t RP
COMMAND
ADDRESS
WRITE
NOP
NOP
PRECHARGE
NOP
BANK
(a or all)
BANK a,
COL n
NOP
ACTIVE
BANK a,
ROW
t WR
DQ
DIN
n
DIN
n+1
TRANSITIONING DATA
Note:
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DON’T CARE
DQM could remain LOW in this example if the WRITE burst is a fixed length of two.
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Operations
PRECHARGE
The PRECHARGE command (see Figure 25 on page 36) is used to deactivate the open
row in a particular bank or the open row in all banks. The bank(s) will be available for a
subsequent row access some specified time (tRP) after the PRECHARGE command is
issued. Input A10 determines whether one or all banks are to be precharged, and in the
case where only one bank is to be precharged, inputs BA0, BA1 select the bank. When all
banks are to be precharged, inputs BA0, BA1 are treated as “Don’t Care.” After a bank has
been precharged, it is in the idle state and must be activated prior to any READ or WRITE
commands being issued to that bank.
Power-Down
Power-down occurs if CKE is registered LOW coincident with a NOP or COMMAND
INHIBIT when no accesses are in progress. If power-down occurs when all banks are
idle, this mode is referred to as precharge power-down; if power-down occurs when
there is a row active in any bank, this mode is referred to as active power-down. Entering
power-down deactivates the input and output buffers, excluding CKE, for maximum
power savings while in standby. The device may not remain in the power-down state
longer than the refresh period (64ms) since no REFRESH operations are performed in
this mode.
The power-down state is exited by registering a NOP or COMMAND INHIBIT and CKE
HIGH at the desired clock edge (meeting tCKS). See Figure 26 on page 37.
Figure 25:
PRECHARGE Command
CLK
CKE
HIGH
CS#
RAS#
CAS#
WE#
A0-A9, A11, A12
All Banks
A10
Bank Selected
BA0, BA1
BANK
ADDRESS
DON’T CARE
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Operations
Figure 26:
Power-Down
((
))
((
))
CLK
tCKS
CKE
> tCKS
((
))
COMMAND
((
))
((
))
NOP
NOP
tRCD
tRAS
All banks idle
Input buffers gated off
Enter power-down mode.
ACTIVE
Exit power-down mode.
tRC
DON’T CARE
Clock Suspend
The clock suspend mode occurs when a column access/burst is in progress and CKE is
registered LOW. In the clock suspend mode, the internal clock is deactivated, “freezing”
the synchronous logic.
For each positive clock edge on which CKE is sampled LOW, the next internal positive
clock edge is suspended. Any command or data present on the input pins at the time of a
suspended internal clock edge is ignored; any data present on the DQ pins remains
driven; and burst counters are not incremented, as long as the clock is suspended. (See
examples in Figure 27 and Figure 28 on page 38.)
Clock suspend mode is exited by registering CKE HIGH; the internal clock and related
operation will resume on the subsequent positive clock edge.
Figure 27:
Clock Suspend During WRITE Burst
T0
T1
NOP
WRITE
T2
T3
T4
T5
NOP
NOP
DIN
n+1
DIN
n+2
CLK
CKE
INTERNAL
CLOCK
COMMAND
ADDRESS
DIN
BANK,
COL n
DIN
n
TRANSITIONING DATA
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37
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Operations
Figure 28:
Clock Suspend During READ Burst
T0
T1
T2
T3
T4
T5
T6
CLK
CKE
INTERNAL
CLOCK
COMMAND
READ
ADDRESS
BANK,
COL n
DQ
NOP
NOP
DOUT
n
NOP
DOUT
n+1
TRANSITIONING DATA
Note:
NOP
NOP
DOUT
n+2
DOUT
n+3
DON’T CARE
For this example, CL = 2, BL = 4 or greater, and DQM is LOW.
Burst Read/Single Write Mode
The burst read/single write mode is entered by programming the WRITE burst mode bit
(M9) in the mode register to a logic 1. In this mode, all WRITE commands result in the
access of a single column location (burst of one), regardless of the programmed BL.
READ commands access columns according to the programmed BL and sequence, just
as in the normal mode of operation (M9 = 0).
Concurrent Auto Precharge
An access command (READ or WRITE) to another bank while an access command with
auto precharge enabled is executing is not allowed by SDRAMs, unless the SDRAM
supports concurrent auto precharge. Micron SDRAMs support concurrent auto
precharge. Four cases where concurrent auto precharge occurs are defined below.
READ with Auto Precharge
• Interrupted by a READ (with or without auto precharge): A READ to bank m will interrupt a READ on bank n, CL later. The precharge to bank n will begin when the READ
to bank m is registered (Figure 29 on page 39).
• Interrupted by a WRITE (with or without auto precharge): A WRITE to bank m will
interrupt a READ on bank n when registered. DQM should be used two clocks prior to
the WRITE command to prevent bus contention. The precharge to bank n will begin
when the WRITE to bank m is registered (Figure 30 on page 39).
WRITE with Auto Precharge
• Interrupted by a READ (with or without auto precharge): A READ to bank m will interrupt a WRITE on bank n when registered, with the data-out appearing CL later. The
precharge to bank n will begin after tWR is met, where tWR begins when the READ to
bank m is registered. The last valid WRITE to bank n will be data-in registered one
clock prior to the READ to bank m (Figure 31 on page 40).
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Operations
• Interrupted by a WRITE (with or without auto precharge): A WRITE to bank m will
interrupt a WRITE on bank n when registered. The precharge to bank n will begin
after tWR is met, where tWR begins when the WRITE to bank m is registered. The last
valid data WRITE to bank n will be data registered one clock prior to a WRITE to
bank m (Figure 32 on page 40).
Figure 29:
READ With Auto Precharge Interrupted by a READ
T0
T1
T2
T3
T4
T5
T6
T7
CLK
COMMAND
BANK n
Internal
States
NOP
READ - AP
BANK n
Page Active
READ - AP
BANK m
NOP
READ with Burst of 4
NOP
NOP
NOP
Idle
Interrupt Burst, Precharge
tRP - BANK m
t RP - BANK n
Page Active
BANK m
Precharge
READ with Burst of 4
BANK n,
COL a
ADDRESS
NOP
BANK m,
COL d
DOUT
a+1
DOUT
a
DQ
DOUT
d
DOUT
d+1
CL = 3 (BANK n)
CL = 3 (BANK m)
TRANSITIONING DATA
Notes:
Figure 30:
DON’T CARE
1. DQM is LOW.
READ With Auto Precharge Interrupted by a WRITE
T0
T1
T2
T3
T4
T5
T6
T7
CLK
COMMAND
BANK n
Internal
States
READ - AP
BANK n
Page
Active
NOP
NOP
NOP
READ with Burst of 4
WRITE - AP
BANK m
NOP
NOP
Interrupt Burst, Precharge
Idle
tRP - BANK n
Page Active
BANK m
ADDRESS
NOP
Write-Back
WRITE with Burst of 4
BANK n,
COL a
t WR - BANK m
BANK m,
COL d
1
DQM
DOUT
a
DQ
CL = 3 (BANK n)
Notes:
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DIN
d
DIN
d+1
DIN
d+2
TRANSITIONING DATA
DIN
d+3
DON’T CARE
1. DQM is HIGH at T2 to prevent DOUT - a + 1 from contending with DIN - d at T4.
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Operations
Figure 31:
WRITE With Auto Precharge Interrupted by a READ
T0
T1
T2
T3
T4
T5
T6
T7
CLK
COMMAND
BANK n
Internal
States
NOP
WRITE - AP
BANK n
Page Active
READ - AP
BANK m
NOP
WRITE with Burst of 4
NOP
NOP
Interrupt Burst, Write-Back
Page Active
DIN
a
DQ
Precharge
tRP - BANK m
READ with Burst of 4
BANK n,
COL a
ADDRESS
NOP
tRP - BANK n
tWR - BANK n
BANK m
NOP
BANK m,
COL d
DOUT
d+1
DOUT
d
DIN
a+1
CL = 3 (BANK m)
TRANSITIONING DATA
Notes:
Figure 32:
DON’T CARE
1. DQM is LOW.
WRITE With Auto Precharge Interrupted by a WRITE
T0
T1
T2
T3
T4
T5
T6
T7
CLK
COMMAND
BANK n
Internal
States
NOP
WRITE - AP
BANK n
Page Active
NOP
NOP
WRITE with Burst of 4
WRITE - AP
BANK m
NOP
NOP
Interrupt Burst, Write-Back Precharge
tRP - BANK n
tWR - BANK n
BANK m
ADDRESS
DQ
Page Active
t WR - BANK m
Write-Back
WRITE with Burst of 4
BANK n,
COL a
DIN
a
BANK m,
COL d
DIN
a+1
DIN
a+2
DIN
d
DIN
d+1
DIN
d+2
TRANSITIONING DATA
Notes:
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256MSDRAM_2.fm - Rev. L 10/07 EN
NOP
DIN
d+3
DON’T CARE
1. DQM is LOW.
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Operations
Table 9:
Truth Table 2 – CKE
Notes 1–4 apply to the entire table
CKEn - 1
CKEn
Current State
Commandn
Actionn
Notes
L
L
L
H
L
Maintain power-down
Maintain self refresh
Maintain clock suspend
Exit power-down
Exit self refresh
Exit clock suspend
Power-down entry
Self refresh entry
Clock suspend entry
H
H
X
X
X
COMMAND INHIBIT or NOP
COMMAND INHIBIT or NOP
X
COMMAND INHIBIT or NOP
AUTO REFRESH
WRITE or NOP
See Table 10 on page 42
5
6
7
H
Power-down
Self refresh
Clock suspend
Power-down
Self refresh
Clock suspend
All banks idle
All banks idle
Reading or writing
Notes:
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1. CKEn is the logic state of CKE at clock edge n; CKEn - 1 was the state of CKE at the previous
clock edge.
2. Current state is the state of the SDRAM immediately prior to clock edge n.
3. Commandn is the command registered at clock edge n, and Actionn is a result of
Commandn.
4. All states and sequences not shown are illegal or reserved.
5. Exiting power-down at clock edge n will put the device in the all banks idle state in time for
clock edge n + 1 (provided that tCKS is met).
6. Exiting self refresh at clock edge n will put the device in the all banks idle state after tXSR is
met. COMMAND INHIBIT or NOP commands should be issued on any clock edges occurring
during the tXSR period. A minimum of two NOP commands must be provided during tXSR
period.
7. After exiting clock suspend at clock edge n, the device will resume operation and recognize
the next command at clock edge n + 1.
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Operations
Table 10:
Truth Table 3 – Current State Bank n, Command to Bank n
Notes 1–6 apply to the entire table; notes appear below and on page 43
Current
State
Any
Idle
Row active
Read
(auto
precharge
disabled)
Write
(auto
precharge
disabled)
CS#
RAS#
CAS#
WE#
H
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
X
H
L
L
L
L
H
H
L
H
H
L
H
H
H
L
H
X
H
H
L
L
H
L
L
H
L
L
H
H
L
L
H
H
X
H
H
H
L
L
H
L
L
H
L
L
L
H
L
L
L
Notes:
Command (Action)
COMMAND INHIBIT (NOP/continue previous operation)
NO OPERATION (NOP/continue previous operation)
ACTIVE (Select and activate row)
AUTO REFRESH
LOAD MODE REGISTER
PRECHARGE
READ (Select column and start READ burst)
WRITE (Select column and start WRITE burst)
PRECHARGE (Deactivate row in bank or banks)
READ (Select column and start new READ burst)
WRITE (Select column and start WRITE burst)
PRECHARGE (Truncate READ burst, start PRECHARGE)
BURST TERMINATE
READ (Select column and start READ burst)
WRITE (Select column and start new WRITE burst)
PRECHARGE (Truncate WRITE burst, start PRECHARGE)
BURST TERMINATE
Notes
7
7
11
10
10
8
10
10
8
9
10
10
8
9
1. This table applies when CKEn-1 was HIGH and CKEn is HIGH (see Table 9 on page 41) and
after tXSR has been met (if the previous state was self refresh).
2. This table is bank-specific, except where noted, that is, the current state is for a specific
bank, and the commands shown are those allowed to be issued to that bank when in that
state. Exceptions are covered in the notes below.
3. Current state definitions:
Idle: The bank has been precharged, and tRP has been met.
Row active: A row in the bank has been activated, and tRCD has been met. No data
bursts/accesses and no register accesses are in progress.
Read: A READ burst has been initiated, with auto precharge disabled, and has
not yet terminated or been terminated.
Write: A WRITE burst has been initiated, with auto precharge disabled, and has
not yet terminated or been terminated.
4. The following states must not be interrupted by a command issued to the same bank. COMMAND INHIBIT or NOP commands or allowable commands to the other bank should be
issued on any clock edge occurring during these states. Allowable commands to the other
bank are determined by its current state and Table 10 and according to Table 11 on
page 44.
Precharging: Starts with registration of a PRECHARGE command and ends when
tRP is met. After tRP is met, the bank will be in the idle state.
Row activating: Starts with registration of an ACTIVE command and ends when tRCD
is met. After tRCD is met, the bank will be in the row active state.
Read w/auto Starts with registration of a READ command with auto precharge
precharge enabled: enabled and ends when tRP has been met. After tRP is met, the bank
will be in the idle state.
Write w/auto Starts with registration of a WRITE command with auto precharge
precharge enabled: enabled and ends when tRP has been met. After tRP is met, the bank
will be in the idle state.
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Operations
5. The following states must not be interrupted by any executable command; COMMAND
INHIBIT or NOP commands must be applied on each positive clock edge during these states.
6.
7.
8.
9.
10.
11.
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Refreshing: Starts with registration of an AUTO REFRESH command and ends when
t
RC is met. After tRC is met, the SDRAM will be in the all banks idle state.
Accessing mode Starts with registration of a LOAD MODE REGISTER command and ends
register: when tMRD has been met. After tMRD is met, the SDRAM will be in the all
banks idle state.
Precharging all: Starts with registration of a PRECHARGE ALL command and ends when
t
RP is met. After tRP is met, all banks will be in the idle state.
All states and sequences not shown are illegal or reserved.
Not bank-specific; requires that all banks are idle.
May or may not be bank-specific; if all banks are to be precharged, all must be in a valid
state for precharging.
Not bank-specific; BURST TERMINATE affects the most recent READ or WRITE burst, regardless of bank.
READs or WRITEs listed in the Command (Action) column include READs or WRITEs with
auto precharge enabled and READs or WRITEs with auto precharge disabled.
Does not affect the state of the bank and acts as a NOP to that bank.
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Operations
Table 11:
Truth Table 4 – Current State Bank n, Command to Bank m
Notes 1–6 apply to the entire table; notes appear below and on page 45
Current
State
Any
Idle
Row
activating,
active, or
precharging
Read
(auto
precharge
disabled)
Write
(auto
precharge
disabled)
Read
(with auto
precharge)
Write
(with auto
precharge)
CS#
RAS#
CAS#
WE#
H
L
X
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
X
H
X
L
H
H
L
L
H
H
L
L
H
H
L
L
H
H
L
L
H
H
L
X
H
X
H
L
L
H
H
L
L
H
H
L
L
H
H
L
L
H
H
L
L
H
X
H
X
H
H
L
L
H
H
L
L
H
H
L
L
H
H
L
L
H
H
L
L
Notes:
Command (Action)
COMMAND INHIBIT (NOP/continue previous operation)
NO OPERATION (NOP/continue previous operation)
Any command otherwise allowed to bank m
ACTIVE (Select and activate row)
READ (Select column and start READ burst)
WRITE (Select column and start WRITE burst)
PRECHARGE
ACTIVE (Select and activate row)
READ (Select column and start new READ burst)
WRITE (Select column and start WRITE burst)
PRECHARGE
ACTIVE (Select and activate row)
READ (Select column and start READ burst)
WRITE (Select column and start new WRITE burst)
PRECHARGE
ACTIVE (Select and activate row)
READ (Select column and start new READ burst)
WRITE (Select column and start WRITE burst)
PRECHARGE
ACTIVE (Select and activate row)
READ (Select column and start READ burst)
WRITE (Select column and start new WRITE burst)
PRECHARGE
Notes
7
7
7, 10
7, 11
9
7, 12
7, 13
9
7, 8, 14
7, 8, 15
9
7, 8, 16
7, 8, 17
9
1. This table applies when CKEn - 1 was HIGH and CKEn is HIGH (see Table 9 on page 41) and
after tXSR has been met (if the previous state was self refresh).
2. This table describes alternate bank operation, except where noted; that is, the current state
is for bank n and the commands shown are those allowed to be issued to bank m (assuming
that bank m is in such a state that the given command is allowable). Exceptions are covered
in the notes below.
3. Current state definitions:
Idle: The bank has been precharged, and tRP has been met.
Row active: A row in the bank has been activated, and tRCD has been met. No
data bursts/accesses and no register accesses are in progress.
Read: A READ burst has been initiated, with auto precharge disabled, and
has not yet terminated or been terminated.
Write: A WRITE burst has been initiated, with auto precharge disabled, and
has not yet terminated or been terminated.
Read w/auto Starts with registration of a READ command with auto precharge
precharge enabled: enabled, and ends when tRP has been met. After tRP is met, the
bank will be in the idle state.
Write w/auto Starts with registration of a WRITE command with auto precharge
precharge enabled: enabled, and ends when tRP has been met. After tRP is met, the
bank will be in the idle state.
4. AUTO REFRESH, SELF REFRESH, and LOAD MODE REGISTER commands may only be issued
when all banks are idle.
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Operations
5. A BURST TERMINATE command cannot be issued to another bank; it applies to the bank
represented by the current state only.
6. All states and sequences not shown are illegal or reserved.
7. READs or WRITEs to bank m listed in the Command (Action) column include READs or
WRITEs with auto precharge enabled and READs or WRITEs with auto precharge disabled.
8. CONCURRENT AUTO PRECHARGE: bank n will initiate the AUTO PRECHARGE command
when its burst has been interrupted by bank m’s burst.
9. Burst in bank n continues as initiated.
10. For a READ without auto precharge interrupted by a READ (with or without auto precharge), the READ to bank m will interrupt the READ on bank n, CL later (see Figure 13 on
page 28).
11. For a READ without auto precharge interrupted by a WRITE (with or without auto precharge), the WRITE to bank m will interrupt the READ on bank n when registered (see
Figures 15 and 16 on page 30). DQM should be used one clock prior to the WRITE command
to prevent bus contention.
12. For a WRITE without auto precharge interrupted by a READ (with or without auto precharge), the READ to bank m will interrupt the WRITE on bank n when registered (see
Figure 23 on page 34), with the data-out appearing CL later. The last valid WRITE to bank n
will be data-in registered one clock prior to the READ to bank m.
13. For a WRITE without auto precharge interrupted by a WRITE (with or without auto precharge), the WRITE to bank m will interrupt the WRITE on bank n when registered (see
Figure 21 on page 34). The last valid WRITE to bank n will be data-in registered one clock
prior to the READ to bank m.
14. For a READ with auto precharge interrupted by a READ (with or without auto precharge),
the READ to bank m will interrupt the READ on bank n, CL later. The precharge to bank n
will begin when the READ to bank m is registered (see Figure 29 on page 39).
15. For a READ with auto precharge interrupted by a WRITE (with or without auto precharge),
the WRITE to bank m will interrupt the READ on bank n when registered. DQM should be
used two clocks prior to the WRITE command to prevent bus contention. The precharge to
bank n will begin when the WRITE to bank m is registered (see Figure 30 on page 39).
16. For a WRITE with auto precharge interrupted by a READ (with or without auto precharge),
the READ to bank m will interrupt the WRITE on bank n when registered, with the data-out
appearing CL later. The precharge to bank n will begin after tWR is met, where tWR begins
when the READ to bank m is registered. The last valid WRITE to bank n will be data-in registered one clock prior to the READ to bank m (see Figure 31 on page 40).
17. For a WRITE with auto precharge interrupted by a WRITE (with or without auto precharge),
the WRITE to bank m will interrupt the WRITE on bank n when registered. The precharge to
bank n will begin after tWR is met, where tWR begins when the WRITE to bank m is registered. The last valid WRITE to bank n will be data registered one clock prior to the WRITE to
bank m (see Figure 32 on page 40).
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Electrical Specifications
Electrical Specifications
Stresses greater than those listed in Table 12 may cause permanent damage to the
device. This is a stress rating only, and functional operation of the device at these or any
other conditions above those indicated in the operational sections of this specification is
not implied. Exposure to absolute maximum rating conditions for extended periods may
affect reliability.
Table 12:
Absolute Maximum Ratings
Parameter
Voltage on VDD; VDDQ supply relative to VSS
Voltage on inputs, NC, or I/O pins relative to VSS
Operating temperature
TA (commercial)
TA (industrial “IT”)
Storage temperature (plastic)
Power dissipation
Min
Max
Units
–1
–1
+4.6
+4.6
V
V
0
–40
–55
–
+70
+85
+150
1
°C
°C
°C
W
Temperature and Thermal Impedance
It is imperative that the SDRAM device’s temperature specifications, shown in Table 13
on page 47, be maintained to ensure the junction temperature is in the proper operating
range to meet data sheet specifications. An important step in maintaining the proper
junction temperature is using the device’s thermal impedances correctly. The thermal
impedances are listed in Table 14 on page 47 for the applicable die revision and packages being made available. These thermal impedance values vary according to the
density, package, and particular design used for each device.
Incorrectly using thermal impedances can produce significant errors. Read Micron technical note TN-00-08, “Thermal Applications” prior to using the thermal impedances
listed in Table 14. To ensure the compatibility of current and future designs, contact
Micron Applications Engineering to confirm thermal impedance values.
The SDRAM device’s safe junction temperature range can be maintained when the TC
specification is not exceeded. In applications where the device’s ambient temperature is
too high, use of forced air and/or heat sinks may be required to satisfy the case temperature specifications.
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Electrical Specifications
Table 13:
Temperature Limits
Parameter
Symbol
Table 14:
0
-40
80
90
0
-40
85
95
0
-40
–
70
85
260
TJ
TA
TPEAK
Units
Notes
°C
1, 2, 3, 4
°C
3
°C
3, 5
°C
1. MAX operating case temperature, TC, is measured in the center of the package on the top
side of the device, as shown in Figure 33, Figure 34, and Figure 35 on page 48.
2. Device functionality is not guaranteed if the device exceeds maximum TC during operation.
3. Both temperature specifications must be satisfied.
4. The case temperature should be measured by gluing a thermocouple to the top center of
the component. This should be done with a 1mm bead of conductive epoxy, as defined by
the JEDEC EIA/JESD51 standards. Care should be taken to ensure the thermocouple bead is
touching the case.
5. Operating ambient temperature surrounding the package.
Thermal Impedance Simulated Values
Die Revision
D
Max
TC
Operating case temperature:
Commercial
Industrial
Junction temperature:
Commercial
Industrial
Ambient temperature:
Commercial
Industrial
Peak reflow temperature
Notes:
Min
Package
Substrate
θ JA (°C/W)
Airflow =
0m/s
54-pin
TSOP
2-layer
4-layer
2-layer
4-layer
2-layer
4-layer
81
44
64.9
51.5
67
40.9
54-ball
VFBGA
60-ball
FBGA
Notes:
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256MSDRAM_2.fm - Rev. L 10/07 EN
θ JA (°C/W)
Airflow =
1m/s
θ JA (°C/W)
Airflow =
2m/s
θ JB (°C/W)
θ JC (°C/W)
63.8
47.3
50.8
41.6
51.2
35.1
57.6
44.5
44.8
38.1
47.8
32.2
45.3
39.1
31.4
31.4
19.7
18.6
10.3
3.2
6.7
1. For designs expected to last beyond the die revision listed, contact Micron Applications
Engineering to confirm thermal impedance values.
2. Thermal resistance data is sampled from multiple lots, and the values should be viewed as
typical.
3. These are estimates; actual results may vary.
47
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Electrical Specifications
Figure 33:
Example Temperature Test Point Location, 54-Pin TSOP: Top View
22.22mm
11.11mm
Test point
10.16mm
5.08mm
Figure 34:
Example Temperature Test Point Location, 54-Ball VFBGA: Top View
8.00mm
4.00mm
Test point
14.00mm
7.00mm
Figure 35:
Example Temperature Test Point Location, 60-Ball FBGA: Top View
8.00mm
4.00mm
Test point
16.00mm
8.00mm
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Electrical Specifications
Table 15:
DC Electrical Characteristics and Operating Conditions
Notes 1, 5, 6 apply to the entire table; notes appear on page 54; VDD, VDDQ = +3.3V ±0.3V
Parameter/Condition
Supply voltage
Input high voltage: Logic 1; All inputs
Input low voltage: Logic 0; All inputs
Input leakage current: Any input 0V ≤ Vin ≤ VDD
(All other pins not under test = 0V)
Output leakage current: DQs are disabled;
0V ≤ Vout ≤ VDDQ
Output levels:
Output high voltage (IOUT = –4mA)
Output low voltage (IOUT = 4mA)
Table 16:
Symbol
Min
Max
Units
Notes
VDD, VDDQ
VIH
VIL
II
3
2
–0.3
–5
3.6
VDD + 0.3
0.8
5
V
V
V
µA
22
22
IOZ
–5
5
µA
VOH
VOL
2.4
–
–
0.4
V
V
IDD Specifications and Conditions (-6A)
Notes 1, 5, 6, 11, 13 apply to the entire table; notes appear on page 54; VDD/VDDQ = +3.3V ±0.3V
Parameter/Condition
tRC
tRC
Operating current: Active mode; Burst = 2; READ or WRITE;
=
(MIN)
Standby current: Power-down mode; All device banks idle; CKE = LOW
Standby current: Active mode; CKE = HIGH; CS# = HIGH; All device banks
active after tRCD met; No accesses in progress
Operating current: Burst mode; Continuous burst; READ or WRITE; All
device banks active
tRFC = tRFC (MIN)
Auto refresh current:
CS# = HIGH; CKE = HIGH
tRFC = 8.125µs
Self refresh current: CKE ≤ 0.2V
Table 17:
Symbol
-6A
Units
Notes
IDD1
135
mA
3, 18, 19, 29
IDD2
IDD3
2
40
mA
mA
30
3, 12, 19, 29
IDD4
135
mA
3, 18, 19, 29
IDD5
285
mA
IDD6
3.5
mA
3, 12, 18,
19, 29, 30
IDD7
2.5
mA
4
IDD Specifications and Conditions (-7E, -75)
Notes 1, 5, 6, 11, 13 apply to the entire table; notes appear on page 54; VDD, VDDQ = +3.3V ±0.3V
Max
Parameter/Condition
Operating current: Active mode;
Burst = 2; Read or write; tRC = tRC (MIN)
Standby current: Power-down mode;
All banks idle; CKE = LOW
Standby current: Active mode;
CKE = HIGH; CS# = HIGH; All banks active after tRCD met; No
accesses in progress
Operating current: Burst mode;
Page burst; Read or write; All banks active
tRFC = tRFC (MIN)
Auto refresh current:
tRFC = 7.81µs
CS# = HIGH; CKE = HIGH
Self refresh current: CKE ≤ 0.2V
Standard
Low power (L)
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256MSDRAM_2.fm - Rev. L 10/07 EN
49
Symbol
-7E
-75
Units
Notes
IDD1
135
125
mA
IDD2
2
2
mA
3, 18, 19,
32
32
IDD3
40
40
mA
3, 12, 19,
32
IDD4
135
135
mA
IDD5
IDD6
IDD7
IDD7
285
3.5
2.5
1.5
270
3.5
2.5
1.5
mA
mA
mA
mA
3, 18, 19,
32
3, 12, 18,
19, 32, 33
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Electrical Specifications
Table 18:
Capacitance
Note 2 applies to the entire table; notes appear on page 54
Parameter – TSOP “TG” Package
Input capacitance: CLK
Input capacitance: All other input-only pins
Input/output capacitance: DQs
Symbol
Min
Max
Units
Notes
CI1
CI2
CIO
2.5
2.5
4.0
3.5
3.8
6.0
pF
pF
pF
29
30
31
CI1
CI2
CIO
1.5
1.5
3.0
3.5
3.8
6.0
pF
pF
pF
34
35
36
Parameter – FBGA “FB” and “FG” Package
Input capacitance: CLK
Input capacitance: All other input-only pins
Input/output capacitance: DQs
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Electrical Specifications
Table 19:
Electrical Characteristics and Recommended AC Operating Conditions (-6A)
Notes 5, 6, 8, 9, 11, 31 apply to the entire table; notes appear on page 54
-6A
Parameter
Symbol
Min
Max
Units
Notes
AC(3)
–
5.4
ns
27
Address hold time
tAH
0.8
–
ns
Address setup time
t
1.5
–
ns
CLK high-level width
t
CH
2.5
–
ns
CLK low-level width
t
CL
2.5
–
ns
CK(3)
6
–
ns
CKE hold time
tCKH
0.8
–
ns
CKE setup time
tCKS
1.5
–
ns
CS#, RAS#, CAS#, WE#, DQM hold time
tCMH
0.8
–
ns
CS#, RAS#, CAS#, WE#, DQM setup time
tCMS
1.5
1.5
ns
Data-in hold time
tDH
0.8
–
ns
Data-in setup time
tDS
1.5
–
ns
tHZ(3)
–
5.4
ns
tLZ
1
–
ns
tOH
3
–
ns
Data-out hold time (no load)
tOHN
1.8
–
ns
ACTIVE to PRECHARGE command
tRAS
42
120,000
ns
tRC
60
–
ns
ACTIVE to READ or WRITE delay
tRCD
18
–
ns
Refresh period
tREF
–
64
ms
AUTO REFRESH period
tRFC
60
–
ns
tRP
18
–
ns
tRRD
Access time from CLK (positive edge)
CL = 3
t
AS
CL = 3
Clock cycle time
Data-out high-impedance time
t
CL = 3
Data-out low-impedance time
Data-out hold time (load)
ACTIVE to ACTIVE command period
PRECHARGE command period
ACTIVE bank a to ACTIVE bank b command
Transition time
WRITE recovery time1
t
Exit SELF REFRESH to ACTIVE command
t
12
–
ns
tT
0.3
1.2
ns
WR
1 CLK + 6ns
12
67
–
–
–
ns
ns
ns
XSR
23
10
28
7
25
20
Notes: 1. Auto precharge mode only. The precharge timing budget (tRP) begins 6ns for -6A after the
first clock delay, after the last WRITE is executed. May not exceed limit set for precharge
mode.
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Electrical Specifications
Table 20:
Electrical Characteristics and Recommended AC Operating Conditions (-7E, -75)
Notes 5, 6, 8, 9, 11 apply to the entire table; notes appear on page 54
-7E
Parameter
Access time from CLK
(positive edge)
Address hold time
Address setup time
CLK high-level width
CLK low-level width
Clock cycle time
Symbol
CL = 3
CL = 2
CL = 3
CL = 2
CKE hold time
CKE setup time
CS#, RAS#, CAS#, WE#, DQM hold time
CS#, RAS#, CAS#, WE#, DQM setup time
Data-in hold time
Data-in setup time
CL = 3
Data-out High-Z time
CL = 2
Data-out Low-Z time
Data-out hold time (load)
Data-out hold time (no load)
ACTIVE-to-PRECHARGE command
ACTIVE-to-ACTIVE command period
ACTIVE-to-READ or WRITE delay
Refresh period (8,192 rows)
Auto refresh period
PRECHARGE command period
ACTIVE bank a to ACTIVE bank b
command
Transition time
Write recovery time
Exit SELF REFRESH to ACTIVE command
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256MSDRAM_2.fm - Rev. L 10/07 EN
-75
Min
Max
Min
Max
Units
Notes
AC(3)
AC(2)
t
AH
t
AS
t
CH
t
CL
tCK(3)
tCK(2)
t
CKH
tCKS
tCMH
tCMS
tDH
tDS
tHZ(3)
tHZ(2)
tLZ
tOH
tOHN
tRAS
tRC
tRCD
tREF
tRFC
tRP
tRRD
–
–
0.8
1.5
2.5
2.5
7
7.5
0.8
1.5
0.8
1.5
0.8
1.5
–
–
1
3
1.8
37
60
15
–
66
15
14
5.4
5.4
–
–
–
–
–
–
–
–
–
–
–
–
5.4
5.4
–
–
–
120,000
–
–
64
–
–
–
–
–
0.8
1.5
2.5
2.5
7.5
10
0.8
1.5
0.8
1.5
0.8
1.5
–
–
1
3
1.8
44
66
20
5.4
6
–
–
–
–
–
–
–
–
–
–
–
–
5.4
6
–
–
–
120,000
–
–
64
–
–
–
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ms
ns
ns
ns
27
tT
WR
0.3
1 CLK + 7ns
0.3
1 CLK + 7.5ns
7
24
14
67
1.2
–
–
–
–
ns
ns
XSR
1.2
–
–
–
–
ns
ns
25
20
t
t
t
t
52
66
20
15
15
75
23
23
37
10
10
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Electrical Specifications
Table 21:
AC Functional Characteristics (-6A)
Notes 5, 6, 7, 8, 9, 11 apply to the entire table; notes appear on page 54
Parameter
Symbol
-6A
Units
Notes
CCD
1
t
CK
17
tCKED
1
tCK
14
CKE to clock enable or power-down exit setup mode
tPED
1
tCK
14
DQM to input data delay
t
DQD
0
t
CK
17
DQM to data mask during WRITEs
t
DQM
0
t
CK
17
DQM to data high-impedance during READs
t
DQZ
2
t
CK
17
WRITE command to input data delay
tDWD
0
tCK
17
Data-in to ACTIVE command
tDAL
4
tCK
15, 211
Data-in to PRECHARGE command
tDPL
2
tCK
16, 21
Last data-in to burst STOP command
tBDL
1
tCK
17
Last data-in to new READ/WRITE command
tCDL
1
tCK
17
Last data-in to PRECHARGE command
tRDL
2
tCK
16, 21
LOAD MODE REGISTER command to ACTIVE or REFRESH command
tMRD
2
tCK
26
tROH(3)
3
tCK
17
t
READ/WRITE command to READ/WRITE command
CKE to clock disable or power-down entry mode
Data-out to high-impedance from PRECHARGE command
CL = 3
Notes: 1. Note 21 on page 54 does not apply for this speed grade and should read “Based on
tCK = 6ns.”
Table 22:
AC Functional Characteristics (-7E, -75)
Notes 5, 6, 7, 8, 9, 11 apply to the entire table; notes appear on page 54
Parameter
Symbol
READ/WRITE command to READ/WRITE command
CKE to clock disable or power-down entry mode
CKE to clock enable or power-down exit setup mode
DQM to input data delay
DQM to data mask during WRITEs
DQM to data High-Z during READs
WRITE command to input data delay
Data-in to ACTIVE command
Data-in to PRECHARGE command
Last data-in to BURST STOP command
Last data-in to new READ/WRITE command
Last data-in to PRECHARGE command
LOAD MODE REGISTER command to ACTIVE or REFRESH command
Data-out to High-Z from PRECHARGE command
CL = 3
CL = 2
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256MSDRAM_2.fm - Rev. L 10/07 EN
53
tCCD
tCKED
tPED
tDQD
tDQM
t
DQZ
DWD
tDAL
tDPL
tBDL
t
CDL
t
RDL
tMRD
tROH(3)
tROH(2)
t
-7E
1
1
1
0
0
2
0
4
2
1
1
2
2
3
2
-75
Units
Notes
1
1
1
0
0
2
0
5
2
1
1
2
2
3
2
tCK
17
14
14
17
17
17
17
15, 21
16, 21
17
17
16, 21
26
17
17
tCK
tCK
tCK
tCK
t
CK
CK
tCK
tCK
tCK
t
CK
t
CK
tCK
tCK
tCK
t
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Notes
Notes
1. All voltages referenced to VSS.
2. This parameter is sampled. VDD, VDDQ = +3.3V; f = 1 MHz, TA = 25°C; pin under test
biased at 1.4V.
3. IDD is dependent on output loading and cycle rates. Specified values are obtained
with minimum cycle time and the outputs open.
4. Enables on-chip refresh and address counters.
5. The minimum specifications are used only to indicate cycle time at which proper
operation over the full temperature range is ensured; (0°C ≤ TA ≤ +70°C for commercial) and (–40°C ≤ TA ≤ +85°C for IT).
6. An initial pause of 100µs is required after power-up, followed by two AUTO REFRESH
commands, before proper device operation is ensured. (VDD and VDDQ must be powered up simultaneously. VSS and VSSQ must be at same potential.) The two AUTO
REFRESH command wake-ups should be repeated any time the tREF refresh requirement is exceeded.
7. AC characteristics assume tT = 1ns.
8. In addition to meeting the transition rate specification, the clock and CKE must transit between VIH and VIL (or between VIL and VIH) in a monotonic manner.
9. Outputs measured at 1.5V with equivalent load:
Q
50pF
10. tHZ defines the time at which the output achieves the open circuit condition; it is not
a reference to VOH or VOL. The last valid data element will meet tOH before going
High-Z.
11. AC operating and IDD test conditions have VIL = 0V and VIH = 3.0V using a measurement reference level of 1.5V. If the input transition time is longer than 1ns, then the
timing is measured from VIL (MAX) and VIH (MIN) and no longer from the 1.5V midpoint. CLK should always be 1.5V referenced to crossover. Refer to Micron technical
note TN-48-09.
12. Other input signals are allowed to transition no more than once every two clocks and
are otherwise at valid VIH or VIL levels.
13. IDD specifications are tested after the device is properly initialized.
14. Timing actually specified by tCKS; clock(s) specified as a reference only at minimum
cycle rate.
15. Timing actually specified by tWR plus tRP; clock(s) specified as a reference only at
minimum cycle rate.
16. Timing actually specified by tWR.
17. Required clocks are specified by JEDEC functionality and are not dependent on any
timing parameter.
18. The IDD current will increase or decrease proportionally according to the amount of
frequency alteration for the test condition.
19. Address transitions average one transition every two clocks.
20. CLK must be toggled a minimum of two times during this period.
21. Based on tCK = 7.5ns for -75 and -7E.
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Notes
22. VIH overshoot: VIH (MAX) = VDDQ + 2V for a pulse width ≤ 3ns, and the pulse width
cannot be greater than one-third of the cycle rate. VIL undershoot: VIL (MIN) = –2V for
a pulse width ≤ 3ns.
23. The clock frequency must remain constant (stable clock is defined as a signal cycling
within timing constraints specified for the clock pin) during access or precharge
states (READ, WRITE, including tWR, and PRECHARGE commands). CKE may be
used to reduce the data rate.
24. Auto precharge mode only. The precharge timing budget (tRP) begins 7ns for -7E and
7.5ns for -75 after the first clock delay, after the last WRITE is executed.
25. Precharge mode only.
26. JEDEC and PC100 specify three clocks.
27. tAC for -75/-7E at CL = 3 with no load is 4.6ns and is guaranteed by design.
28. Parameter guaranteed by design.
29. PC100 specifies a maximum of 4pF.
30. PC100 specifies a maximum of 5pF.
31. PC100 specifies a maximum of 6.5pF.
32. For -75, CL = 3 and tCK = 7.5ns; for -7E, CL = 2 and tCK = 7.5ns.
33. CKE is HIGH during REFRESH command period tRFC (MIN) else CKE is LOW. The
IDD6 limit is actually a nominal value and does not result in a fail value.
34. PC133 specifies a minimum of 2.5pF.
35. PC133 specifies a minimum of 2.5pF.
36. PC133 specifies a minimum of 3.0pF.
37. For operating frequencies ≤ 45 MHz, tCKS = 3.0ns.
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Timing Diagrams
Timing Diagrams
Figure 36:
Initialize and Load Mode Register
T0
CK
((
))
CKE
((
))
((
))
COMMAND
((
))
((
))
tCK
T1
((
))
((
))
tCKH
tCKS
Tn + 1
To + 1
tCL
((
))
((
))
tCH
((
))
((
))
((
))
((
))
((
))
Tp + 1
Tp + 2
Tp + 3
((
))
tCMS tCMH
NOP
PRECHARGE
((
))
((
))
AUTO
REFRESH
((
))
NOP
NOP
((
))
AUTO
REFRESH
((
))
NOP
NOP
((
))
DQM/
DQML, DQMU
((
))
((
))
((
))
((
))
((
))
((
))
((
))
((
))
A0–A9,
A11, A12
((
))
((
))
((
))
((
))
((
))
((
))
((
))
((
))
A10
((
))
((
))
((
))
((
))
((
))
((
))
((
))
((
))
((
))
((
))
((
))
((
))
((
))
((
))
BA0, BA1
DQ
ALL BANKS
SINGLE BANK
((
))
((
))
ALL
BANKS
High-Z
((
))
T = 100µs
MIN
LOAD MODE
REGISTER
tAS
NOP
tAH 5
ROW
CODE
tAS
ACTIVE
tAH
ROW
CODE
BANK
((
))
tRP
Power-up:
VDD and
CLK stable
Precharge
all banks
tRFC
tRFC
AUTO REFRESH
AUTO REFRESH
tMRD
Program Mode Register 1, 3, 4
DON’T CARE
UNDEFINED
Notes:
PDF: 09005aef8091e6d1/Source: 09005aef8091e6a8
256MSDRAM_2.fm - Rev. L 10/07 EN
1.
2.
3.
4.
5.
The mode register may be loaded prior to the AUTO REFRESH cycles if desired.
If CS is HIGH at clock HIGH time, all commands applied are NOP.
JEDEC and PC100 specify three clocks.
Outputs are guaranteed High-Z after command is issued.
A12 should be a LOW at tP + 1.
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256Mb: x4, x8, x16 SDRAM
Timing Diagrams
Figure 37:
Power-Down Mode
T0
T1
tCK
CLK
T2
tCL
tCKS
tCH
CKE
tCKS
tCKH
tCMS tCMH
COMMAND
PRECHARGE
NOP
NOP
DQM/
DQML, DQMU
A0–A9,
A11, A12
ALL BANKS
A10
SINGLE BANK
tAS
BA0, BA1
Tn + 1
Tn + 2
((
))
((
))
((
))
((
))
((
))
((
))
((
))
((
))
((
))
((
))
((
))
((
))
((
))
((
))
((
))
((
))
((
))
((
))
ROW
((
))
((
))
((
))
((
))
ROW
((
))
((
))
((
))
((
))
BANK
((
))
((
))
tCKS
NOP
ACTIVE
tAH
BANK(S)
High-Z
DQ
Two clock cycles
Input buffers gated off while in
power-down mode
Precharge all
active banks
All banks idle
All banks idle, enter
power-down mode
Exit power-down mode
DON’T CARE
UNDEFINED
Notes:
PDF: 09005aef8091e6d1/Source: 09005aef8091e6a8
256MSDRAM_2.fm - Rev. L 10/07 EN
1. Violating refresh requirements during power-down may result in a loss of data.
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256Mb: x4, x8, x16 SDRAM
Timing Diagrams
Figure 38:
Clock Suspend Mode
T0
T1
T2
tCK
CLK
T3
T4
T5
T6
T7
T8
T9
tCL
tCH
tCKS tCKH
CKE
tCKS
tCKH
tCMS tCMH
COMMAND
READ
NOP
NOP
NOP
NOP
NOP
WRITE
NOP
tCMS tCMH
DQM/
DQML, DQMU
A0–A9,
A11, A12
tAS
tAH
COLUMN m
2
tAS
tAH
tAS
tAH
COLUMN e 2
A10
BA0, BA1
BANK
BANK
tAC
tOH
tAC
DQ
tLZ
DOUT m
tHZ
DOUT m + 1
tDS
tDH
DIN e
DIN + 1
DON’T CARE
UNDEFINED
Notes:
PDF: 09005aef8091e6d1/Source: 09005aef8091e6a8
256MSDRAM_2.fm - Rev. L 10/07 EN
1. For this example, BL = 2, CL = 3, and auto precharge is disabled.
2. x16: A9, A11 and A12 = “Don’t Care”
x8: A11 and A12 = “Don’t Care”
x4: A12 = “Don’t Care”
58
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©1999 Micron Technology, Inc. All rights reserved.
256Mb: x4, x8, x16 SDRAM
Timing Diagrams
Figure 39:
Auto Refresh Mode
T0
CLK
T1
tCK
T2
((
))
((
))
tCH
((
))
((
))
((
))
CKE
COMMAND
tCKS
tCKH
tCMS
tCMH
PRECHARGE
NOP
((
))
( ( NOP
))
AUTO
REFRESH
NOP
A0–A9,
A11, A12
ALL BANKS
A10
SINGLE BANK
tAS
BA0, BA1
AUTO
REFRESH
NOP
ACTIVE
((
))
((
))
((
))
((
))
((
))
((
))
ROW
((
))
((
))
((
))
((
))
ROW
((
))
((
))
High-Z
((
))
((
))
((
))
tRP
tRFC
Precharge all
active banks
PDF: 09005aef8091e6d1/Source: 09005aef8091e6a8
256MSDRAM_2.fm - Rev. L 10/07 EN
((
))
( ( NOP
))
tAH
BANK(S)
Notes:
To + 1
((
))
((
))
((
))
DQM/
DQML, DQMU
DQ
Tn + 1
tCL
BANK
((
))
tRFC
DON’T CARE
1. tRFC must not be interrupted by any executable command; COMMAND INHIBIT or NOP
must be applied on each positive edge during tRFC.
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©1999 Micron Technology, Inc. All rights reserved.
256Mb: x4, x8, x16 SDRAM
Timing Diagrams
Figure 40:
Self Refresh Mode
T0
CLK
T1
tCK
tCL
tCH
T2
tCKS
≥ tRAS(MIN)1
CKE
tCKS
tCKH
tCMS
tCMH
COMMAND
PRECHARGE
Tn + 1
((
))
((
))
AUTO
REFRESH
((
))
((
))
((
) )or COMMAND
NOP ( (
((
))
((
))
((
))
((
))
A0–A9,
A11,A12
((
))
((
))
((
))
((
))
((
))
((
))
((
))
((
))
((
))
((
))
((
))
((
))
ALL BANKS
SINGLE BANK
tAS
BA0, BA1
DQ
High-Z
((
))
AUTO
REFRESH
((
))
tRP
Precharge all
active banks
tXSR2
Enter self refresh mode
Exit self refresh mode
(Restart refresh time base)
CLK stable prior to exiting
self refresh mode
PDF: 09005aef8091e6d1/Source: 09005aef8091e6a8
256MSDRAM_2.fm - Rev. L 10/07 EN
INHIBIT
tAH
BANK(S)
Notes:
To + 2
))
DQM/
DQML, DQMU
A10
To + 1
((
))
((
))
((
))
NOP
((
))
((
))
1.
2.
3.
DON’T CARE
No maximum time limit for self refresh. tRAS (MAX) applies to non-self refresh mode.
requires minimum of two clocks regardless of frequency or timing.
As a general rule, any time self refresh is exited, the DRAM may not reenter the self refresh
mode until all rows have been refreshed by the AUTO REFRESH command at the distributed
refresh rate, tREF, or faster. However, the following exceptions are allowed:
3a. The DRAM has been in self refresh mode for a minimum of 64mS prior to exiting.
3b. tXSR is not violated.
3c. At least two AUTO REFRESH commands are preformed during each 7.81µs interval while
the DRAM remains out of the self refresh mode.
tXSR
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©1999 Micron Technology, Inc. All rights reserved.
256Mb: x4, x8, x16 SDRAM
Timing Diagrams
Figure 41:
Read – Without Auto Precharge
T0
T1
tCK
CLK
T2
T3
T4
T5
T6
T7
T8
NOP
ACTIVE
tCL
tCH
tCKS
tCKH
tCMS
tCMH
CKE
COMMAND
ACTIVE
NOP
READ
tCMS
NOP
NOP
NOP
PRECHARGE
tCMH
DQM/
DQML, DQMU
tAS
A0–A9,
A11, A12
tAS
COLUMN m 2
ROW
tAH
ALL BANKS
ROW
A10
tAS
BA0, BA1
tAH
ROW
ROW
SINGLE BANK
DISABLE AUTO PRECHARGE
tAH
BANK
BANK
BANK
tAC
tOH
tAC
DQ
DOUT m
tLZ
tRCD
tAC
tOH
DOUT m + 1
BANK
tAC
tOH
tOH
DOUT m + 2
DOUT m + 3
tHZ
tRP
CAS Latency
tRAS
tRC
DON’T CARE
UNDEFINED
Notes:
PDF: 09005aef8091e6d1/Source: 09005aef8091e6a8
256MSDRAM_2.fm - Rev. L 10/07 EN
1. For this example, BL = 4, CL = 2, and the READ burst is followed by a “manual” PRECHARGE.
2. x16: A9, A11, and A12 = “Don’t Care”
x8: A11 and A12 = “Don’t Care”
x4: A12 = “Don’t Care”
61
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©1999 Micron Technology, Inc. All rights reserved.
256Mb: x4, x8, x16 SDRAM
Timing Diagrams
Figure 42:
Read – With Auto Precharge
T0
T1
tCK
CLK
tCKS
T2
T3
T4
T5
T6
T7
T8
NOP
ACTIVE
tCL
tCH
tCKH
CKE
tCMS tCMH
COMMAND
ACTIVE
NOP
READ
tCMS
NOP
NOP
NOP
NOP
tCMH
DQM/
DQML, DQMU
tAS
A0–A9,
A11, A12
tAH
ROW
ENABLE AUTO PRECHARGE
ROW
tAS
BA0, BA1
COLUMN m 2
ROW
tAS
A10
tAH
ROW
tAH
BANK
BANK
BANK
tAC
tOH
tAC
DQ
DOUT m
tLZ
tRCD
tAC
tOH
DOUT m + 1
tAC
tOH
DOUT m + 2
tOH
DOUT m + 3
tHZ
tRP
CAS Latency
tRAS
tRC
DON’T CARE
UNDEFINED
Notes:
PDF: 09005aef8091e6d1/Source: 09005aef8091e6a8
256MSDRAM_2.fm - Rev. L 10/07 EN
1. For this example, BL = 4 and CL = 2.
2. x16: A9, A11, and A12 = “Don’t Care”
x8: A11 and A12 = “Don’t Care”
62
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©1999 Micron Technology, Inc. All rights reserved.
256Mb: x4, x8, x16 SDRAM
Timing Diagrams
Figure 43:
Single Read – Without Auto Precharge
T0
T1
tCK
CLK
T2
T3
T4
T5
NOP 2
NOP 2
T6
T7
T8
tCL
tCH
tCKS
tCKH
CKE
tCMS tCMH
COMMAND
ACTIVE
NOP
READ
tCMS
PRECHARGE
NOP
ACTIVE
NOP
tCMH
DQM/
DQML, DQMU
tAS
A0–A9,
A11,A12
tAS
COLUMN m3
ROW
tAH
ALL BANKS
ROW
ROW
A10
tAS
BA0, BA1
tAH
ROW
DISABLE AUTO PRECHARGE
tAH
SINGLE BANKS
BANK
BANK
BANK(S)
tOH
tAC
DQ
tLZ
tRCD
BANK
DOUT m
tHZ
tRP
CAS Latency
tRAS
tRC
DON’T CARE
UNDEFINED
Notes:
PDF: 09005aef8091e6d1/Source: 09005aef8091e6a8
256MSDRAM_2.fm - Rev. L 10/07 EN
1. For this example, BL = 1, CL = 2, and the READ burst is followed by a “manual” PRECHARGE.
2. PRECHARGE command not allowed (would violate tRAS).
3. x16: A9, A11, and A12 = “Don’t Care”
x8: A11 and A12 = “Don’t Care”
x4: A12 = “Don’t Care”
63
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©1999 Micron Technology, Inc. All rights reserved.
256Mb: x4, x8, x16 SDRAM
Timing Diagrams
Figure 44:
Single Read – With Auto Precharge
T0
T1
tCK
CLK
tCKS
T2
T3
T4
T5
T6
T7
T8
tCL
tCH
tCKH
CKE
tCMS tCMH
COMMAND
ACTIVE
NOP
NOP2
NOP2
READ
tCMS
NOP
NOP
ACTIVE
NOP
tCMH
DQM/
DQML, DQMU
tAS
A0–A9, A11
tAH
ROW
ENABLE AUTO PRECHARGE
ROW
tAS
BA0, BA1
COLUMN m3
ROW
tAS
A10
tAH
ROW
tAH
BANK
BANK
BANK
tAC
t OH
DOUT m
DQ
tRCD
CAS Latency
tHZ
tRP
tRAS
tRC
DON’T CARE
UNDEFINED
Notes:
PDF: 09005aef8091e6d1/Source: 09005aef8091e6a8
256MSDRAM_2.fm - Rev. L 10/07 EN
1. For this example, BL = 1 and CL = 2.
2. PRECHARGE command not allowed (would violate tRAS).
3. x16: A9, A11, and A12 = “Don’t Care”
x8: A11 and A12 = “Don’t Care”
x4: A12 = “Don’t Care”
64
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©1999 Micron Technology, Inc. All rights reserved.
256Mb: x4, x8, x16 SDRAM
Timing Diagrams
Figure 45:
Alternating Bank Read Accesses
T0
T1
tCK
CLK
T2
T3
T4
T5
NOP
ACTIVE
T6
T7
T8
READ
NOP
ACTIVE
tCL
tCH
tCKS
tCKH
tCMS
tCMH
CKE
COMMAND
ACTIVE
NOP
READ
tCMS
NOP
tCMH
DQM/
DQML, DQMU
tAS
A0-A9, A11, A12
tAS
A10
COLUMN m 2
tAH
COLUMN b 2
ROW
ENABLE AUTO PRECHARGE
ROW
ENABLE AUTO PRECHARGE
ROW
tAS
BA0, BA1
tAH
ROW
ROW
ROW
tAH
BANK 0
BANK 0
BANK 3
tAC
tOH
tAC
DQ
DOUT m
tLZ
tRCD - BANK 0
BANK 3
tAC
tOH
DOUT m + 1
BANK 0
tAC
tOH
DOUT m + 2
tAC
tOH
DOUT m + 3
tRP - BANK 0
CAS Latency - BANK 0
tAC
tOH
DOUT b
tRCD - BANK 0
tRAS - BANK 0
tRC - BANK 0
tRCD - BANK 3
tRRD
CAS Latency - BANK 3
DON’T CARE
UNDEFINED
Notes:
PDF: 09005aef8091e6d1/Source: 09005aef8091e6a8
256MSDRAM_2.fm - Rev. L 10/07 EN
1. For this example, BL = 4 and CL = 2.
2. x16: A9, A11, and A12 = “Don’t Care”
x8: A11 and A12 = “Don’t Care”
x4: A12 = “Don’t Care”
65
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©1999 Micron Technology, Inc. All rights reserved.
256Mb: x4, x8, x16 SDRAM
Timing Diagrams
Figure 46:
Read – Full-Page Burst
T0
T1
T2
tCL
CLK
T3
T4
T5
T6
((
))
((
))
tCK
tCH
tCKS
tCMH
ACTIVE
NOP
READ
tCMS
NOP
NOP
NOP
NOP
tCMH
tAS
tAH
tAH
NOP
BURST TERM
NOP
NOP
((
))
((
))
ROW
tAS
((
))
((
))
((
))
((
))
COLUMN m 2
ROW
tAS
BA0, BA1
Tn + 4
((
))
((
))
DQM/
DQML, DQMU
A10
Tn + 3
((
))
((
))
tCMS
A0–A9,
A11, A12
Tn + 2
tCKH
CKE
COMMAND
Tn + 1
tAH
BANK
((
))
((
))
BANK
tAC
tAC
tOH
DOUT m
DQ
tAC
DOUT m+1
tLZ
tRCD
CAS Latency
tAC ( (
tOH ) )
tOH
DOUT
((
))
m+2
((
))
tAC
tOH
tOH
DOUT m-1
Dout m
DOUT m+1
512 (x16) locations within same row
1,024 (x8) locations within same row
2,048 (x4) locations within same row
Full page completed
Full-page burst does not self-terminate.
3
Can use BURST TERMINATE command.
Notes:
PDF: 09005aef8091e6d1/Source: 09005aef8091e6a8
256MSDRAM_2.fm - Rev. L 10/07 EN
tAC
tOH
tHZ
DON’T CARE
UNDEFINED
1. For this example, CL = 2.
2. x16: A9, A11, and A12 = “Don’t Care”
x8: A11 and A12 = “Don’t Care”
x4: A12 = “Don’t Care”
3. Page left open; no tRP.
66
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©1999 Micron Technology, Inc. All rights reserved.
256Mb: x4, x8, x16 SDRAM
Timing Diagrams
Figure 47:
Read – DQM Operation
T0
T1
tCK
CLK
tCKS
tCKH
tCMS
tCMH
T2
T3
T4
T5
NOP
NOP
T6
T7
T8
NOP
NOP
NOP
tCL
tCH
CKE
COMMAND
ACTIVE
NOP
READ
tCMS
NOP
tCMH
DQM/
DQML, DQMU
tAS
A0–A9,
A11, A12
tAS
A10
COLUMN m 2
tAH
ENABLE AUTO PRECHARGE
ROW
tAS
BA0, BA1
tAH
ROW
DISABLE AUTO PRECHARGE
tAH
BANK
BANK
tAC
tOH
DQ
tAC
DOUT m
tLZ
tRCD
tHZ
tAC
tOH
DOUT m + 2
tLZ
tOH
DOUT m + 3
tHZ
CAS Latency
DON’T CARE
UNDEFINED
Notes:
PDF: 09005aef8091e6d1/Source: 09005aef8091e6a8
256MSDRAM_2.fm - Rev. L 10/07 EN
1. For this example, BL = 4 and CL = 2.
2. x16: A9, A11, and A12 = “Don’t Care”
x8: A11 and A12 = “Don’t Care”
x4: A12 = “Don’t Care”
67
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©1999 Micron Technology, Inc. All rights reserved.
256Mb: x4, x8, x16 SDRAM
Timing Diagrams
Figure 48:
Write – Without Auto Precharge
T0
tCK
CLK
T1
T2
tCL
T3
T4
T5
T6
NOP
NOP
NOP
NOP
T7
T8
T9
tCH
tCKS
tCKH
tCMS
tCMH
CKE
COMMAND
ACTIVE
NOP
WRITE
PRECHARGE
NOP
ACTIVE
tCMS tCMH
DQM/
DQML, DQMU
tAS
A0–A9,
A11, A12
ROW
tAH
ALL BANKs
ROW
tAS
BA0, BA1
COLUMN m2
ROW
tAS
A10
tAH
ROW
tAH
BANK
DISABLE AUTO PRECHARGE
SINGLE BANK
BANK
BANK
tDS
tDH
DIN m
DQ
tDS
tDH
DIN m + 1
tDS
tDH
DIN m + 2
tDS
tDH
DIN m + 3
t WR 3
tRCD
tRAS
BANK
tRP
tRC
DON’T CARE
Notes:
PDF: 09005aef8091e6d1/Source: 09005aef8091e6a8
256MSDRAM_2.fm - Rev. L 10/07 EN
1. For this example, BL = 4, and the WRITE burst is followed by a “manual” PRECHARGE.
2. 14ns to 15ns is required between <DIN m + 3> and the PRECHARGE command, regardless of
frequency.
3. x16: A9, A11, and A12 = “Don’t Care”
x8: A11 and A12 = “Don’t Care”
x4: A12 = “Don’t Care”
68
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©1999 Micron Technology, Inc. All rights reserved.
256Mb: x4, x8, x16 SDRAM
Timing Diagrams
Figure 49:
Write – With Auto Precharge
T0
tCK
CLK
tCKS
tCKH
tCMS
tCMH
T1
T2
tCL
T3
T4
T5
T6
T7
T8
T9
NOP
NOP
NOP
NOP
NOP
NOP
ACTIVE
tCH
CKE
COMMAND
ACTIVE
NOP
WRITE
tCMS tCMH
DQM/
DQML, DQMU
tAS
A0–A9,
A11, A12
tAH
ROW
ENABLE AUTO PRECHARGE
ROW
tAS
BA0, BA1
COLUMN m 2
ROW
tAS
A10
tAH
ROW
tAH
BANK
BANK
tDS
tDH
DIN m
DQ
BANK
tDS
tDH
DIN m + 1
tDS
tDH
DIN m + 2
tDS
tDH
DIN m + 3
tRCD
tRAS
tWR
tRP
tRC
DON’T CARE
Notes:
PDF: 09005aef8091e6d1/Source: 09005aef8091e6a8
256MSDRAM_2.fm - Rev. L 10/07 EN
1. For this example, BL = 4.
2. x16: A9, A11, and A12 = “Don’t Care”
x8: A11 and A12 = “Don’t Care”
x4: A12 = “Don’t Care”
69
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©1999 Micron Technology, Inc. All rights reserved.
256Mb: x4, x8, x16 SDRAM
Timing Diagrams
Figure 50:
Single Write – Without Auto Precharge
T0
tCK
CLK
T1
T2
tCL
T3
T4
NOP 2
NOP 2
T5
T6
T7
T8
ACTIVE
NOP
tCH
tCKS
tCKH
tCMS
tCMH
CKE
COMMAND
ACTIVE
NOP
WRITE
PRECHARGE
NOP
tCMS tCMH
DQM/
DQML, DQMU
tAS
A0–A9, A11
tAH
ALL BANKS
ROW
ROW
tAS
BA0, BA1
COLUMN m 3
ROW
tAS
A10
tAH
tAH
DISABLE AUTO PRECHARGE
SINGLE BANK
BANK
BANK
BANK
tDS
BANK
tDH
DIN m
DQ
tRCD
tRAS
tRP
t WR 4
tRC
DON’T CARE
Notes:
PDF: 09005aef8091e6d1/Source: 09005aef8091e6a8
256MSDRAM_2.fm - Rev. L 10/07 EN
1. For this example, BL = 1, and the WRITE burst is followed by a “manual” PRECHARGE.
2. 14ns to 15ns is required between <DIN m> and the PRECHARGE command, regardless of frequency. With a single WRITE, tWR has been increased to meet minimum tRAS
requirement.
3. x16: A8, A9, and A11 = “Don’t Care”
x8: A9 and A11 = “Don’t Care”
x4: A11 = “Don’t Care”
4. PRECHARGE command not allowed (would violate tRAS).
70
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Timing Diagrams
Figure 51:
Single Write – With Auto Precharge
T0
tCK
CK
tCKS
tCKH
tCMS
tCMH
T1
tCL
T2
T3
T4
T5
T6
T7
NOP2
WRITE
NOP
NOP
NOP
T8
T9
tCH
CKE
COMMAND
NOP2
ACTIVE
NOP2
tCMS
ACTIVE
NOP
tCMH
DQM/
DQML, DQMU
tAS
A0–A9,
A11, A12
tAH
ROW
ENABLE AUTO PRECHARGE
ROW
ROW
tAS
BA0, BA1
COLUMN m3
ROW
tAS
A10
tAH
tAH
BANK
BANK
tDS
BANK
tDH
DIN m
DQ
tRCD
tRAS
tWR4
tRP
tRC
DON’T CARE
Notes:
PDF: 09005aef8091e6d1/Source: 09005aef8091e6a8
256MSDRAM_2.fm - Rev. L 10/07 EN
1. For this example, BL = 1.
2. Requires one clock plus time (7ns to 7.5ns) with auto precharge or 14ns to 15ns with PRECHARGE.
3. x16: A9, A11, and A12 = “Don’t Care”
x8: A11 and A12 = “Don’t Care”
x4: A12 = “Don’t Care”
4. WRITE command not allowed (would violate tRAS).
71
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©1999 Micron Technology, Inc. All rights reserved.
256Mb: x4, x8, x16 SDRAM
Timing Diagrams
Figure 52:
Alternating Bank Write Accesses
T0
tCK
CLK
T1
T2
tCL
T3
T4
T5
T6
T7
T8
T9
NOP
NOP
ACTIVE
tCH
tCKS
tCKH
tCMS
tCMH
CKE
COMMAND
ACTIVE
NOP
WRITE
tCMS
NOP
ACTIVE
NOP
WRITE
tCMH
DQM/
DQML, DQMU
tAS
A0–A9,
A11, A12
tAS
A10
COLUMN m 3
tAH
COLUMN b 3
ROW
ENABLE AUTO PRECHARGE
ROW
ENABLE AUTO PRECHARGE
ROW
tAS
BA0, BA1
tAH
ROW
ROW
ROW
tAH
BANK 0
BANK 0
tDS
tDH
DIN m
DQ
BANK 1
tDS
tDH
DIN m + 1
tDS
BANK 1
tDH
tDS
DIN m + 2
tDH
DIN m + 3
tDS
tDH
DIN b
tWR - BANK 0
tRCD - BANK 0
BANK 0
tDS
tDH
DIN b + 1
tDS
tDH
DIN b + 2
tRP - BANK 0
tDS
tDH
DIN b + 3
tRCD - BANK 0
tRAS - BANK 0
tRC - BANK 0
tRRD
tRCD - BANK 1
tWR - BANK 1
DON’T CARE
Notes:
PDF: 09005aef8091e6d1/Source: 09005aef8091e6a8
256MSDRAM_2.fm - Rev. L 10/07 EN
1. For this example, BL = 4.
2. Requires one clock plus time (7ns or 7.5ns) with auto precharge or 14ns to 15ns with PRECHARGE.
3. x16: A9, A11, and A12 = “Don’t Care”
x8: A11 and A12 = “Don’t Care”
x4: A12 = “Don’t Care”
72
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©1999 Micron Technology, Inc. All rights reserved.
256Mb: x4, x8, x16 SDRAM
Timing Diagrams
Figure 53:
Write – Full-Page Burst
T0
T1
T2
tCL
CLK
T3
T4
T5
((
))
((
))
tCK
tCH
tCKS
tCKH
COMMAND
tCMH
ACTIVE
NOP
WRITE
NOP
NOP
NOP
tCMS tCMH
tAS
A10
((
))
((
))
NOP
BURST TERM
NOP
((
))
((
))
COLUMN m 1
tAH
((
))
((
))
ROW
tAS
BA0, BA1
tAH
ROW
tAS
Tn + 3
((
))
((
))
DQM/
DQML, DQMU
A0–A9,
A11, A12
Tn + 2
((
))
((
))
CKE
tCMS
Tn + 1
tAH
BANK
((
))
((
))
BANK
tDS
tDH
DIN m
DQ
tDS
tDH
DIN m + 1
tRCD
tDS
tDH
DIN m + 2
tDS
tDH
DIN m + 3
((
))
((
))
tDS
DIN m - 1
512 (x16) locations within same row
1,024 (x8) locations within same row
2,048 (x4) locations within same row
Full page completed
Notes:
PDF: 09005aef8091e6d1/Source: 09005aef8091e6a8
256MSDRAM_2.fm - Rev. L 10/07 EN
tDH
Full-page burst does
not self-terminate.
Can use BURST TERMINATE
command to stop.2, 3
DON’T CARE
1. x16: A9, A11, and A12 = “Don’t Care”
x8: A11 and A12 = “Don’t Care”
x4: A12 = “Don’t Care”
2. tWR must be satisfied prior to PRECHARGE command.
3. Page left open; no tRP.
73
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©1999 Micron Technology, Inc. All rights reserved.
256Mb: x4, x8, x16 SDRAM
Timing Diagrams
Figure 54:
Write – DQM Operation
T0
T1
tCK
CLK
T2
T3
T4
T5
NOP
NOP
NOP
T6
T7
NOP
NOP
tCL
tCH
tCKS
tCKH
tCMS
tCMH
CKE
COMMAND
ACTIVE
NOP
WRITE
tCMS tCMH
DQM/
DQML, DQMU
tAS
A0–A9,
A11, A12
tAH
ENABLE AUTO PRECHARGE
ROW
tAS
BA0, BA1
COLUMN m 2
ROW
tAS
A10
tAH
tAH
DISABLE AUTO PRECHARGE
BANK
BANK
tDS
tDH
tDS
DIN m
DQ
tDH
DIN m + 2
tDS
tDH
DIN m + 3
tRCD
DON’T CARE
Notes:
PDF: 09005aef8091e6d1/Source: 09005aef8091e6a8
256MSDRAM_2.fm - Rev. L 10/07 EN
1. For this example, BL = 4.
2. x16: A9, A11, and A12 = “Don’t Care”
x8: A11 and A12 = “Don’t Care”
x4: A12 = “Don’t Care”
74
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©1999 Micron Technology, Inc. All rights reserved.
256Mb: x4, x8, x16 SDRAM
Package Dimensions
Package Dimensions
Figure 55:
54-Pin Plastic TSOP (400 mil)
0.10
1.2 MAX
0.375 ±0.075 TYP
PIN #1 ID
0.80 TYP
(FOR REFERENCE
ONLY)
22.22 ±.08
2X R 0.75
2X R 1.00
2X 0.71
PLATED LEAD FINISH: 90% Sn, 10% Pb OR 100%Sn
PLASTIC PACKAGE MATERIAL: EPOXY NOVOLAC
PACKAGE WIDTH AND LENGTH DO NOT
INCLUDE MOLD PROTRUSION. ALLOWABLE
PROTRUSION IS 0.25 PER SIDE.
2X 0.10
2.80
GAGE PLANE
10.16 ±0.08
0.25
+0.10
0.10
-0.05
11.76 ±0.20
SEE DETAIL A
0.15
+0.03
-0.02
0.50 ±0.10
0.80
DETAIL A
Notes:
PDF: 09005aef8091e6d1/Source: 09005aef8091e6a8
256MSDRAM_2.fm - Rev. L 10/07 EN
1. All dimensions in millimeters.
2. Package width and length do not include mold protrusion; allowable mold protrusion is
0.25mm per side.
3. “2X” means the notch is present in two locations (both ends of the device).
75
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256Mb: x4, x8, x16 SDRAM
Package Dimensions
Figure 56:
60-Ball FBGA “FB” Package, 8mm x 16mm (x4, x8)
0.850 ±0.05
0.10 A
SEATING PLANE
2.40 ±0.05
CTR
60X Ø 0.45
DIMENSIONS APPLY
TO SOLDER BALLS
POST REFLOW. PREREFLOW DIAMETER
IS 0.42 ON A 0.33 NSMD
BALL PAD.
SOLDER BALL MATERIAL:
62% Sn, 36% Pb, 2% Ag OR
96.5% Sn. 3% Ag, 0.5% Cu
A
SUBSTRATE:
PLASTIC LAMINATE
8.00 ±0.10
5.60
0.80
TYP
BALL #1 ID
ENCAPSULATION MATERIAL:
EPOXY NOVOLAC
BALL #1 ID
BALL A1
BALL
A8
0.80
TYP
8.00 ±0.05
16.00 ±0.10
CL
11.20
5.60
2.80
1.20 MAX
4.00 ±0.05
Notes:
PDF: 09005aef8091e6d1/Source: 09005aef8091e6a8
256MSDRAM_2.fm - Rev. L 10/07 EN
1. All dimensions in millimeters.
2. Recommended pad size for PCB is 0.33mm ±0.025mm.
3. Topside part marking decode can be found at: www.micron.com/support/designsupport/
tools/fbga/decoder.
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©1999 Micron Technology, Inc. All rights reserved.
256Mb: x4, x8, x16 SDRAM
Package Dimensions
Figure 57:
54-Ball VFBGA “FG” Package, 8mm x 14mm (x16)
0.65 ±0.05
SEATING PLANE
0.10 C
C
6.40
1.00 MAX
BALL A1 ID
0.80 TYP
54X Ø0.45
SOLDER BALL DIAMETER
REFERS TO POST REFLOW
CONDITION. THE PREREFLOW DIAMETER IS Ø0.42
BALL A9
BALL A1 ID
BALL A1
0.80 TYP
CL
6.40
14.00 ±0.10
3.20 ±0.05
7.00 ±0.05
3.20 ±0.05
CL
4.00 ±0.05
MOLD COMPOUND: EPOXY NOVOLAC
SUBSTRATE MATERIAL: PLASTIC LAMINATE
8.00 ±0.10
SOLDER BALL MATERIAL: 62% Sn, 36% Pb, 2% Ag OR
96.5% Sn, 3%Ag, 0.5% Cu
SOLDER MASK DEFINED BALL PADS: Ø 0.40
Notes:
1. All dimensions in millimeters.
2. Recommended pad size for PCB is 0.4mm ±0.065mm.
3. Topside part marking decode can be found at: http://www.micron.com/decoder.
®
8000 S. Federal Way, P.O. Box 6, Boise, ID 83707-0006, Tel: 208-368-3900
[email protected] www.micron.com Customer Comment Line: 800-932-4992
Micron, the M logo, and the Micron logo are trademarks of Micron Technology, Inc. All other trademarks are the property of
their respective owners.
This data sheet contains minimum and maximum limits specified over the complete power supply and temperature range
set forth herein. Although considered final, these specifications are subject to change, as further product development and
data characterization sometimes occur.
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256MSDRAM_2.fm - Rev. L 10/07 EN
77
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©1999 Micron Technology, Inc. All rights reserved.