MOSEL VITELIC V826664K24S 2.5 VOLT 64M x 64 HIGH PERFORMANCE UNBUFFERED DDR SDRAM MODULE PRELIMINARY Features Description ■ 184 Pin Unbuffered 67,108,864 x 64 bit Organization DDR SDRAM Modules ■ Utilizes High Performance 32M x 8 DDR SDRAM in TSOPII-66 Packages ■ Single +2.5V (± 0.2V) Power Supply ■ Programmable CAS Latency, Burst Length, and Wrap Sequence (Sequential & Interleave) ■ Auto Refresh (CBR) and Self Refresh ■ All Inputs, Outputs are SSTL-2 Compatible ■ 8192 Refresh Cycles every 64 ms ■ Serial Presence Detect (SPD) ■ DDR SDRAM Performance The V826664K24S memory module is organized 67,108,864 x 64 bits in a 184 pin memory module. The 64M x 64 memory module uses 16 MoselVitelic 32M x 8 DDR SDRAM. The x64 modules are ideal for use in high performance computer systems where increased memory density and fast access times are required. Component Used tCK tAC Clock Frequency (max.) B1 B0 A1 Units 143 133 125 MHz (PC266A) (PC266B) (PC200) Clock Cycle Time CAS Latency = 2.5 V826664K24S Rev. 1.0 April 2002 7 7.5 8 ns 1 V826664K24S MOSEL VITELIC Functional Block Diagram CS1 CS0 DQS0 DM0 DM I/O 7 I/O 6 I/O 1 I/O 0 I/O 5 I/O 4 I/O 3 I/O 2 DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 DQS4 DM4 CS DQS DM I/O 0 I/O 1 I/O 6 I/O 7 I/O 2 I/O 3 I/O 4 I/O 5 D0 CS DQS D8 DM I/O 7 I/O 6 I/O 1 I/O 0 I/O 5 I/O 4 I/O 3 I/O 2 CS DQ32 DQ33 DQ34 DQ35 DQ36 DQ37 DQ38 DQ39 DM I/O 7 I/O 6 I/O 1 I/O 0 I/O 5 I/O 4 I/O 3 I/O 2 CS DQ40 DQ41 DQ42 DQ43 DQ44 DQ45 DQ46 DQ47 DM I/O 7 I/O 6 I/O 1 I/O 0 I/O 5 I/O 4 I/O 3 I/O 2 CS DQ48 DQ49 DQ50 DQ51 DQ52 DQ53 DQ54 DQ55 DQ56 DQ57 DQ58 DQ59 DQ60 DQ61 DQ62 DQ63 DM I/O 7 I/O 6 I/O 1 I/O 0 I/O 5 I/O 4 I/O 3 I/O 2 DQS D4 DM I/O 0 I/O 1 I/O 6 I/O 7 I/O 2 I/O 3 I/O 4 I/O 5 CS DQS D12 DQS5 DM5 DQS1 DM1 DM I/O 7 I/O 6 I/O 1 I/O 0 I/O 5 I/O 4 I/O 3 I/O 2 DQ8 DQ9 DQ10 DQ11 DQ12 DQ13 DQ14 DQ15 CS DQS DM I/O 0 I/O 1 I/O 6 I/O 7 I/O 2 I/O 3 I/O 4 I/O 5 D1 CS DQS D9 DQS D5 DM I/O 0 I/O 1 I/O 6 I/O 7 I/O 2 I/O 3 I/O 4 I/O 5 CS DQS D13 DQS6 DM6 DQS2 DM2 DM I/O 7 I/O 6 I/O 1 I/O 0 I/O 5 I/O 4 I/O 3 I/O 2 DQ16 DQ17 DQ18 DQ19 DQ20 DQ21 DQ22 DQ23 CS DM DQS I/O 0 I/O 1 I/O 6 I/O 7 I/O 2 I/O 3 I/O 4 I/O 5 D2 CS DQS D10 DQS D6 DM I/O 0 I/O 1 I/O 6 I/O 7 I/O 2 I/O 3 I/O 4 I/O 5 CS DQS D14 DQS7 DM7 DQS3 DM3 DM I/O 7 I/O 6 I/O 1 I/O 0 I/O 5 I/O 4 I/O 3 I/O 2 DQ24 DQ25 DQ26 DQ27 DQ28 DQ29 DQ30 DQ31 CS DQS DM I/O 0 I/O 1 I/O 6 I/O 7 I/O 2 I/O 3 I/O 4 I/O 5 D3 CS DQS D11 CS DQS D7 DM I/O 0 I/O 1 I/O 6 I/O 7 I/O 2 I/O 3 I/O 4 I/O 5 CS DQS D15 *Clock Net Wiring Dram1 Serial PD SCL BA0 - BA1 A0 - A12 SDA A0 A1 A2 SA0 SA1 SA2 CK0/CK0 CK1/CK1 CK2/CK2 CAS CAS: SDRAMs D0 - D15 VSS VDDID 4 SDRAMs 6 SDRAMs 6 SDRAMs Card Edge A0-A12: SDRAMs D0 - D15 RAS: SDRAMs D0 - D15 VREF Dram2 R=120Ω Dram3 *(Cap.) Dram4 *(Cap.) Dram5 BA0-BA1: SDRAMs D0 - D15 RAS VDD /VDDQ Clock Wiring Clock SDRAMs Input 0.1uF 0.1uF 0.1uF CKE1 CKE0 CKE: SDRAMs D8 - D15 CKE: SDRAMs D0 - D7 WE WE: SDRAMs D0 - D15 D0 - D15 D0 - D15 D0 - D15 D0 - D15 Strap: see Note 4 V826664K24S Rev. 1.0 April 2002 2 *If four DRAMs are loaded, Cap will replace DRAM3,4 Dram6 Notes: 1. DQ-to-I/O wiring is shown as recommended but may be changed. 2. DQ/DQS/DM/CKE/S relationships must be maintained as shown. 3. DQ, DQS, DM resistors: 22 Ohms. 4. VDDID strap connections (for memory device VDD, VDDQ): STRAP OUT (OPEN): VDD = VDDQ STRAP IN (VSS): VDD ≠VDDQ. V826664K24S MOSEL VITELIC Part Number Information V 8 2 66 64 K 2 4 S X T G - XX SPEED A1 (100MHZ@CL2) B0 ([email protected]) B1 (133MHZ@CL2) MOSEL VITELIC MANUFACTURED DDRSDRAM LEAD FINISH G = GOLD 2.5V COMPONENT PACKAGE, T = TSOP WIDTH DEPTH COMPONENT REV LEVEL 184 PIN Unbuffered DIMM X8 COMPONENT STTL REFRESH RATE 8K V826664K24S Rev. 1.0 April 2002 4 BANKS 3 V826664K24S MOSEL VITELIC Pin Configurations (Front Side/Back Side) Pin Front Pin Front Pin Front Pin Back Pin Back Pin Back 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 VREF DQ0 VSS DQ1 DQS0 DQ2 VDD DQ3 NC NC VSS DQ8 DQ9 DQS1 VDDQ CK1 CK1 VSS DQ10 DQ11 CKE0 VDDQ DQ16 DQ17 DQS2 VSS A9 DQ18 A7 VDDQ DQ19 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 A5 DQ24 VSS DQ25 DQS3 A4 VDD DQ26 DQ27 A2 Vss A1 CB0* CB1* VDD DQS8* A0 CB2* VSS CB3* BA1 Key Key DQ32 VDDQ DQ33 DQS4 DQ34 VSS BA0 DQ35 DQ40 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 VDDQ WE DQ41 CAS VSS DQS5 DQ42 DQ43 VDD NC DQ48 DQ49 VSS CK2 CK2 VDDQ DQS6 DQ50 DQ51 VSS VDDID DQ56 DQ57 VDD DQS7 DQ58 DQ59 VSS NC SDA SCL 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 VSS DQ4 DQ5 VDDQ DM0 DQ6 DQ7 VSS NC NC A13* VDDQ DQ12 DQ13 DM1 VDD DQ14 DQ15 CKE1 VDDQ BA2* DQ20 A12 VSS DQ21 A11 DM2 VDD DQ22 A8 DQ23 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144 VSS A6 DQ28 DQ29 VDDQ DM3 A3 DQ30 VSS DQ31 CB4* CB5* VDDQ CK0* CK0* VSS DM8* A10 CB6* VDDQ CB7* Key key VSS DQ36 DQ37 VDD DM4 DQ38 DQ39 VSS DQ44 154 155 156 157 158 159 160 161 162 163 164 165 166 167 168 169 170 171 172 173 174 175 176 177 178 179 180 181 182 183 184 RAS DQ45 VDDQ CS0 CS1 DM5 VSS DQ46 DQ47 NC VDDQ DQ52 DQ53 NC VDD DM6 DQ54 DQ55 VDDQ NC DQ60 DQ61 VSS DM7 DQ62 DQ63 VDDQ SA0 SA1 SA2 VDDSPD 53 54 55 56 57 58 59 60 61 145 146 147 148 149 150 151 152 153 Notes: * These pins are not used in this module. Pin Names Pin Pin Description Pin Pin Description CK1, CK1, CK2, CK2 Differential Clock Inputs VDDQ DQs Power Supply CS0 Chip Select Input VSS Ground CKE0 Clock Enable Input VREF Reference Power Supply RAS, CAS, WE Commend Sets Inputs VDDSPD Power Supply for SPD A0 ~ A12 Address SA0~SA2 E2 PROM Address Inputs BA0, BA1 Bank Address SCL E2 PROM Clock DQ0~DQ63 Data Inputs/Outputs SDA E2 PROM Data I/O DQS0~DQS7 Data Strobe Inputs/Outputs VDDID VDD Identification Flag DM0~DM7 Data-in Mask DU Do not Use VDD Power Supply NC No Connection V826664K24S Rev. 1.0 April 2002 4 V826664K24S MOSEL VITELIC Serial Presence Detect Information Bin Sort: B1 (PC266A @ CL = 2) B0 (PC266B @ CL = 2.5) A1 (PC200 @ CL = 2) Function Supported A1 B0 Byte # Function described 0 Defines # of Bytes written into serial memory at module manufacturer 128bytes 80h 1 Total # of Bytes of SPD memory device 256bytes 08h 2 Fundamental memory type SDRAM DDR 07h 3 # of row address on this assembly 13 0Dh 4 # of column address on this assembly 10 0Ah 5 # of module Rows on this assembly 2 Bank 02h 6 Data width of this assembly 64 bits 40h 7 .........Data width of this assembly - 00h 8 VDDQ and interface standard of this assembly SSTL 2.5V 04h 9 DDR SDRAM cycle time at CAS Latency =2.5 10 DDR SDRAM Access time from clock at CL=2.5 11 DIMM configuration type(Non-parity, Parity, ECC) 12 Refresh rate & type 13 Primary DDR SDRAM width 14 Error checking DDR SDRAM data width 15 Minimum clock delay for back-to-back random column address 16 DDR SDRAM device attributes : Burst lengths supported 17 DDR SDRAM device attributes : # of banks on each DDR SDRAM 18 8ns 7.5ns B1 Hex value 7ns ±0.8ns ±0.75ns ±0.75ns A1 B0 B1 80h 75h 70h 80h 75h 75h Non-parity, ECC 00h 7.8us & Self refresh 82h x8 08h N/A 00h tCCD=1CLK 01h 2,4,8 0Eh 4 banks 04h DDR SDRAM device attributes : CAS Latency supported 2,2.5 0Ch 19 DDR SDRAM device attributes : CS Latency 0CLK 01h 20 DDR SDRAM device attributes : WE Latency 1CLK 02h 21 DDR SDRAM module attributes Differential clock / non Registered 20h 22 DDR SDRAM device attributes : General +/-0.2V voltage tolerance 00h 23 DDR SDRAM cycle time at CL =2 24 DDR SDRAM Access time from clock at CL =2 25 DDR SDRAM cycle time at CL =1.5 - - - 00h 26 DDR SDRAM Access time from clock at CL =1.5 - - - 00h 27 Minimum row precharge time (=tRP) 20ns 20ns 20ns 50h 50h 50h 28 Minimum row activate to row active delay(=tRRD) 15ns 15ns 15ns 3Ch 3Ch 3Ch V826664K24S Rev. 1.0 April 2002 10ns 10ns 7.5ns ±0.8ns ±0.75ns ±0.75ns 5 A0h A0h 75h 80h 75h 75h V826664K24S MOSEL VITELIC Serial Presence Detect Information (cont.) Function Supported Byte # Function described Hex value A1 B0 B1 A1 B0 B1 29 Minimum RAS to CAS delay(=tRCD ) 20ns 20ns 20ns 50h 50h 50h 30 Minimum active to precharge time(=tRAS) 50ns 45ns 45ns 32h 2Dh 2Dh 31 Module ROW density 32 Command and address signal input setup time 1.1ns 0.9ns 0.9ns B0h 90h 90h 33 Command and address signal input hold time 1.1ns 0.9ns 0.9ns B0h 90h 90h 34 Data signal input setup time 0.6ns 0.5ns 0.5ns 60h 50h 50h 35 Data signal input hold time 0.6ns 0.5ns 0.5ns 60h 50h 50h 36-40 256MB 40h Superset information (may be used in future) 00h 41 SDRAM device minimum active to active/auto-refresh time (=tRC ) 70ns 65ns 65ns 46h 41h 41h 42 SDRAM device minimum active to autorefresh to active/auto-refresh time (=tRFC) 80ns 75ns 75ns 50h 4Bh 4Bh 43 SDRAM device maximum device cycle time (=tCK MAX) 12ns 12ns 12ns 30h 30h 30h 44 SDRAM device maximum skew between DQS and DQ signals (=tDQSQ) 0.6ns 0.5ns 0.5ns 3Ch 32h 32h 45 SDRAM device maximum read datahold skew factor (=tQHS) 1ns 0.75ns 0.75ns A0h 75h 75h 46-61 Superset information (may be used in future) - 00h Initial release 00h 62 SPD data revision code 63 Checksum for Bytes 0 ~ 62 64 Manufacturer JEDEC ID code Mosel Vitelic 40h ....... Manufacturer JEDEC ID code Mosel Vitelic 40h 65 -71 72 73-90 - Manufacturing location E8h 23h 01h Module part number (ASCII) V826664K24S 91 Manufacturer revison code (For PCB) 0 00 92 Manufacturer revison code (For component) 0 00 93 Manufacturing date (Week) - - 94 Manufacturing date (Year) - - Assembly serial # - - 99~127 Manufacturer specific data (may be used in future) Undefined 00h 128~255 Open for customer use Undefined 00h 95~98 V826664K24S Rev. 1.0 April 2002 6 F3h V826664K24S MOSEL VITELIC DC Operating Conditions (TA = 0 to 70°C, Voltage referenced to VSS = 0V) Parameter Symbol Min Typ. Max Unit Power Supply Voltage VDD 2.3 2.5 2.7 V Power Supply Voltage VDDQ 2.3 2.5 2.7 V Input High Voltage VIH VREF + 0.15 - VDDQ + 0.3 V Input Low Voltage VIL -0.3 - VREF - 0.15 V I/O Termination Voltage VTT VREF - 0.04 VREF VREF + 0.04 V VREF 1.15 1.25 1.35 V II -2 - 2 µA Output Leakage Current IOz -5 - 5 µA Output High Current (VOUT = 1.95V) IOH -16.8 - - mA Output Low Current (VOUT = 0.35V) IOL 16.8 - - mA Reference Voltage Input Leakage Current Note 1 2 3 Notes: 1. VDDQ must not exceed the level of VDD . 2. VIL (min) is acceptable -1.5V AC pulse width with ð 5ns of duration. 3. The value of VREF is approximately equal to 0.5VDDQ. AC Operating Conditions (TA = 0 to 70 °C, Voltage referenced to VSS = 0V) Parameter Symbol Min Input High (Logic 1) Voltage, DQ, DQS and DM signals VIH(AC) VREF + 0.31 Input Low (Logic 0) Voltage, DQ, DQS and DM signals VIL(AC) Input Differential Voltage, CK and CK inputs VID(AC) Input Crossing Point Voltage, CK and CK inputs VIX(AC) Max Unit Note V VREF - 0.31 V 0.7 VDDQ + 0.6 V 1 0.5*VDDQ-0.2 0.5*VDDQ+0.2 V 2 Notes: 1. VID is the magnitude of the difference between the input level on CK and the input on CK. 2. The value of VIX is expected to equal 0.5*VDDQ of the transmitting device and must track variations in the DC level of the same. V826664K24S Rev. 1.0 April 2002 7 V826664K24S MOSEL VITELIC AC Operating Test Conditions (TA = 0 to 70°C, Voltage referenced to VSS = 0V) Parameter Value Unit Reference Voltage VDDQ x 0.5 V Termination Voltage VDDQ x 0.5 V AC Input High Level Voltage (VIH, min) VREF + 0.31 V AC Input Low Level Voltage (VIL, max) VREF - 0.31 V VREF V Output Timing Measurement Reference Level Voltage VTT V Input Signal maximum peak swing 1.5 V Input minimum Signal Slew Rate 1 V/ns Termination Resistor (RT) 50 Ohm Series Resistor (R S) 25 Ohm Output Load Capacitance for Access Time Measurement (C L) 30 pF Input Timing Measurement Reference Level Voltage Vtt=0.5*VDDQ RT=50Ω Output Z0=50Ω CLOAD=30pF VREF =0.5*V DDQ Output Load Circuit (SSTL_2) Input/Output Capacitance (VDD = 2.5V, VDDQ = 2.5V, TA = 25°C, f = 1MHz) Parameter Symbol Min Max Unit Input capacitance (A0 ~ A11, BA0 ~ BA1, RAS, CAS, WE) CIN1 60 75 pF Input capacitance (CKE0) CIN2 40 48 pF Input capacitance (CS0) CIN3 40 48 pF Input capacitance (CLK1, CLK2) CIN4 30 32 pF Data & DQS input/output capacitance (DQ 0~DQ63) COUT 10 12 pF Input capacitance (DM0~DM8) CIN5 10 12 pF V826664K24S Rev. 1.0 April 2002 8 V826664K24S MOSEL VITELIC DDR SDRAM MODULE IDD SPEC TABLE Symbol B1 (DDR266@CL=2) Typical Worst IDD0 1210 1230 IDD1 1440 IDD2P B0 (DDR266@ CL=2.5) Unit Worst Typical Worst 1210 1230 980 1050 mA 1530 1440 1530 1130 1250 mA 610 650 610 650 490 530 mA IDD2F 770 850 770 850 650 690 mA IDD2Q 690 730 690 730 570 600 mA IDD3P 650 690 650 690 530 570 mA IDD3N 810 890 810 890 650 730 mA IDD4R 1770 2000 1770 2000 1450 1650 mA IDD4W 1890 2200 1890 2200 1530 1690 mA IDD5 1890 2200 1890 2200 1530 1690 mA Normal 32 32 32 32 32 32 mA Low power 16 16 16 16 16 16 mA 3100 3500 3100 3500 2450 2850 mA IDD6 IDD7 Typical A1 (DDR200@CL=2) * Module IDD was calculated on the basis of component IDD and can be differently measured according to DQ loading cap. Detailed test conditions for DDR SDRAM IDD1 & IDD IDD1 : Operating current: One bank operation 1. Typical Case : Vdd = 2.5V, T=25’ C 2. Worst Case : Vdd = 2.7V, T= 10’ C 3. Only one bank is accessed with tRC(min), Burst Mode, Address and Control inputs on NOP edge are changing once per clock cycle. lout = 0mA 4. Timing patterns - DDR200(100Mhz, CL=2) : tCK = 10ns, CL2, BL=4, tRCD = 2*tCK, tRAS = 5*tCK Read : A0 N R0 N N P0 N A0 N - repeat the same timing with random address changing *50% of data changing at every burst - DDR266B(133Mhz, CL=2.5) : tCK = 7.5ns, CL=2.5, BL=4, tRCD = 3*tCK, tRC = 9*tCK, tRAS = 5*tCK Read : A0 N N R0 N P0 N N N A0 N - repeat the same timing with random address changing *50% of data changing at every burst - DDR266A (133Mhz, CL=2) : tCK = 7.5ns, CL=2, BL=4, tRCD = 3*tCK, tRC = 9*tCK, tRAS = 5*tCK Read : A0 N N R0 N P0 N N N A0 N - repeat the same timing with random address changing *50% of data changing at every burst Legend : A=Activate, R=Read, W=Write, P=Precharge, N=NOP V826664K24S Rev. 1.0 April 2002 9 V826664K24S MOSEL VITELIC AC Characteristics (AC operating conditions unless otherwise noted) (PC266A) Parameter Symbol Min Row Cycle Time tRC 65 Auto Refresh Row Cycle Time tRFC Row Active Time (PC200) Min Max Min Max Unit - 65 - 70 - ns 75 - 75 - 80 - ns tRAS 45 120K 45 120K 50 120K ns Row Address to Column Address Delay tRCD 20 - 20 - 20 - ns Row Active to Row Active Delay tRRD 15 - 15 - 15 - ns Column Address to Column Address Delay tCCD 1 - 1 - 1 - CLK Row Precharge Time tRP 20 - 20 - 20 - ns Write Recovery Time tWR 15 - 15 - 15 - ns Last Data-In to Read Command tDRL 1 - 1 - 1 - CLK Auto Precharge Write Recovery + Precharge Time tDAL 35 - 35 - 35 - ns System Clock Cycle Time CAS Latency = 2.5 tCK 7 12 7.5 12 8 12 ns 7.5 12 10 12 10 12 ns CAS Latency = 2 Max (PC266B) Note Clock High Level Width tCH 0.45 0.55 0.45 0.55 0.45 0.55 CLK Clock Low Level Width tCL 0.45 0.55 0.45 0.55 0.45 0.55 CLK Data-Out edge to Clock edge Skew tAC -0.75 0.75 -0.75 0.75 -0.8 0.8 ns DQS-Out edge to Clock edge Skew tDQSCK -0.75 0.75 -0.75 0.75 -0.8 0.8 ns DQS-Out edge to Data-Out edge Skew tDQSQ - 0.5 - 0.5 - 0.6 ns Data-Out hold time from DQS tQH tHPmin -0.75ns - tHPmin -0.75ns - tHPmin -0.75ns - ns 1 Clock Half Period tHP tCH/L min - tCH/L min - tCH/L min - ns 1 Input Setup Time (fast slew rate) tIS 0.9 - 0.9 - 1.1 - ns 2,3,5,6 Input Hold Time (fast slew rate) tIH 0.9 - 0.9 - 1.1 - ns 2,3,5,6 Input Setup Time (slow slew rate) tIS 1.0 - 1.0 - 1.1 - ns 2,4,5,6 Input Hold Time (slow slew rate) tIH 1.0 - 1.0 - 1.1 - ns 2,4,5,6 tIPW 2.2 - 2.2 - - - ns 6 Write DQS High Level Width tDQSH 0.4 0.6 0.4 0.6 0.4 0.6 CLK Write DQS Low Level Width tDQSL 0.4 0.6 0.4 0.6 0.4 0.6 CLK CLK to First Rising edge of DQS-In tDQSS 0.75 1.25 0.75 1.25 0.75 1.25 CLK Data-In Setup Time to DQS-In (DQ & DM) tDS 0.5 - 0.5 - 0.6 - ns 7 Data-in Hold Time to DQS-In (DQ & DM) tDH 0.5 - 0.5 - 0.6 - ns 7 DQ & DM Input Pulse Width tDIPW 1.75 - 1.75 - 2 - ns Read DQS Preamble Time tRPRE 0.9 1.1 0.9 1.1 0.9 1.1 CLK Read DQS Postamble Time tRPST 0.4 0.6 0.4 0.6 0.4 0.6 CLK Input Pulse Width V826664K24S Rev. 1.0 April 2002 10 V826664K24S MOSEL VITELIC AC Characteristics (cont.) (PC266A) Parameter Symbol Min Write DQS Preamble Setup Time tWPRES 0 Write DQS Preamble Hold Time tWPREH Write DQS Postamble Time (PC266B) Max (PC200) Min Max Min Max Unit - 0 - 0 - CLK 0.25 - 0.25 - 0.25 - CLK tWPST 0.4 0.6 0.4 0.6 0.4 0.6 CLK Mode Register Set Delay tMRD 2 - 2 - 2 - CLK Power Down Exit Time tPDEX 10 - 10 - 10 - ns Exit Self Refresh to Non-Read Command tXSNR 75 - 75 - 80 - ns Exit Self Refresh to Read Command tXSRD 200 - 200 - 200 - CLK Average Periodic Refresh Interval tREFI - 7.8 - 7.8 - 7.8 us Note 8 Notes: 1. This calculation accounts for tDQSQ(max), the pulse width distortion of on-chip circuit and jitter. 2. Data sampled at the rising edges of the clock : A0~A11, BA0~BA1, CKE, CS, RAS, CAS, WE. 3. For command/address input slew rate >=1.0V/ns 4. For command/address input slew rate >=0.5V/ns and <1.0V/ns 5. CK, CK slew rates are >=1.0V/ns 6. These parameters guarantee device timing, but they are not necessarily tested on each device, and they may be guaranteed by design or tester correlation. 7. Data latched at both rising and falling edges of Data Strobes(DQS) : DQ, DM 8. Minimum of 200 cycles of stable input clocks after Self Refresh Exit command, where CKE is held high, is required to complete Self Refresh Exit and lock the internal DLL circuit of DDR SDRAM. Absolute Maximum Ratings Parameter Symbol Rating Unit Ambient Temperature TA 0 ~ 70 °C Storage Temperature TSTG -55 ~ 125 °C VIN , V OUT -0.5 ~ 3.6 V VDD -0.5 ~ 3.6 V VDDQ -0.5 ~ 3.6 V Output Short Circuit Current IOS 50 mA Power Dissipation PD 9 W TSOLDER 260 • 10 °C • Sec Voltage on Any Pin relative to VSS Voltage on VDD relative to VSS Voltage on VDDQ relative to V SS Soldering Temperature • Time Note: Operation at above absolute maximum rating can adversely affect device reliability V826664K24S Rev. 1.0 April 2002 11 V826664K24S MOSEL VITELIC Package Dimensions Units : Inches (Millimeters) 5.25 ± 0.006 (133.350 ± 0.15) 0.089 (2.26) 5.077 (128.950) A 0.7 (17.80) B 1.95 (49.53) 2.55 (64.77) (10.00) 0.393 (2X) 0.157 (4.00) 1.25 ± 0.006 (31.75 ± 0.15) 0.142 Max (3.81 Max) 0.050 ± 0.0039 (1.270 ± 0.10) 0.250 (6.350) 0.100 0.157 (4.00) 0.039 ± 0.002 (1.000 ± 0.050) (2.50 ) 0.26 (6.62) 0.1496 (3.80) 2.175 0.0078 ±0.006 (0.20 ±0.15) 0.071 (1.80) 0.050 (1.270) Detail A V826664K24S Rev. 1.0 April 2002 Detail B 12 V826664K24S MOSEL VITELIC Label Information Module Density MOSEL VITELIC Part Number Criteria of PC2100 or PC1600 DIMM manufacture date code V826664K04SXXX-XX 512MB CLXX PC2100U-2533-080-A XXXX-XXXXXXX Assembly in Taiwan PC2100 U - 2533 - 08 0 - A UNBUFFERED DIMM Gerber file JEDEC CL = 2.5 (CLK) tRCD = 3 (CLK) tRP = 3 (CLK) V826664K24S Rev. 1.0 April 2002 SPD Revision 0 13 CAS Latency V826664K24S MOSEL VITELIC WORLDWIDE OFFICES U.S.A. TAIWAN SINGAPORE UK & IRELAND 3910 NORTH FIRST STREET SAN JOSE, CA 95134 PHONE: 408-433-6000 FAX: 408-433-0952 7F, NO. 102 MIN-CHUAN E. ROAD, SEC. 3 TAIPEI PHONE: 886-2-2545-1213 FAX: 886-2-2545-1209 10 ANSON ROAD #23-13 INTERNATIONAL PLAZA SINGAPORE 079903 PHONE: 65-3231801 FAX: 65-3237013 NO 19 LI HSIN ROAD SCIENCE BASED IND. PARK HSIN CHU, TAIWAN, R.O.C. PHONE: 886-3-579-5888 FAX: 886-3-566-5888 JAPAN SUITE 50, GROVEWOOD BUSINESS CENTRE STRATHCLYDE BUSINESS PARK BELLSHILL, LANARKSHIRE, SCOTLAND, ML4 3NQ PHONE: 44-1698-748515 FAX: 44-1698-748516 ONZE 1852 BUILDING 6F 2-14-6 SHINTOMI, CHUO-KU TOKYO 104-0041 PHONE: 03-3537-1400 FAX: 03-3537-1402 GERMANY (CONTINENTAL EUROPE & ISRAEL) BENZSTRASSE 32 71083 HERRENBERG GERMANY PHONE: +49 7032 2796-0 FAX: +49 7032 2796 22 U.S. SALES OFFICES WEST CENTRAL / EAST 3910 NORTH FIRST STREET SAN JOSE, CA 95134 PHONE: 408-433-6000 FAX: 408-433-0952 604 FIELDWOOD CIRCLE RICHARDSON, TX 75081 PHONE: 214-352-3775 FAX: 214-904-9029 © Copyright , MOSEL VITELIC Corp. Printed in U.S.A. MOSEL VITELIC subjects its products to normal quality control sampling techniques which are intended to provide an assurance of high quality products suitable for usual commercial applications. MOSEL VITELIC does not do testing appropriate to provide 100% product quality assurance and does not assume any liability for consequential or incidental arising from any use of its products. If such products are to be used in applications in which personal injury might occur from failure, purchaser must do its own quality assurance testing appropriate to such applications. The information in this document is subject to change without notice. MOSEL VITELIC makes no commitment to update or keep current the information contained in this document. No part of this document may be copied or reproduced in any form or by any means without the prior written consent of MOSEL-VITELIC. V826664K24S Rev. 1.0 April 2002 14