LMC568 Low Power Phase-Locked Loop General Description Features The LMC568 is an amplitude-linear phase-locked loop consisting of a linear VCO, fully balanced phase detectors, and a carrier detect output. LMCMOS™ technology is employed for high performance with low power consumption. n n n n n n The VCO has a linearized control range of ± 30% to allow demodulation of FM and FSK signals. Carrier detect is indicated when the PLL is locked to an input signal greater than 26 mVrms. LMC568 applications include FM SCA and TV second audio program decoders, FSK data demodulators, and voice pagers. Typical Application Demodulates ± 15% deviation FM/FSK signals Carrier Detect Output with hysteresis Operation to 500 kHz input frequency Low THD — 0.5% typ. for ± 10% deviation 2V to 9V supply voltage range Low supply current drain (100 kHz input frequency, refer to notes pg. 3) DS009135-1 Order Number LMC568CM or LMC568CN See NS Package Number M08A or N08E LMCMOS™ is a trademark of National Semiconductor Corporation. © 1999 National Semiconductor Corporation DS009135 www.national.com LMC568 Low Power Phase-Locked Loop May 1999 Absolute Maximum Ratings (Note 1) Soldering Information Dual-In-Line Package Soldering (10 seconds) 260˚C Small Outline Package Vapor Phase (60 seconds) 215˚C Infrared (15 seconds) 220˚C See AN-450 “Surface Mounting Methods and their Effect on Product Reliability” for other methods of soldering surface mount devices. If Military/Aerospace specified devices are required, please contact the National Semiconductor Sales Office/ Distributors for availability and specifications. Input Voltage, Pin 3 Supply Voltage, Pin 4 Output Voltage, Pin 8 Voltage at All Other Pins Output Current, Pin 8 Package Dissipation Operating Temperature Range (TA) Storage Temperature Range 2 Vp–p 10V 13V Vs to Gnd 30 mA 500 mW −25˚C to +125˚C −55˚C to +150˚C Note 1: “Absolute Maximum Ratings” indicate limits beyond which damage to the device may occur. Operating Ratings indicate conditions for which the device is functional, but do not guarantee specific performance limits. Electrical Characteristics Test Circuit, TA = 25˚C, VS = 5V, RtCt #2, Sw. 1 Pos. 0; and no input unless otherwise noted. Symbol I4 Parameter Power Supply Current Conditions RtCt # 1, Quiescent or Activated Min Typ Max Units 0.75 1.5 mAdc 1.2 2.4 VS = 2V 0.35 VS = 5V VS = 9V V3 Input D.C. Bias 0 R3 Input Resistance 40 I8 Output Leakage 1 f0 Center Frequency Fosc ÷2 RtCt #2, Measure Oscillator Frequency and Divide by 2 VS = 2V VS = 5V Vin 103 1.0 Set Input Frequency Equal to f0 Measured Above, Increase Input Level until Pin 8 Goes Low. 16 25 26 42 VS = 9V 45 1.5 Output ″Sat″ Voltage Input Level > Threshold Choose RL for Specified I8 I8 = 2 mA 0.06 I8 = 20 mA 0.7 Measure Fosc with Sw. 1 in Pos. 0, 1, and 2; VS = 2V 30 VS = 5V VS = 9V 40 mVrms mVrms 0.15 Vdc % 55 60 Bandwidth Skew 1 fmax %/V 8 V8 THD 2.0 15 Starting at Input Threshold, Decrease Input Level until Pin 8 Goes High Vout kHz VS = 2V Input Hysteresis ∆BW 115 VS = 5V ∆Vin L.D.B.W. Largest Detection Bandwidth nAdc 105 Center Frequency Shift with Supply Input Threshold kΩ 100 98 90 VS = 9V ∆f0 mVdc Recovered Audio Typical Application Circuit Input = 100 mVrms, F = 100 kHz Fmod = 400 Hz, ± 10 kHz Dev. VS = 2V 170 VS = 5V 270 VS = 9V 400 ±5 % mVrms Total Harmonic Distortion Typical Application Circuit as Above, Measure Vout Distortion. 0.5 % Signal to Noise Ratio Typical Application Circuit Remove Modulation, Measure Vn (S + N)/N = 20 log (Vout/Vn). 65 dB RtCt #3, Measure Oscillator Frequency and Divide by 2 700 kHz Highest Center Freq. www.national.com 2 Test Circuit DS009135-3 RtCt Rt Ct #1 100k 300 pF #2 10k 300 pF #3 5.1k 62 pF OUTPUT TAKEOFF The output signal is taken off the loop filter at pin 2. Pin 2 is the combined output of the phase detector and control input of the VCO for the phase-locked loop (PLL). The nominal pin 2 source resistance is 80 kΩ, requiring the use of an external buffer transistor to drive nominal loads. For small values of C2, the PLL will have a fast acquisition time and the pull-in range will be set by the built-in VCO frequency stops, which also determine the largest detection bandwidth (LDBW). Increasing C2 results in improved noise immunity at the expense of acquisition time, and the pull-in range will become narrower than the LDBW. However, the maximum hold-in range will always equal the LDBW. The 2 kHz de-emphasis pole shown may be modified or omitted as required by the application. Notes to Typical Application SUPPLY DECOUPLING The decoupling of supply pin 4 becomes more critical at high supply voltages with high operating frequencies, requiring C4 to be placed as close to possible to pin 4. Also, due to pin voltages tracking supply, a large C4 is necessary for low frequency PSRR. OSCILLATOR TIMING COMPONENTS The voltage-controlled oscillator (VCO) on the LMC568 must be set up to run at twice the frequency of the input signal. The components shown in the typical application are for Fosc = 200 kHz (100 kHz input frequency). For operation at lower frequencies, increase the capacitor value; for higher frequencies proportionally reduce the resistor values. If low distortion is not a requirement, the series diode/resistor between pins 6 and 5 may be omitted. This will reduce VCO supply dependence and increase Vout by approximately 2 dB with THD = 2% typical. The center frequency as a function of Rt and Ct is given by: CARRIER DETECT Pin 1 is the output of a negative-going amplitude detector which has a nominal 0 signal output of 7/9 Vs. The output at pin 8 is an N-channel FET switch to ground which is activated when the PLL is locked and the input is of sufficient amplitude to cause pin 1 to fall below 2/3 Vs. The carrier detect threshold is internally set to 26 mVrms typical on a 5V supply. Capacitor C1 in conjunction with the nominal 40 kΩ pin 1 internal resistance forms the output filter. The size of C1 is a tradeoff between slew rate and carrier ripple at the output comparator. Optional resistor RH increases the hysteresis in the pin 8 output for applications such as audio mute control. The minimum allowable value for RH is 330 kΩ. To allow for I.C. and component value tolerences, the oscillator timing components will require a trim. This is generally accomplished by using a variable resistor as part of Rt, although Ct could also be padded. The amount of initial frequency variation due to the LMC568 itself is given in the electrical specifications; the total trim range must also accommodate the tolerances of Rt and Ct. INPUT PIN The input pin 3 is internally ground-referenced with a nominal 40 kΩ resistor. Signals that are centered on 0V may be directly coupled to pin 3; however, any d.c. potential must be isolated via C3. 3 www.national.com LMC568 Typical Performance Characteristics Frequency Drift with Temperature Peak Deviation vs Input Signal Level DS009135-7 www.national.com Pull-In Range as a Function of C2 DS009135-8 4 DS009135-9 Physical Dimensions inches (millimeters) unless otherwise noted SO Package (M) Order Number LMC568CM NS Package Number M08A Molded Dual-In-Line Package (N) Order Number LMC568CN NS Package Number N08E 5 www.national.com LMC568 Low Power Phase-Locked Loop Notes LIFE SUPPORT POLICY NATIONAL’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT AND GENERAL COUNSEL OF NATIONAL SEMICONDUCTOR CORPORATION. As used herein: 1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and whose failure to perform when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury to the user. National Semiconductor Corporation Americas Tel: 1-800-272-9959 Fax: 1-800-737-7018 Email: [email protected] www.national.com National Semiconductor Europe Fax: +49 (0) 1 80-530 85 86 Email: [email protected] Deutsch Tel: +49 (0) 1 80-530 85 85 English Tel: +49 (0) 1 80-532 78 32 Français Tel: +49 (0) 1 80-532 93 58 Italiano Tel: +49 (0) 1 80-534 16 80 2. A critical component is any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness. National Semiconductor Asia Pacific Customer Response Group Tel: 65-2544466 Fax: 65-2504466 Email: [email protected] National Semiconductor Japan Ltd. Tel: 81-3-5639-7560 Fax: 81-3-5639-7507 National does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and National reserves the right at any time without notice to change said circuitry and specifications.