PROTEC PA5322

ANALOG PRODUCTS DIVISION
FEATURES
GENERAL DESCRIPTION
ADC and DAC:

100 dB dynamic range

–90 dB THD

8 kHz to 200 kHz sampling frequency

I2S, left justified and right justified audio data format, 1624 bits

128, 192, 256, 384, 512, 768 and 1024 MCLK to LRCK
ratios

Independent ADC and DAC sampling frequencies and
clocks

Advanced multi-bit delta-sigma with low sensitivity to
clock jitter

Single power supply from 3V to 5.5V

Hardware mode or SPI or 2-wire uC interface
ADC:

4-to-1 MUX for analog inputs

Direct 2 VRMS analog input

ADC PGA from 11.5 dB to –11.5 dB in 0.5 dB per step

Digital attenuation from 6.5 dB to 89.5 dB in 0.5 dB per
step

Optional high pass filter to remove analog DC offset
DAC:

Digital volume control from 0 dB to 120 dB attenuation in
0.5 dB per step, with soft ramp and zero crossing
transition

De-emphasis filter for 32, 44.1 and 48 kHz sampling
frequencies

Selectable fast and slow roll-off filters

95 dB dynamic range

-85 dB THD+N

Up to 200 kHz sampling frequency

I2S audio data format, 16-24 bits

Single power supply 4.5 V to 5.5V
5KΩ
PA5322 is a low cost high performance stereo audio CODEC.
PA5322 performs stereo digital to analog conversion and
analog to digital conversion continuously from 8 kHz to 200
kHz sampling frequency. PA5322 is ideal for high
performance cost sensitive consumer audio applications.
APPLICATIONS





AIN1L/R
AIN2L/R
AIN3L/R
AIN4L/R
DVD recorder
Personal video recorder
LCD and digital TVs
Car audio
AV receiver
PA5322 can accept I²S; left justified and right justified serial
audio data formats up to 24-bit word length. ADC and DAC
operate on independent sampling frequencies and clocks. The
device uses advanced multi-bit (∆-∑) delta-sigma modulation
technique to convert data between digital and analog.
The multi-bit (∆-∑) delta-sigma modulators makes the device
with low sensitivity to clock jitter and low out of band noise.
PA5322 can operate either in the hardware mod or the
software mode. In the hardware mode, pin M0, M1, M2 and
M3 set the operation of the device. In the software mode,
PA5322 provides SPI or 2-wire micro-controller interfaces to
configure its operations.
BLOCK DIAGRAM
CE/MO
CCLK/M2
CDATA/M1
95248
PA5322
100dB, 24-Bit, 192 kHz Stereo Audio CODEC
µC Interface
ADC
Clock Manager
Input
MUX/MIX
PGA
Multilevel
Sigma Delta ADC
DSP
ADC
Serial Port
ADCMCLK
ADCSDOUT/M3
ADCLRCK
ADCSCLK
5KΩ
DACSDIN
DACLRCK
DACSCLK
DAC
Serial Port
DACMCLK
DSP
Multilevel
Sigma Delta DAC
Output Amp
Low Pass Filter
DAC
Clock Manager
ORDERING INFORMATION
Temperature Range
-40 to 85 °C
Package
Part Number
SSOP-28
PA5322-T7
561 E. Elliot Road #175 Chandler, AZ 85225 Tel: (480) 539-2900. Fax: (480) 632-1715
www.protekanalog.com
95248 Rev.0. 01/10
NOT FOR USE IN LIFE SUPPORT SYSTEMS
AOUTL
AOUTR
PA5322
100dB, 24-Bit, 192 kHz Stereo Audio CODEC
ANALOG PRODUCTS DIVISION
PIN CONFIGURATION
DACSDIN
1
28
DACLRCK
2
27
AOUTR
AOUTL
DACSCLK
3
26
DACREFP
DACMCLK
4
25
AIN4L
ADCLRCK
5
24
AIN3L
ADCSCLK
6
23
AIN2L
VDDD
7
22
VDDA
GNDD
8
21
GNDA
ADCMCLK
9
20
AIN1L
ADCSDOUT/M3
10
19
AIN1R
CCLK/M2
11
18
AIN2R
CDATA/M1
12
17
AIN3R
CE/M0
13
16
AIN4R
MUTE
14
15
ADCREFP
PIN DESCRIPTIONS
Pin
Pin No.
Pin Description
ADC Pin.
AIN1L/R
20, 19
Analog input 1 left and right channels
AIN2L/R
23, 18
Analog input 2 left and right channels
AIN3L/R
24, 17
Analog input 3 left and right channels
AIN4L/R
25, 16
Analog input 4 left and right channels
ADCMCLK
9
ADC master clock
ADCSDOUT/M3
10
ADC PCM serial data output
ADCLRCK
5
ADC PCM serial data left and right channel frame clock
ADCSCLK
6
ADC PCM serial data bit clock
DACMCLK
4
DAC master clock
DACSDIN
1
DAC PCM serial data input
DACLRCK
2
DAC PCM serial data left and right channel frame clock
DACSCLK
3
DAC PCM serial data bit clock
AOUTL/R
28, 27
MUTE
14
DAC analog output left and right channels
Mute pin, active when detect 8K zero input in both left and right channels or users
choose to mute the DAC
DAC Pin.
CE/M0
13
SPI uC interface chip select or 2-wire AD0
CCLK/M2
11
SPI or 2-wire (I2C compatible) uC interface clock
CDATA/M1
12
SPI or 2-wire (I2C compatible) uC interface data
Micro-Controller Pin or Hardware Mode Pin.
VDDD/GNDD
7, 8
Digital power supply
VDDA/GNDA
22, 21
Analog power supply
ADCREFP/DACREFP
15, 26
Analog filtering pins
561 E. Elliot Road #175 Chandler, AZ 85225 Tel: (480) 539-2900. Fax: (480) 632-1715
www.protekanalog.com
95248 Rev.0. 01/10
NOT FOR USE IN LIFE SUPPORT SYSTEMS
PA5322
100dB, 24-Bit, 192 kHz Stereo Audio CODEC
ANALOG PRODUCTS DIVISION
In hardware mode, the mode pins function as follows:
Pin
Pin No.
M3
10
M2
11
M1:M0
12, 13
Pin Description
2
External pull-up (47k resistor) – ADC and DAC I S serial data format
External pull-down (47k resistor) – ADC and DAC LJ serial data format
0 – no de-emphasis
1 – 44.1 kHz de-emphasis filter on
00 – select AIN1
01 – select AIN2
10 – select AIN3
11 – select AIN4
RECOMMENDED OPERATING CONDITIONS
ABSOLUTE MAXIMUM RATINGS
Analog Supply Voltage ………………… MIN 3.0V MAX 5.5V
Digital Supply Voltage ………………… MIN 3.0V MAX 5.5V
Supply Voltage …………………………. MIN-0.3V MAX +7.0V
Input Voltage ………………… MIN GND-0.3V MAX VDD+0.3V
Operating Temperature………………..MIN -40°C MAX +85°C
Storage Temperature…………………MIN -65°C MAX +150°C
Note: Continuous operation at or beyond these conditions may
permanently damage the device.
ADC ANALOG AND FILTER CHARACTERISTICS AND SPECIFICATIONS
Test conditions are as the following unless otherwise specify:
VDDA=+5.0V, VDDD=+5.0V, GNDA=0V, GNDD=0V, Ambient temperature=+25C, Fs=48 KHz, 96 KHz or 192 KHz, MCLK/LRCK=256.
PARAMETER
MIN
TYP
MAX
UNIT
Dynamic Range (Note 1)
85
95
100
dB
THD+N
-90
-86
-80
dB
Channel Separation (1KHz)
80
85
90
dB
Signal to Noise ratio
85
95
100
ADC Performance
Inter-channel Gain Mismatch
0.1
Gain Error
dB
dB
±5
%
0.4535
Fs
Filter Frequency Response – Single Speed
Pass-band
0
Stop-band
0.5465
Pass-band Ripple
Fs
±0.05
Stop-band Attenuation
70
dB
dB
Filter Frequency Response – Double Speed
Pass-band
0
Stop-band
0.5833
Pass-band Ripple
0.4167
Fs
±0.005
Stop-band Attenuation
Fs
70
dB
dB
Filter Frequency Response – Quad Speed
Pass-band
0
Stop-band
0.7917
Pass-band Ripple
0.2083
Fs
±0.005
561 E. Elliot Road #175 Chandler, AZ 85225 Tel: (480) 539-2900. Fax: (480) 632-1715
www.protekanalog.com
95248 Rev.0. 01/10
NOT FOR USE IN LIFE SUPPORT SYSTEMS
Fs
dB
PA5322
100dB, 24-Bit, 192 kHz Stereo Audio CODEC
ANALOG PRODUCTS DIVISION
Stop-band Attenuation
70
dB
Analog Input
Full Scale Input Level (Note 2)
Input Impedance
2*(VDDA/5)
Vrms
10
KΩ
Note
1. The value is measured used A-weighted filter. If not use, the result will decrease 2-3 dB.
2. PA5322 allows direct 2 VRMS inputs if external 5 K resistors are used in serial with the analog input pins. 1 VRMS inputs can directly apply to the
analog input pins.
DAC ANALOG AND FILTER CHARACTERISTICS AND SPECIFICATIONS
Test conditions are as the following unless otherwise specify:
VDDA=+5.0V, VDDD=+5.0V, GNDA=0V, GNDD=0V, Ambient temperature=+25C, Fs=48 KHz, 96 KHz or 192 KHz, MCLK/LRCK=256.
PARAMETER
MIN
TYP
MAX
UNIT
Dynamic Range (Note 1)
85
98
100
dB
THD+N
-90
-82
-75
dB
Channel Separation (1KHz)
80
85
90
dB
Signal to Noise ratio
85
97
100
dB
DAC Performance
Inter-channel Gain Mismatch
0.05
dB
Filter Frequency Response – Single Speed, Fast Roll-off Filter
Pass-band
0
Stop-band
0.5465
Pass-band Ripple
0.4535
Fs
±0.05
Stop-band Attenuation
Fs
53
dB
dB
Filter Frequency Response – Double Speed, Fast Roll-off Filter
Pass-band
0
Stop-band
0.5833
Pass-band Ripple
Stop-band Attenuation
0.4167
Fs
±0.005
dB
Fs
56
dB
Filter Frequency Response – Quad Speed, Fast Roll-off Filter
Pass-band
0
Stop-band
0.7917
Pass-band Ripple
0.2083
±0.006
Stop-band Attenuation
Fs
Fs
50
dB
dB
Filter Frequency Response – Single Speed, Slow Roll-off Filter
Pass-band
0
Stop-band
0.5833
Pass-band Ripple
0.4167
Fs
±0.05
Stop-band Attenuation
Fs
65
dB
dB
Filter Frequency Response – Double Speed, Slow Roll-off Filter
Pass-band
0
Stop-band
0.7917
Pass-band Ripple
0.2083
±0.005
Stop-band Attenuation
85
Filter Frequency Response – Quad Speed, Slow Roll-off Filter
561 E. Elliot Road #175 Chandler, AZ 85225 Tel: (480) 539-2900. Fax: (480) 632-1715
www.protekanalog.com
95248 Rev.0. 01/10
NOT FOR USE IN LIFE SUPPORT SYSTEMS
Fs
Fs
dB
dB
PA5322
ANALOG PRODUCTS DIVISION
100dB, 24-Bit, 192 kHz Stereo Audio CODEC
Pass-band
0
Stop-band
0.8958
0.1042
Pass-band Ripple
±0.005
Stop-band Attenuation
55
dB
dB
De-emphasis Error at 1 KHz (Single Speed Mode Only)
Fs = 32KHz
Fs = 44.1KHz
Fs = 48KHz
Analog Output
0.002
0.013
0.0009
Full Scale Output Level
0.7*VDDA
Output Impedance
Load Resistance
Fs
Fs
dB
Vpp
120
Ω
2
KΩ
Load Capacitance
100
PF
MAX
UNIT
Note
1. The value is measured used A-weighted filter.
DC CHARACTERISTICS AND SPECIFICATIONS
PARAMETER
MIN
Normal Operation Mode
VDDD=VDDA=5.0V:
VDDD Current
VDDA Current
VDDD=VDDA=3.3V:
VDDD Current
VDDA Current
Power Down Mode
VDDD=VDDA=5.0V:
VDDD Current
VDDA Current
VDDD=VDDA=3.3V:
VDDD Current
VDDA Current
Digital Voltage Level
Input High-level Voltage
TYP
42
55
mA
34
50
mA
TBD
TBD
TBD
TBD
2.0
V
Input Low-level Voltage
0.8
Output High-level Voltage
VDDD
Output Low-level Voltage
0
V
V
V
Mute Pin Drive Capability
3.0
mA
SERIAL AUDIO PORT SWITCHING SPECIFICATIONS
PARAMETER
Symbol
MIN
MCLK frequency
MCLK duty cycle
40
LRCK frequency
LRCK duty cycle
40
SCLK frequency
MAX
UNIT
51.2
MHz
60
%
200
KHz
60
%
26
MHz
SCLK pulse width low
TSCLKL
15
ns
SCLK Pulse width high
TSCLKH
15
ns
561 E. Elliot Road #175 Chandler, AZ 85225 Tel: (480) 539-2900. Fax: (480) 632-1715
www.protekanalog.com
95248 Rev.0. 01/10
NOT FOR USE IN LIFE SUPPORT SYSTEMS
PA5322
ANALOG PRODUCTS DIVISION
100dB, 24-Bit, 192 kHz Stereo Audio CODEC
SCLK falling to LRCK edge
TSLR
–10
SCLK falling to SDOUT valid
TSDO
0
10
ns
ns
SDIN valid to SCLK rising setup time
TSDIS
10
ns
SCLK rising to SDIN hold time
TSDIH
10
ns
LRCK
Input
tsclkl
tsclkh
tslr
SLCK
Input
tsdo
tsclkw
SDOUT
tsdis
tsdih
SDIN
Serial Audio Port Timing
SERIAL CONTROL PORT SWITCHING SPECIFICATIONS
PARAMETER
Symbol
MIN
MAX
UNIT
10
MHz
SPI Mode
SPI_CLK clock frequency
SPI_CLK edge to SPI_CSn falling
TSPICS
5
ns
SPI_CSn High Time Between transmissions
TSPISH
500
ns
SPI_CSn falling to SPI_CLK edge
TSPISC
10
ns
SPI_CLK low time
TSPICL
45
ns
SPI_CLK high time
TSPICH
45
ns
SPI_DIN to SPI_CLK rising setup time
TSPIDS
10
ns
SPI_CLK rising to DATA hold time
TSPIDH
15
ns
2-wire Mode
SCL Clock Frequency
FSCL
Bus Free Time Between Transmissions
TTWID
4.7
100
us
Start Condition Hold Time
TTWSTH
4.0
us
Clock Low time
TTWCL
4.0
us
Clock High Time
TTWCH
4.0
us
Setup Time for Repeated Start Condition
TTWSTS
4.7
us
SDA Hold Time from SCL Falling
TTWDH
0.1
us
SDA Setup time to SCL Rising
TTWDS
100
Rise Time of SCL
TTWR
25
us
Fall Time SCL
TTWF
25
ns
ns
561 E. Elliot Road #175 Chandler, AZ 85225 Tel: (480) 539-2900. Fax: (480) 632-1715
www.protekanalog.com
95248 Rev.0. 01/10
NOT FOR USE IN LIFE SUPPORT SYSTEMS
KHz
PA5322
100dB, 24-Bit, 192 kHz Stereo Audio CODEC
ANALOG PRODUCTS DIVISION
T SPIDS
T SPIDH
SPI_DIN
T SPICL
SPI_CLK
T SPICH
SPI_CSn
T SPIC S
T SPISH
T SPISC
Serial Control Port SPI Timing
SDA
T TW STS
T TW STH
SCL
T TW CL
T TW DH
T T W ID
T TW DS
T TW CH
S
T TW F
S
P
T TW R
Serial Control Port 2-wire Timing
RECOMMENDED APPLICATION CIRCUIT
VDDD
7
47µH
0.1µF
7
8
10µF
1
2
DAC SERIAL
AUDIO DATA
3
4
5
6
ADC SERIAL
AUDIO DATA
9
10
11
MCU
INTERFACE
12
13
EXTERNAL
MUTE CIRCUIT
14
VDDD
AOUTL
GNDD
AOUTR
DACSDIN
DACREFP
DACLRCK
AIN4L
DACSCLK
AIN3L
DACMCLK
AIN2L
ADCLRCK
AIN1L
ADCSCLK
VDDA
ADCMCLK
GNDA
ADCSOUT
AIN1R
CCLK
AIN2R
CDATA
AIN3R
CE
AIN4R
MUTE
ADCREFP
28
Vout L/R TO
EXTERNAL LPE
27
26
25
5KΩ
4.7µF
24
5KΩ
4.7µF
23
5KΩ
4.7µF
20
5KΩ
0.1µF
10µF
ANALOG
LEFT INPUTS
4.7µF
VDDA
47µH
22
10µF
21
19
5KΩ
18
5KΩ
17
5KΩ
16
5KΩ
0.1µF
4.7µF
4.7µF
4.7µF
ANALOG
RIGHT INPUTS
4.7µF
15
10µF
0.1µF
561 E. Elliot Road #175 Chandler, AZ 85225 Tel: (480) 539-2900. Fax: (480) 632-1715
www.protekanalog.com
95248 Rev.0. 01/10
NOT FOR USE IN LIFE SUPPORT SYSTEMS
PA5322
ANALOG PRODUCTS DIVISION
100dB, 24-Bit, 192 kHz Stereo Audio CODEC
AUDIO DATA SAMPLING FREQUENCY AND CLOCKS
According to the input serial audio data sampling frequency, the device can work in three speed modes: single speed, double speed
or quad speed modes. The ranges of the sampling frequency in these three modes are listed in Table1.
ADCSampleRate bits in ADC Control 2 register (RAM address 0x02) or DACSampleRate bits in DAC Control 2 register (RAM
address 0x07) set the speed mode.
By default, the device can detect the speed mode automatically when sampling rate falls within the Fs Auto Detection Ranges listed in
Table1.
In this auto detection mode, sampling frequency outside the specified ranges is not supported. ADC and DAC have separate auto
detection so ADC and DAC sampling frequencies can be completely independent.
Table 1. Sampling Frequency and CLK/LRCK Ration
Speed Mode
Sampling Frequency
Fs Auto Detection Range
MCLK/LRCK Ratio
Single Speed
8kHz – 50kHz
8kHz – 50kHz
256, 384, 512, 768, 1024
Double Speed
50kHz – 100kHz
84kHz – 100kHz
128, 192, 256, 384, 512
Quad Speed
100kHz – 200kHz
167kHz – 200kHz
128, 192, 256
The device uses separate master clocks, LRCK clocks and SCLK clocks for the ADC and DAC. The allowed MCLK/LRCK ratios in
each speed mode are also listed in Table1. The device always detects MCLK/LRCK ratio automatically.
HARDWARE MODE
The device can operate in the hardware mode or the software mode. The default is the hardware mode. To change the hardware
mode to the software mode, set SCPEn bit of Chip Control register (RAM address 0x00) to 1.
2
In the hardware mode, pin M3 sets I S or left justified ADC and DAC serial port mode, pin M2 sets DAC de-emphasis filter on or off,
and pins M1 and pin M0 select one of the four ADC analog inputs.
Please refer to PIN DESCRIPTIONS section for detail settings.
POWER UP AND DOWN
The chip internal power on reset will reset the device when VDDD ramps from ground to supply voltage level. When VDDD and VDDA
are present to the device, applying ADCMCLK and ADCLRCK will startup the ADC and applying DACMCLK and DACLRCK will start
up the DAC.
During the DAC startup, DAC analog outputs ramp gradually from ground to mid level to minimize audible pop noise. This gradual
ramp feature can be turned off by setting ClickFree bit of DAC Control 1 register (RAM address 0x06) to 0.
ADC and DAC can power up or down independently. In the software mode, ADC or DAC can power down through ADCPDN bit or
DACPDN bit of Chip Control register (RAM address 0x00). In the hardware mode, ADC can power down by stopping ADCMCLK or
ADCLRCK, and DAC can power down by stopping DACMCLK or DACLRCK.
MICRO-CONTROLLER CONFIGURATION INTERFACE
The device supports standard SPI and 2-wire micro-controller configuration interface. External micro-controller can completely
configure the device through writing to internal configuration registers.
The identical device pins are used to configure either SPI or 2-wire interface. In SPI mode, pin CE, CCLK and CDATA function as
SPI_CSn, SPI_CLK and SPI_DIN. In 2-wire mode, pin CE, CCLK and CDATA function as AD0, SCL and SDA.
To select SPI mode, apply high to low transition signal to CE pin. Otherwise the device will operate in 2-wire interface mode.
SPI
PA5322 has a SPI (Serial Peripheral Interface) compliant synchronous serial slave controller inside the chip. It provides the ability to
allow the external master SPI controller to access the internal registers, and thus control the operations of chip.
All lines on the SPI bus are unidirectional: The SPI_CLK is generated by the master controller and is primarily used to synchronize
data transfer, the SPI_DIN line carries data from the master to the slave; SPI_CSn is generated by the master to select PA5322.
The timing diagram of this interface is given in Figure 1. The high to low transition at SPI_CSn pin indicates the SPI interface
selected. Each write procedure contains 3 words, i.e. Chip Address plus R/W bit, internal register address and internal register data.
Every word length is fixed at 8 bits. The input SPI_DIN data are sampled at the rising edge of SPI_CLK clock. The MSB bit in each
word is transferred firstly. The transfer rate can be up to 10M bps.
561 E. Elliot Road #175 Chandler, AZ 85225 Tel: (480) 539-2900. Fax: (480) 632-1715
www.protekanalog.com
95248 Rev.0. 01/10
NOT FOR USE IN LIFE SUPPORT SYSTEMS
PA5322
100dB, 24-Bit, 192 kHz Stereo Audio CODEC
ANALOG PRODUCTS DIVISION
Chip Address
7 bits - 0010000
SPI_DIN
0
5
1
R/
Wb
6
RAM
8 bits
7
8
9
Register Data
8 bits
14
15
16
17
22
23
SPI_CLK
SPI_CSn
RAM = Register Address Mapping
Figure1. SPI Configuration Interface Timing Diagram
2-WIRE
2-wire interface is a bi-directional serial bus that uses a serial data line (SDA) and a serial clock line (SCL) for data transfer. The
timing diagram for data transfer of this interface is given in Figure 2. Data are transmitted synchronously to SCL clock on the SDA line
on a byte-by-byte basis. Each bit in a byte is sampled during SCL high with MSB bit being transmitted firstly. Each transferred byte is
followed by an acknowledge bit from receiver to pull the SDA low. The transfer rate of this interface can be up to 100k bps.
SDA
1-7
SCL
8
9
1-7
8
9
1-7
S
8
P
START ADDRESS
R/W
ACK
DATA
ACK
DATA
STOP
Figure2. Complete Data Transfer 2-wire Interface
A master controller initiates the transmission by sending a “start” signal, which is defined as a high-to-low transition at SDA while SCL
is high. The first byte transferred is the slave address. It is a seven-bit chip address followed by a RW bit. The chip address must be
001000x, where x equals AD0 (pin CE). The RW bit indicates the slave data transfer direction. Once an acknowledge bit is received,
the data transfer starts to proceed on a byte-by-byte basis in the direction specified by the RW bit. The master can terminate the
communication by generating a “stop” signal, which is defined as a low-to-high transition at SDA while SCL is high.
In 2-wire interface mode, the registers can be written and read. The formats of “write” and “read” instructions are shown in Table 2
and Table 3. Please note that, to read data from a register, you must set R/W bit to 0 to access the register address and then set R/W
to 1 to read data from the register. There are no acknowledge bit after data to be written or read, this is the only difference from the
2
I C protocol.
Table 2 Write Data to Register in 2-wire Interface Mode
Chip Address
001000
R/W
AD0
Register Address
Data to be written
0
ACK
RAM
ACK
DATA
Table 3 Read Data from Register in 2-wire Interface Mode
Chip Address
001000
Chip Address
001000
R/W
Register Address
0
ACK
R/W
Data to be read
AD0
1
ACK
AD0
RAM
DATA
561 E. Elliot Road #175 Chandler, AZ 85225 Tel: (480) 539-2900. Fax: (480) 632-1715
www.protekanalog.com
95248 Rev.0. 01/10
NOT FOR USE IN LIFE SUPPORT SYSTEMS
PA5322
ANALOG PRODUCTS DIVISION
100dB, 24-Bit, 192 kHz Stereo Audio CODEC
CONFIGURATION REGISTER DEFINITION
SPI and 2-wire configuration interface share the same registers because there is only one interface active at any time. There are total
of 11 user programmable 8-bit registers in this device.
These registers control the operations of ADC and DAC. External master controller can access these registers by using the slave
address specified in RAM (Register Address Map) register as shown in Table 2.
Table 2 Bit Content of Register Address Map
Bit Name
Bit
Description
RAM Address
7:0
The address of the register to be accessed:
0x00 – Chip Control (default)
0x01 – ADC Control 1
0x02 – ADC Control 2
0x03 – ADC Mute Control
0x04 – ADC Left Gain Control
0x05 – ADC Right Gain Control
0x06 – DAC Control 1
0x07 – DAC Control 2
0x08 – DAC Mute Control
0x09 – DAC Left Volume Control
0x0a – DAC Right Volume Control
Chip Control – 0x00
Bit Name
Bit
SCPEn
7
Reserved
6:5
ADCPDN
4
Reserved
3
DACPDN
2
Reserved
1:0
Description
0 – hardware mode (default)
1 – software (control port) mode
Reserved
0 – normal (default)
1 – ADC low power mode
Reserved
0 – normal (default)
1 – DAC low power mode
Reserved
ADC Control 1 – 0x01
Bit Name
AINMIX
Bit
7:3
HPF
2
Reserved
1:0
Description
00000 – AIN1 input to ADC (default)
xxx1 – AIN1 input ADC
xx1x – AIN2 input ADC
x1xx – AIN3 input ADC
1xxx – AIN4 input ADC
0 – ADC HPF enable (default)
1 – ADC HPF disable
Reserved
ADC Control 2 – 0x02
Bit Name
ADCSampleRate
Bit
7:6
ADCSPDataMode
5:3
Description
00 – ADC speed mode auto detect (default)
01 –single speed mode
10 –double speed mode
11 –quad speed mode
000 – Left justified, up to 24 bit data
561 E. Elliot Road #175 Chandler, AZ 85225 Tel: (480) 539-2900. Fax: (480) 632-1715
www.protekanalog.com
95248 Rev.0. 01/10
NOT FOR USE IN LIFE SUPPORT SYSTEMS
PA5322
ANALOG PRODUCTS DIVISION
SCLKRatio
2:1
Reserved
0
100dB, 24-Bit, 192 kHz Stereo Audio CODEC
001 – I2S, up to 24 bit data (default)
010 – Right justified, 16 bit data
011 – Reserved
100 – Reserved
101 – Right justified, 24 bit data
110 – Reserved
111 – Reserved
00 – 32
01 – 48
10 – 64 (default)
11 – 128
Reserved
ADC Mute Control – 0x03
Bit Name
Bit
ADCMute
7
Reserved
6
ADCRampRate
5:4
ADCL=R
3
ADCSoftRamp
2
ADCZeroCrs
1
Reserved
0
Description
0 – normal (default)
1 – mute ADC digital output
Reserved
These bits define ADC gain control ramp rate:
00 – 0.5 dB per 4 LRCK (default)
01 – 0.5 dB per 8 LRCK
10 – 0.5 dB per 16 LRCK
11 – 0.5 dB per 32 LRCK
0 – normal (default)
1 – both channel gain control is set by ADC Left Gain Control register
ADC soft ramp at mute or gain change:
0 – Disabled
1 – Enabled (default)
ADC mute or gain change at zero crossing signal level to minimize audible noise
0 – Disabled
1 – Enabled (default)
Reserved
ADC Left Gain Control – 0x04
Bit Name
ADCGainL
Bit
7:0
Description
1110 1000 – 6.0 dB gain (PGA)
1110 1001 – 6.5 dB gain (PGA)
1110 1010 – 7.0 dB gain (PGA)
1110 1011 – 7.5 dB gain (PGA)
1110 1100 – 8.0 dB gain (PGA)
1110 1101 – 8.5 dB gain (PGA)
1110 1110 – 9.0 dB gain (PGA)
1110 1111 – 9.5 dB gain (PGA)
1111 0000 – 10.0 dB gain (PGA)
1111 0001 – 10.5 dB gain (PGA)
1111 0010 – 11.0 dB gain (PGA)
1111 0011 – 11.5 dB gain (PGA)
1111 0100 – 6.0 dB attenuation (PGA)
1111 0101 – 5.5 dB attenuation (PGA)
1111 0110 – 5.0 dB attenuation (PGA)
1111 0111 – 4.5 dB attenuation (PGA)
1111 1000 – 4.0 dB attenuation (PGA)
1111 1001 – 3.5 dB attenuation (PGA)
1111 1010 – 3.0 dB attenuation (PGA)
561 E. Elliot Road #175 Chandler, AZ 85225 Tel: (480) 539-2900. Fax: (480) 632-1715
www.protekanalog.com
95248 Rev.0. 01/10
NOT FOR USE IN LIFE SUPPORT SYSTEMS
PA5322
ANALOG PRODUCTS DIVISION
100dB, 24-Bit, 192 kHz Stereo Audio CODEC
1111 1011 – 2.5 dB attenuation (PGA)
1111 1100 – 2.0 dB attenuation (PGA)
1111 1101 – 1.5 dB attenuation (PGA)
1111 1110 – 1.0 dB attenuation (PGA)
1111 1111 – 0.5 dB attenuation (PGA)
0000 0000 – no gain or attenuation (default)
0000 0001 – 0.5 dB gain (PGA)
0000 0010 – 1.0 dB gain (PGA)
0000 0011 – 1.5 dB gain (PGA)
0000 0100 – 2.0 dB gain (PGA)
0000 0101 – 2.5 dB gain (PGA)
0000 0110 – 3.0 dB gain (PGA)
0000 0111 – 3.5 dB gain (PGA)
0000 1000 – 4.0 dB gain (PGA)
0000 1001 – 4.5 dB gain (PGA)
0000 1010 – 5.0 dB gain (PGA)
0000 1011 – 5.5 dB gain (PGA)
0000 1100 – 6.0 dB gain (PGA)
0000 1101 – 11.5 dB attenuation (PGA)
0000 1110 – 11.0 dB attenuation (PGA)
0000 1111 – 10.5 dB attenuation (PGA)
0001 0000 – 10.0 dB attenuation (PGA)
0001 0001 – 9.5 dB attenuation (PGA)
0001 0010 – 9.0 dB attenuation (PGA)
0001 0011 – 8.5 dB attenuation (PGA)
0001 0100 – 8.0 dB attenuation (PGA)
0001 0101 – 7.5 dB attenuation (PGA)
0001 0110 – 7.0 dB attenuation (PGA)
0001 0111 – 6.5 dB attenuation (PGA)
0001 1000 – 6.0 dB attenuation (PGA)
0001 1001 – 6.5 dB attenuation (6 dB PGA + digital attenuation)
0001 1010 – 7.0 dB attenuation (6 dB PGA + digital attenuation)
……..
1011 1111 – 89.5 dB attenuation (6 dB PGA + digital attenuation)
ADC Right Gain Control – 0x05
Bit Name
Bit
Description
ADCGainR
7:0
Same as ADCGainL settings for ADC right channel
DAC Control 1 – 0x06
Bit Name
Bit
Description
Reserved
7:6
ClickFree
5
SlowFilter
4
Reserved
0 – disable pop noise suppression power up and down
1 – enable pop noise suppression power up and down (default)
0 – fast filter roll off (default)
1 – slow filter roll off
0 – DAC analog output no phase inversion (default)
1 – DAC analog output 180 degree phase inversion
Reserved
InvL
InvR
Reserved
3:2
1:0
DAC Control 2 – 0x07
Bit Name
DACSampleRate
Bit
7:6
DACSPDataMode
5:3
Description
00 – DAC speed mode auto detect (default)
01 – single speed mode
10 – double speed mode
11 – quad speed mode
000 – Left justified, up to 24 bit data
561 E. Elliot Road #175 Chandler, AZ 85225 Tel: (480) 539-2900. Fax: (480) 632-1715
www.protekanalog.com
95248 Rev.0. 01/10
NOT FOR USE IN LIFE SUPPORT SYSTEMS
PA5322
ANALOG PRODUCTS DIVISION
DeEmphasisMode
2:1
Reserved
0
100dB, 24-Bit, 192 kHz Stereo Audio CODEC
001 – I2S, up to 24 bit data (default)
010 – Right justified, 16 bit data
011 – Reserved
100 – Reserved
101 – Right justified, 24 bit data
110 – Reserved
111 – Reserved
00 – De-emphasis filter disabled (default)
01 – De-emphasis filter for Fs=32 KHz
10 – De-emphasis filter for Fs=44.1 KHz
11 – De-emphasis filter for Fs=48 KHz
Reserved
DAC Mute Control – 0x08
Bit Name
Bit
Description
DACMute
7
DACRampRate
6
AutoMute
5
DACL=R
4
DACSoftRamp
3
DACZeroCrs
1
Reserved
0
0 – un-mute analog outputs for both channels (default)
1 – mute analog outputs for both channels
These bits define volume control ramp rate:
00 – 0.5 dB per 4 LRCK (default)
01 – 0.5 dB per 8 LRCK
10 – 0.5 dB per 16 LRCK
11 – 0.5 dB per 32 LRCK
Auto mute function: long period of zero inputs (8k audio samples) will mute the analog output.
Any single non-zero input will un-mute. 0 – disable
1 – enable (default)
0 – normal (default)
1 – both channel volume control is set by Left Volume Control register
Soft ramp at mute and volume change:
0 – Disabled
1 – Enabled (default)
Mute or volume change at zero crossing signal level to minimize audible noise
0 – Disabled
1 – Enabled (default)
Reserved
DAC Left Volume Control – 0x09
Bit Name
Bit
Description
DACVolumeL
7:0
Digital volume control setting attenuates the signal in 0.5 dB incremental from 0 to –120 dB.
Max setting is –120 dB.
0000 0000 – no attenuation (default)
0000 0001 – 0.5 dB attenuation
0000 0010 – 1.0 dB attenuation
0000 0011 – 1.5 dB attenuation
……..
DAC Right Volume Control – 0x0a
Bit Name
Bit
Description
DACVolumeR
7:0
Same as DACVolumeL settings for DAC right channel
Digital Audio Interface
The device provides three formats of serial audio data interface to the input of the DAC or output from the ADC through LRCK, SCLK
2
and SDIN/SDOUT pins. The three formats are I S, left justified and right justified. In the hardware mode, the formats are selected
through pin M3.
561 E. Elliot Road #175 Chandler, AZ 85225 Tel: (480) 539-2900. Fax: (480) 632-1715
www.protekanalog.com
95248 Rev.0. 01/10
NOT FOR USE IN LIFE SUPPORT SYSTEMS
PA5322
100dB, 24-Bit, 192 kHz Stereo Audio CODEC
ANALOG PRODUCTS DIVISION
In the software mode, the formats are selected by ADCSPDataMode bits of ADC Control 2 register (RAM address 0x02) or
DACSPDataMode bits DAC Control 2 register (RAM address 0x07). DACSDIN is sampled by PA5322 on the rising edge of
DACSCLK. ADC data is out on ADCSDOUT and changes on the falling edge of ADCSCLK. The relationship of SDATA
(SDIN/SDOUT), SCLK and LRCK with the three formats is shown below through Figure 3 to Figure 5.
1 SCLK
1
SDATA
2
1 SCLK
3
n- 2 n- 1
MSB
n
1
LSB
MSB
2
3
n- 2 n- 1
n
LSB
SCLK
LEFT CHANNEL
LRCK
RIGHT CHANNEL
2
Figure 3. I S Audio Data Format up to 24-bit
SDATA
1
2
3
n- 2 n- 1
MSB
n
1
LSB
MSB
2
3
n- 2 n- 1
n
LSB
SCLK
LRCK
RIGHT CHANNEL
LEFT CHANNEL
Figure 4. Left Justified Audio Data Format up to 24-bit
1
SDATA
2
3
n- 2 n- 1
MSB
n
1
LSB
MSB
2
3
n- 2 n- 1
n
LSB
SCLK
LRCK
RIGHT CHANNEL
LEFT CHANNEL
Figure 5. Right Justified Audio Data Format up to 24-bit
Analog Input Multiplex and Programmable Gain Control
PA5322 allows direct 2 VRMS inputs if external 5 K resistors are used in serial with the analog input pins. Please refer to Figure 6.
VRMS inputs can directly apply to the analog input pins.
In the hardware mode, the analog input is selected through mode pins M1 and M0. In the software mode, the analog input is selected
through AINMIX bits of ADC Control 1 register (RAM address 0x01). In the software mode, more than one input can apply to the
analog input pins to achieve mixing effects.
5k
5k
5k
5k
5k
AIN1L/R
AIN2L/R
AIN3L/R
AIN4L/R
5k
5k
5k
5k
+12 dB to –12 dB PGA
Opamp
PA5322
Figure 6. ADC Left and Right Inputs
The ADC has an analogue input PGA and digital gain control for each stereo channel. The analog PGA has a range of +12 dB to –12
dB gains in 0.5 dB per step. The digital gain control allows further attenuation (after the PGA) from 12.5 dB to 96 dB in 0.5 dB per
step. ADC Left Gain Control register (RAM address 0x04) and ADC Right Gain Control register (RAM address 0x05) allows
independent control of left and right channel gains.
561 E. Elliot Road #175 Chandler, AZ 85225 Tel: (480) 539-2900. Fax: (480) 632-1715
www.protekanalog.com
95248 Rev.0. 01/10
NOT FOR USE IN LIFE SUPPORT SYSTEMS
PA5322
ANALOG PRODUCTS DIVISION
100dB, 24-Bit, 192 kHz Stereo Audio CODEC
Zero crossing detection and soft ramp control circuits are provided for the ADC gain control (ADC Mute Control register, RAM address
0x03). This feature minimizes the audible click and “zipper” noise as the gain values change.
DAC Fade In and Fade Out Transition
When DACMute bit in DAC Mute Control register (RAM address 0x08) is set, the analog outputs go to mute level (common mode
voltage) gradually at the rate set by DACRampRate bits in the same register. Upon the release of the DACMute bit, the analog
outputs go up gradually at the same rate set by DACRampRate bits. Please refer to Figure 7.
The fade in and fade out feature can be set or disabled by DACSoftRamp bit in the same register.
Mute Bit
Volume
Level
AOUT
Figure 7. Fade In/Out Diagram
The fade in and fade out feature is also available when AutoMute bit in DAC Mute Control register (RAM address 0x08) is set to
detect long stream of zero input data.
561 E. Elliot Road #175 Chandler, AZ 85225 Tel: (480) 539-2900. Fax: (480) 632-1715
www.protekanalog.com
95248 Rev.0. 01/10
NOT FOR USE IN LIFE SUPPORT SYSTEMS
PA5322
ANALOG PRODUCTS DIVISION
100dB, 24-Bit, 192 kHz Stereo Audio CODEC
PACKAGE DIMENSIONS AND MEASUREMENTS
28-pin SSOP Outline Dimensions
561 E. Elliot Road #175 Chandler, AZ 85225 Tel: (480) 539-2900. Fax: (480) 632-1715
www.protekanalog.com
95248 Rev.0. 01/10
NOT FOR USE IN LIFE SUPPORT SYSTEMS
PA5322
ANALOG PRODUCTS DIVISION
100dB, 24-Bit, 192 kHz Stereo Audio CODEC
Life Support Policy
PROTEK ANALOG'S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT
DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF PROTEK DEVICES.
561 E. Elliot Road #175 Chandler, AZ 85225 Tel: (480) 539-2900. Fax: (480) 632-1715
www.protekanalog.com
95248 Rev.0. 01/10
NOT FOR USE IN LIFE SUPPORT SYSTEMS