RICHTEK RT7248

®
RT7248
2A, 18V, 340kHz Synchronous Step-Down Converter
General Description
Features
±1.5% High Accuracy Feedback Voltage
Input Voltage Range : 4.5V to 18V
2A Output Current
Integrated N-MOSFETs
Current Mode Control
340kHz Fixed Frequency Operation
Output Adjustable Voltage Range : 0.923V to 15V
Efficiency Up to 95%
Programmable Soft-Start
Stable with Low ESR Ceramic Output Capacitors
Cycle-by Cycle Over Current Protection
Input Under Voltage Lockout
Output Under Voltage Protection
Thermal Shutdown Protection
RoHS Compliant and Halogen Free
The RT7248 is a high efficiency, monolithic synchronous
step-down DC/DC converter that can deliver up to 2A output
current from a 4.5V to 18V input supply. The RT7248's
current mode architecture and external compensation
allow the transient response to be optimized over a wide
input range and loads. Cycle-by-cycle current limit
provides protection against shorted outputs and soft-start
eliminates input current surge during start up. The RT7248
also provides under voltage protection and thermal
shutdown protection. The low current (< 3μA) shutdown
mode provides output disconnection, enabling easy power
management in battery-powered systems. The RT7248
is available in SOP-8 (Exposed Pad) package.
Marking Information
RT7248xGSP : Product Number
RT7248x
GSPYMDNN
Applications
x : H or N
Wireless AP/Router
Set-Top-Box
Industrial and Commercial Low Power Systems
LCD Monitors and TVs
Green Electronics/Appliances
Point of Load Regulation of High-Performance DSPs
YMDNN : Date Code
Simplified Application Circuit
VIN
VIN
CIN
BOOT
CBOOT
RT7248
Chip Enable
R1
COUT
FB
CC
CSS
GND
Copyright © 2012 Richtek Technology Corporation. All rights reserved.
September 2012
VOUT
EN
SS
DS7248-01
L
SW
RC
COMP
R2
CP
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RT7248
Ordering Information
Pin Configurations
RT7248
(TOP VIEW)
Package Type
SP : SOP-8 (Exposed Pad-Option 2)
Lead Plating System
G : Green (Halogen Free and Pb Free)
H : UVP Hiccup
N : UVP Disabled
BOOT
VIN
2
SW
GND
3
GND
8
SS
7
EN
6
COMP
5
FB
9
4
SOP-8 (Exposed Pad)
Note :
Richtek products are :
`
RoHS compliant and compatible with the current requirements of IPC/JEDEC J-STD-020.
`
Suitable for use in SnPb or Pb-free soldering processes.
Functional Pin Description
Pin No.
Pin Name
Pin Function
1
BOOT
Bootstrap for High Side Gate Driver. Connect a 100nF or greater ceramic
capacitor from BOOT to SW pins.
2
VIN
Input Supply Voltage, 4.5V to 18V. Must bypass with a suitable large
ceramic capacitor.
3
SW
Phase Node. Connect this pin to external L-C filter.
4, 9 (Exposed Pad)
GND
Ground. The exposed pad must be soldered to a large PCB and connected
to GND for maximum power dissipation.
Feedback Input Pin. This pin is connected to the converter output. It is used
to set the output of the converter to regulate to the desired value via an
external resistive voltage divider. For an adjustable output, an external
resistive voltage divider is connected to this pin.
5
FB
6
COMP
Compensation Node. COMP is used to compensate the regulation control
loop. Connect a series RC network from COMP to GND. In some cases, an
additional capacitor from COMP to GND is required.
7
EN
Enable Input pin. A logic high enables the converter; a logic low forces the
IC into shutdown mode reducing the supply current to less than 3μA. Attach
this pin to VIN with a 100kΩ pull up resistor for automatic startup.
8
SS
Soft-Start Control Input. SS controls the soft-start period. Connect a
capacitor from SS to GND to set the soft-start period. A 0.1μF capacitor
sets the soft-start period to 15.5ms.
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is a registered trademark of Richtek Technology Corporation.
DS7248-01
September 2012
RT7248
Function Block Diagram
VIN
Internal
Regulator
Oscillator
Slope Comp
Shutdown
VA VCC
Comparator
1.2V
Foldback
Control
+
-
EN
5kΩ
Current Sense
Amplifier
+
-
RSENSE
0.4V
+
UV
Comparator
Lockout
Comparator
+
2.5V
VA
BOOT
Q
R
Q
SW
+
Current
Comparator
VCC
S
150mΩ
130m Ω
GND
6µA
SS
0.923V
+
+
Error Amp
FB
COMP
Operation
Shutdown Comparator
UV Comparator
Activate internal regulator once EN input level is larger
than the target level. Force IC to enter shutdown mode
when the EN input level is lower than 0.4V.
As FB voltage is lower than the UV voltage, it will activate
a UV protect scheme.
Internal Regulator
Provide internal power for logic control and switch gate
drivers.
The output voltage COMP of the error amplifier is adjusted
comparing FB signal with the internal reference voltage
and SS signal.
Lockout Comparator
Current Sense Amplifier
Activate the Current Comparator, release lock-out logic,
and enable the switches as EN input level is larger than
lockout voltage. Otherwise, the switches still locks out.
RSENSE detects the peak current of the high-side switch.
This signal is amplified by the Current Sense Amplifier
and added with a Slope Compensation. Then, it controls
the switches by comparing this signal with the COMP
voltage.
Oscillator
Error Amp
The oscillator provides internal clock and controls the
converter's switching frequency.
Foldback Control
Dynamically adjust the internal clock. It provides a slower
frequency as a lower FB voltage.
Copyright © 2012 Richtek Technology Corporation. All rights reserved.
DS7248-01
September 2012
is a registered trademark of Richtek Technology Corporation.
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RT7248
Absolute Maximum Ratings
(Note 1)
Supply Voltage, VIN ----------------------------------------------------------------------------------------------Input Voltage, SW -------------------------------------------------------------------------------------------------VBOOT − VSW --------------------------------------------------------------------------------------------------------Other Pins Voltages ----------------------------------------------------------------------------------------------Power Dissipation, PD @ TA = 25°C
SOP-8 (Exposed Pad) --------------------------------------------------------------------------------------------Package Thermal Resistance (Note 2)
SOP-8 (Exposed Pad), θJA ---------------------------------------------------------------------------------------SOP-8 (Exposed Pad), θJC --------------------------------------------------------------------------------------Junction Temperature ---------------------------------------------------------------------------------------------Lead Temperature (Soldering, 10 sec.) -----------------------------------------------------------------------Storage Temperature Range ------------------------------------------------------------------------------------ESD Susceptibility (Note 3)
HBM (Human Body Model) ---------------------------------------------------------------------------------------
Recommended Operating Conditions
−0.3V to 20V
−0.3V to (VIN + 0.3V)
−0.3V to 6V
−0.3V to 20V
1.333W
75°C
15°C
150°C
260°C
−65°C to 150°C
2kV
(Note 4)
Supply Voltage, VIN ----------------------------------------------------------------------------------------------- 4.5V to 18V
Junction Temperature Range ------------------------------------------------------------------------------------- −40°C to 125°C
Ambient Temperature Range ------------------------------------------------------------------------------------- −40°C to 85°C
Electrical Characteristics
(VIN = 12V, TA = 25°C unless otherwise specified)
Parameter
Symbol
Shutdown Supply Current
Test Conditions
Min
Typ
Max
Unit
VEN = 0V
--
0.5
3
μA
--
0.8
1.2
mA
0.909
0.923
0.937
V
--
940
--
μA/V
Supply Current
ICC
VEN = 3 V, VFB = 1V
Feedback Voltage
VFB
4.5V ≤ VIN ≤ 23V
Error Amplifier Transconductance GEA
ΔIC = ±10μA
High Side Switch-On Resistance
RDS(ON)1
--
150
--
mΩ
Low Side Switch-On Resistance
RDS(ON)2
--
130
--
mΩ
High Side Switch Leakage Current
VEN = 0V, VSW = 0V
--
0
10
μA
Upper Switch Current Limit
COMP to Current Sense
Transconductance
Oscillator Frequency
Short Circuit Oscillation
Frequency
Maximum Duty Cycle
Min.Duty Cycle, VBOOT−SW = 4.8V
--
4
--
A
GCS
--
3.7
--
A/V
fOSC1
300
340
380
kHz
fOSC2
VFB = 0V
--
100
--
kHz
DMAX
VFB = 0.7V
--
93
--
%
Minimum On-Time
tON
--
100
--
ns
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is a registered trademark of Richtek Technology Corporation.
DS7248-01
September 2012
RT7248
Parameter
EN Input Threshold
Voltage
Symbol
Test Conditions
Min
Typ
Max
Unit
Logic High
VIH
2.7
--
18
Logic Low
VIL
--
--
0.4
3.8
4.2
4.5
V
--
320
--
mV
VIN Rising
V
Input Under Voltage Lockout Threshold
VUVLO
Input Under Voltage Lockout Hysteresis
ΔVUVLO
Soft-Start Current
ISS
VSS = 0V
--
6
--
μA
Soft-Start Period
tSS
CSS = 0.1μF
--
15.5
--
ms
Thermal Shutdown
TSD
--
150
--
°C
Note 1. Stresses beyond those listed “Absolute Maximum Ratings” may cause permanent damage to the device. These are
stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the
operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions may affect
device reliability.
Note 2. θJA is measured at TA = 25°C on a high effective thermal conductivity four-layer test board per JEDEC 51-7. θJC is
measured at the exposed pad of the package.
Note 3. Devices are ESD sensitive. Handling precaution is recommended.
Note 4. The device is not guaranteed to function outside its operating conditions..
Copyright © 2012 Richtek Technology Corporation. All rights reserved.
DS7248-01
September 2012
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RT7248
Typical Application Circuit
2
VIN
4.5V to 18V
CIN
10µF
REN 100k
CSS
0.1µF
VIN
BOOT
1
RT7248
SW 3
R1
26.1k
7 EN
8 SS
4, 9 (Exposed Pad)
GND
CBOOT
L
100nF 10µH
FB 5
COMP
6
CC
3.3nF
RC
13k
VOUT
3.3V/2A
COUT
22µF x 2
R2
10k
CP
Open
Table 1. Recommended Component Selection
VOUT (V) R1 (kΩ)
R2 (kΩ)
RC (kΩ)
CC (nF)
L (μH)
COUT (μF)
8
76.8
10
27
3.3
22
22 x 2
5
45.3
10
20
3.3
15
22 x 2
3.3
26.1
10
13
3.3
10
22 x 2
2.5
16.9
10
9.1
3.3
6.8
22 x 2
1.8
9.53
10
5.6
3.3
4.7
22 x 2
1.2
3
10
3.6
3.3
3.6
22 x 2
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is a registered trademark of Richtek Technology Corporation.
DS7248-01
September 2012
RT7248
Typical Operating Characteristics
Efficiency vs. Output Current
Output Voltage vs. Input Voltage
100
3.330
90
VIN = 4.5V
VIN = 12V
VIN = 17V
70
3.320
Output Voltage (V)
Efficiency (%)
80
60
50
40
30
3.310
3.300
3.290
20
3.280
10
VOUT = 3.3V, IOUT = 1A
VOUT = 3.3V
0
3.270
0
0.25
0.5
0.75
1
1.25
1.5
1.75
2
4
6
8
Output Current (A)
0.945
3.308
0.940
3.306
Output Voltage (V)
Reference Voltage (V)
3.310
0.935
0.930
VIN = 17V
VIN = 4.5V
VIN = 12V
0.920
0.915
14
18
3.304
3.302
3.300
VIN = 4.5V
VIN = 17V
VIN = 12V
3.298
3.294
VOUT = 3.3V
VOUT = 3.3V
3.292
0.900
-50
-25
0
25
50
75
100
0
125
0.25
0.5
Temperature (°C)
0.75
1
1.25
1.5
1.75
2
Output Current (A)
Switching Frequency vs. Input Voltage
Switching Frequency vs. Temperature
380
370
370
Switching Frequency (kHz)1
380
360
350
340
330
320
310
360
350
340
VIN = 17V
VIN = 12V
VIN = 4.5V
330
320
310
VOUT = 3.3V, IOUT = 0A
300
VOUT = 3.3V
300
3
6
9
12
15
Input Voltage (V)
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DS7248-01
16
3.296
0.910
0.905
Switching Frequency (kHz)1
12
Output Voltage vs. Output Current
Reference Voltage vs. Temperature
0.950
0.925
10
Input Voltage (V)
September 2012
18
-50
-25
0
25
50
75
100
125
Temperature (°C)
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RT7248
Current Limit vs. Temperature
Load Transient Response
6.0
Current Limit (A)
5.5
VOUT
(100mV/Div)
5.0
4.5
4.0
VIN = 17V
VIN = 12V
3.5
3.0
2.5
VOUT = 3.3V
IOUT
(1A/Div)
VIN = 12V, VOUT = 3.3V, IOUT = 0A to 2A
2.0
-50
-25
0
25
50
75
100
125
Time (100μs/Div)
Temperature (°C)
Switching
Load Transient Response
VOUT
(5mV/Div)
VOUT
(100mV/Div)
VSW
(5V/Div)
IOUT
(1A/Div)
VIN = 12V, VOUT = 3.3V, IOUT = 1A to 2A
IL
(1A/Div)
Time (100μs/Div)
Time (2.5μs/Div)
Power On from VIN
Power Off from VIN
VIN
(5V/Div)
VIN
(5V/Div)
VOUT
(2V/Div)
VOUT
(2V/Div)
IL
(2A/Div)
IL
(2A/Div)
VIN = 12V, VOUT = 3.3V, IOUT = 2A
Time (10ms/Div)
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VIN = 12V, VOUT = 3.3V, IOUT = 2A
VIN = 12V, VOUT = 3.3V, IOUT = 2A
Time (10ms/Div)
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DS7248-01
September 2012
RT7248
Power On from EN
Power Off from EN
VEN
(5V/Div)
VEN
(5V/Div)
VOUT
(2V/Div)
VOUT
(2V/Div)
IL
(2A/Div)
IL
(2A/Div)
VIN = 12V, VOUT = 3.3V, IOUT = 2A
Time (10ms/Div)
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DS7248-01
September 2012
VIN = 12V, VOUT = 3.3V, IOUT = 2A
Time (10ms/Div)
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RT7248
Application Information
Output Voltage Setting
Soft-Start
The resistive divider allows the FB pin to sense the output
voltage as shown in Figure 1.
The RT7248 provides soft-start function. The soft-start
function is used to prevent large inrush current while
converter is being powered-up. The soft-start timing can
be programmed by the external capacitor between SS and
GND. An internal current source ISS (6μA) charges an
external capacitor to build a soft-start ramp voltage. The
VFB voltage will track the internal ramp voltage during softstart interval. The typical soft start time is calculated as
follows :
0.923 × CSS
Soft-Start time tSS =
, if CSS capacitor
ISS
VOUT
R1
FB
RT7248
R2
GND
Figure 1. Output Voltage Setting
The output voltage is set by an external resistive voltage
divider according to the following equation :
VOUT = VREF ⎛⎜ 1+ R1 ⎞⎟
⎝ R2 ⎠
Where VREF is the reference voltage (0.923V typ.).
External Bootstrap Diode
Connect a 100nF low ESR ceramic capacitor between
the BOOT pin and SW pin. This capacitor provides the
gate driver voltage for the high side MOSFET.
It is recommended to add an external bootstrap diode
between an external 5V and BOOT pin for efficiency
improvement when input voltage is lower than 5.5V or duty
ratio is higher than 65% .The bootstrap diode can be a
low cost one such as IN4148 or BAT54. The external 5V
can be a 5V fixed input from system or a 5V output of the
RT7248. Note that the external boot voltage must be lower
than 5.5V
5V
BOOT
100nF
RT7248
is 0.1μF, then soft-start time =
Chip Enable Operation
The EN pin is the chip enable input. Pulling the EN pin
low (<0.4V) will shut down the device. During shutdown
mode, the RT7248 quiescent current drops to lower than
3μA. Driving the EN pin high (>2.5V, <18V) will turn on
the device again. For external timing control, the EN pin
can also be externally pulled high by adding a REN resistor
and CEN capacitor from the VIN pin (see Figure 3).
EN
VIN
REN
EN
RT7248
CEN
GND
Figure 3. Enable Timing Control
An external MOSFET can be added to implement digital
control on the EN pin when no system voltage above 2.5V
is available, as shown in Figure 4. In this case, a 100kΩ
pull-up resistor, REN, is connected between VIN and the
EN pin. MOSFET Q1 will be under logic control to pull
down the EN pin.
SW
VIN
Figure 2. External Bootstrap Diode
0.923 × 0.1μ
≒ 15.5ms
6μ
EN
REN
100k
EN
Q1
RT7248
GND
Figure 4. Digital Enable Control Circuit
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is a registered trademark of Richtek Technology Corporation.
DS7248-01
September 2012
RT7248
Under Voltage Protection
Over Temperature Protection
Hiccup Mode
For the RT7248H, it provides Hiccup Mode Under Voltage
Protection (UVP). When the VFB voltage drops below 0.4V,
the UVP function will be triggered to shut down switching
operation. If the UVP condition remains for a period, the
RT7248H will retry automatically. When the UVP condition
is removed, the converter will resume operation. The UVP
is disabled during soft-start period.
Hiccup Mode
Inductor Selection
The inductor value and operating frequency determine the
ripple current according to a specific input and output
voltage. The ripple current ΔIL increases with higher VIN
and decreases with higher inductance.
VOUT
(2V/Div)
V
V
ΔIL = ⎡⎢ OUT ⎤⎥ × ⎡⎢1− OUT ⎤⎥
VIN ⎦
⎣ f ×L ⎦ ⎣
ILX
(2A/Div)
IOUT = Short
Time (25ms/Div)
Figure 5. Hiccup Mode Under Voltage Protection
Clamp Mode
For the RT7248N, it provides inductor current clamp mode.
Clamp Mode
Having a lower ripple current reduces not only the ESR
losses in the output capacitors but also the output voltage
ripple. High frequency with small ripple current can achieve
the highest efficiency operation. However, it requires a
large inductor to achieve this goal.
For the ripple current selection, the value of ΔIL = 0.24(IMAX)
will be a reasonable starting point. The largest ripple
current occurs at the highest VIN. To guarantee that the
ripple current stays below the specified maximum, the
inductor value should be chosen according to the following
equation :
⎡ VOUT ⎤ ⎡
VOUT ⎤
L =⎢
× ⎢1 −
⎥
⎥
⎣ f × ΔIL(MAX) ⎦ ⎣ VIN(MAX) ⎦
The inductor's current rating (caused a 40°C temperature
rising from 25°C ambient) should be greater than the
maximum load current and its saturation current should
be greater than the short circuit peak current limit. Please
see Table 2 for the inductor selection reference.
VOUT
(2V/Div)
ILX
(1A/Div)
IOUT = Short
Time (1ms/Div)
Figure 6. Clamp Mode
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DS7248-01
The RT7248 features an Over Temperature Protection
(OTP) circuitry to prevent from overheating due to
excessive power dissipation. The OTP will shut down
switching operation when junction temperature exceeds
150°C. Once the junction temperature cools down by
approximately 20°C, the converter will resume operation.
To maintain continuous operation, the maximum junction
temperature should be lower than 125°C.
September 2012
Table 2. Suggested Inductors for Typical
Application Circuit
Component
Supplier
Series
Dimensions
(mm)
TDK
VLF10045
10 x 9.7 x 4.5
TDK
TAIYO
YUDEN
SLF12565
12.5 x 12.5 x 6.5
NR8040
8x8x4
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RT7248
CIN and COUT Selection
The input capacitance, C IN, is needed to filter the
trapezoidal current at the source of the high side MOSFET.
To prevent large ripple current, a low ESR input capacitor
sized for the maximum RMS current should be used. The
approximate RMS current equation is given :
V
IRMS = IOUT(MAX) OUT
VIN
VIN
−1
VOUT
This formula has a maximum at VIN = 2VOUT, where
IRMS = IOUT / 2. This simple worst case condition is
commonly used for design because even significant
deviations do not offer much relief.
Choose a capacitor rated at a higher temperature than
required. Several capacitors may also be paralleled to
meet size or height requirements in the design.
For the input capacitor, two 10μF low ESR ceramic
capacitors are suggested. For the suggested capacitor,
please refer to Table 3 for more details.
The selection of COUT is determined by the required ESR
to minimize voltage ripple.
Moreover, the amount of bulk capacitance is also a key
for COUT selection to ensure that the control loop is stable.
Loop stability can be checked by viewing the load transient
response as described in a later section.
The output ripple, ΔVOUT , is determined by :
1
⎤
ΔVOUT ≤ ΔIL ⎡⎢ESR +
8fCOUT ⎥⎦
⎣
The output ripple will be the highest at the maximum input
voltage since ΔIL increases with input voltage. Multiple
capacitors placed in parallel may be needed to meet the
ESR and RMS current handling requirement. Higher values,
lower cost ceramic capacitors are now becoming available
in smaller case sizes. Their high ripple current, high voltage
rating and low ESR make them ideal for switching regulator
applications. However, care must be taken when these
capacitors are used at input and output. When a ceramic
capacitor is used at the input and the power is supplied
by a wall adapter through long wires, a load step at the
output can induce ringing at the input, VIN. At best, this
ringing can couple to the output and be mistaken as loop
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instability. At worst, a sudden inrush of current through
the long wires can potentially cause a voltage spike at
VIN large enough to damage the part.
Thermal Considerations
For continuous operation, do not exceed the maximum
operation junction temperature 125°C. The maximum
power dissipation depends on the thermal resistance of
IC package, PCB layout, the rate of surroundings airflow
and temperature difference between junction to ambient.
The maximum power dissipation can be calculated by
following formula :
PD(MAX) = (TJ(MAX) − TA ) / θJA
Where T J(MAX) is the maximum operation junction
temperature , TA is the ambient temperature and the θJA is
the junction to ambient thermal resistance.
For recommended operating conditions specification, the
maximum junction temperature is 125°C. The junction to
ambient thermal resistance θJA is layout dependent. For
SOP-8 (Exposed Pad) package, the thermal resistance
θJA is 75°C/W on the standard JEDEC 51-7 four-layers
thermal test board. The maximum power dissipation at
TA = 25°C can be calculated by following formula :
P D(MAX) = (125°C − 25°C) / (75°C/W) = 1.333W
(min.copper area PCB layout)
P D(MAX) = (125°C − 25°C) / (49°C/W) = 2.04W
(70mm2copper area PCB layout)
The thermal resistance θJA of SOP-8 (Exposed Pad) is
determined by the package architecture design and the
PCB layout design. However, the package architecture
design has been designed. If possible, it's useful to
increase thermal performance by the PCB layout copper
design. The thermal resistance θJA can be decreased by
adding copper area under the exposed pad of SOP-8
(Exposed Pad) package.
As shown in Figure 7, the amount of copper area to which
the SOP-8 (Exposed Pad) is mounted affects thermal
performance. When mounted to the standard
SOP-8 (Exposed Pad) pad (Figure 7.a), θJA is 75°C/W.
Adding copper area of pad under the SOP-8 (Exposed
Pad) (Figure 7.b) reduces the θJA to 64°C/W. Even further,
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DS7248-01
September 2012
RT7248
increasing the copper area of pad to 70mm2 (Figure 7.e)
reduces the θJA to 49°C/W.
The maximum power dissipation depends on operating
ambient temperature for fixed T J(MAX) and thermal
resistance θJA. The Figure 8 of derating curves allows the
designer to see the effect of rising ambient temperature
on the maximum power dissipation allowed.
(a) Copper Area = (2.3 x 2.3) mm2, θJA = 75°C/W
2.2
Four-Layer PCB
Power Dissipation (W)
2.0
1.8
Copper Area
70mm2
50mm2
30mm2
10mm2
Min.Layout
1.6
1.4
1.2
1.0
0.8
(b) Copper Area = 10mm2, θJA = 64°C/W
0.6
0.4
0.2
0.0
0
25
50
75
100
125
Ambient Temperature (°C)
Figure 8. Derating Curve of Maximum Power Dissipation
(c) Copper Area = 30mm2 , θJA = 54°C/W
(d) Copper Area = 50mm2 , θJA = 51°C/W
(e) Copper Area = 70mm2 , θJA = 49°C/W
Figure 7. Themal Resistance vs. Copper Area Layout
Design
Copyright © 2012 Richtek Technology Corporation. All rights reserved.
DS7248-01
September 2012
is a registered trademark of Richtek Technology Corporation.
www.richtek.com
13
RT7248
away from the SW node to prevent stray capacitive noise
pick-up.
Layout Consideration
Follow the PCB layout guidelines for optimal performance
of the RT7248.
`
Keep the traces of the main current paths as short and
wide as possible.
`
Put the input capacitor as close as possible to the device
pins (VIN and GND).
`
SW node is with high frequency voltage swing and
should be kept at small area. Keep analog components
VIN
GND
`
Connect feedback network behind the output capacitors.
Keep the loop area small. Place the feedback
components near the RT7248.
`
An example of PCB layout guide is shown in Figure 9
for reference.
SW GND
VIN
CBOOT
Input capacitor must
be placed as close
to the IC as possible.
8
BOOT
L
VOUT
REN
CSS
CIN
VIN
2
SW
3
GND
4
GND
CC
SS
7
EN
6
COMP
5
FB
9
The feedback components
must be connected as close
to the device as possible.
CP
RC
R1
R2
COUT
VOUT
GND
SW node is with high frequency voltage swing and should
be kept at small area. Keep analog components away from
the SW node to prevent stray capacitive noise pick-up
Figure 9. PCB Layout Guide
Table 3. Suggested Capacitors for CIN and COUT
Location
Component Supplier
Part No.
Capacitance (μF)
Case Size
CIN
MURATA
GRM31CR61E106K
10
1206
CIN
TDK
C3225X5R1E106K
10
1206
CIN
TAIYO YUDEN
TMK316BJ106ML
10
1206
COUT
MURATA
GRM31CR60J476M
47
1206
COUT
TDK
C3225X5R0J476M
47
1210
COUT
MURATA
GRM32ER71C226M
22
1210
COUT
TDK
C3225X5R1C22M
22
1210
Copyright © 2012 Richtek Technology Corporation. All rights reserved.
www.richtek.com
14
is a registered trademark of Richtek Technology Corporation.
DS7248-01
September 2012
RT7248
Outline Dimension
H
A
M
EXPOSED THERMAL PAD
(Bottom of Package)
Y
J
X
B
F
C
I
D
Dimensions In Millimeters
Symbol
Dimensions In Inches
Min
Max
Min
Max
A
4.801
5.004
0.189
0.197
B
3.810
4.000
0.150
0.157
C
1.346
1.753
0.053
0.069
D
0.330
0.510
0.013
0.020
F
1.194
1.346
0.047
0.053
H
0.170
0.254
0.007
0.010
I
0.000
0.152
0.000
0.006
J
5.791
6.200
0.228
0.244
M
0.406
1.270
0.016
0.050
X
2.000
2.300
0.079
0.091
Y
2.000
2.300
0.079
0.091
X
2.100
2.500
0.083
0.098
Y
3.000
3.500
0.118
0.138
Option 1
Option 2
8-Lead SOP (Exposed Pad) Plastic Package
Richtek Technology Corporation
5F, No. 20, Taiyuen Street, Chupei City
Hsinchu, Taiwan, R.O.C.
Tel: (8863)5526789
Richtek products are sold by description only. Richtek reserves the right to change the circuitry and/or specifications without notice at any time. Customers should
obtain the latest relevant information and data sheets before placing orders and should verify that such information is current and complete. Richtek cannot
assume responsibility for use of any circuitry other than circuitry entirely embodied in a Richtek product. Information furnished by Richtek is believed to be
accurate and reliable. However, no responsibility is assumed by Richtek or its subsidiaries for its use; nor for any infringements of patents or other rights of third
parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Richtek or its subsidiaries.
DS7248-01
September 2012
www.richtek.com
15