RICHTEK RT8859M

®
RT8859M
Multi-Phase PWM Controller for CPU Core Power Supply
General Description
Features
The RT8859M is a VR12/IMVP7 compliant CPU power
controller which includes two voltage rails : a 4/3/2/1 phase
synchronous buck controller, the CORE VR, and a single
phase buck controller, the AXG VR. The RT8859M adopts
G-NAVP TM (Green Native AVP), which is Richtek's
z
proprietary topology derived from finite DC gain
compensator with current mode control, making it an easy
setting PWM controller, meeting all Intel CPU
requirements of AVP (Active Voltage Positioning). Based
on the G-NAVPTM topology, the RT8859M also features a
quick response mechanism for optimized AVP performance
during load transient. The RT8859M supports mode
transition function with various operating states. A serial
VID (SVID) interface is built in the RT8859M to
communicate with Intel VR12/IMVP7 compliant CPU. The
RT8859M supports VID on-the-fly function with three
different slew rates: Fast, Slow and Decay. By utilizing
the G-NAVPTM topology, the operating frequency of the
RT8859M varies with VID, load and input voltage to further
enhance the efficiency even in CCM. The built-in high
accuracy DAC converts the SVID code ranging from 0.25V
to 1.52V with 5mV per step. The RT8859M integrates a
high accuracy ADC for platform setting functions, such as
no-load offset or over-current level. The RT8859M provides
VR ready output signals of both CORE VR and AXG VR.
It also features complete fault protection functions
including over voltage, under voltage, negative voltage, over
current and under voltage lockout. The RT8859M is
available in a WQFN-56L 7x7 small foot print package.
z
Applications
z
z
z
VR12 / IMVP7 Intel Core Supply
Notebook/ Desktop Computer/ Servers Multi-phase CPU
Core Supply
AVP Step-Down Converter
Copyright © 2012 Richtek Technology Corporation. All rights reserved.
DS8859M-05 July 2012
z
z
z
z
z
z
z
z
z
z
z
z
z
z
z
z
z
z
z
4/3/2/1 + 1 Phase PWM Controller
G-NAVPTM Topology
Serial VID Interface
0.5% DAC Accuracy
Differential Remote Voltage Sensing
Built-in ADC for Platform Programming
Accurate Current Balance
System Thermal Compensated AVP
Diode Emulation Mode at Light Load Condition for
Multiple and Single Phase
Fast Transient Response
VR12 / IMVP7 Compatible Power Management
States
VR Ready Indicator
Thermal Throttling
Current Monitor Output
Switching Frequency up to 1MHz per Phase
OVP, UVP, OCP, NVP, UVLO
Slew Rate Setting/Address Flip Function
External No-Load Offset Setting for both Rails
DVID Improvement
Small 56-Lead WQFN Package
RoHS Compliant and Halogen Free
Ordering Information
RT8859M
Package Type
QW : WQFN-56L 7x7 (W-Type)
Lead Plating System
G : Green (Halogen Free and Pb Free)
Z : ECO (Ecological Element with
Halogen Free and Pb free)
Note :
Richtek products are :
`
RoHS compliant and compatible with the current
requirements of IPC/JEDEC J-STD-020.
`
Suitable for use in SnPb or Pb-free soldering processes.
is a registered trademark of Richtek Technology Corporation.
www.richtek.com
1
RT8859M
Pin Configurations
Marking Information
(TOP VIEW)
DVIDA
QRSET
PWM2
PWM1
PWM3
PWM4
TONSET
TONSETA
DVD
DVDA
VRHOT
TSEN
TSENA
OCSET
RT8859MGQW
RT8859MGQW : Product Number
RT8859M
GQW
YMDNN
56 55 54 53 52 51 50 49 48 47 46 45 44 43
ISEN2P
ISEN2N
ISEN1N
ISEN1P
ISEN3P
ISEN3N
ISEN4N
ISEN4P
RSET
COMP
FB
RGND
DVID
OFS
1
42
2
41
3
40
4
39
5
38
6
37
7
36
GND
8
35
34
9
33
10
57
11
32
31
12
13
30
14
29
OCSETA
VCC
VR_RDY
VRA_RDY
EN
PWMA
QRSETA
ISENAP
ISENAN
COMPA
FBA
RGNDA
OFSA
SR_ADDF
YMDNN : Date Code
RT8859MZQW
RT8859MZQW : Product Number
RT8859M
ZQW
YMDNN
YMDNN : Date Code
IMON
IMONFB
ADD
VCLK
VDIO
ALERT
IBIAS
SETINI
SETINIA
TMPMAX
ICCMAX
ICCMAXA
IMONFBA
IMONA
15 16 17 18 19 20 21 22 23 24 25 26 27 28
WQFN-56L 7x7
Copyright © 2012 Richtek Technology Corporation. All rights reserved.
www.richtek.com
2
is a registered trademark of Richtek Technology Corporation.
DS8859M-05 July 2012
Copyright © 2012 Richtek Technology Corporation. All rights reserved.
DS8859M-05 July 2012
VSSAXG_SENSE
LOAD
12V
12V
12V
12V
VCCAXG_SENSE
12V
VIN
12V
RNTC
5V
VIN
12V
VCC
PWM
VCC
PWM
VCC
12V
12V
12V
5V
Chip Enable
PWM
LGATE
RT9612
PHASE
UGATE PGND
BOOT
RT9612
LGATE
PHASE
UGATE PGND
BOOT
RT9612
LGATE
PHASE
UGATE PGND
BOOT
RNTC
TONSETA
PWMA
38 EN
1 ISEN2P
2 ISEN2N
54 PWM2
4 ISEN1P
3 ISEN1N
53 PWM1
35 ISENAP
34 ISENAN
31
RGNDA
37
41 VCC
10
12V
VCCIO
12V
BOOT
RNTC
RNTC
RNTC
LGATE
PHASE
BOOT
PHASE
LGATE
RT9612
PWM
PGND UGATE
VCC
RT9612
PWM
5V
5V
5V
ALERT
VDIO
VCLK
VR_RDY
VRA_RDY
PGND UGATE
VCC
ISEN4P 8
ISEN4N 7
12
RGND
57 (Exposed Pad)
GND
PWM4 51
ADD 17
ISEN3P 5
6
ISEN3N
PWM3 52
VRHOT 46
FB 11
COMP
IMONFB 16
TSEN 45
IBIAS 21
IMON 15
OCSET 43
33 COMPA
32
FBA
25
26
29
30
36
55
14
22
23
24
OCSETA 42
OFS
SETINI
SETINIA
TMPMAX
ICCMAX
ICCMAXA
SR_ADDF
OFSA
QRSETA
QRSET
27 IMONFBA
44 TSENA
48 DVD
47 DVDA
56 DVIDA
13 DVID
VCLK 18
VDIO 19
20
ALERT
VRA_RDY 39
VR_RDY 40
RT8859M
TONSET
9 RSET
28 IMONA
49
50
VCCIO
12V
12V
RNTC
VCC_SENSE
5V
VSS_SENSE
LOAD
RT8859M
Typical Application Circuit
Thermal Compensation at Voltage Loop
is a registered trademark of Richtek Technology Corporation.
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3
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4
LOAD
Copyright © 2012 Richtek Technology Corporation. All rights reserved.
VSSAXG_SENSE
RNTC
VCCAXG_SENSE
12V
12V
12V
12V
12V
VIN
12V
5V
VCC
PWM
VCC
PWM
12V
12V
12V
5V
Chip Enable
PWM
LGATE
RT9612
PHASE
UGATE PGND
BOOT
VCC
RT9612
LGATE
PHASE
UGATE PGND
BOOT
RT9612
LGATE
PHASE
UGATE PGND
BOOT
RNTC
VIN
12V
FBA
PWMA
38 EN
1 ISEN2P
2 ISEN2N
54 PWM2
4 ISEN1P
3 ISEN1N
53 PWM1
34 ISENAN
31
RGNDA
35 ISENAP
37
41 VCC
32
33 COMPA
27 IMONFBA
48 DVD
47 DVDA
44 TSENA
56 DVIDA
14 OFS
28 IMONA
9 RSET
25
26
29
30
36
55
14
22
23
24
10
12V
VCCIO
12V
BOOT
RNTC
RNTC
LGATE
PHASE
BOOT
PHASE
LGATE
RT9612
PWM
PGND UGATE
VCC
RT9612
PWM
5V
5V
ALERT
VDIO
VCLK
VR_RDY
VRA_RDY
PGND UGATE
VCC
ISEN4P 8
ISEN4N 7
12
RGND
57 (Exposed Pad)
GND
PWM4 51
ADD 17
ISEN3P 5
6
ISEN3N
PWM3 52
VRHOT 46
FB 11
COMP
IMONFB 16
TSEN 45
IBIAS 21
IMON 15
OCSET 43
OCSETA 42
ICCMAX
ICCMAXA
SR_ADDF
OFSA
QRSETA
QRSET
OFS
SETINI
SETINIA
TMPMAX
VCLK 18
VDIO 19
20
ALERT
VRA_RDY 39
VR_RDY 40
RT8859M
TONSET
49 TONSETA
50
VCCIO
12V
12V
RNTC
VCC_SENSE
5V
VSS_SENSE
LOAD
RT8859M
Thermal Compensation at Current Loop
is a registered trademark of Richtek Technology Corporation.
DS8859M-05 July 2012
Copyright © 2012 Richtek Technology Corporation. All rights reserved.
DS8859M-05 July 2012
12V
12V
Chip Enable
12V
5V
*
VCC
PWM
VCC
RNTC
12V
12V
5V
* : Optional
DVID
13
TONSETA
GND
EN
43 OCSET
38
1 ISEN2P
2 ISEN2N
54 PWM2
49
4 ISEN1P
3 ISEN1N
28 IMONA
53 PWM1
41 VCC
10
ISEN4P 8
ISEN4N 7
12
RGND
PWM4 51
ADD 17
ISEN3P 5
6
ISEN3N
PWM3 52
VRHOT 46
FB 11
COMP
SETINIA
OFS 14
26 ICCMAXA SR_ADDF 29
27 IMONFBA
36 QRSETA
VR_RDY 40
37
VCLK 18
PWMA
42 OCSETA
VDIO 19
30
20
OFSA
ALERT
31
RGNDA
SETINI 22
32
FBA
TMPMAX 24
25
33 COMPA
ICCMAX
39
QRSET 55
VRA_RDY
56
DVIDA
DVD 48
34 ISENAN
IBIAS 21
35
IMON 15
ISENAP
44
TSENA
47 DVDA
IMONFB 16
TSEN 45
23
57 (Exposed Pad)
PWM
LGATE
RT9619
PHASE
UGATE PGND
BOOT
*
RT9619
LGATE
PHASE
UGATE PGND
BOOT
5V
Floating
RT8859M
TONSET
9 RSET
50
12V
5V
12V
BOOT
LGATE
PHASE
BOOT
PHASE
LGATE
RT9619
PWM
PGND UGATE
VCC
*
RT9619
PWM
PGND UGATE
VCC
*
RNTC
VTT
VTT
5V
12V
5V
5V
12V
12V
RNTC
VCC_SENSE
5V
VSS_SENSE
LOAD
RT8859M
AXG VR Disabled
is a registered trademark of Richtek Technology Corporation.
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5
RT8859M
Functional Pin Description
Pin No.
Pin Name
Pin Function
4, 1, 5, 8
ISEN [1:4] P
Positive Current Sense Pin of Phase 1, 2, 3 and 4.
3, 2, 6, 7
ISEN [1:4] N
Negative Current Sense Pin of Phase 1, 2, 3 and 4.
9
RSET
Multi-Phase CORE VR Ramp Setting. This is used to set the multi-phase
CORE VR loop external ramp slope.
10
COMP
Multi-Phase CORE VR Compensation. This pin is the output node of the error
amplifier.
11
FB
Multi-Phase CORE VR Feedback. This is the negative input node of the error
amplifier.
12
RGND
Return Ground for Multi-Phase CORE VR. This pin is the negative node of the
differential remote voltage sensing.
13
DVID
Connect a resistor and a capacitor from this pin to GND to improve DVID
performance. Short this pin to GND if this function is not needed.
14
OFS
15
IMON
16
IMONFB
17
ADD
Output Voltage Offset Setting.
Current Monitor Output. This pin outputs a voltage proportional to the output
current.
Current Monitor Output Gain External Setting. Connect this pin with one resistor
to CPU VCC_SENSE, while the IMON pin is connected to ground with another
resistor. The current monitor output gain can be set by the ratio of these two
resistors.
VR Address Setting Pin.
18
VCLK
Synchronous Clock from CPU.
19
VDIO
Controller and CPU Data Transmission Interface.
20
ALERT
SVID Alert Pin (Active Low).
21
IBIAS
Internal Bias Current Setting. Connect this pin to GND via a resistor to set the
internal current.
22
SETINI
CORE VR VINITIAL Setting.
23
SETINIA
AXG VR VINITIALA Setting.
24
TMPMAX
25
ICCMAX
26
ICCMAXA
ADC Input for Single-Phase AXG VR Maximum Current Setting.
27
IMONFBA
Single-Phase AXG VR Current Monitor Output Gain External Setting. Connect
this pin with one resistor to AXG rail VCCAXG_SENSE, while IMONA pin is
connected to ground with another resistor. The current monitor output gain can
be set by the ratio of these two resistors.
28
IMONA
Single-Phase AXG VR Current Monitor Output. This pin outputs a voltage
proportional to the output current.
29
SR_ADDF
Address Flip and DVID Slew Rate Setting. Set the pin to GND if fast slew rate=
10mV/μs and slow slew rate = 2.5mV/μs is used.
30
OFSA
31
RGNDA
ADC Input for Multi-Phase CORE VR Maximum Temperature Setting. This pin
is also used for AXG VR’s offset selection.
ADC Input for Multi-Phase CORE VR Maximum Current Setting. This pin is also
used for CORE VR’s offset selection.
AXG VR Output Voltage Offset Setting.
Return Ground for Single-Phase AXG VR. This pin is the negative node of the
differential remote voltage sensing.
Copyright © 2012 Richtek Technology Corporation. All rights reserved.
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is a registered trademark of Richtek Technology Corporation.
DS8859M-05 July 2012
RT8859M
Pin No.
32
FBA
33
COMPA
34
35
36
ISENAN
ISENAP
QRSETA
Pin Function
Single-Phase AXG VR Feedback. This is the negative input node of the
error amplifier.
Single-Phase AXG VR Compensation. This pin is the output node of the
error amplifier.
Negative Current Sense Pin of Single-Phase AXG VR.
Positive Current Sense Pin of Single-Phase AXG VR.
Single-Phase AXG VR Quick Response Time Setting.
37
PW MA
PWM Output for Single-Phase AXG VR.
38
EN
Chip Enable (Active High)
39
VRA_RDY
VR Ready Indicator of Single-Phase AXG VR.
40
VR_RDY
VR Ready Indicator of Multi-Phase CORE VR.
41
VCC
Chip Power. Connect this pin to 5V via an RC filter.
OCSETA
Single-Phase AXG VR Over Current Protection Setting. Place a
resistive voltage divider between VCC and ground and connect the joint
of the voltage divider to the OCSETA pin. The voltage at the OCSET pin
determines the over current threshold, ILIMITA .
43
OCSET
Multi-Phase CORE VR Over Current Protection Setting. Place a
resistive voltage divider between VCC and ground and connect the joint
of the voltage divider to the OCSET pin. The voltage at the OCSET pin
determines the over current threshold, ILIMIT.
44
TSENA
Thermal Monitor Sense Point of AXG VR.
45
TSEN
Thermal Monitor Sense Point of CORE VR.
46
VRHOT
Thermal Monitor Output (Active Low).
47
DVDA
48
DVD
49
TONSETA
50
TONSET
42
51, 52, 54, 53
Pin Name
Divided Voltage Detection of AXG VR. Connect this pin to a voltage
divider from the single-phase power stage input power for input voltage
detection.
Divided Voltage Detection of CORE VR. Connect this pin to a voltage
divider from the multi-phase power stage input power for input voltage
detection.
Single-Phase AXG VR On-Time Setting. Connect this pin to VIN with
one resistor to set ripple size in PWM mode.
Multi-Phase CORE VR On-Time Setting. Connect this pin to VIN with
one resistor to set ripple size in PWM mode.
PW M [4 :1]
PWM Output for CH1, 2, 3 and 4.
55
QRSET
Multi-Phase CORE VR Quick Response Time Setting.
56
DVIDA
57 (Exposed Pad)
GND
Connect a resistor and a capacitor from this pin to GND to improve
DVID performance. Short this pin to GND if this function is not needed.
Ground. The exposed pad must be soldered to a large PCB and
connected to GND for maximum power dissipation.
Copyright © 2012 Richtek Technology Corporation. All rights reserved.
DS8859M-05 July 2012
is a registered trademark of Richtek Technology Corporation.
www.richtek.com
7
RT8859M
IMON
Current
Monitor
Current
Monitor
VSET
VSETA
Offset
Generator
VR_RDY
UVLO
GND
ADC
DAC
Control &
Protection Logic
+
SVID XCVR
Soft-Start & Slew
Rate Control
VRA_RDY
DVDA
DVD
VCC
EN
ALERT
VDIO
VCLK
ADD
VRHOT
ICCMAXA
TSENA
TSEN
SR_ADDF
MUX
From Control Logic
RGNDA
ICCMAX
SETINIA
SETINI
TMPMAX
OFSA
IMONFBA
IMONA
IMONFB
Function Block Diagram
VSETA
FBA
COMPA
ERROR
AMP
+
PWM
CMP
+
Offset
Cancellation
-
QRSET
QRSETA
TON
Gen
PWMA
-
TONSETA
Set VIDA
Fast & Slow
DVIDA
Set VID
Fast & Slow
1/20
DVID
OVP/UVP/NVP
From Control Logic
OFS
To Protection Logic
1/20
Offset
Generator
ISENAP
ISENAN
+
20
-
OCP
OCSETA
DAC
Soft-Start & Slew
Rate Control
FB
+
RGND
VSET
+
-
COMP
+
Offset
Cancellation
PWM
CMP
TONSET
PWM1
-
+
+
TON
Gen
QR
CMP
-
PHASE
Selector
PWM2
PWM3
PWM4
VQR_TRIP
IBIAS
RSET
ISEN4P
ISEN4N
+
ISEN3P
ISEN3N
+
-
-
10
Current Balance
SUM
10
ISEN2P
+
ISEN2N
-
ISEN1P
+
10
-
ISEN1N
To Protection Logic
OVP/UVP/NVP
OCP
10
OCSET
Copyright © 2012 Richtek Technology Corporation. All rights reserved.
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is a registered trademark of Richtek Technology Corporation.
DS8859M-05 July 2012
RT8859M
Table 1. VR12 VID Code Table
VID7
VID6
VID5
VID4
VID3
VID2
VID1
VID0
0
0
0
0
0
0
0
0
0
0
0.000
0
0
0
0
0
0
0
1
0
1
0.250
0
0
0
0
0
0
1
0
0
2
0.255
0
0
0
0
0
0
1
1
0
3
0.260
0
0
0
0
0
0
0
0
0
0
1
1
0
0
0
1
0
0
4
5
0.265
0.270
0
0
0
0
0
1
1
0
0
6
0.275
0
0
0
0
0
1
1
1
0
7
0.280
0
0
0
0
1
0
0
0
0
8
0.285
0
0
0
0
0
0
0
0
1
1
0
0
0
1
1
0
0
0
9
A
0.290
0.295
0
0
0
0
1
0
1
1
0
B
0.300
0
0
0
0
1
1
0
0
0
C
0.305
0
0
0
0
1
1
0
1
0
D
0.310
0
0
0
0
0
0
0
0
1
1
1
1
1
1
0
1
0
0
E
F
0.315
0.320
0
0
0
1
0
0
0
0
1
0
0.325
0
0
0
1
0
0
0
1
1
1
0.330
0
0
0
1
0
0
1
0
1
2
0.335
0
0
0
0
0
0
1
1
0
0
0
1
1
0
1
0
1
1
3
4
0.340
0.345
0
0
0
1
0
1
0
1
1
5
0.350
0
0
0
1
0
1
1
0
1
6
0.355
0
0
0
1
0
1
1
1
1
7
0.360
0
0
0
0
0
0
1
1
1
1
0
0
0
0
0
1
1
1
8
9
0.365
0.370
0
0
0
1
1
0
1
0
1
A
0.375
0
0
0
1
1
0
1
1
1
B
0.380
0
0
0
1
1
1
0
0
1
C
0.385
0
0
0
1
1
1
0
1
1
D
0.390
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
1
1
1
E
F
0.395
0.400
0
0
1
0
0
0
0
0
2
0
0.405
0
0
1
0
0
0
0
1
2
1
0.410
0
0
1
0
0
0
1
0
2
2
0.415
0
0
0
0
1
1
0
0
0
0
0
1
1
0
1
0
2
2
3
4
0.420
0.425
0
0
1
0
0
1
0
1
2
5
0.430
0
0
1
0
0
1
1
0
2
6
0.435
0
0
1
0
0
1
1
1
2
7
0.440
0
0
1
0
1
0
0
0
2
8
0.445
Copyright © 2012 Richtek Technology Corporation. All rights reserved.
DS8859M-05 July 2012
Hex
Voltage
is a registered trademark of Richtek Technology Corporation.
www.richtek.com
9
RT8859M
VID7
VID6
VID5
VID4
VID3
VID2
VID1
VID0
0
0
1
0
1
0
0
1
2
9
0.450
0
0
1
0
1
0
1
0
2
A
0.455
0
0
1
0
1
0
1
1
2
B
0.460
0
0
1
0
1
1
0
0
2
C
0.465
0
0
0
0
1
1
0
0
1
1
1
1
0
1
1
0
2
2
D
E
0.470
0.475
0
0
1
0
1
1
1
1
2
F
0.480
0
0
1
1
0
0
0
0
3
0
0.485
0
0
1
1
0
0
0
1
3
1
0.490
0
0
0
0
1
1
1
1
0
0
0
0
1
1
0
1
3
3
2
3
0.495
0.500
0
0
1
1
0
1
0
0
3
4
0.505
0
0
1
1
0
1
0
1
3
5
0.510
0
0
1
1
0
1
1
0
3
6
0.515
0
0
0
0
1
1
1
1
0
1
1
0
1
0
1
0
3
3
7
8
0.520
0.525
0
0
1
1
1
0
0
1
3
9
0.530
0
0
1
1
1
0
1
0
3
A
0.535
0
0
1
1
1
0
1
1
3
B
0.540
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
1
3
3
C
D
0.545
0.550
0
0
1
1
1
1
1
0
3
E
0.555
0
0
1
1
1
1
1
1
3
F
0.560
0
1
0
0
0
0
0
0
4
0
0.565
0
0
1
1
0
0
0
0
0
0
0
0
0
1
1
0
4
4
1
2
0.570
0.575
0
1
0
0
0
0
1
1
4
3
0.580
0
1
0
0
0
1
0
0
4
4
0.585
0
1
0
0
0
1
0
1
4
5
0.590
0
1
0
0
0
1
1
0
4
6
0.595
0
0
1
1
0
0
0
0
0
1
1
0
1
0
1
0
4
4
7
8
0.600
0.605
0
1
0
0
1
0
0
1
4
9
0.610
0
1
0
0
1
0
1
0
4
A
0.615
0
1
0
0
1
0
1
1
4
B
0.620
0
0
1
1
0
0
0
0
1
1
1
1
0
0
0
1
4
4
C
D
0.625
0.630
0
1
0
0
1
1
1
0
4
E
0.635
0
1
0
0
1
1
1
1
4
F
0.640
0
1
0
1
0
0
0
0
5
0
0.645
0
0
1
1
0
0
1
1
0
0
0
0
0
1
1
0
5
5
1
2
0.650
0.655
Copyright © 2012 Richtek Technology Corporation. All rights reserved.
www.richtek.com
10
Hex
Voltage
is a registered trademark of Richtek Technology Corporation.
DS8859M-05 July 2012
RT8859M
VID7
VID6
VID5
VID4
VID3
VID2
VID1
VID0
0
1
0
1
0
0
1
1
5
3
0.660
0
1
0
1
0
1
0
0
5
4
0.665
0
1
0
1
0
1
0
1
5
5
0.670
0
1
0
1
0
1
1
0
5
6
0.675
0
1
0
1
0
1
1
1
5
7
0.680
0
1
0
1
1
0
0
0
5
8
0.685
0
1
0
1
1
0
0
1
5
9
0.690
0
1
0
1
1
0
1
0
5
A
0.695
0
1
0
1
1
0
1
1
5
B
0.700
0
1
0
1
1
1
0
0
5
C
0.705
0
1
0
1
1
1
0
1
5
D
0.710
0
1
0
1
1
1
1
0
5
E
0.715
0
1
0
1
1
1
1
1
5
F
0.720
0
1
1
0
0
0
0
0
6
0
0.725
0
1
1
0
0
0
0
1
6
1
0.730
0
1
1
0
0
0
1
0
6
2
0.735
0
1
1
0
0
0
1
1
6
3
0.740
0
1
1
0
0
1
0
0
6
4
0.745
0
1
1
0
0
1
0
1
6
5
0.750
0
1
1
0
0
1
1
0
6
6
0.755
0
1
1
0
0
1
1
1
6
7
0.760
0
1
1
0
1
0
0
0
6
8
0.765
0
1
1
0
1
0
0
1
6
9
0.770
0
1
1
0
1
0
1
0
6
A
0.775
0
1
1
0
1
0
1
1
6
B
0.780
0
1
1
0
1
1
0
0
6
C
0.785
0
1
1
0
1
1
0
1
6
D
0.790
0
1
1
0
1
1
1
0
6
E
0.795
0
1
1
0
1
1
1
1
6
F
0.800
0
1
1
1
0
0
0
0
7
0
0.805
0
1
1
1
0
0
0
1
7
1
0.810
0
1
1
1
0
0
1
0
7
2
0.815
0
1
1
1
0
0
1
1
7
3
0.820
0
1
1
1
0
1
0
0
7
4
0.825
0
1
1
1
0
1
0
1
7
5
0.830
0
1
1
1
0
1
1
0
7
6
0.835
0
1
1
1
0
1
1
1
7
7
0.840
0
1
1
1
1
0
0
0
7
8
0.845
0
1
1
1
1
0
0
1
7
9
0.850
0
1
1
1
1
0
1
0
7
A
0.855
0
1
1
1
1
0
1
1
7
B
0.860
Copyright © 2012 Richtek Technology Corporation. All rights reserved.
DS8859M-05 July 2012
Hex
Voltage
is a registered trademark of Richtek Technology Corporation.
www.richtek.com
11
RT8859M
VID7
VID6
VID5
VID4
VID3
VID2
VID1
VID0
Hex
Voltage
0
1
1
1
1
1
0
0
7
C
0.865
0
1
1
1
1
1
0
1
7
D
0.870
0
1
1
1
1
1
1
0
7
E
0.875
0
1
1
1
1
1
1
1
7
F
0.880
1
0
0
0
0
0
0
0
8
0
0.885
1
0
0
0
0
0
0
1
8
1
0.890
1
0
0
0
0
0
1
0
8
2
0.895
1
0
0
0
0
0
1
1
8
3
0.900
1
0
0
0
0
1
0
0
8
4
0.905
1
0
0
0
0
1
0
1
8
5
0.910
1
0
0
0
0
1
1
0
8
6
0.915
1
0
0
0
0
1
1
1
8
7
0.920
1
0
0
0
1
0
0
0
8
8
0.925
1
0
0
0
1
0
0
1
8
9
0.930
1
0
0
0
1
0
1
0
8
A
0.935
1
0
0
0
1
0
1
1
8
B
0.940
1
0
0
0
1
1
0
0
8
C
0.945
1
0
0
0
1
1
0
1
8
D
0.950
1
0
0
0
1
1
1
0
8
E
0.955
1
0
0
0
1
1
1
1
8
F
0.960
1
0
0
1
0
0
0
0
9
0
0.965
1
0
0
1
0
0
0
1
9
1
0.970
1
0
0
1
0
0
1
0
9
2
0.975
1
0
0
1
0
0
1
1
9
3
0.980
1
0
0
1
0
1
0
0
9
4
0.985
1
0
0
1
0
1
0
1
9
5
0.990
1
0
0
1
0
1
1
0
9
6
0.995
1
0
0
1
0
1
1
1
9
7
1.000
1
0
0
1
1
0
0
0
9
8
1.005
1
0
0
1
1
0
0
1
9
9
1.010
1
0
0
1
1
0
1
0
9
A
1.015
1
0
0
1
1
0
1
1
9
B
1.020
1
0
0
1
1
1
0
0
9
C
1.025
1
0
0
1
1
1
0
1
9
D
1.030
1
0
0
1
1
1
1
0
9
E
1.035
1
0
0
1
1
1
1
1
9
F
1.040
1
0
1
0
0
0
0
0
A
0
1.045
1
0
1
0
0
0
0
1
A
1
1.050
1
0
1
0
0
0
1
0
A
2
1.055
1
0
1
0
0
0
1
1
A
3
1.060
1
0
1
0
0
1
0
0
A
4
1.065
Copyright © 2012 Richtek Technology Corporation. All rights reserved.
www.richtek.com
12
is a registered trademark of Richtek Technology Corporation.
DS8859M-05 July 2012
RT8859M
VID7
VID6
VID5
VID4
VID3
VID2
VID1
VID0
1
0
1
0
0
1
0
1
A
5
1.070
1
0
1
0
0
1
1
0
A
6
1.075
1
0
1
0
0
1
1
1
A
7
1.080
1
0
1
0
1
0
0
0
A
8
1.085
1
0
1
0
1
0
0
1
A
9
1.090
1
0
1
0
1
0
1
0
A
A
1.095
1
0
1
0
1
0
1
1
A
B
1.100
1
0
1
0
1
1
0
0
A
C
1.105
1
0
1
0
1
1
0
1
A
D
1.110
1
0
1
0
1
1
1
0
A
E
1.115
1
0
1
0
1
1
1
1
A
F
1.120
1
0
1
1
0
0
0
0
B
0
1.125
1
0
1
1
0
0
0
1
B
1
1.130
1
0
1
1
0
0
1
0
B
2
1.135
1
0
1
1
0
0
1
1
B
3
1.140
1
0
1
1
0
1
0
0
B
4
1.145
1
0
1
1
0
1
0
1
B
5
1.150
1
0
1
1
0
1
1
0
B
6
1.155
1
0
1
1
0
1
1
1
B
7
1.160
1
0
1
1
1
0
0
0
B
8
1.165
1
0
1
1
1
0
0
1
B
9
1.170
1
0
1
1
1
0
1
0
B
A
1.175
1
0
1
1
1
0
1
1
B
B
1.180
1
0
1
1
1
1
0
0
B
C
1.185
1
0
1
1
1
1
0
1
B
D
1.190
1
0
1
1
1
1
1
0
B
E
1.195
1
0
1
1
1
1
1
1
B
F
1.200
1
1
0
0
0
0
0
0
C
0
1.205
1
1
0
0
0
0
0
1
C
1
1.210
1
1
0
0
0
0
1
0
C
2
1.215
1
1
0
0
0
0
1
1
C
3
1.220
1
1
0
0
0
1
0
0
C
4
1.225
1
1
0
0
0
1
0
1
C
5
1.230
1
1
0
0
0
1
1
0
C
6
1.235
1
1
0
0
0
1
1
1
C
7
1.240
1
1
0
0
1
0
0
0
C
8
1.245
1
1
0
0
1
0
0
1
C
9
1.250
1
1
0
0
1
0
1
0
C
A
1.255
1
1
0
0
1
0
1
1
C
B
1.260
1
1
0
0
1
1
0
0
C
C
1.265
1
1
0
0
1
1
0
1
C
D
1.270
Copyright © 2012 Richtek Technology Corporation. All rights reserved.
DS8859M-05 July 2012
Hex
Voltage
is a registered trademark of Richtek Technology Corporation.
www.richtek.com
13
RT8859M
VID7
VID6
VID5
VID4
VID3
VID2
VID1
VID0
1
1
0
0
1
1
1
0
C
E
1.275
1
1
0
0
1
1
1
1
C
F
1.280
1
1
0
1
0
0
0
0
D
0
1.285
1
1
0
1
0
0
0
1
D
1
1.290
1
1
0
1
0
0
1
0
D
2
1.295
1
1
0
1
0
0
1
1
D
3
1.300
1
1
0
1
0
1
0
0
D
4
1.305
1
1
0
1
0
1
0
1
D
5
1.310
1
1
0
1
0
1
1
0
D
6
1.315
1
1
0
1
0
1
1
1
D
7
1.320
1
1
0
1
1
0
0
0
D
8
1.325
1
1
0
1
1
0
0
1
D
9
1.330
1
1
0
1
1
0
1
0
D
A
1.335
1
1
0
1
1
0
1
1
D
B
1.340
1
1
0
1
1
1
0
0
D
C
1.345
1
1
0
1
1
1
0
1
D
D
1.350
1
1
0
1
1
1
1
0
D
E
1.355
1
1
0
1
1
1
1
1
D
F
1.360
1
1
1
0
0
0
0
0
E
0
1.365
1
1
1
0
0
0
0
1
E
1
1.370
1
1
1
0
0
0
1
0
E
2
1.375
1
1
1
0
0
0
1
1
E
3
1.380
1
1
1
0
0
1
0
0
E
4
1.385
1
1
1
0
0
1
0
1
E
5
1.390
1
1
1
0
0
1
1
0
E
6
1.395
1
1
1
0
0
1
1
1
E
7
1.400
1
1
1
0
1
0
0
0
E
8
1.405
1
1
1
0
1
0
0
1
E
9
1.410
1
1
1
0
1
0
1
0
E
A
1.415
1
1
1
0
1
0
1
1
E
B
1.420
1
1
1
0
1
1
0
0
E
C
1.425
1
1
1
0
1
1
0
1
E
D
1.430
1
1
1
0
1
1
1
0
E
E
1.435
1
1
1
0
1
1
1
1
E
F
1.440
1
1
1
1
0
0
0
0
F
0
1.445
1
1
1
1
0
0
0
1
F
1
1.450
1
1
1
1
0
0
1
0
F
2
1.455
1
1
1
1
0
0
1
1
F
3
1.460
1
1
1
1
0
1
0
0
F
4
1.465
1
1
1
1
0
1
0
1
F
5
1.470
1
1
1
1
0
1
1
0
F
6
1.475
Copyright © 2012 Richtek Technology Corporation. All rights reserved.
www.richtek.com
14
Hex
Voltage
is a registered trademark of Richtek Technology Corporation.
DS8859M-05 July 2012
RT8859M
VID7
VID6
VID5
VID4
VID3
VID2
VID1
VID0
1
1
1
1
0
1
1
1
F
7
1.480
1
1
1
1
1
0
0
0
F
8
1.485
1
1
1
1
1
0
0
1
F
9
1.490
1
1
1
1
1
0
1
0
F
A
1.495
1
1
1
1
1
0
1
1
F
B
1.500
1
1
1
1
1
1
0
0
F
C
1.505
1
1
1
1
1
1
0
1
F
D
1.510
1
1
1
1
1
1
1
0
F
E
1.515
1
1
1
1
1
1
1
1
F
F
1.520
Copyright © 2012 Richtek Technology Corporation. All rights reserved.
DS8859M-05 July 2012
Hex
Voltage
is a registered trademark of Richtek Technology Corporation.
www.richtek.com
15
RT8859M
Table 2. Serial VID Command
Code
Commands
Master Payload
Contents
Slave Payload
Contents
Description
00h
Not Supported
N/A
N/A
N/A
01h
SetVID_Fast
VID code
N/A
02h
SetVID_Slow
VID code
N/A
03h
SetVID_Decay
VID code
N/A
04h
SetPS
05h
SetRegADR
06h
SetRegDAT
07h
GetReg
08h
1Fh
Not Supported
Byte indicating
power states
Pointer of
registers in data
table
New data register
content
Pointer of
registers in data
table
Specified
register
contents
N/A
N/A
Copyright © 2012 Richtek Technology Corporation. All rights reserved.
www.richtek.com
16
Set new target VID code, VR jumps to new
VID target with controlled default “fast” slew
rate 12.5mV/μs.
Set new target VID code, VR jumps to new
VID target with controlled default “slow” slew
rate 3.125mV/μs.
Set new target VID code, VR jumps to new
VID target, but doest not control the slew
rate. The output voltage decays at a rate
proportional to the load current
N/A
Set power state
N/A
Set the pointer of the data register
N/A
Write the contents to the data register
Slave returns the contents of the specified
register as the payload.
N/A
is a registered trademark of Richtek Technology Corporation.
DS8859M-05 July 2012
RT8859M
Table 3. SVID Data and Configuration Register
Index
Register Name
Description
Access
Default
00h
Vendor_ID
Vendor ID
RO
1Eh
01h
02h
05h
Product_ID
Product_Revision
Protocol_Version
RO
RO
RO
59h
01h
01h
06h
VR_Capability
Product ID
Product Revision
SVID Protocol version
Bit mapped register, identifies the SVID VR
Capabilities and which of the optional telemetry
register are supported.
RO
81h
10h
Status_1
Data register containing the status of VR
R-M, W-PWM
00h
11h
Status_2
R-M, W-PWM
00h
12h
Temperature_Zone
R-M, W-PWM
00h
15h
Output_Current
Data register containing the status of transmission.
Data register showing temperature Zone that have
been entered.
Data register showing direct ADC conversion of
output current, scaled to ICC_MAX = ADC full range.
Binary format (IE : 64h = 100/255 ICC_MAX)
R-M, W-PWM
00h
1Ch
Status_2_Lastread
The register contains a copy of the Status_2
R-M, W-PWM
00h
21h
ICC_Max
Data register containing the maximum ICC the
platform supports.
Binary format in A. (IE : 64h = 100A)
RO, Platform
N/A
RO, Platform
N/A
RO
0Ah
RO
02h
RW, Master
FBh
RW, Master
00h
RW, Master
00h
RW, Master
00h
RW, Master
00h
RW, Master
30h
22h
Temp_Max
24h
SR_fast
25h
SR_slow
30h
VOUT_Max
31h
VID_Setting
32h
Power_State
33h
Offset
34h
Multi_VR_Config
35h
Pointer
Data register containing the maximum temperature
the platform supports.
Binary format in °C. (IE : 64h = 100°C)
Not supported by AXG VR.
Data register containing the capability of fast slew
rate the platform can sustain. Binary format in
mV/μs. (IE : 0Ah = 10 mV/μs)
Data register containing the capability of slow slew
rate.
Binary format in mV/μs. (IE : 02h = 2mV/μs)
The register is programmed by the master and sets
the maximum VID.
Data register containing currently programmed VID
Register containing the current programmed power
state
Set offset in VID steps
Bit mapped data register which configures multiple
VRs’ behavior on the same bus
Scratch pad register for temporary storage of the
SetRegADR pointer register
Notes :
RO = Read Only
RW = Read/Write
R-M = Read by Master
W-PWM = Write by PWM only
Platform = programmed by platform
Master = programmed by the master
PWM = programmed by the VR control IC
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17
RT8859M
Absolute Maximum Ratings
z
z
z
z
z
z
z
z
z
z
(Note 1)
VCC to GND --------------------------------------------------------------------------------------------------------- −0.3V to 6.5V
RGNDx to GND ----------------------------------------------------------------------------------------------------- −0.3V to 0.3V
TONSETx to GND -------------------------------------------------------------------------------------------------- −0.3V to 28V
Others ----------------------------------------------------------------------------------------------------------------- −0.3V to (VCC + 0.3V)
Power Dissipation, PD @ TA = 25°C
WQFN−56L 7x7 ----------------------------------------------------------------------------------------------------- 3.226W
Package Thermal Resistance (Note 2)
WQFN−56L 7x7, θJA ----------------------------------------------------------------------------------------------- 31°C/W
WQFN−56L 7x7, θJC ---------------------------------------------------------------------------------------------- 6°C/W
Junction Temperature ---------------------------------------------------------------------------------------------- 150°C
Lead Temperature (Soldering, 10 sec.) ------------------------------------------------------------------------ 260°C
Storage Temperature Range ------------------------------------------------------------------------------------- −65°C to 150°C
ESD Susceptibility (Note 3)
HBM (Human Body Model) --------------------------------------------------------------------------------------- 2kV
Recommended Operating Conditions
z
z
z
(Note 4)
Supply Voltage, VCC ---------------------------------------------------------------------------------------------- 4.5V to 5.5V
Junction Temperature Range ------------------------------------------------------------------------------------- −40°C to 125°C
Ambient Temperature Range ------------------------------------------------------------------------------------- −40°C to 85°C
Electrical Characteristics
(VCC = 5V, TA = 25°C, unless otherwise specified)
Parameter
Symbol
Test Conditions
Min
Typ
Max
Unit
---
12
--
20
5
mA
μA
−0.5
0
0.5
%VID
−5
−8
−8
0
0
0
5
8
8
mV
mV
mV
--
--
500
μA
2.5
10
3.125
12.5
3.75
15
mV/μs
RLOAD = 47kΩ
--
80
--
dB
CLOAD = 5pF
--
10
--
MHz
CLOAD = 10pF (Gain = −4,
RLOAD = 47kΩ, VOUT = 0.5V to −3V)
--
5
--
V/μs
Supply Input
Supply Current
Shutdown Current
Reference and DAC
DAC Accuracy
IVCC
ISHDN
VEN = 1.05V, Not Switching
VEN = 0V
VFB
VDAC = 1.000 to 1.520 (No Load, Active
Mode)
VDAC = 0.800 to 1.000
VDAC = 0.500 to 0.800
VDAC = 0.250 to 0.500
IRGND
VEN = 1.05V, Not Switching
RGND Current
RGND Current
Slew Rate
Dynamic VID Slew Rate SR
Set VID Slow, SR_ADDF pin = 0V
Set VID Fast, SR_ADDF pin = 0V
Error Amplifier
DC Gain
ADC
Gain-Bandwidth Product GBW
Slew Rate
SR
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RT8859M
Parameter
Symbol
Test Conditions
Min
Typ
Max
Unit
0.3
--
3.6
V
--
250
--
μA
−0.75
--
0.75
mV
Impedance at Negative Input RISENxN
1
--
--
MΩ
Impedance at Positive Input
1
--
--
MΩ
CORE VR
--
10
--
AXG VR
--
20
--
−50
--
100
mV
Output Voltage Range
VCOMP
RLOAD = 47kΩ
MAX Source/Sink Current
IOUTEA
VCOMP = 2V
Current Sense Amplifier
Input Offset Voltage
VOSCS
RISENxP
DC Gain
V/V
Input Range
VISEN_IN
V ISEN Linearity
VISEN_ACC
−30mV < V ISEN_IN < 50mV
−1
--
1
%
TONSETx Pin Voltage
VTON
IRTON = 80μA, VDAC = 0.75V
--
1.07
--
V
CCM On-Time Setting
tON
IRTON = 80μA, PS0, PS1
275
305
335
ns
TONSETx Input Current
Range
IRTON
25
--
280
μA
On-Time in PS2 (Core only)
tON_PS2
--
85
--
%
Minimum Off-Time
tOFF
--
250
--
ns
2.09
2.14
2.19
V
tON Setting
With Respect to PS0 tON
IBIAS
IBIAS Pin Voltage
VIBIAS
RIBIAS = 53.6kΩ
QRSET
Quick Response On-Time
Setting
tONx_QR
VDAC = 0.75V, VQRSET = 1.2V,
IRTON = 80μA
--
305
--
ns
QRSET Source Current
IQRSET
Before UVLO
--
80
--
μA
No Load Line Setting
Threshold
VIH
VCC − 0.5
--
--
V
VIL
QRSET Voltage before
UVLO, Relative to V CC
--
--
VCC − 1.8
V
OFS Function
OFS Enable/Disable
Threshold Voltage
VEN_OFS
VOFS > VEN_OFS before EN
rising
0.7
1.2
--
V
VID = 1V, V OFS = 1.83V
1.62
1.63
1.64
VID = 1V, V OFS = 0.9V
0.69
0.7
0.71
VID = 1V, V OFS = 1.2V
0.9
1
1.01
1
--
--
MΩ
0.97
1
1.03
V
--
1
--
mV
4.04
4.24
4.44
V
--
100
--
mV
100
150
200
mV
Offset Voltage
Impedance
VOUT
ROFS
V
RSET Setting
RSET Voltage
VRSET
RSET Voltage, VDAC = 1V
Zero Current Detection
Zero Current Detection
Threshold
Protection
VZCD
ISEN1P (AP) − ISEN1N (AN)
Under Voltage Lock-out
(UVLO)Threshold
Absolute Over Voltage
(OVP) Protection Threshold
ΔV UVLO
Falling Edge, 100mV
Hysteresis
Falling Edge Hysteresis
VOVABS
With respect to VOUT_Max
VUVLO
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19
RT8859M
Parameter
Symbol
Test Conditions
Divided Input Voltage
Detection (DVDx)
Threshold
Delay of UVLO, DVDx
Delay of OVP
tOV
Under Voltage Protection
(UVP) Threshold
VUV
Delay of UVP
tUVP
VISENxN Falling below Threshold
Negative Voltage
Protection Threshold
VNVP
After OVP, Falling Edge
Delay of NVP
tNVP
VISENxN Falling below Threshold
Min
Typ
Max
Unit
1.01
1.06
1.11
V
VDVDx
VDVDx Threshold
VDVDHYS
Falling Edge Hysteresis
--
25
--
mV
tUVLO
Rising Above Threshold
VISENxN Rising Above Threshold, Pin
OFS Disable
Measured at ISEN1N/ISENAN with
respect to unloaded output voltage
(UOV) (for 0.8 < UOV < 1.52)
--
3
--
μs
--
1
--
μs
−350
−300
−250
mV
--
3
--
μs
−100
−50
--
mV
--
1
--
μs
GILIMIT = V OCSET / (V ISENxP
− VISENxN), VOCSET = 2.400V,
(V ISENxP − VISENxN) = 50mV
43.2
48
52.8
GILIMITA = VOCSETA / (V ISENAP
− VISENAN), VOCSETA = 2.4V, (VISENAP
− VISENAN) = 50mV
43.2
48
52.8
--
15
--
0.7
--
--
--
--
0.3
Current Limit Gain Setting
GILIMIT
(per phase)
Current Limit Latch
NILIM
Counter (per phase)
EN Input
Logic-High VIH
Threshold
Logic-Low VIL
Voltage
Times of UGATE Rising
V/V
Times
V
Logic Inputs
EN Hysteresis
VENHYS
--
30
--
mV
Leakage Current of EN
IEN
−1
--
1
μA
Logic-High VIH
0.665
--
--
Logic-Low VIL
--
--
0.367
VCLK, VDIO
Input
Threshold
Voltage
V
VCLK,VDIO Hysteresis
VHYS
--
70
--
mV
Leakage Current of
ADD,VCLK,VDIO
ILEAK_IN
−1
--
1
μA
ALERT
VALERT
IALERT = 10mA
--
--
0.13
V
SVID Ready Delay Time
tA
From EN = high until VR Controller is
ready to accept SVID command
--
--
2
ms
VR_RDY Trip Threshold
VTH_VR_RDY
VISENxN − 1 VDAC
--
−100
--
mV
VR_RDY Low Voltage
VVR_RDY
IVR_RDY = 4mA
--
--
0.4
V
VR_RDY Delay
tVR_RDY
VISENxN = VINITIAL to VR_RDY High
--
100
--
μs
ALERT Low Voltage
Power On Sequence
st
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RT8859M
Parameter
Symbol
Test Conditions
Min
Typ
Max
Unit
--
--
0.13
V
3.2
3.3
3.4
V
ILEAK_OUT
−1
--
1
μA
PWM Source Resistor
RPWM_SOURCE
--
30
--
Ω
PWM Sink Resistor
RPWM_SINK
--
15
--
Ω
6
8
10
μA
--
16
--
μA
--
128
--
μA
--
16
--
μA
--
--
2
V
5
25
26.25
MHz
4
--
8.3
ns
Thermal Throttling
VRHOT Output Voltage
Current Monitor
Current Monitor Maximum
Output Voltage in
Operating Range
V VRHOT
IVRHOT = 10mA
V IMON
VDAC = 1V,
VFB − VCC_SENSE = 100mV,
RIMONFB = 10kΩ, RIMON = 330kΩ
High Impedance Output
PWMx, ALERT, VRx_RDY,
VRHOT
PWM Driving Capability
DVID, DVIDA, ICCMAX, ICCMAXA, and TMPMAX Pin Current
Current Sourcing Out from
During dynamic VID fast event
IDVIDx
DVIDx Pin to GND
Current Sinking In from 5V
IICCMAX
After VR_RDY
to ICCMAX Pin
Current Sourcing Out from
After VRA_RDY
IICCMAXA
ICCMAXA Pin to GND
Current Sinking In from 5V
ITMPMAX
After VR_RDY
to TMPMAX Pin
DVID and DVIDA Maximum Voltage
Maximum Allowable
Voltage at DVIDx Pin
SVID
SVID Frequency
SVID Clock to Data Delay
Setup Time of VDIO
Hold Time of VDIO
VDVIDx_MAX
During Dynamic VID Event
fSVID
tCO
tSU
tHLD
7
--
--
ns
14
--
--
ns
VINITIAL Setting
SETINIx Threshold
Voltage
V SETINI0
For VINITIAL = 0V
0
--
8
V SETINI0_9
For VINITIAL = 0.9V
17
--
20
V SETINI1_0
For VINITIAL = 1V
32.5
--
42.5
V SETINI1_1
For VINITIAL = 1.1V
57.5
--
67.5
V SETINI1_5
For VINITIAL = 1.5V
82.5
--
100
Set SVID address 0000 0001
--
--
0.35
Set SVID address 0010 0011
0.7
--
3
Set SVID address 0100 0101
VCC − 0.2
--
--
%V CC
ADD Threshold
VIL
ADD Input Logic-Low
Threshold Logic-Medium VIM
Voltage
Logic-High
VIH
Copyright © 2012 Richtek Technology Corporation. All rights reserved.
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21
RT8859M
Parameter
Symbol
Test Conditions
Min
Typ
Max
Unit
CICCMAX1
CICCMAX2
CICCMAX3
CICCMAXA1
VICCMAX = 12.74%VCC
VICCMAX = 25.284%VCC
VICCMAX = 50.372%VCC
VICCMAX = 3.332%VCC
29
61
125
5
32
64
128
8
35
67
131
11
Digital Code of ICCMAXA
CICCMAXA2
CICCMAXA3
CTMPMAX1
VICCMAX = 6.468%VCC
VICCMAX = 12.74%VCC
VICCMAX = 33.516%VCC
13
29
82
16
32
85
19
35
88
decimal
Digital Code of TMPMAX
CTMPMAX2
CTMPMAX3
COCR1
COCR2
VICCMAX = 39.396%VCC
VICCMAX = 49.196%VCC
VIMON(A) = 3.3V
VIMON(A) = 2.208V
97
122
252
167
100
125
255
170
103
128
255
173
decimal
COCR3
VIMON(A) = 1.107V
82
85
88
tOCR
--
--
500
μs
VTSEN
20
--
20
mV
tTZ
--
--
4
ms
ADC
Digital Code of ICCMAX
Digital Code of Output
Current Report
Updating Period of Output
Current Report
Tolerance Band of
Temperature_Zone Trip
Points b7, b6, b5
Updating Period of
Temperature_Zone
decimal
decimal
Note 1. Stresses beyond those listed “Absolute Maximum Ratings” may cause permanent damage to the device. These are
stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in
the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions may
affect device reliability.
Note 2. θJA is measured at TA = 25°C on a high effective thermal conductivity four-layer test board per JEDEC 51-7. θJC is
measured at the exposed pad of the package.
Note 3. Devices are ESD sensitive. Handling precaution is recommended.
Note 4. The device is not guaranteed to function outside its operating conditions.
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RT8859M
Typical Operating Characteristics
CORE VR Power On
CORE VR Power Off from EN
V CORE
(1V/Div)
V CORE
(1V/Div)
VR_RDY
(2V/Div)
ALERT
(2V/Div)
VR_RDY
(2V/Div)
EN
(2V/Div)
VDIO
(1V/Div)
PWM1
(5V/Div)
VCORE = 1.1V, ILOAD = 5A
VCORE = 1.1V, ILOAD = 5A
Time (100μs/Div)
Time (1ms/Div)
CORE VR Dynamic VID Up
CORE VR Dynamic VID Up
Fast Slew Rate
Slow Slew Rate,
V CORE
(500mV/Div)
V CORE
(500mV/Div)
VCLK
(1V/Div)
ALERT
(2V/Div)
VDIO
(2V/Div)
VCLK
(1V/Div)
VCORE = 0.7V up to 1.2V, ILOAD = 20A
ALERT
(2V/Div)
VDIO
(2V/Div)
VCORE = 0.7V up to 1.2V, ILOAD = 20A
Time (40μs/Div)
Time (100μs/Div)
CORE VR Dynamic VID Down
CORE VR Dynamic VID Down
Fast Slew Rate,
Slow Slew Rate,
V CORE
(500mV/Div)
V CORE
(500mV/Div)
VCLK
(1V/Div)
ALERT
(2V/Div)
VDIO
(2V/Div)
VCLK
(1V/Div)
ALERT
(2V/Div)
VDIO
(2V/Div)
VCORE = 1.2V down to 0.7V, ILOAD = 20A
Time (40μs/Div)
Copyright © 2012 Richtek Technology Corporation. All rights reserved.
DS8859M-05 July 2012
VCORE = 1.2V down to 0.7V, ILOAD = 20A
Time (100μs/Div)
is a registered trademark of Richtek Technology Corporation.
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23
RT8859M
CORE VR Load Transient Response
V CORE
(50mV/Div)
CORE VR Load Transient Response
V CORE
(50mV/Div)
70A
I LOAD
5A
70A
I LOAD
5A
VCORE = 1.1V, fLOAD = 300Hz, ILOAD = 5A to 70A
VCORE = 1.1V, fLOAD = 300Hz, ILOAD = 70A to 5A
Time (100μs/Div)
Time (100μs/Div)
CORE VR OCP
CORE VR OVP & NVP
V CORE
(2V/Div)
VR_RDY
(2V/Div)
V CORE
(1V/Div)
PWM1
(5V/Div)
VR_RDY
(1V/Div)
I LOAD
(100A/Div)
PWM1
(5V/Div)
VCORE = 1.1V
VCORE = 1.1V
Time (100μs/Div)
Time (40μs/Div)
CORE VR UVP
VIMON vs. Load Current
3.3
3.0
2.7
2.4
VIMON (V)
V CORE
(1V/Div)
VR_RDY
(1V/Div)
2.1
1.8
1.5
1.2
0.9
PWM1
(5V/Div)
0.6
VCORE = 1.1V, ILOAD = 1A
0.3
0.0
Time (1ms/Div)
0
10
20
30
40
50
60
70
80
90
100
Load Current (A)
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DS8859M-05 July 2012
RT8859M
AXG VR Power On
AXG VR Power Off from EN
VAXG
(1V/Div)
VAXG
(1V/Div)
VDIO
(1V/Div)
VRA_RDY
(1V/Div)
ALERT
(1V/Div)
EN
(1V/Div)
VRA_RDY
(2V/Div)
PWMA
(10V/Div)
VAXG = 1.1V, ILOAD = 5A
VAXG = 1.1V, ILOAD = 5A
Time (100μs/Div)
Time (1ms/Div)
AXG VR Dynamic VID Up
AXG VR Dynamic VID Up
Fast Slew Rate
Slow Slew Rate
VAXG
(500mV/Div)
VAXG
(500mV/Div)
VCLK
(2V/Div)
VDIO
(2V/Div)
VCLK
(2V/Div)
VDIO
(2V/Div)
ALERT
(2V/Div)
VAXG = 0.7V up to 1.2V, ILOAD = 20A
ALERT
(2V/Div)
VAXG = 0.7V up to 1.2V, ILOAD = 20A
Time (40μs/Div)
Time (100μs/Div)
AXG VR Dynamic VID Down
AXG VR Dynamic VID Down
Fast Slew Rate,
Slow Slew Rate,
VAXG
(500mV/Div)
VAXG
(500mV/Div)
VCLK
(2V/Div)
VDIO
(2V/Div)
VCLK
(2V/Div)
VDIO
(2V/Div)
ALERT
(2V/Div)
VAXG = 1.2V down to 0.7V, ILOAD = 20A
Time (40μs/Div)
Copyright © 2012 Richtek Technology Corporation. All rights reserved.
DS8859M-05 July 2012
ALERT
(2V/Div)
VAXG = 1.2V down to 0.7V, ILOAD = 20A
Time (100μs/Div)
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RT8859M
AXG VR Load Transient Response
VAXG
(50mV/Div)
AXG VR Load Transient Response
VAXG
(50mV/Div)
22A
I LOAD
2A
22A
I LOAD
2A
VAXG = 1.1V, fLOAD = 300Hz, ILOAD = 2A to 22A
VAXG = 1.1V, fLOAD = 300Hz, ILOAD = 22A to 2A
Time (100μs/Div)
Time (100μs/Div)
AXG VR OCP
AXG VR OVP & NVP
VAXG
(2V/Div)
VAXG
(1V/Div)
VRA_RDY
(2V/Div)
VRA_RDY
(1V/Div)
PWMA
(10V/Div)
PWMA
(5V/Div)
I LOAD
(50A/Div)
VAXG = 1.1V
VAXG = 1.1V
Time (100μs/Div)
Time (100μs/Div)
AXG VR UVP
VIMONA vs. Load Current
3.3
3.0
VAXG
(1V/Div)
2.7
2.4
VIMONA (V)
2.1
VRA_RDY
(1V/Div)
1.8
1.5
1.2
0.9
PWMA
(5V/Div)
0.6
VAXG = 1.1V, ILOAD = 1A
0.3
0.0
Time (1ms/Div)
0
3
6
9
12
15
18
21
24
27
30
Load Current (A)
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RT8859M
Thermal Monitoring
TSEN
(100mV/Div)
VRHOT
(1V/Div)
TSEN from 1.7V Sweep to 1.9V, ILOAD = 0A
Time (400μs/Div)
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RT8859M
Application Information
The RT8859M is a CPU power controller which includes
two voltage rails : a 4/3/2/1 phase synchronous buck
controller, the CORE VR, and a single phase buck
controller, the AXG VR. The RT8859M is compliant with
Intel VR12/IMVP7 voltage regulator specification to fulfill
Intel's CPU power supply requirements of both CORE and
AXG voltage rails. A Serial VID (SVID) interface is built-in
in the RT8859M to communicate with Intel VR12/IMVP7
compliant CPU.
The RT8859M adopts G-NAVPTM (Green Native AVP),
which is Richtek's proprietary topology derived from finite
DC gain compensator with current mode control, making
it an easy setting PWM controller, meeting all Intel CPU
requirements of AVP (Active Voltage Positioning). The load
line can be easily programmed by setting the DC gain of
the error amplifier. The RT8859M has fast transient
response due to the G-NAVPTM commanding variable
switching frequency. Based on the G-NAVPTM topology,
the RT8859M also features a quick response mechanism
for optimized AVP performance during load transient.
The G-NAVPTM topology also represents a high efficiency
system with green power concept. With the G-NAVPTM
topology, the RT8859M becomes a green power controller
with high efficiency under heavy load, light load, and very
light load conditions. The RT8859M supports mode
transition function with various operating states, including
multi-phase, single phase and diode emulation modes.
These different operating states allow the overall power
control system to have the lowest power loss. By utilizing
the G-NAVPTM topology, the operating frequency of the
RT8859M varies with VID, load, and input voltage to further
enhance the efficiency even in CCM.
The built-in high accuracy DAC converts the SVID code
ranging from 0.25V to 1.52V with 5mV per step. The
RT8859M supports VID on-the-fly function with three
different slew rates : Fast, Slow and Decay. The RT8859M
also builds in a high accuracy ADC for some platform
setting functions, such as no-load offset or over-current
level. The controller supports both DCR and sense resistor
current sensing. The RT8859M provides power VR ready
signals for both CORE VR and AXG VR. It also features
Copyright © 2012 Richtek Technology Corporation. All rights reserved.
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28
complete fault protection functions including over voltage,
under voltage, negative voltage, over current and under
voltage lockout. The RT8859M is available in a WQFN56L 7x7 small footprint package.
General Loop Functions
VR Rail Addressing and Slew rate Setting
The voltage level at the ADD pin defines the VR addresses
of the RT8859M. User can also flip the VR address by
properly setting the voltage on SR_ADDF pin. There are
three valid voltage levels for ADD pin : VCC (5V), floating,
and GND. Connecting the ADD pin to one of these three
voltage levels can set the addresses of both CORE VR
and AXG VR according to the following table. The All Call
address, 1111, 1110, can only be used with SetVID or
SetPS commands.
Address
Flip
ADD Level
VCC
No
Yes
VR1 (CORE) VR1 (AXG)
Address
Address
0100
0101
Floating
0010
0011
GND
0000
0001
VCC
0101
0100
Floating
0011
0010
GND
0001
0000
The RT8859M can also program the dynamic VID slew
rate by setting the SR_ADDF pin. After POR, the
RT8859M will detect the voltage level on the SR_ADDF
pin and latch the status of the address and the dynamic
VID slew rate. Below is the setting table of SR_ADDF.
The recommended voltage tolerance is (recommended
voltage ±25mV). Make sure the voltage divider at
SR_ADDF pin uses the same VCC as pin 41 (VCC).
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DS8859M-05 July 2012
RT8859M
Recommended
SR_ADDF Voltage
(if VCC = 5V)
Address
Flipped
VR0 Fast
Slew Rate
(mV/μs)
VR0 Slow
Slew Rate
(mV/μs)
VR1 Fast
Slew Rate
(mV/μs)
VR1 Slow
Slew Rate
(mV/μs)
5
Yes
10
2.5
10
2.5
4.766
Yes
10
2.5
10
5
4.609
Yes
10
5
10
2.5
4.453
Yes
10
5
10
5
4.297
Yes
15
3.75
10
2.5
4.141
Yes
15
3.75
10
5
3.984
Yes
15
7.5
10
2.5
3.828
Yes
15
7.5
10
5
3.672
Yes
20
5
10
2.5
1.797
No
20
10
10
5
1.641
No
20
10
10
2.5
1.484
No
20
5
10
5
1.328
No
20
5
10
2.5
1.172
No
15
7.5
10
5
1.016
No
15
7.5
10
2.5
0.859
No
15
3.75
10
5
0.703
No
15
3.75
10
2.5
0.547
No
10
5
10
5
0.391
No
10
5
10
2.5
0.234
No
10
2.5
10
5
0
No
10
2.5
10
2.5
Copyright © 2012 Richtek Technology Corporation. All rights reserved.
DS8859M-05 July 2012
is a registered trademark of Richtek Technology Corporation.
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29
RT8859M
Power Ready (POR) Detection
latches.
VCC
+
4.24V
DVD
+
1.06V
EN
DVDA
POR
CMP
Chip EN
+
1.06V
CMP
+
0.7V
CMP
CMP
-
Figure 1. Power Ready (POR) Detection
Precise Reference Current Generation
The RT8859M includes complicated analog circuits inside
the controller. These analog circuits need very precise
reference voltage/current to drive these analog devices.
The RT8859M will auto generate a 2.14V voltage source
at the IBIAS pin, and a 53.6kΩ resistor is required to be
connected between IBIAS and analog ground. Through
this connection, the RT8859M will generate a 40μA current
from the IBIAS pin to analog ground, and this 40μA current
will be mirrored inside the RT8859M for internal use. Note
that other types of connection or other values of resistance
applied at the IBIAS pin may cause failure of the
RT8859M's functions, such as slew rate control, OFS
accuracy, etc. In other words, the IBIAS pin can only be
connected with a 53.6kΩ resistor to GND. The resistance
accuracy of this resistor is recommended to be 1% or
higher.
Copyright © 2012 Richtek Technology Corporation. All rights reserved.
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30
2.14V
+
-
During start-up, the RT8859M will detect the voltage at
the voltage input pins : VCC, EN, DVD and DVDA. When
VCC > 4.24V, VDVD > 1.06V and VDVDA > 1.06V, the
RT8859M will recognize the power state of system to be
ready (POR = high) and wait for enable command at the
EN pin. After POR = high and VEN > 0.7V, the RT8859M
will enter start-up sequence for both CORE rail and AXG
rail. If the voltage at any voltage pin drops below low
threshold (POR = low), the RT8859M will enter power down
sequence and all the functions will be disabled. Normally,
connecting system VTT (1.05V) to the EN pin and power
stage VIN (12V, through a voltage divider) to the DVD pin is
recommended. 2ms (max) after the chip has been
enabled, the SVID circuitry will be ready. All the protection
latches (OVP, OCP, UVP) will be cleared only after POR
= low. The condition of VEN = low will not clear these
Current
Mirror
+
-
IBIAS
53.6k
Figure 2. IBIAS Setting
ICCMAX, ICCMAXA and TMPMAX
The RT8859M provides ICCMAX, ICCMAXA and TMPMAX
pins for platform users to set the maximum level of output
current or VR temperature : ICCMAX for CORE VR max
current, ICCMAXA for AXG VR max current, and TMPMAX
for CORE VR max temperature.
To set ICCMAX, ICCMAXA and TMPMAX, platform
designers should use resistive voltage divider on these
three pins. The current of the divider should be several
milliamps to avoid noise effect. The 3 items share the
same algorithms : the ADC divides 5V into 255 levels.
Therefore, the LSB = 5 / 255 = 19.6mV, which means
19.6mV applied to ICCMAX pin equals to 1A setting. For
example, if the maximum level of temperature is desired
to be 120°C, the voltage applied to TMPMAX should be
120 x 19.6mV = 2.352V. The ADC circuit inside these
three pins will decode the voltage applied and store the
maximum current/temperature setting into ICC_Max and
Temp_Max registers. The ADC monitors and decodes the
voltage at these three pins only ONCE after power up.
After ADC decoding (only once), a 128μA current will be
generated at the ICCMAXA pin for internal use. Make sure
the voltage at the ICCMAXA pin is greater than 1.55V to
guarantee proper functionality.
VCC
ICCMAX
A/D
Converter
ICCMAXA
TMPMAX
I
Figure 3. ADC Pins Setting
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RT8859M
The RT8859M will NOT take any action even when the VR
output current or temperature exceeds its maximum
setting at these ADC pins. The maximum level settings
at these ADC pins are different from over current protection
or over temperature protection. In other words, these
maximum level setting pins are only for platform users to
define their system operating conditions and these
messages will only be utilized by the CPU.
VINITIAL Setting
The initial startup voltage of the RT8859M can be set by
platform users through the SETINI and the SETINIA pins.
Voltage divider circuits are recommended to be applied to
the SETINI and the SETINIA pins. The initial startup voltage
relates to the SETINI pin voltage setting as shown in Table
4. Recommended voltage setting at the SETINIA pin is
also shown in Table 4.
Table 4. SETINI (SETINIA) Pin Setting
Initial Startup
Voltage
Recommended SETINI Pin
Voltage
1.5V
7 x VCC ≒ 4.375V
8
1.1V
5 x VCC ≒ 3.125V
8
1V
3 x VCC ≒ 1.875V
8
0.9V
0V
3 x VCC ≒ 0.9375V
16
1 x VCC ≒ 0.3125V or GND
16
Copyright © 2012 Richtek Technology Corporation. All rights reserved.
DS8859M-05 July 2012
Start-Up Sequence
The RT8859M utilizes an internal soft-start sequence which
strictly follows Intel VR12/IMVP7 start-up sequence
specifications. After POR = high and EN = high, the
controller considers all the power inputs ready and enters
start-up sequence. If VINITIAL = 0, VOUT is programmed to
stay at 0V for 2ms waiting for SVID command. If VINITIAL
≠ 0 , VOUT will ramp up to VINITIAL voltage (which is not
zero) immediately after both POR = high and EN= high.
After VOUT reaches target VINITIAL, VOUT will stay at VINITIAL
waiting for SVID command. After the RT8859M receives
valid VID code (typically SetVID_Slow command), VOUT
will ramp up to the target voltage with specified slew rate
(see section “Data and Configuration Register”). After
VOUT reaches target voltage (VID voltage for VINITIAL = 0 or
VINITIAL for VINITIAL ≠ 0), the RT8859M will send out
VR_RDY signal to indicate that the power state of the
RT8859M is ready. The VR ready circuit is an open-drain
structure, so a pull-up resistor connected to a voltage
source is recommended.
Power Down Sequence
Similar to the start-up sequence, the RT8859M also
utilizes a soft shutdown mechanism during turn-off. After
EN = low, the internal reference voltage (positive terminal
of compensation EA) starts ramping down with 3.125mV/
μs slew rate, and VOUT will follow the reference voltage to
0V. After VOUT drops below 0.2V, the RT8859M shuts down
and all functions (drivers) are disabled. The VR_RDY and
VRA_RDY will be pulled down immediately after POR =
low or EN = low.
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31
RT8859M
VCC
DVD
(DVDA)
POR
EN
SVID
XX
Valid
xx
2ms
0.2V
VOUT, CORE
MAX Phases
PWM
Hi-Z
SVID defined
MAX Phases
Hi-Z
0.2V
VOUT, AXG
1 Phase CCM
PWMA
Hi-Z
SVID defined
1 Phase CCM
Hi-Z
100µs
VR_RDY
100µs
VRA_RDY
Figure 4 (a). Power Sequence for the RT8859M (VINITIAL = VINITIALA = 0V)
VCC
DVD
POR
EN
SVID
XX
Valid
xx
2ms
VINITIAL
0.2V
VOUT, CORE
MAX Phases
PWM
Hi-Z
SVID defined
MAX Phases
Hi-Z
VINITIALA
0.2V
VOUT, AXG
1 Phase CCM
PWMA
Hi-Z
SVID defined
1 Phase CCM
Hi-Z
100µs
VR_RDY
100µs
VRA_RDY
Figure 4 (b). Power Sequence for the RT8859M (VINITIAL ≠ 0V, VINITIALA ≠ 0V)
Copyright © 2012 Richtek Technology Corporation. All rights reserved.
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32
is a registered trademark of Richtek Technology Corporation.
DS8859M-05 July 2012
RT8859M
VIN, CORE
CORE VR
CCRCOT
PWM
Logic
Active Phase Determination : Before POR
Driver
COMP2
VOUT, CORE
L
RX
+
-
CMP
CX
RC
LS_FET
AI
VCS
+
-
C
ISENxP
ISENxN
C2
Offset
Canceling
R2
COMP
EA
+
+
The number of active phases is determined by the internal
circuitry that monitors the ISENxN voltages during startup. Normally, the CORE VR operates as a 4-phase PWM
controller. Pulling ISEN4N to VCC programs a 3-phase
operation, pulling ISEN3N and ISEN4N to VCC programs
a 2-phase operation, and pulling ISEN2N, ISEN3N and
ISEN4N to VCC programs a 1-phase operation. Before
POR, CORE VR detects whether the voltages of ISEN2N,
ISEN3N and ISEN4N are higher than “V CC − 1V”
respectively to decide how many phases should be active.
Phase selection is only active during POR. When POR =
high, the number of active phases is determined and
latched. The unused ISENxP pins are recommended to
be connected to VCC and unused PWM pins can be left
floating.
HS_FET
PWMx
FB
RGND
C1
R1
VCC_SENSE
VSS_SENSE
VDAC, CORE
Figure 5. CORE VR : Simplified Schematic for Droop
and Remote Sense in CCM
Droop Setting (with Temperature Compensation)
It's very easy to achieve Active Voltage Positioning (AVP)
by properly setting the error amplifier gain due to the native
droop characteristics. The target is to have
VOUT = VDAC − ILOAD x RDROOP
Loop Control
The CORE VR adopts Richtek's proprietary G-NAVPTM
topology. G-NAVPTM is based on the finite gain peak current
mode with CCRCOT (Constant Current Ripple Constant
On-Time) topology. The output voltage, VOUT, CORE, will
decrease with increasing output load current. The control
loop consists of PWM modulators with power stages,
current sense amplifiers and an error amplifier as shown
in Figure 5.
Similar to the peak current mode control with finite
compensator gain, the HS_FET on-time is determined by
CCRCOT on-time generator. When load current increases,
VCS increases, the steady state COMP voltage also
increases and induces VOUT, CORE to decrease, thus
achieving AVP. A near-DC offset canceling is added to the
output of EA to eliminate the inherent output offset of finite
gain peak current mode controller.
(1)
Then solving the switching condition VCOMP2 = VCS in
Figure 5 yields the desired error amplifier gain as
A V = R2 =
R1
AI × RSENSE
RDROOP
(2)
where AI is the internal current sense amplifier gain. RSENSE
is the current sense resistor. If no external sense resistor
present, it is the DCR of the inductor. RDROOP is the
equivalent load line resistance as well as the desired static
output impedance.
VOUT
AV2 > AV1
AV2
AV1
0
Load Current
Figure 6. CORE VR : Error Amplifier gain (AV) Influence
on VOUT Accuracy
Since the DCR of the inductor is temperature dependent,
it affects the output accuracy at hot conditions.
Temperature compensation is recommended for the
lossless inductor DCR current sense method. Figure 7
shows a simple but effective way of compensating the
Copyright © 2012 Richtek Technology Corporation. All rights reserved.
DS8859M-05 July 2012
is a registered trademark of Richtek Technology Corporation.
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33
RT8859M
temperature variations of the sense resistor using an NTC
thermistor placed in the feedback path.
C2
COMP
RGND
R1a
R1b
FB
+
EA
+
R2
C1
RNTC
Usually, R1a is set to equal RNTC (25°C). R1b is selected
to linearize the NTC's temperature characteristic. For a
given NTC, design is to get R1b and R2 and then C1 and
C2. According to equation (2), to compensate the
temperature variations of the sense resistor, the error
amplifier gain (AV) should have the same temperature
coefficient with RSENSE. Hence
A V, HOT
RSENSE, HOT
=
A V, COLD RSENSE, COLD
(3)
From equation (2), AV can be obtained at any temperature
(T°C) as shown below :
R2
A V, T °C =
(4)
R1a // RNTC, T °C + R1b
The standard formula for the resistance of NTC thermistor
as a function of temperature is given by :
) ( )}
1
β⎡
− 1 ⎤
⎢⎣ T+273
298 ⎥⎦
(5)
Where R25°C is the thermistor's nominal resistance at room
temperature, β is the thermistor's material constant in
Kelvins, and T is the thermistor's actual temperature in
Celsius.
To calculate DCR value at different temperature can use
the equation as below :
DCRT°C = DCR25°C x [1 + 0.00393 x (T − 25)]
(6)
where 0.00393 is the temperature coefficient of copper.
For a given NTC thermistor, solving equation (4) at room
temperature (25°C) yields :
R2 = AV,
25°C
x (R1b + R1a // RNTC, 25°C)
(7)
where AV, 25°C is the error amplifier gain at room temperature
and can be obtained from equation (2). R1b can be obtained
by substituting (7) to (3),
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34
(8)
Droop Disable
VSS_SENSE
Figure 7. CORE VR : Loop Setting with Temperature
Compensation
RNTC, T°C = R25°C
RSENSE, HOT ⎞
⎛
⎜1 − R
⎟
SENSE, COLD ⎠
⎝
VCC_SENSE
VDAC
{(
e
R1b =
RSENSE, HOT
x (R1a / /RNTC, HOT ) − (R1a / /RNTC, COLD )
RSENSE, COLD
The CORE VR's droop function can be enabled or disabled
with different connections of the QRSET pin. The
connection of the QRSET pin is usually a voltage divider
circuit which is described later in the Quick Response
section. Before POR, the RT8859M will source 80μA
current from the QRSET pin to the external voltage divider
to determine the voltage level while the RT8859M is still
not powered on. Before POR, if the voltage at the QRSET
pin is higher than VCC − 0.5V, the CORE VR will operate
in droop enabled mode. If the voltage is lower than
VCC − 1.8V, the CORE VR will operate without droop
function, which means at the DC level of DAC voltage. For
example, a 5V voltage divided by two 1kΩ resistors
connected to the QRSET pin generates 2.54V (5V/2 +
80μA x 1kΩ/2) before POR and 2.5V (5V/2) after POR.
Loop Compensation
Optimized compensation of the CORE VR allows for best
possible load step response of the regulator's output. A
type-I compensator with one pole and one zero is adequate
for proper compensation. Figure 8 shows the compensation
circuit. Prior design procedure shows how to select the
resistive feedback components for the error amplifier gain.
Next, C1 and C2 must be calculated for the compensation.
The target is to achieve constant resistive output impedance
over the widest possible frequency range.
The pole frequency of the compensator must be set to
compensate the output capacitor ESR zero :
fP =
1
2 x π x C x RC
(9)
Where C is the capacitance of output capacitor, and RC is
the ESR of output capacitor. C2 can be calculated as
follows :
C2 =
C x RC
R2
(10)
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RT8859M
The zero of compensator has to be placed at half of the
switching frequency to filter the switching related noise.
Such that,
1
C1 =
(11)
(R1b + R1a // RNTC, 25°C ) × π × fSW
when the inductor current reverses at light or negative
load currents. With reversed inductor current, the phase
goes high earlier than normal, extending the on-time by a
period equal to the HS-FET rising dead time.
TON Setting
For better efficiency of the given load range, the maximum
switching frequency is suggested to be :
1
fS(MAX) (kHz) =
x
TON − THS−Delay
High frequency operation optimizes the application for the
smaller component size, trading off efficiency due to higher
switching losses. This may be acceptable in ultra portable
devices where the load currents are lower and the
controller is powered from a lower voltage supply. Low
frequency operation offers the best overall efficiency at
the expense of component size and board space. Figure
8 shows the On-Time setting Circuit. Connect a resistor
(RTON) between VIN,CORE and TONSET to set the on-time
of UGATE :
−12
24.4 x 10 x RTON
(12)
tON (VDAC < 1.2V) =
VIN − VDAC
VDAC(MAX) + ILOAD(MAX) x ⎡⎣RON _ LS−FET + DCR − RDROOP ⎤⎦
VIN(MAX) + ILOAD(MAX) x ⎡⎣RON _ LS−FET − RON _ HS−FET ⎤⎦
(14)
Where fS(MAX) is the maximum switching frequency, tHSDELAY is the turn-on delay of HS-FET, VDAC(MAX) is the
Maximum VDAC of application, VIN(MAX) is the Maximum
application Input voltage, ILOAD(MAX) is the maximum load
of application, RON_LS-FET is the Low side FET RDS(ON),
RON_HS-FET is the High side FET RDS(ON), DCRL is the
inductor DCR, and RDROOP is the load line setting.
where tON is the UGATE turn on period, VIN is Input voltage
of the CORE VR, and VDAC is the DAC voltage.
When VDAC is larger than 1.2V, the equivalent switching
frequency may be over 500kHz, and this too fast switching
frequency is unacceptable. Therefore, the CORE VR
implements a pseudo constant frequency technology to
avoid this disadvantage of CCRCOT topology. When VDAC
is larger than 1.2V, the on-time equation will be modified
to :
−12
tON (VDAC ≥ 1.2V) =
20.33 x 10 x RTON x VDAC
VIN − VDAC
(13)
During PS2/PS3 operation, the CORE VR shrinks its ontime for the purpose of reducing output voltage ripple
caused by DCM operation. The shrink percentage is 15%
compared with original on-time setting by equation (12)
or (13). That is, after setting the PS0 operation on-time,
the PS2/PS3 operation on-time is 0.85 times the original
on-time.
On-time translates only roughly to switching frequencies.
The on-times guaranteed in the Electrical Characteristics
are influenced by switching delays in external HS-FET.
Also, the dead-time effect increases the effective on-time,
which in turn reduces the switching frequency. It occurs
only in CCM and during dynamic output voltage transitions
Copyright © 2012 Richtek Technology Corporation. All rights reserved.
DS8859M-05 July 2012
CCRCOT
On-Time
Computer
TONSET
VDAC
RTON
R1
VIN, CORE
C1
On-Time
Figure 8. CORE VR : On-Time Setting with RC Filter
Differential Remote Sense Setting
The CORE VR includes differential, remote-sense inputs
to eliminate the effects of voltage drops along the PC
board traces, CPU internal power routes and socket
contacts. The CPU contains on-die sense pins, VCC_SENSE
and VSS_SENSE. Connect RGND to VSS_SENSE. Connect FB
to VCC_SENSE with a resistor to build the negative input
path of the error amplifier. The VDAC and the precision
voltage reference are referred to RGND for accurate remote
sensing.
Current Sense Setting
The current sense topology of the CORE VR is continuous
inductor current sensing. Therefore, the controller can be
less noise sensitive. Low offset amplifiers are used for
loop control and over current detection. The internal current
sense amplifier gain (Ai) is fixed to be 10. The ISENxP
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35
RT8859M
and ISENxN denote the positive and negative input of the
current sense amplifier of any phase.
Users can either use a current sense resistor or the
inductor's DCR for current sensing. Using the inductor's
DCR allows higher efficiency as shown in Figure 9. Refer
to below equation for optimum transient performance :
L = R ×C
(15)
X
X
DCR
0.36μH
(16)
RX =
= 3.6kΩ
1mΩ x 100nF
VOUT, CORE
L
RX
ISENxP
DCR
CX
+ VX -
ISENxN
Figure 9. CORE VR : Lossless Inductor Sensing
Considering the inductance tolerance, the resistor RX has
to be tuned on board by examining the transient voltage.
If the output voltage transient has an initial dip below the
minimum load line requirement with a slow recovery, RX
is chosen too small. Vice versa, with a resistance too
large the output voltage transient has only a small initial
dip and the recovery is too fast causing a ring back.
Using current sense resistor in series with the inductor
can have better accuracy, but the efficiency is a trade-off.
Considering the equivalent inductance (LESL) of the current
sense resistor, an RC filter is recommended. The RC filter
calculation method is similar to the above mentioned
inductor DCR sensing method.
Current Balance
The CORE VR implements internal current balance
mechanism in the current loop. The CORE VR senses
and compares per-phase current signal with average
current. If the sensed current of any particular phase is
larger than average current, the on-time of this phase will
be adjusted to be shorter.
No Load Offset (SVID & Platform)
The CORE VR features no load offset function which
provides the possibility of wide range positive offset of
output voltage. The no-load offset function can be
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36
implemented through the SVID interface or OFS pin. Users
can disable pin offset function by simply connecting OFS
pin to GND. The RT8859M will latch the OFS status after
POR.
If pin offset function is enabled, users can decide whether
to disable SVID OFS or not by selecting proper resistor
values of ICCMAX pin. After receiving a valid VID, the
RT8859M sinks in 16μA from ICCMAX pin. The voltage on
ICCMAX is
(17)
VICCMAX = R2
x VCC − 16μA (R1//R2)
R1 + R2
If VICCMAX <1V, then the output voltage is
VOUT = VDAC − ILOAD x RDROOP + VPIN−OFS
(18)
If VICCMAX >1V, then the output voltage is
VOUT = VDAC − ILOAD x RDROOP + VPIN−OFS
(19)
+ VSVID−OFS
The pin offset voltage is set by supplying a voltage into
OFS pin. The linear range of offset pin voltage is from
0.9V to 1.83V. The pin offset voltage can be calculated as
below :
VPIN−OFS = VOFS − 1.2V
(20)
For example, supplying 1.3V at OFS pin will achieve
100mV offset at the output. Connecting a filter capacitor
between the OFS pin and GND is necessary. Designers
can design the offset slew rate by properly setting the
filter bandwidth.
Operation Mode Transition
RT8859M supports operation mode transition function at
the CORE VR for the SetPS command of Intel's VR12/
IMVP7 CPU. The default operation mode of the CORE
VR is PS0, which is full phase CCM operation. Other
operation modes includes PS1 (single phase CCM
operation) and PS2 (single phase DEM operation).
After receiving SetPS command, the CORE VR will
immediately change to the new operation state. When
the CORE VR receives SetPS command of PS1 operation
mode, the CORE VR operates as a single phase CCM
controller, and only channel 1 is active. The CORE VR will
disable phase 2, phase 3 and phase 4 by disabling Internal
PWM logic drivers at PWM2, PWM3 and PWM4 pins
(PWM = high impedance state). Therefore, 3 external
drivers which support tri-state shutdown are required for
compatibility with PS1 operation mode.
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RT8859M
When the CORE VR receives SetPS command of PS2
operation mode, the CORE VR operates as a single phase
DCM controller, and only channel 1 is active with diode
emulation operation. The CORE VR will disable phase 2,
phase 3 and phase 4 by disabling Internal PWM logic
drivers at PWM2, PWM3 and PWM4 pins (PWM = high
impedance state). Therefore, 4 external drivers which
support tri-state shutdown are required for compatibility
with PS2 operation state.
Ramp Amplitude Adjust
If the CORE VR receives dynamic VID change command
(SetVID), the CORE VR will automatically enter PS0
operation mode and all phases will be activated. After
VOUT,CORE reaches target voltage, the CORE VR will stay
at PS0 state and ignore former SetPS command. Only
re-sending SetPS command after SetVID command will
the CORE VR be forced into PS1 or PS2 operation states
again.
57.6 x 10−12 = tON x (VIN − VDAC) x 1/RSET
When the CORE VR enters PS2 operation mode, the
internal ramp of CORE VR will be modified for the reason
of stability. In case of smooth transition into PS2, the
CCM ramp amplitude should be designed properly. The
RT8859M provides RSET pin for platform users to set the
ramp amplitude of the CORE VR in CCM. The criteria is
to set the ramp amplitude proportional to the on-time (when
VDAC < 1.2V). The equation will be :
(21)
where 57.6 x 10−12 is an internal coefficient of analog
circuit.
According to equation (12), the RSET equation can be
simplified to :
RRSET = 0.4236 x RTON
(22)
Thermal Monitoring and Temperature Reporting
Dynamic VID Enhancement
During a dynamic VID event, the charging (dynamic VID
up) or discharging (dynamic VID down) current causes
unwanted load-line effect which degrades the settling time
performance. The DVID pin can be used to compensate
the load-line effect, so that the output voltage can settle
to the target value more quickly.
During a dynamic VID up event, the RT8859M sources
out a current (IDVID) to DVID pin. The voltage on DVID pin
is added to DAC during DVID rising to enhance the dynamic
VID performance. Connecting a capacitor in parallel with
a resistor to DVID pin is recommended.
I DVID is 8μA during a SetVID_Fast event. If it is a
SetVID_Slow event, IDVID automatically shrinks to 2μA (if
slow slew rate is 0.25x fast slew rate) or 4μA (if slow slew
rate is 0.5x fast slew rate). This function is null during a
dynamic VID down event.
DAC
IDVID
+
Slew Rate
Control
DVID
Event
1/20
+
EA
-
DVID
FB
Figure 10. DVID Compensation Circuit
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DS8859M-05 July 2012
The CORE VR provides thermal monitoring function via
sensing TSEN pin voltage. Through the voltage divider
resistors, R1 and RNTC, the voltage of TSEN will be
proportional to VR temperature. When VR temperature
rises, TSEN voltage also rises. The ADC circuit of the
CORE VR monitors the voltage variation at the TSEN pin
from 1.46V to 1.845V with 55mV resolution. This voltage
is then decoded into digital format and stored into
Temperature_Zone register.
V
CC
R2
NTC
TSEN
R1
Figure 11. CORE VR : Thermal Monitoring Circuit
To meet Intel's VR12/IMVP7 specification, platform users
have to set the TSEN voltage to meet the temperature
variation of VR from 75% to 100% VR max temperature.
For example, if the VR max temperature is 100°C, platform
users have to set the TSEN voltage to be 1.515V when
VR temperature reaches 82°C and 1.845V when VR
temperature reaches 100°C. Detailed voltage setting
versus temperature variation is shown in Table 5. The
thermometer code is implemented in Temperature_Zone
register.
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RT8859M
Table 5. Temperature_Zone Register
VRHOT
SVID Thermal
Alert
b7
100%
1.845V
b6
97%
1.79V
Comparator Trip Points Temperatures Scaled to maximum = 100%
Voltage Represents Assert bit Minimum Level
b5
94%
1.735V
b4
91%
1.68V
The VRHOT pin is an open-drain structure that sends out
active low VRHOT signal. When b6 of Temperature_Zone
register asserts to 1 (when TSEN voltage rises above
1.79V), the ALERT signal will be asserted to low, which is
so-called SVID thermal alert. In the mean time, the CORE
VR will assert bit 1 data to 1 in Status_1 register. The
ALERT assertion will be de-asserted when b5 of
Temperature_Zone register is de-asserted from 1 to 0
(which means TSEN voltage falls under 1.735V), and bit 1
of Status_1 register will also be cleared to 0. The bit 1
assertion of Status_1 is not latched and cannot be cleared
by GetReg command.
When b7 of Temperature_Zone register asserts to 1 (when
TSEN voltage rises above 1.845V), the VRHOT signal will
be asserted to low. The VRHOT assertion will be deasserted when b6 of Temperature_Zone register is deasserted from 1 to 0 (which means TSEN voltage falls
under 1.79V).
It is typically recommended to connect a pull-up resistor
from the VRHOT pin to a voltage source.
Current Monitoring and Current Reporting
The CORE VR provides current monitoring function via
sensing the voltage difference of IMONFB pin and output
voltage. In G-NAVPTM technology, the output voltage is
dependent to output current, and the current monitoring
function is achieved by this characteristic of output voltage.
Figure 12 shows the current monitoring setting principle.
The equivalent output current will be sensed from IMONFB
pin and mirrored to IMON pin. The resistor connected to
IMON pin determines voltage gain of the IMON output.
The current monitor indicator equation is shown as :
I
x RDROOP x RIMON
(23)
VIMON = LOAD
RIMONFB
where ILOAD is the output load current, RDROOP is the
equivalent load line resistance, and RIMON and RIMONFB are
the current monitor current setting resistors.
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38
b3
88%
1.625V
b2
85%
1.57V
b1
82%
1.515V
b0
75%
1.46V
In VR12/IMVP7 specification, the voltage signal of current
monitoring will be restricted by a maximum value. Platform
designers have to select RIMON to meet the maximum
voltage of IMON at full load. To find RIMON and RIMONFB
based on :
VIMON(MAX)
RIMON
(24)
=
RIMONFB IMAX x RDROOP
where the VIMON(MAX) is the maximum voltage at full load,
and I(MAX) is the full load current of VR.
Current Mirror
VFB + 2(VISEN, Total)
OLL EN
+
VCC_SENSE
-
IMirror
VFB
IMONFB RIMONFB
IMON
RIMON
Figure 12. CORE VR : Current Monitoring Circuit
When the droop function is disabled, VCC_SENSE no longer
varies with output current, so the current monitoring
function is adaptively changed internally under this
situation. The equation will be rewritten as :
I
x RDCR x RIMON x 2
VIMON, NO_DROOP = LOAD
RIMONFB
(25)
VIMON(MAX)
RIMON
=
RIMONFB IMAX x RDCR x 2
(26)
The ADC circuit of the CORE VR monitors the voltage
variation at the IMON pin from 0V to 3.3V, and this voltage
is decoded into digital format and stored into
Output_Current register. The ADC divides 3.3V into 255
levels, so LSB = 3.3V/255 = 12.941mV. Platform
designers should design VIMON to be 3.3V at ICCMAX.
For example, when load current = 50% x ICCMAX, VIMON
= 1.65V and Output_Current register = 7Fh.
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RT8859M
The IMON pin is an output of the internal operational
amplifier and sends out IMON signal. When the data of
Output_Current register reaches 255d (when IMON voltage
rises above 3.3V), the ALERT signal will be asserted to
low, which is so-called SVID ICCMAX alert. In the mean
time, the CORE VR will assert the bit 2 data to 1 in
Status_1 register. The ALERT assertion will be de-asserted
when the data of Output_Current register decreases to
242d (when IMON voltage falls under 3.144V). The bit 2
assertion of Status_1 register is latched and can only be
cleared when two criteria are met : the data of
Output_Current register decreases to 242d (when IMON
voltage falls under 3.144V) and the GetReg command is
sent to the Status_1 register of the CORE VR.
Quick Response
Current Mirror
QR trigger
VDAC
+
-
IMirror
IMONFB RIMONFB
Therefore, with a little modification of equation (12), the
pulse width of quick response pulse can be calculated
as :
V
tON, QR = QRSET x tON
1.2
−12
=
20.33 x 10 x RTON x VQRSET
VIN − VDAC
After generating a quick response pulse, the pulse is then
applied to the on-time generation circuit, and all the active
phases' on-times will be overridden by the quick response
pulse.
Over Current Protection
The CORE VR compares a programmable current limit
set point to the voltage from the current sense amplifier
output of each phase for Over Current Protection (OCP).
Therefore, the OCP mechanism of the RT8859M
implements per-phase current protections. The voltage
applied to the OCSET pin defines the desired current limit
threshold, ILIMIT :
VCC_SENSE
VOCSET = 48 x ILIMIT x RSENSE
Figure 13. CORE VR : Quick Response Triggering
Circuit
The CORE VR utilizes a quick response feature to support
heavy load current demand during instantaneous load
transient. The CORE VR monitors the current of the
IMONFB pin, and this current is mirrored to internal quick
response circuit. At steady state, this mirrored current
will not trigger a quick response. When the VOUT, CORE
voltage drops abruptly due to load apply transient, the
mirrored current flowing into quick response circuit will
also increase instantaneously. When the mirrored current
instantaneously rises above 5μA , quick response will be
triggered.
When quick response is triggered, the quick response
circuit will generate a quick response pulse. The internal
quick response pulse generation circuit is similar to the
on-time generation circuit. The only difference is the
QRSET pin. The voltage at the QRSET pin also influences
the pulse width of quick response. A voltage divider circuit
is recommended to be applied to the QRSET pin.
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(27)
(28)
Connect a resistive voltage divider from VCC to GND, and
the joint of the resistive voltage divider is connected to
the OCSET pin as shown in Figure 14. For a given ROC2,
⎛ VCC
⎞
ROC1 = ROC2 x ⎜
− 1⎟
V
⎝ OCSET
⎠
(29)
VCC
ROC1
OCSET
ROC2
Figure 14. OCP Setting without Temperature
Compensation
The current limit is triggered when per-phase inductor
current exceeds the current limit threshold, ILIMIT, as
defined by VOCSET. The driver will then be forced to turn off
UGATE until the condition is cleared. If the over current
condition of any phase remains valid for 15 cycles, the
CORE VR will trigger OCP latch. Latched OCP forces
PWM into high impedance, which disables internal PWM
logic drivers. If the over current condition is not valid for 15
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RT8859M
continuous cycles, the OCP latch counter will be reset.
When OCP is triggered by the CORE VR, the AXG VR
will also enter soft shut down sequence.
ROC1b =
If inductor DCR is used as the current sense component,
temperature compensation is recommended for proper
protection under all conditions. Figure 15 shows a typical
OCP setting with temperature compensation.
where
α=
RSENSE, HOT
DCR25°C x [1 + 0.00393 x (THOT − 25)]
=
RSENSE, COLD DCR25°C x [1 + 0.00393 x (TCOLD − 25)]
(36)
VCC
ROC1a
REQU, T°C = ROC1a // RNTC, T°C
OCSET
ROC2
Figure 15. OCP Setting with Temperature Compensation
Usually, ROC1a is selected to be equal to the thermistor's
nominal resistance at room temperature. Ideally, assume
VOCSET has the same temperature coefficient as RSENSE
(Inductor DCR) :
VOCSET, HOT
RSENSE, HOT
=
VOCSET, COLD RSENSE, COLD
(31)
Re-write (31) from (30) to get VOCSET at room temperature
ROC1a // RNTC, COLD + ROC1b + ROC2
RSENSE, HOT
=
ROC1a // RNTC, HOT + ROC1b + ROC2
RSENSE, COLD
(32)
VOCSET, 25°C =
(33)
Solving (32) and (33) yields ROC1b and ROC2
ROC2 =
α x REQU, HOT − REQU, COLD + (1 − α ) x REQU, 25°C
VCC
x (1 − α )
(34)
VOCSET, 25°C
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40
The over voltage protection circuit of the CORE VR
monitors the output voltage via the ISEN1N pin after POR.
The supported maximum operating VID of the VR (V(MAX))
is stored in the VOUT_Max register. Once VISEN1N
exceeds “V(MAX) + 150mV”, OVP is triggered and latched.
The CORE VR will try to turn on low side MOSFETs and
turn off high side MOSFETs of all active phases of the
CORE VR to protect the CPU. When OVP is triggered by
the CORE VR, the AXG VR will also enter soft shut down
sequence. A 1μs delay is used in OVP detection circuit
to prevent false trigger. Note that if OFS pin is higher than
0.9V before power up, OVP will trigger at “VMAX +850mV”.
Negative Voltage Protection (NVP)
ROC2
ROC1a / /RNTC, T°C + ROC1b + ROC2
ROC2
ROC1a / /RNTC, 25°C + ROC1b + ROC2
(37)
(30)
According to the basic circuit calculation, we can get
VOCSET at any temperature:
VCC x
(35)
Over Voltage Protection (OVP)
NTC
ROC1b
VOCSET, T °C = VCC x
(α − 1) x ROC2 + α x REQU, HOT − REQU, COLD
(1 − α )
During OVP latch state, the CORE VR also monitors the
ISEN1N pin for negative voltage protection. Since the OVP
latch will continuously turn on all low side MOSFETs of
the CORE VR, the CORE VR may suffer negative output
voltage. As a consequence, when the ISEN1N voltage
drops below −0.05V after triggering OVP, the CORE VR
will trigger NVP to turn off all low side MOSFETs of the
CORE VR while the high side MOSFETs still remains off.
After triggering NVP, if the output voltage rises above 0V,
the OVP latch will restart to turn on all low side MOSFETs.
Therefore, the output voltage may travel between 0V and
−0.05V due to OVP latch and NVP triggering. The NVP
function will be active only after OVP is triggered. A 1μs
delay is used in NVP detection circuit to prevent false
trigger.
Under Voltage Protection (UVP)
The CORE VR implements under voltage protection of
VOUT,CORE. If ISEN1N is less than the internal reference
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RT8859M
VIN, AXG
AXG VR Disable
The AXG VR can be disabled by connecting ISENAN to a
voltage higher than “VCC − 1V”. If not in use, ISENAP,
TSENA and DVDA are recommended to be connected to
VCC, while PWMA is left floating. When AXG VR is
disabled, all SVID commands related to AXG VR will be
rejected.
Loop Control
The AXG VR adopts Richtek's proprietary G-NAVPTM
topology. G-NAVPTM is based on the finite gain peak current
mode with CCRCOT (Constant Current Ripple Constant
On-Time) topology. The output voltage, VOUT, AXG, will
decrease with increasing output load current. The control
loop consists of a PWM modulator with power stage, a
current sense amplifier and an error amplifier as shown in
Figure 16.
RX
+
-
VCS
AI
CX
RC
C
ISENAP
+
ISENAN
-
C1
C2
Offset
Canceling
R2
COMPA
EA
+
FBA
RGNDA
R1
VCCAXG_SENSE
VSSAXG_SENSE
VDAC, AXG
Figure 16. AXG VR : Simplified Schematic for Droop and
Remote Sense in CCM
Droop Setting (with Temperature Compensation)
It's very easy to achieve Active Voltage Positioning (AVP)
by properly setting the error amplifier gain due to the native
droop characteristics. The target is to have
VOUTAXG = VDACAXG − ILOAD x RDROOP
(38)
, then solving the switching condition VCOMP2 = VCS in
Figure 16 yields the desired error amplifier gain as
A x RSENSE
(39)
A V = R2 = I
R1
RDROOP
where AI is the internal current sense amplifier gain, RSENSE
is the current sense resistance (an external sense resistor
or the DCR of the inductor), and RDROOP is the equivalent
load line resistance as well as the desired static output
impedance.
Since the DCR of the inductor is temperature dependent,
the output accuracy may be affected at high temperature
conditions. Temperature compensation is recommended
for the lossless inductor DCR current sense method.
Figure 17 shows a simple but effective way of
compensating the temperature variations of the sense
resistor by using an NTC thermistor placed in the feedback
path.
C2
COMPA
EA
+
FBA
+
Similar to the peak current mode control with finite
compensator gain, the HS_FET on-time is determined by
CCRCOT on-time generator. When load current increases,
VCS increases, the steady state COMPA voltage also
increases and induces VOUT, AXG to decrease, thus achieving
AVP. A near-DC offset canceling is added to the output of
EA to cancel the inherent output offset of finite-gain peak
current mode controller.
VOUT, AXG
L
LS_FET
+
AXG VR
Driver
CMP
Under Voltage Lock Out (UVLO)
During normal operation, if the voltage at the VCC or DVD
pin drops below POR threshold, the CORE VR will trigger
UVLO. The UVLO protection forces all high side MOSFETs
and low side MOSFETs off by shutting down internal PWM
logic drivers. A 3μs delay is used in UVLO detection circuit
to prevent false trigger.
HS_FET
CCRCOT
PWMA
PWM
Logic
COMPA2
by 300mV, the CORE VR will trigger UVP latch. The UVP
latch will turn off both high side and low side MOSFETs.
When UVP is triggered by the CORE VR, the AXG VR
will also enter soft shut down sequence. A 3μs delay is
used in UVP detection circuit to prevent false trigger. If
platform OFS function is enabled (OFS pin not connected
to GND), the UVP function will be disabled.
RGNDA
R2
C1
R1b
R1a
VCCAXG_SENSE
RNTC
VSSAXG_SENSE
VDAC,AXG
Figure 17. AXG VR : Loop Setting with Temperature
Compensation
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RT8859M
Usually, R1a is set to equal RNTC (25°C) and R1b is selected
to linearize the NTC's temperature characteristic. For a
given NTC, the design procedure is to get R1b and R2
first, and then C1 and C2 next. According to equation (39),
to compensate the temperature variations of the sense
resistor, the error amplifier gain (AV) should have the same
temperature coefficient as RSENSE. Hence :
A V, HOT
RSENSE, HOT
(40)
=
A V, COLD RSENSE, COLD
From (37), Av can be obtained at any temperature (T°C)
as :
R2
A V, T °C =
(41)
R1a // RNTC, T °C + R1b
circuit which is described later in the Quick Response
section. Before POR, the RT8859M will source 80μA
current from the QRSETA pin to the external voltage divider
to determine the voltage level while the RT8859M is still
not powered on. Before POR, if the voltage at the QRSETA
pin is higher than 4.5V, the AXG VR will operate in droopenabled mode. If the voltage is lower than 3.2V, the AXG
VR will operate without droop function, which means at
the DC level of DAC voltage. For example, a 5V voltage
divided by two 1kΩ resistors connected to the QRSETA
pin generates 2.54V (5V/2 + 80μA x 1kΩ/2) before POR
and 2.5V (5V/2) after POR.
Loop Compensation
The standard formula for the resistance of NTC thermistor
as a function of temperature is given by :
{(
RNTC, T°C = R25°C e
) ( )}
1
β⎡
− 1 ⎤
298 ⎦⎥
⎣⎢ T+273
(42)
where R25°C is the thermistor's nominal resistance at room
temperature, β is the thermistor's material constant in
Kelvins, and T is the thermistor actual temperature in
Celsius.
To calculate DCR value at different temperatures, use the
equation below :
DCRT°C = DCR25°C x [1+ 0.00393 x (T − 25)]
(43)
where 0.00393 is the temperature coefficient of copper.
For a given NTC thermistor, solving equation (41) at room
temperature (25°C) yields
R2 = AV,
25°C
x (R1b + R1a // RNTC, 25°C)
(44)
where AV, 25°C is the error amplifier gain at room temperature
and can be obtained from equation (39). R1b can be
obtained by substituting (44) to (40),
R1b =
RSENSE, HOT
x (R1a / /RNTC, HOT ) − (R1a / /RNTC, COLD )
RSENSE, COLD
RSENSE, HOT ⎞
⎛
⎜1 − R
⎟
SENSE, COLD ⎠
⎝
Optimized compensation of the AXG VR allows for best
possible load step response of the regulator's output. A
type-I compensator with one pole and one zero is adequate
for a proper compensation. Figure 17 shows the
compensation circuit. Prior design procedure shows how
to select the resistive feedback components for the error
amplifier gain. Next, C1 and C2 must be calculated for the
compensation. The target is to achieve constant resistive
output impedance over the widest possible frequency
range.
The pole frequency of the compensator must be set to
compensate the output capacitor ESR zero :
1
fP =
(46)
2 x π x C x RC
where C is the capacitance of output capacitor, and RC is
the ESR of output capacitor. C2 can be calculated as
below :
C x RC
(47)
R2
The zero of compensator has to be placed at half of the
switching frequency to filter the switching related noise.
Such that,
C2 =
C1 =
(45)
1
(R1b + R1a / /RNTC, 25°C ) x π x fSW
(48)
Droop Disable
TON Setting
The AXG VR's droop function can be enabled or disabled
with different connections of the QRSETA pin. The
connection of the QRSETA pin is usually a voltage divider
High frequency operation optimizes the application by
allowing smaller component size, but with the trade-off of
efficiency due to higher switching losses. This may be
acceptable in ultra portable devices where the load currents
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42
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RT8859M
are lower and the controller is powered from a lower voltage
supply. Low frequency operation offers the best overall
efficiency at the expense of component size and board
space. Figure 19 shows the on-time setting circuit.
Connect a resistor (RTON) between VIN, GFX and TONSETA
to set the on-time of UGATE :
−12
24.4 x 10 x RTON
(49)
tON (VDAC < 1.2V) =
VIN − VDACGFX
where tON is the UGATE turn-on period, VIN is the input
voltage of the AXG VR, and VDAC, AXG is the DAC voltage.
When VDAC, AXG is larger than 1.2V, the equivalent switching
frequency may be too fast at over 500kHz, which is
unacceptable. Therefore, the AXG VR implements a pseudo
constant frequency technology to avoid this disadvantage
of CCRCOT topology. When VDAC, AXG is larger than 1.2V,
the on-time equation will be modified to :
−12
t ON (VDAC
20.33 x 10 x RTON x VDAC, AXG
≥ 1.2V) =
VIN − VDAC, AXG
(50)
On-time translates only roughly to switching frequencies.
The on-times guaranteed in the Electrical Characteristics
are influenced by switching delays in the external HSFET. Also, the dead-time effect increases the effective
on-time, which in turn reduces the switching frequency. It
occurs only in CCM, and during dynamic output voltage
transitions when the inductor current reverses at light or
negative load currents. With reversed inductor current,
the phase go high earlier than normal, extending the ontime by a period equal to the HS-FET rising dead time.
For better efficiency of the given load range, the maximum
switching frequency is suggested to be :
1
fS(MAX) (kHz) =
x
tON − THS−Delay
CCRCOT
On-Time
Computer
TONSETA
RTON
R1
VIN, AXG
C1
VDAC, AXG
On-Time
Figure 18. AXG VR : On-Time setting with RC Filter
Differential Remote Sense Setting
The AXG VR includes differential, remote sense inputs to
eliminate the effects of voltage drops along the PC board
traces, CPU internal power routes and socket contacts.
The CPU contains on-die sense pins VCCAXG_SENSE and
VSSAXG_SENSE. Connect the RGNDA to VSSAXG_SENSE.
Connect the FBA to VCCAXG_SENSE with a resistor to build
the negative input path of the error amplifier. The VDAC,AXG
and the precision voltage reference are referred to RGNDA
for accurate remote sensing.
Current Sense Setting
The current sense topology of the AXG VR is continuous
inductor current sensing. Therefore, the controller can be
less noise sensitive. Low offset amplifiers are used for
loop control and over current detection. The internal current
sense amplifier gain (AI) is fixed to be 20. The ISENAP
and ISENAN denote the positive and negative input of the
current sense amplifier.
Users can either use a current sense resistor or the
inductor's DCR for current sensing. Using inductor's DCR
allows higher efficiency as shown in Figure 19. Refer to
below equation for optimum transient performance :
L =R x C
(52)
X
X
DCR
For example, choosing L = 0.36μH with 1mΩ DCR and
VDAC(MAX) + ILOAD(MAX) x ⎡⎣RON _ LS−FET + DCR − RDROOP ⎤⎦ CX = 100nF yields :
VIN(MAX) + ILOAD(MAX) x ⎡⎣RON _ LS−FET − RON _ HS−FET ⎤⎦
0.36μH
RX =
= 3.6k Ω
(53)
1m
Ω × 100nF
(51)
VOUT, AXG
where fS(MAX) is the maximum switching frequency, tHSDELAY is the turn-on delay of HS-FET, VDAC(MAX) is the
maximum VDAC, AXG of application, VIN(MAX) is the maximum
application input voltage, ILOAD(MAX) is the maximum load
of application, RON_LS-FET is the Low side FET RDS(ON),
RON_HS-FET is the High side FET RDS(ON), DCR is the
inductor DCR, and RDROOP is the load line setting.
Copyright © 2012 Richtek Technology Corporation. All rights reserved.
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L
RX
ISENAP
DCR
CX
+ VX -
ISENAN
Figure 19. AXG VR : Lossless Inductor Sensing
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RT8859M
Considering the inductance tolerance, the resistor RX has
to be tuned on board by examining the transient voltage.
If the output voltage transient has an initial dip below the
minimum load line requirement with a slow recovery, RX
is chosen too small. Vice versa, if the resistance is too
large the output voltage transient has only a small initial
dip and the recovery becomes too fast, causing a ring
back to occur.
Using current sense resistor in series with the inductor
can have better accuracy, but at the expense of efficiency.
Considering the equivalent inductance (LESL) of the
current sense resistor, an RC filter is recommended. The
RC filter calculation method is similar to the above
mentioned inductor DCR sensing method.
No Load Offset (SVID & Platform)
The AXG VR features no load offset function which provides
the possibility of wide range positive offset of output voltage.
The no load offset function can be implemented through
the SVID interface or OFSA pin. Users can disable pin
offset function by simply connecting OFSA pin to GND.
The RT8859M will latch the OFSA status after POR.
If pin offset function is enabled, users can decide either to
disable SVID OFS or not by selecting proper resistor
values of TMPMAX pin. After receiving a valid VID, the
RT8859M sinks in 16μA from TMPMAX pin. The voltage
on TMPMAX is
(54)
VTMPMAX = R2
x VCC − 16μA (R1 // R2)
R1 + R2
If VTMPMAX <1V, then the output voltage is
VOUT = VDAC − ILOAD x RDROOP + VPIN−OFS
(55)
If VTMPMAX >1V, then the output voltage is
VOUT = VDAC − ILOAD x RDROOP + VPIN−OFS
+ VSVID−OFS
(56)
The pin offset voltage is set by supplying a voltage into
OFSA pin. The linear range of offset pin voltage is from
0.9V to 1.83V. The pin offset voltage can be calculated as
below :
VPIN−OFSA = VOFSA − 1.2V
(57)
For example, supplying 1.3V at OFSA pin will achieve
100mV offset at the output. Connecting a filter capacitor
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between the OFSA pin and GND is necessary. Designers
can design the offset slew rate by properly setting the
filter bandwidth.
Operation Mode Transition
The RT8859M supports operation mode transition function
at AXG VR for the SetPS command of Intel VR12/IMVP7
CPU. The default operation mode of the AXG VR is PS0,
which is CCM operation. Other operation mode includes
PS2 (single phase DEM operation).
After receiving SetPS command, the AXG VR will
immediately change to the new operation state. When
the AXG VR receives SetPS command of PS2 operation
mode, the AXG VR operates as a single phase DCM
controller and diode emulation operation is activated.
Therefore, an external driver which supports tri-state
shutdown is required for compatibility with PS2 operation
state.
If the AXG VR receives dynamic VID change command
(SetVID), the AXG VR will automatically enter PS0
operation mode. After VOUT, AXG reaches target voltage,
the AXG VR will stay at PS0 state and ignore former SetPS
command. Only by resending SetPS command after
SetVID command will the AXG VR be forced into PS2
operation state again.
Dynamic VID Enhancement
During a dynamic VID event, the charging (dynamic VID
up) or discharging (dynamic VID down) current causes
unwanted load-line effect which degrades the settling time
performance. The DVIDA pin can be used to compensate
the load-line effect, so that the output voltage can settle
to the target value more quickly.
During a dynamic VID up event, the RT8859M sources
out a current (IDVIDA) to DVIDA pin. The voltage on DVIDA
pin is added to DAC during DVID rising to enhance the
dynamic VID performance. Connecting a capacitor in
parallel with a resistor to DVIDA pin is recommended.
IDVIDA is 8μA during a SetVID_Fast event. If it is a
SetVID_Slow event, IDVIDA automatically shrinks to 2μA
(if slow slew rate is 0.25x fast slew rate) or 4μA(if slow
slew rate is 0.5x fast slew rate). This function is null during
a dynamic VID down event.
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RT8859M
Table 6. Temperature_Zone register
DAC
Slew Rate
Control
IDVIDA
+
DVID
Event DVIDA
1/20
+
EA
-
FBA
Figure 20. DVID Compensation Circuit
Thermal Monitoring and Temperature Reporting
The AXG VR provides thermal monitoring function via
sensing TSENA pin voltage. Through the voltage divider
resistors, R1 and RNTC, the voltage of TSENA will be
proportional to VR temperature. When VR temperature
rises, the TSENA voltage also rises. The ADC circuit of
the AXG VR monitors the voltage variation at the TSENA
pin from 1.46V to 1.845V with 55mV resolution. This
voltage is then decoded into digital format and stored into
Temperature_Zone register.
VCC
R2
NTC
TSENA
R1
Figure 21. AXG VR : Thermal Monitoring Circuit
To meet Intel's VR12/IMVP7 specification, platform users
have to set the TSENA voltage to meet the temperature
variation of VR from 75% to 100% VR max temperature.
For example, if the VR max temperature is 100°C,
platform users have to set the TSENA voltage to be 1.46V
when VR temperature reaches 75°C and 1.845V when
VR temperature reaches 100°C. Detailed voltage setting
versus temperature variation is shown in Table 6. The
thermometer code is implemented in Temperature_Zone
register.
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VRHOT
SVID Thermal Alert
b7
100%
1.845V
b6
97%
1.79V
Comparator Trip Points
Temperatures Scaled to maximum = 100%
Voltage Represents Assert bit Minimum Level
b5
94%
1.735V
b4
91%
1.68V
b3
88%
1.625V
b2
85%
1.57V
b1
b0
82%
75%
1.515V 1.46V
The VRHOT pin is an open-drain structure that sends out
active-low VRHOT signal. When b6 of Temperature_Zone
register asserts to 1 (when TSENA voltage rises above
1.79V), the ALERT signal will be asserted to low, which is
so-called SVID thermal alert. In the mean time, the AXG
VR will assert the bit 1 data to 1 in Status_1 register. The
ALERT assertion will be de-asserted when b5 of
Temperature_Zone register is de-asserted from 1 to 0
(which means TSENA voltage falls under 1.735V), and
the bit 1 of Status_1 register will also be cleared to 0. The
bit 1 assertion of Status_1 is not latched and cannot be
cleared by GetReg command.
When b7 of Temperature_Zone register asserts to 1 (when
TSENA voltage rises above 1.845V), the VRHOT signal
will be asserted to low. The VRHOT assertion will be deasserted when b6 of Temperature_Zone register is deasserted from 1 to 0 (which means TSENA voltage falls
under 1.79V).
The thermal monitoring function of the AXG VR can be
disabled by connecting TSENA to VCC. If TSENA is
disabled, all the SVID commands related to
Temperature_Zone register of the AXG VR will be rejected.
Current Monitoring and Current Reporting
The AXG VR provides current monitoring function via
sensing the IMONFBA pin. In G-NAVPTM technology, the
output voltage is dependent on the output current, and
the current monitoring function is achieved by this output
voltage characteristic. Figure 22 shows the current
monitoring setting principle. The equivalent output current
will be sensed from the IMONFBA pin and mirrored to the
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RT8859M
IMONA pin. The resistor connected to the IMONA pin
determines the voltage gain of the IMONA output.
The current monitor indicator equation is shown as :
I
x RDROOP x RIMONA
(58)
VIMONA = LOAD
RIMONFBA
Where ILOAD is the output load current, RDROOP is the
equivalent load line resistance, and RIMONA and RIMONFBA
are the current monitor current setting resistors.
In VR12/IMVP7 specification, the voltage signal of current
monitoring will be restricted by a maximum value. Platform
designers have to select RIMONA to meet the maximum
voltage of IMONA at full load. Find RIMONA and RIMONFBA
based on :
VIMONA(MAX)
RIMONA
=
RIMONFBA IMAX x RDROOP
(59)
where VIMONA(MAX) is the maximum voltage at full load,
and IMAX is the full load current of VR.
designers should design VIMONA to be 3.3V at ICCMAXA.
For example, when load current = 50% x ICCMAXA,
VIMONA = 1.65V and Output_Current register = 7Fh.
The IMONA pin is an output of the internal operational
amplifier and sends out IMONA signal. When the data of
Output_Current register reaches 255d (when IMONA
voltage rises above 3.3V), the ALERT signal will be
asserted to low, which is so-called SVID ICCMAXA alert.
In the mean time, the AXG VR will assert the bit 2 data to
1 in Status_1 register. The ALERT assertion will be deasserted when the data of Output_Current register
decreases to 242d (when IMONA voltage falls under
3.144V). The bit 2 assertion of Status_1 register is latched
and can only be cleared when two criteria are met : the
data of Output_Current register decreases to 242d (when
IMONA voltage falls under 3.144V) and the GetReg
command is sent to the Status_1 register of the AXG VR.
Quick Response
Current Mirror
Current Mirror
VFBA + 2(VISENA)
OLL EN
+
VCCAXG_SENSE
QR trigger
-
IMirror
VFBA
IMirror
IMONFBA RIMONFBA
VDAC, AXG
+
VCCAXG_SENSE
-
IMONFBA RIMONFBA
IMONA RIMONA
Figure 23. AXG VR : Quick Response Triggering Circuit
Figure 22. AXG VR : Current Monitoring Circuit
When the droop function is disabled, VCCAXG_SENSE no
longer varies with output current, so the current monitoring
function is adaptively changed internally under this
situation. The equation will be rewritten as :
VIMONA, NO_DROOP =
2 x ILOAD x RRDCR x RIMONA
RIMONFBA
(60)
VIMONA(MAX)
RIMONA
=
RIMONFBA 2 x IMAX x RDCR
(61)
The ADC circuit of the AXG VR monitors the voltage
variation at the IMONA pin from 0V to 3.3V, and this
voltage is decoded into digital format and stored into the
Output_Current register. The ADC divides 3.3V into 255
levels, so LSB = 3.3V/255 = 12.941mV. Platform
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46
The AXG VR utilizes a quick response feature to support
heavy load current demand during instantaneous load
transient. The AXG VR monitors the current of the
IMONFBA pin, and this current is mirrored to internal quick
response circuit. At steady state, this mirrored current
will not trigger a quick response. When the VOUT, AXG voltage
drops abruptly due to load apply transient, the mirrored
current into quick response circuit will also increase
instantaneously. When the mirrored current
instantaneously rises above 5μA, quick response will be
triggered.
When quick response is triggered, the quick response
circuit will generate a quick response pulse. The internal
quick response pulse generation circuit is similar to the
on-time generation circuit. The only difference is the
QRSETA pin. The voltage at the QRSETA pin also
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RT8859M
influences the pulse width of quick response. A voltage
divider circuit is recommended to be applied to the
QRSETA pin. Therefore, with a little modification of
equation (49), the pulse width of quick response pulse
can be calculated as :
tON, QR
V
= QRSETA x tON
1.2
−12
=
20.33 x 10 x RTON x VQRSETA
VIN − VDAC, AXG
(62)
the over current condition is not valid for 15 continuous
cycles, the OCP latch counter will be reset. When OCP
is triggered by the AXG VR, the CORE VR will also enter
soft shut down sequence.
If inductor DCR is used as the current sense component,
temperature compensation is recommended for proper
protection under all conditions. Figure 25 shows a typical
OCP setting with temperature compensation.
VCC
After generating a quick response pulse, the pulse is then
applied to the on-time generation circuit and the AXG VR's
on-time will be overridden by the quick response pulse.
ROC1a
NTC
ROC1b
OCSETA
Over Current Protection
The AXG VR compares a programmable current limit set
point to the voltage from the current sense amplifier output
of each phase for Over Current Protection (OCP).
Therefore, the OCP mechanism of the RT8859M
implements per-phase current protections. The voltage
applied to the OCSETA pin defines the desired current
limit threshold ILIMIT :
VOCSETA = 48 x ILIMIT x RSENSE
(63)
Connect a resistive voltage divider from VCC to GND, and
the joint of the resistive voltage divider is connected to
the OCSETA pin as shown in Figure 24. For a given ROC2,
⎛ VCC
⎞
ROC1 = ROC2 x ⎜
− 1⎟
⎝ VOCSET
⎠
ROC2
Figure 25. AXG VR : OCP Setting with Temperature
Compensation
Usually, ROC1a is Selected to be equal to the thermistor's
nominal resistance at room temperature. Ideally, assume
VOCSET has the same temperature coefficient as RSENSE
(Inductor DCR) :
VOCSETA, HOT
RSENSE, HOT
=
(64)
VOCSETA, COLD RSENSE, COLD
According to the basic circuit calculation, we can get
VOCSETA at any temperature :
VOCSETA, T°C =
VCC
VCC x
ROC1
OCSETA
(65)
Re-write (64) from (65) to get VOCSETA at room temperature:
ROC2
Figure 24. AXG VR : OCP Setting without Temperature
Compensation
The current limit is triggered when inductor current
exceeds the current limit threshold, ILIMIT, as defined by
VOCSETA. The driver will then be forced to turn off UGATE
until the condition is cleared. If the over current condition
of any phase remains valid for 15 cycles, the AXG VR will
trigger OCP latch. Latched OCP forces PWM into high
impedance, which disables internal PWM logic drivers. If
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DS8859M-05 July 2012
ROC2
ROC1a / /RNTC, 25°C + ROC1b + ROC2
ROC1a // RNTC, COLD + ROC1b + ROC2
RSENSE, HOT
=
ROC1a // RNTC, HOT + ROC1b + ROC2
RSENSE, COLD
(66)
VOCSETA, 25°C =
VCC x
ROC2
ROC1a / /RNTC, 25°C + ROC1b + ROC2
(67)
Solving (66) and (67) yields ROC1b and ROC2
ROC2 =
α × REQU, HOT − REQU, COLD + (1 − α ) × REQU, 25°C
VCC
(68)
× (1 − α )
VOCSETA, 25°C
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RT8859M
ROC1b =
(α − 1) × ROC2 + α × REQU, HOT − REQU, COLD
(69)
(1 − α )
where
α=
RSENSE, HOT
DCR25°C × [1 + 0.00393 × (THOT − 25)]
=
RSENSE, COLD DCR25°C × [1 + 0.00393 × (TCOLD − 25)]
(70)
REQU, T°C = ROC1a // RNTC, T°C
(71)
Over Voltage Protection (OVP)
The over voltage protection circuit of the AXG VR monitors
the output voltage via the ISENAN pin after POR. The
supported maximum operating VID of the VR (V(MAX) ) is
stored in the VOUT_Max register. Once VISENAN
exceeds “V(MAX) + 150mV”, OVP is triggered and latched.
The AXG VR will try to turn on low side MOSFETs and
turn off high side MOSFETs of the AXG VR to protect the
CPU. When OVP is triggered by the AXG VR, the CORE
VR will also enter shut down sequence. A 1μs delay is
used in OVP detection circuit to prevent false trigger. Note
that if OFSA pin is higher than 0.9V before power up,
OVP would trigger when “VMAX + 850mV”.
Negative Voltage Protection (NVP)
During OVP latch state, the AXG VR also monitors the
ISENAN pin for negative voltage protection. Since the OVP
latch will continuously turn on all low side MOSFETs of
the AXG VR, the AXG VR may suffer negative output
voltage. As a consequence, when the ISENAN voltage
drops below −0.05V after triggering OVP, the AXG VR will
trigger NVP to turn off all low side MOSFETs of the AXG
VR while the high side MOSFETs still remaining off. After
triggering NVP, if the output voltage rises above 0V, the
OVP latch will restart to turn on all low side MOSFETs.
Therefore, the output voltage may bounce between 0V
and −0.05V due to OVP latch and NVP triggering. The
NVP function will be active only after OVP is triggered. A
1μs delay is used in NVP detection circuit to prevent false
trigger.
Under Voltage Protection (UVP)
The AXG VR implements under voltage protection of VOUT,
AXG. If VFBA is less than the internal reference by 300mV,
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the AXG VR will trigger UVP latch. The UVP latch will
turn off both high side and low side MOSFETs. When
UVP is triggered by the AXG VR, the CORE VR will also
enter soft shut down sequence. A 3μs delay is used in
UVP detection circuit to prevent false trigger. If platform
OFSA function is enabled (OFSA pin not connected to
GND), the UVP function will be disabled.
Under Voltage Lock Out (UVLO)
During normal operation, if the voltage at the VCC or DVD
pin drops below POR threshold, the AXG VR will trigger
UVLO. The UVLO protection forces all high side MOSFETs
and low side MOSFETs off by shutting down internal PWM
logic driver. A 3μs delay is used in UVLO detection circuit
to prevent false trigger.
Inductor Selection
The switching frequency and ripple current determine the
inductor value as follows :
V − VOUT
LMIN = IN
× TON
(72)
IRipple(MAX)
where tON is the UGATE turn-on period.
Higher inductance yields in less ripple current and hence
higher efficiency. The downside is a slower transient
response of the power stage to load transients. This might
increase the need for more output capacitors, thus driving
up the cost. Select a low loss inductor having the lowest
possible DC resistance that fits in the allotted dimensions.
The core must be large enough not to be saturated at the
peak inductor current.
Output Capacitor Selection
Output capacitors are used to obtain high bandwidth for
the output voltage beyond the bandwidth of the converter
itself. Usually, the CPU manufacturer recommends a
capacitor configuration. Two different kinds of output
capacitors are typically used : bulk capacitors closely
located next to the inductors, and ceramic output
capacitors in close proximity to the load. Latter ones are
for mid-frequency decoupling with especially small ESR
and ESL values, while the bulk capacitors have to provide
enough stored energy to overcome the low frequency
bandwidth gap between the regulator and the CPU.
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Thermal Considerations
Layout Considerations
For continuous operation, do not exceed absolute
maximum junction temperature. The maximum power
dissipation depends on the thermal resistance of the IC
package, PCB layout, rate of surrounding airflow, and
difference between junction and ambient temperature. The
maximum power dissipation can be calculated by the
following formula :
Careful PC board layout is critical to achieve low switching
losses and clean, stable operation. The switching power
stage requires particular attention. If possible, mount all
of the power components on the top side of the board
with their ground terminals flushed against one another.
Follow these guidelines for optimum PC board layout :
`
Keep the high current paths short, especially at the
ground terminals.
`
Keep the power traces and load connections short. This
is essential for high efficiency.
`
When trade-offs in trace lengths must be made, it’s
preferable to let the inductor charging path be longer
than the discharging path.
`
Place the current sense component close to the
controller. ISENxP and ISENxN connections for current
limit and voltage positioning must be made using Kelvin
sense connections to guarantee current sense accuracy.
The PCB trace from the sense nodes should be
paralleled back to the controller.
`
Route high speed switching nodes away from sensitive
analog areas (COMP, FB, ISENxP, ISENxN, etc...)
PD(MAX) = (TJ(MAX) − TA) / θJA
where TJ(MAX) is the maximum junction temperature, TA is
the ambient temperature, and θJA is the junction to ambient
thermal resistance.
For recommended operating condition specifications, the
maximum junction temperature is 125°C. The junction to
ambient thermal resistance, θJA, is layout dependent. For
WQFN-56L 7x7 packages, the thermal resistance, θJA, is
31°C/W on a standard JEDEC 51-7 four-layer thermal test
board. The maximum power dissipation at TA = 25°C can
be calculated by the following formula :
PD(MAX) = (125°C − 25°C) / (31°C/W) = 3.226W for
WQFN-56L 7x7 package
The maximum power dissipation depends on the operating
ambient temperature for fixed T J (MAX) and thermal
resistance, θJA. The derating curve in Figure 26 allows
the designer to see the effect of rising ambient temperature
on the maximum power dissipation.
Maximum Power Dissipation (W)1
3.5
Four Layers PCB
3.0
2.5
2.0
1.5
1.0
0.5
0.0
0
25
50
75
100
125
Ambient Temperature (°C)
Figure 26. Derating Curve of Maximum Power
Dissipation
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49
RT8859M
Outline Dimension
2
1
2
1
DETAIL A
Pin #1 ID and Tie Bar Mark Options
Note : The configuration of the Pin #1 identifier is optional,
but must be located within the zone indicated.
Symbol
Dimensions In Millimeters
Dimensions In Inches
Min
Max
Min
Max
A
0.700
0.800
0.028
0.031
A1
0.000
0.050
0.000
0.002
A3
0.175
0.250
0.007
0.010
b
0.150
0.250
0.006
0.010
D
6.900
7.100
0.272
0.280
D2
5.150
5.250
0.203
0.207
E
6.900
7.100
0.272
0.280
E2
5.150
5.250
0.203
0.207
e
L
0.400
0.350
0.016
0.450
0.014
0.018
W-Type 56L QFN 7x7 Package
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RT8859M
Richtek Technology Corporation
5F, No. 20, Taiyuen Street, Chupei City
Hsinchu, Taiwan, R.O.C.
Tel: (8863)5526789
Richtek products are sold by description only. Richtek reserves the right to change the circuitry and/or specifications without notice at any time. Customers should
obtain the latest relevant information and data sheets before placing orders and should verify that such information is current and complete. Richtek cannot
assume responsibility for use of any circuitry other than circuitry entirely embodied in a Richtek product. Information furnished by Richtek is believed to be
accurate and reliable. However, no responsibility is assumed by Richtek or its subsidiaries for its use; nor for any infringements of patents or other rights of third
parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Richtek or its subsidiaries.
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