RT8113 Single Phase VR11.1 PWM Controller with 7-bit VID General Description The RT8113 is a single-phase PWM buck controller with one integrated MOSFET driver for advanced microprocessor applications such as Atom VCORE or Ibexpeak Graphic Power. This controller maintains the same features as the multi-phase product family. However, it reduces the output to one phase for lower current systems. Features of this controller include adjustable operation frequency, power good indication, external error amplifer compensation, over voltage protection, over current protection, droop enable/disable capability, externally adjustable offset voltage, load transient enhancement (quick response), and enable/shutdown pin to achieve optimal power management solution for various applications. The RT8113 comes in a WQFN-24L 4x4 package. Ordering Information RT8113 Package Type QW : WQFN-24L 4x4 (W-Type) Lead Plating System G : Green (Halogen Free and Pb Free) Features Single-Phase Power Conversion One Embedded MOSFET Driver with Internal Bootstrap Diode VID Table for Intel VR11.1 Continuous Differential Inductor DCR Current Sense Droop Enable/Disable Capability Adjustable Soft-Start Adjustable Frequency Typically at 200kHz Power Good Indication Adjustable Over Current Protection Over Voltage Protection Over Temperature Protection Small 24-Lead WQFN Package RoHS Compliant and Halogen Free Applications Atom VCORE Power Ibexpeak Graphic Power Low Voltage, High Current DC/DC Converter Pin Configurations (TOP VIEW) VID2 VID3 VID4 VID5 VID6 VID7 Note : Richtek products are : RoHS compliant and compatible with the current requirements of IPC/JEDEC J-STD-020. ` Suitable for use in SnPb or Pb-free soldering processes. Marking Information DZ= : Product Code DZ=YM DNN YMDNN : Date Code 24 23 22 21 20 19 VID1 OCSET FBRTN SS COMP FB 1 18 2 17 3 16 GND 4 15 25 5 6 14 13 7 8 PGOOD BOOT UGATE PHASE VCC12 LGATE 9 10 11 12 ADJ OFS RT/EN VCC5 ISP ISN ` WQFN-24L 4x4 DS8113-02 April 2011 www.richtek.com 1 RT8113 Typical Application Circuit 12V C11 R20 RT8113 R19 7 14 VCC12 12V C9 Exposed Pad (25) 9 Option for Disable Drop ADJ Q3 EN PHASE 15 LGATE ISP 2 R16 R1 C1 NTC Q1 L1 R2 VOUT Q2 13 OCSET ISN 11 R5 12 R6 D1 Option for Positive OFS R13 C5 Load R8 VCC5 8 OFS R14 C14 C2 10 C10 C3 R4 R3 RT/EN RRT R18 R15 GND BOOT 17 UGATE 16 FB 6 COMP Option for Negative OFS 19, 20, 21, 22, 23, 24, 1 VID [7:1] 18 PGOOD PGOOD FBRTN 5 3 SS 4 R7 C6 R9 R10 C7 C8 Option R11 R12 VCC_SNS VSS_SNS C12 C13 R17 VTT Function Block Diagram VCC12 Fault Logic Offset OFS Transient Response Enhancement FB Driver Logic MOSFET Driver EA + BOOT UGATE PHASE LGATE GND COMP + CMP PWM - + RT/EN - OV Modulation Waveform Generator OT Thermal Protection + 150mV EAP VID [7:1] FBRTN VR11 VID Table VID Off SS PGOOD Soft Start and Fault Logic +- OC OCSET + /10 OV OC Control MOSFET Driver POR Power On Reset ADJ Current Sense ISP ISN VCC12 5V Regulator VCC5 www.richtek.com 2 DS8113-02 April 2011 RT8113 Functional Pin Description Pin No. Pin Name Pin Function 2 OCSET Over Current Protection Threshold Set Pin. 3 FBRTN 4 SS 5 COMP Return Ground. This pin is Negative Node of the differential Remote Voltage sending. Soft-Start Ramp Slope Set Pin. Connect this pin to FBRTN by a Capacitor to Adjust soft-start slew rate. Compensation Pin. Output of Error Amplifier and Input of PWM comparator. 6 FB Inverting Input of Error Amplifier. 7 ADJ 8 OFS 9 RT/EN Droop Set Pin. Connect a resistor from this pin to GND sets the load line slope. Voltage Offset Pin. This pin sets No-Load Output Voltage Offset. Connect a resistor from this Pin to VCC5 or GND to bidirection set the output voltage no-load offset. Switching Frequency Set Pin. Connect this pin to GND via a resistor to adjust switching frequency and operate with droop function. Connect this pin to VCC5 via a resistor to adjust switching frequency and operate without droop function. 10 VCC5 Internal 5V Regulator Output. 11 ISP Non-Invertering Input of Current Sense Amplifier. 12 ISN Invertering Input of Current Sense Amplifier. 13 LGATE Lower Gate Driver. This pin drives the gate of low side MOSFETs. 14 VCC12 15 PHASE 16 UGATE 17 BOOT 18 PGOOD 12V Power Supply Input Pin. Switch Node of High side Driver. Connect this pin to high-side MOSFETs sources together with the low side MOSFETs drains and inductor. Upper Gate Driver. This pin drives the gate of the high-side MOSFETs. Bootstrap Power Pin. This pin powers the high-side MOSFETs drivers. Connect this pin to the junction of the bootstrap capacitor with the cathode of the bootstrap diode. Power Good Indicator. 19 to 24,1 VID7 to VID1 DAC Voltage Identification Inputs. 25 GND (Exposed Pad) DS8113-02 April 2011 Ground Pin. The exposed pad must be soldered to a large PCB and connected to AGND for maximum power dissipation. www.richtek.com 3 RT8113 Table 1. Output Voltage Program Pin Name VID7 VID6 VID5 VID4 VID3 VID2 VID1 Nominal Output Voltage DACOUT 0 0 0 0 0 0 0 OFF 0 0 0 0 0 0 1 1.60000V 0 0 0 0 0 1 0 1.58750V 0 0 0 0 0 1 1 1.57500V 0 0 0 0 0 0 0 0 1 1 0 0 0 1 1.56250V 1.55000V 0 0 0 0 1 1 0 1.53750V 0 0 0 0 1 1 1 1.52500V 0 0 0 1 0 0 0 1.51250V 0 0 0 1 0 0 1 1.50000V 0 0 0 1 0 1 0 1.48750V 0 0 0 0 0 0 1 1 0 1 1 0 1 0 1.47500V 1.46250V 0 0 0 1 1 0 1 1.45000V 0 0 0 1 1 1 0 1.43750V 0 0 0 1 1 1 1 1.42500V 0 0 1 0 0 0 0 1.41250V 0 0 1 0 0 0 1 1.40000V 0 0 0 0 1 1 0 0 0 0 1 1 0 1 1.38750V 1.37500V 0 0 0 0 1 1 0 0 1 1 0 0 0 1 1.36250V 1.35000V 0 0 1 0 1 1 0 1.33750V 0 0 1 0 1 1 1 1.32500V 0 0 1 1 0 0 0 1.31250V 0 0 1 1 0 0 1 1.30000V 0 0 1 1 0 1 0 1.28750V 0 0 0 0 1 1 1 1 0 1 1 0 1 0 1.27500V 1.26250V 0 0 1 1 1 0 1 1.25000V 0 0 1 1 1 1 0 1.23750V 0 0 1 1 1 1 1 1.22500V 0 1 0 0 0 0 0 1.21250V 0 1 0 0 0 0 1 1.20000V 0 0 1 1 0 0 0 0 0 0 1 1 0 1 1.18750V 1.17500V 0 1 0 0 1 0 0 1.16250V 0 1 0 0 1 0 1 1.15000V 0 1 0 0 1 1 0 1.13750V 0 1 0 0 1 1 1 1.12500V To be continued www.richtek.com 4 DS8113-02 April 2011 RT8113 Table 1. Output Voltage Program Pin Name Nominal Output Voltage DACOUT VID7 0 VID6 1 VID5 0 VID4 1 VID3 0 VID2 0 VID1 0 0 1 0 1 0 0 1 1.10000V 0 1 0 1 0 1 0 1.08750V 0 1 0 1 0 1 1 1.07500V 0 1 0 1 1 0 0 1.06250V 0 1 0 1 1 0 1 1.05000V 0 0 1 1 0 0 1 1 1 1 1 1 0 1 1.03750V 1.02500V 0 0 1 1 1 1 0 0 0 0 0 0 0 1 1.01250V 1.00000V 0 1 1 0 0 1 0 0.98750V 0 0 1 1 1 1 0 0 0 1 1 0 1 0 0.97500V 0.96250V 0 0 1 1 1 1 0 0 1 1 0 1 1 0 0.95000V 0.93750V 0 0 1 1 1 1 0 1 1 0 1 0 1 0 0.92500V 0.91250V 0 1 1 1 0 0 1 0.90000V 0 0 1 1 1 1 1 1 0 0 1 1 0 1 0.88750V 0.87500V 0 1 1 1 1 0 0 0.86250V 0 1 1 1 1 0 1 0.85000V 0 0 1 1 1 1 1 1 1 1 1 1 0 1 0.83750V 0.82500V 1 1 0 0 0 0 0 0 0 0 0 0 0 1 0.81250V 0.80000V 1 0 0 0 0 1 0 0.78750V 1 1 0 0 0 0 0 0 0 1 1 0 1 0 0.77500V 0.76250V 1 0 0 0 1 0 1 0.75000V 1 0 0 0 1 1 0 0.73750V 1 1 0 0 0 0 0 1 1 0 1 0 1 0 0.72500V 0.71250V 1 0 0 1 0 0 1 0.70000V 1 1 0 0 0 0 1 1 0 0 1 1 0 1 0.68750V 0.67500V 1 1 0 0 0 0 1 1 1 1 0 0 0 1 0.66250V 0.65000V 1 0 0 1 1 1 0 0.63750V 1 0 0 1 1 1 1 0.62500V 1.11250V To be continued DS8113-02 April 2011 www.richtek.com 5 RT8113 Table 1. Output Voltage Program Pin Name Nominal Output Voltage DACOUT VID7 1 VID6 0 VID5 1 VID4 0 VID3 0 VID2 0 VID1 0 1 1 0 0 1 1 0 0 0 0 0 1 1 0 0.60000V 0.58750V 1 0 1 0 0 1 1 0.57500V 1 1 0 0 1 1 0 0 1 1 0 0 0 1 0.56250V 0.55000V 1 0 1 0 1 1 0 0.53750V 1 0 1 0 1 1 1 0.52500V 1 0 1 1 0 0 0 0.51250V 1 0 1 1 0 0 1 0.50000V 1 1 1 1 1 1 1 OFF www.richtek.com 6 0.61250V DS8113-02 April 2011 RT8113 Absolute Maximum Ratings (Note 1) Supply Input Voltage, VCC12 --------------------------------------------------------------------- −0.3V to 15V BOOTx to GND DC -------------------------------------------------------------------------------------------------------- −0.3V to 30V < 200ns ------------------------------------------------------------------------------------------------- −0.3V to 42V PHASEx to GND DC -------------------------------------------------------------------------------------------------------- −2V to 15V < 200ns ------------------------------------------------------------------------------------------------- −5V to 30V UGATEx to GND -------------------------------------------------------------------------------------- (VPHASE − 0.3V) to (VBOOT + 0.3V) < 200ns ------------------------------------------------------------------------------------------------- (VPHASE − 5V) to (VBOOT + 5V) LGATEx to GND -------------------------------------------------------------------------------------- (GND − 0.3V) to (VCC + 0.3V) < 200ns ------------------------------------------------------------------------------------------------- (GND − 5V) to (VCC + 5V) Other Pins ---------------------------------------------------------------------------------------------- –0.3V to 6.5V Power Dissipation, PD @ TA = 25°C WQFN-24L 4x4 --------------------------------------------------------------------------------------- 1.923W Package Thermal Resistance (Note 2) WQFN-24L 4x4, θJA ---------------------------------------------------------------------------------- 52°C/W WQFN-24L 4x4, θJC --------------------------------------------------------------------------------- 7°C/W Lead Temperature (Soldering, 10 sec.) ---------------------------------------------------------- 260°C Junction Temperature -------------------------------------------------------------------------------- 150°C Storage Temperature Range ----------------------------------------------------------------------- –65°C to 150°C ESD Susceptibility (Note 3) HBM (Human Body Mode) ------------------------------------------------------------------------- 2kV MM (Machine Mode) --------------------------------------------------------------------------------- 200V Recommended Operating Conditions (Note 4) Supply Input Voltage, VCC12 ----------------------------------------------------------------------- 12V ±10% Junction Temperature Range ------------------------------------------------------------------------- −40°C to 125°C Ambient Temperature Range ------------------------------------------------------------------------- −40°C to 85°C Electrical Characteristics (TA = 25°C, unless otherwise specified) Parameter VCC12 Supply Input Min Typ Max Unit -- 6 -- mA I LOAD = 10mA 4.9 10 5 -- 5.1 -- V mA VCC12 Rising Threshold VCC12_TH VCC12 Rising 9.2 9.7 10.2 V VCC12 Hysteresis VCC12_HY VCC12 Falling -- 0.9 -- V VCC5 Rising Threshold VCC5_TH VCC5 Rising 4.4 4.6 4.8 V VCC5 Hysteresis VCC5_HY VCC5 Falling -- 0.4 -- V VCC12 Supply Current Symbol Test Conditions I CC VCC5 Power VCC5 Output Voltage VCC5 Output Sourcing VCC5 I VCC5 Power-On Reset To be continued DS8113-02 April 2011 www.richtek.com 7 To be continued RT8113 Parameter Symbol RT/EN Chip Disable Threshold VDIS Running Frequency f OSC RT Pin Voltage VRT, GND RT Pin Voltage VRT, VDD Modulation Gain ARAMP Test Conditions RRT = 60kΩ RRT = 60kΩ, connected between RT/EN and GND RRT = 60kΩ, connected between RT/EN and VCC5 Min Typ Max Unit -- -- 0.4 V 180 200 220 kHz 1.52 1.6 1.68 V VCC5− VCC5− VCC5− 1.68 1.6 1.52 V RRT = 60kΩ -- 22 -- %/V 1V to 1.6V −0.5 -- 0.5 % 0.8V to 1V −5 -- 5 mV 0.5V to 0.8V −8 -- 8 mV Reference Voltage Accuracy DAC Accuracy VID Threshold Logic-Low VIL Voltage Logic-High VIH Error Amplifier VID [7:1] -- -- 0.4 V VID [7:1] 0.8 -- -- V DC Gain ADC No Load -- 80 -- dB Gain-Bandwidth GBW CLOAD = 10pF -- 10 -- MHz Slew Rate SR CLOAD = 10pF 10 -- -- V/μs Output Voltage Range VCOMP 0.5 -- 3.6 V Maximum Current I EA_SLEW Slew 300 -- -- μA Power Sequence PGOOD Low Voltage VPGOOD I PGOOD = 4mA -- -- 0.4 V Soft-Start Delay t D1 After POR, from EN = High to VOUT Rising 0 -- 5 ms VBOOT Duration t D3 0.05 -- 3 ms t D5 Measured from final VOUT value to PGOOD = High 0.05 -- 3 ms Maximum Current I GMMAX VCSP = 1.3V, sink current from CSN 100 -- -- μA Input Offset Voltage VOSCS −1.5 0 1.5 mV PGOOD Delay Current Sense Amplifier Soft Start Soft Start Current I SS1 Slew 12 16 20 μA VID Change Current I SS2 Slew 120 160 200 μA 0.6 1 -- A -- 1 -- Ω 0.6 1 -- A -- 0.8 -- Ω 125 150 175 mV −10 -- 10 mV Gate Driver UGATE Drive Source UGATE Drive Sink BOOT – PHASE = 12V, UGATE – PHASE = 6V BOOT – PHASE = 8V, RUGATEsk 250mA Source Current I UGATEsr LGATE Drive Source I LGATEsr VCC12 = 12V, VLGATE = 6V LGATE Drive Sink RLGATEsk 250mA Sink Current Protection Over-Voltage Threshold VOVP OCP Input Offset Voltage VOCOFS Sweep FB Voltage, VFB − VEAP To be continued www.richtek.com 8 DS8113-02 April 2011 RT8113 Parameter Over Temperature Shutdown Setpoint Symbol Test Conditions Min Typ Max Unit TSD -- 160 -- °C UGATE Rise Time trUGATE - 15 - ns UGATE Fall Time tfUGATE - 10 - ns LGATE Rise Time trLGATE - 15 - ns LGATE Rise Time tfLGATE - 10 - ns Dynamic Characteristic Ciss = 3000pF Note 1. Stresses listed as the above “Absolute Maximum Ratings” may cause permanent damage to the device. These are for stress ratings. Functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may remain possibility to affect device reliability. Note 2. θJA is measured in natural convection at TA = 25°C on a high effective thermal conductivity four-layer test board of JEDEC 51-7 thermal measurement standard. The measurement case position of θJC is on the exposed pad of the package. Note 3. Devices are ESD sensitive. Handling precaution is recommended. Note 4. The device is not guaranteed to function outside its operating conditions. DS8113-02 April 2011 www.richtek.com 9 RT8113 Typical Operating Characteristics Start Up from RT/EN Power Off from RT/EN VID = 0.9V, ILOAD = 1A VID = 0.9V, ILOAD = 1A VOUT (1V/Div) VOUT (1V/Div) RT/EN (2V/Div) RT/EN (2V/Div) PGOOD (2V/Div) PGOOD (2V/Div) UGATE (20V/Div) UGATE (20V/Div) Time (1ms/Div) Time (400μs/Div) Dynamic VID Up Dynamic VID Down VID from 1.3V down to 0.675V, ILOAD = 16A VID from 0.675V up to 1.3V, ILOAD = 16A VOUT (500mV/Div) VOUT (500mV/Div) VID1 (1V/Div) VID1 (1V/Div) Time (40μs/Div) Time (40μs/Div) Load Transient Response Load Transient Response 1.2V -> I LOAD 20A 1.2V -> I LOAD 7A Time (10μs/Div) www.richtek.com 10 VID = 1.3V, fLOAD = 1kHz, ILOAD = 20A to 7A VOUT (20mV/Div) VOUT (20mV/Div) VID = 1.3V, fLOAD = 1kHz, ILOAD = 7A to 20A 20A 7A Time (10μs/Div) DS8113-02 April 2011 RT8113 Over Voltage Protection Over Current Protection VFB (1V/Div) VOUT (1V/Div) PGOOD (5V/Div) PGOOD (5V/Div) UGATE (20V/Div) I LOAD (50A/Div) UGATE (50V/Div) LGATE (10V/Div) Time (200μs/Div) DS8113-02 April 2011 Time (20μs/Div) www.richtek.com 11 RT8113 Applications Information Supply voltage, VCC5 regulation and POR There are two supply voltage pins built-in in the RT8113, VCC12 and VCC5. VCC12 is a power input pin which receives external 12V voltage for embedded driver logic operation. VCC5 is a power output pin which is the output of an internal 5V LDO regulator. The mentioned 5V LDO regulator regulates VCC12 to generate a 5V voltage source for internal gate logic and external circuit biasing, e.g., OCP biasing. Since the VCC5 voltage is regulated, the variation of VCC5 (2%) will be much smaller than Platform ATX +5V (5%~7%). The maximum supply current of VCC5 is 10mA, which is designed only for controller circuit biasing. The recommended configuration of the RT8113 supply voltages is as follows: Platform ATX +12V to the VCC12 pin, and decoupling capacitors on the VCC12 and VCC5 pins (minimum 0.1μF). The initialization of the RT8113 requires both the voltage on the VCC12 and VCC5 to be ready. Since VCC5 is regulated internally from VCC12, the VCC5 voltage will be ready (>4.6V) after VCC12 reaches about 7V, so there is no power sequence problem between VCC12 and VCC5. After VCC5 > 4.6V and VCC12 > 9.6V, the internal power-on-reset (POR) signal goes high. This POR signal indicates the power supply voltages are all ready and initiates soft-start sequence. When POR = low, The RT8113 will try to turn off both high-side and low-side MOSFETs to prevent catastrophic failure. VCC12 9.6V + CMP - 4.6V + CMP - VCC5 POR POR : Power ON Reset Figure 1. Circuit for Power Ready Detection www.richtek.com 12 Switching Frequency The switching frequency of the RT8113 is set by an external resistor connected from the RT/EN pin either to GND or to VCC5. If the resistor is connected from RT/EN to GND, the load line function will be enabled as well. More details will be described in the Load Line section. The frequency follows the graph in Figure 2. 1000 Switching Frequency (kHz)1 The RT8113 is a single-phase synchronous buck DC/DC converter with embedded MOSFET driver. The internal VID DAC is designed to interface with the Intel 7-bit VR11.X compatible VID table for Ibexpeak platform CPU’s AXG VR application. 800 600 400 200 0 0 10 20 30 40 50 60 70 80 RRT (kΩ) Figure 2. Switching Frequency vs. RRT Resistance Chip Enable The enable function of the RT8113 is combined in the RT/EN pin. Besides frequency setting function, pulling the RT/EN pin to GND can also force the RT8113 to enter soft shutdown sequence. It is recommended to connect a control switch from the RT/EN pin to GND in parallel with RT setting resistors. The RT8113 will enter soft shutdown sequence when the control switch is turned on. Soft-Start The VOUT soft-start slew rate is set by a capacitor from the SS pin to FBRTN. Before power on reset (POR = low), the SS pin is held at GND. After power on reset (POR = high) and an extra delay of 1600μs (tD1), the controller initiates ramping up. VOUT will always trace VEAP during normal operation of the RT8113, where VEAP is the positive input of compensation error amplifier, which can be described as VEAP = VDAC − VADJ (The definition of VADJ will be described later in the Load Line section). The first ramping up duration of VOUT (tD2) ramps VOUT to VBOOT. DS8113-02 April 2011 RT8113 After VOUT ramps to VBOOT, the RT8113 stays in this state for 800μs (tD3) waiting for valid VID code sent by CPU. After receiving valid VID code, VOUT continues ramping up or down to the voltage specified by VID code. After VOUT ramps to VEAP = VDAC − VADJ, the RT8113 stays in this state for 1600μs (tD5) and then asserts PGOOD = high. The ramping slew rate of tD2 and tD4 is controlled by the external capacitor connected to SS pin. The voltage of the SS pin will always be VEAP+0.7V, where the mentioned 0.7V is the typical turn-on threshold of an internal power switch. Before PGOOD = high, the slew rate of VEAP is limited to 16μA/CSS. When PGOOD = high, the slew rate of VEAP is limited to 160μA/CSS, which is 10 times faster than soft start slew rate for dynamic VID feature. The soft start waveform is shown in Figure 4. C2 C3 R3 R2 R1 VOUT FB Soft Start Current (ISS) is Limited and Variant Soft Start Circuit VDAC C1 COMP EA + EAP (Error AMP Positive Input) ISS SS CSS ADJ RADJ Figure 3. Circuit for Soft-Start and Dynamic VID VCC5 VCC12 4.6V 9.6V VDAC SS VOUT VBOOT PGOOD tD1 tD2 tD3 tD4 tD5 Figure 4. Soft-Start Wave forms DS8113-02 April 2011 www.richtek.com 13 RT8113 tD1 is the delay time from power on reset state to the beginning of VOUT rising. 0.7V x CSS 16μA tD2 is the soft-start time from VOUT = 0 to VOUT = VBOOT . V x CSS tD2 = BOOT 16μA tD3 is the dwelling time for VOUT = VBOOT . tD1 = 1600μs + tD3 ≅ 800μs. tD4 is the soft-start time from VOUT = VBOOT to VOUT = VDAC . VDAC - VBOOT x Css tD4 ≅ 16μA tD5 is the power good delay time. tD5 ≅ 1600μs. Dynamic VID Output Voltage Differential Sensing The RT8113 can accept VID input changing while the controller is running. This allows the output voltage (VOUT) to change while the DC/DC converter is running and supplying current to the load. This is commonly referred to as VID on-the-fly (OTF). A VID OTF can occur under either light or heavy load conditions. The CPU changes the VID inputs in multiple steps from the start code to the finish code. This change can be positive or negative. Theoretically, V OUT should follow V DAC, which is a staircase waveform, but in real application, the bandwidth of the converter is finite while the staircase waveform needs infinite bandwidth to follow. Thus, undesired VOUT overshoot (when VDAC changes up) or undershoot (when VDAC changes down) is often observed in these type of designs. However, for the RT8113, as mentioned before in the Soft-Start section, VDAC slew rate is limited by ISS2/CSS when PGOOD = high. This slew rate limiter works as a low-pass filter of VDAC and makes the bandwidth of VDAC waveform finite. By smoothening VDAC staircase waveform, VOUT will no longer overshoot or undershoot. On the other hand, CSS will increase the settling time of VOUT during VID OTF. In most cases, a 1nF to 30nF ceramic capacitor will be suitable for CSS. The RT8113 uses a high-gain low-offset error amplifier for differential sensing. The CPU voltage is sensed between the FB and FBRTN pins. A resistor (RFB) connects the FB pin with the positive remote sense pin of the CPU (VCCP), while the FBRTN pin connects directly to the negative remote sense pin of the CPU (VCCN). The error amplifier compares VEAP (= VDAC − VADJ) with the VFB to regulate the output voltage. www.richtek.com 14 No-Load Offset In Figure 5, IOFSN and IOFSP are used to generate no-load offset. Either IOFSN or IOFSP is active during normal operation. Connect a resistor from OFS pin to GND to activate IOFSN. IOFSN flows through RFB from the FB pin to VCCP. In this case, a negative no-load offset voltage (VOFSN) is generated. VOFSN = IOFSN x RFB = 0.8 x RFB ROFS Connect a resistor from the OFS pin to VCC5 to activate IOFSP. IOFSP flows through RFB from the VCCP to the FB pin. In this case, a positive no-load offset voltage (VOFSP) is generated. 6.4 x RFB VOFSP = IOFSP x RFB = ROFS DS8113-02 April 2011 RT8113 C2 CFB R1 C1 IOFSP RFB VCC_SNS (Positive Remote Sense Pin of CPU) FB IOFSP + + +- EAP COMP - VDAC - VSS_SNS (Negative Remote Sense Pin of CPU) FBRTN RADJ ADJ Figure 5. Circuit for VOUT Differential Sensing and No Load Offset Load Transient Quick Response In steady state, the voltage of VFB is controlled to be very close to VEAP. However While a load step transient from light load to heavy load could cause VFB to be lower than VEAP by several tens of mV. In conventional buck converter design (without non-linear control) for CPU VR application, due to limited control bandwidth, it is hard for the VR to prevent VOUT undershoot during quick load transient from light load to heavy load. Hence, the RT8113 builds in a state-of-the-art quick response function which detects load CFB VOUT transient by comparing VFB and VEAP. If VFB suddenly drops below “VEAP − VQR”where VQR is a predetermined voltage (~40mV), the quick response indicator QR rises up. When QR = high, the RT8113 turns on all high side MOSFETs and turns off all low side MOSFETs. The sensitivity of quick response can be adjusted by varying the values of CFB and RFB. Smaller RFB and/or larger CFB will make QR easier to be triggered. Figure 6 is the circuit and typical waveforms. C2 RFB R1 IOUT VOUT C1 COMP FB QR Circuit VEAP = VDAC - VADJ EA + QR Figure 6. Load Transient Quick Response DS8113-02 April 2011 www.richtek.com 15 RT8113 Output Current Sensing The RT8113 provides a low input offset current-sense amplifier (CSA) to monitor the output current. The output current of CSA (IX) is used for load line control and overcurrent protection. In this inductor current sensing topology, RS and CS must be set according to the equation below : L = RS x CS DCR 700nA is a typical value of the CSA input offset current. VOFS-CSA is the input offset voltage of CSA. VOFS-CSA of the RT8113 is smaller than +/- 1.5mV. Usually, “VOFS-CSA + 700n x (RCSP + RS - RCSN)” is negligible except at very light load and the equation can be simplified as the equation below : I x DCR IX = L RCSN Then the output current of CSA will follow the equation below : I x DCR - VOFS-CSA + 700n x (RCSP + RS - RCSN ) IX = L RCSN VIN BOOT UGATE R1 C1 L DCR RS CS PHASE R2 LGATE CSA: Current Sense Amplifier C2 ISP + 700nA IX VOFS_CSA RCSP + - 700nA ISN - RCSN Figure 7. Circuit for Current Sensing www.richtek.com 16 DS8113-02 April 2011 RT8113 Load Line The RT8113 utilizes inductor DCR current sense technique for load line control function. The sensed inductor current IX is multiplied by 0.5 and sent to ADJ pin. After the current 0.5 x IX injects into the ADJ resistors, the voltage of the ADJ pin is established. The VADJ is then multiplied by 0.1 and subtracted by VDAC to generate VEAP. Because IX is a PTC (Positive Temperature Coefficient) current, an NTC (Negative Temperature Coefficient) resistor is needed to connect ADJ pin to GND. If the NTC resistor is properly selected to compensate the temperature coefficient of IX, the voltage on ADJ pin will be proportional to IOUT without temperature effect. In the RT8113, the positive input of error amplifier is “VDAC − 0.1 x VADJ” and VOUT will follow “VDAC − 0.1 x VADJ”. Thus, the output voltage which decreases linearly with IOUT is obtained. The load line is defined as : 1 x IX x R ADJ 2 ΔVOUT ΔVADJ DCR x R ADJ 1 LL(Load Line) = = x = ΔIOUT 10 ΔIOUT 20 x RCSN ΔVADJ = Basically, the resistance of RADJ sets the resistance of the load line. The temperature coefficient of R ADJ compensates the temperature effect of the load line. The load line function of the RT8113 can be disabled by connecting the RT/EN pin resistor to VCC5 instead of GND. When the RT/EN pin resistor is connected to VCC5, the current-sense circuit works normally while VEAP no longer contains droop, and the reference voltage of the error amplifier will remain equal to VDAC regardless of output current. The running frequency of the RT8113 will always be the same whether connecting RT/EN to VCC5 or GND. Over Current Protection (OCP) In Figure 8, VOCSET is equal to VCC x R2/(R1 + R2). For the RT8113, VADJ is proportional to IOUT and is thermally compensated. Once VADJ is larger than VOCSET, OCP is triggered and latched. The OCP function will not be influenced by enabling or disabling load line since the voltage on the ADJ pin always contains real-time information of load current. Once OCP is triggered, the RT8113 will turn off both high-side MOSFETs and low side MOSFETs. DS8113-02 April 2011 VCC5 or VCC12 ADJ R1 OCSET + CMP - OCP R2 Figure 8. Over Current Protection Over Voltage Protection (OVP) The over-voltage protection monitors the output voltage via the FB pin. Once VFB exceeds“VEAP + 150mV”, OVP is triggered and latched. The RT8113 will turn on low-side MOSFET and turn off high side MOSFET to protect CPU. A 20μs delay is used in OVP detection circuit to prevent false trigger. Over Temperature Protection (OTP) The over-temperature protection function of the RT8113 is built inside the controller to prevent overheat damage. OTP occurs when the die temperature of the RT8113 exceeds 160°C, in which the RT8113 then turns off both high-side MOSFETs and low side MOSFETs. Loop Compensation The RT8113 is a voltage mode controller and requires external compensation. To compensate a typical voltage mode buck converter, there are two ordinary compensation schemes, commonly known as type-II compensator and type-III compensator. The choice of using type-II or typeIII compensator lies with the platform designers, and the main concern deals with the position of the capacitor ESR zero and mid-frequency to high-frequency gain boost. Typically, the ESR zero of output capacitor will tend to stabilize the effect of output LC double poles. Hence, the position of the output capacitor ESR zero in frequency domain may influence the design of voltage loop compensation. Figure 9 shows a typical control loop using type-III compensator. Below is the compensator design procedure. www.richtek.com 17 RT8113 VIN OSC Driver PWM Comparator L - ΔVOSC VOUT Driver + COUT ESR The ESR zero is contributed by the ESR associated with the output capacitance. Note that this requires the output capacitor to have enough ESR to satisfy stability requirements. The ESR zero of the output capacitor is expressed as the following equation : 1 fESR = 2π x COUT x ESR ZFB ZIN EA + fP2 fP3 Gain fZ1 fZ2 COMP Modulator Gain Compensation Gain Closed Loop Gain REF C1 C3 R2 VOUT 0 R3 R1 COMP EA + ZIN FB LOG ZFB C2 LOG REF fLC fESR fC Frequency Figure 10. Bode PLot of Loop Gain Figure 9. Compensation Circuit 1) Modulator Characteristic The modulator consists of the PWM comparator and power stage. The PWM comparator compares error amplifier EA output (COMP) with oscillator (OSC) sawtooth wave to provide a pulse-width modulated (PWM) gate-driving signal. The PWM wave is smoothed out by the output filter, LOUT and COUT. The output voltage (VOUT) is sensed and fed to the inverting input of the error amplifier. The modulator transfer function is the small-signal transfer function of VOUT/VCOMP (output voltage over the error amplifier output). This transfer function is dominated by a DC gain, a double pole, and an ESR zero as shown in Figure 10. The DC gain of the modulator is the input voltage (VIN) divided by the peak-to-peak oscillator voltage VOSC. The output LC filter introduces a double pole, 40dB/decade gain slope above its corner resonant frequency, and a total phase lag of 180 degrees. The resonant frequency of the LC filter is expressed as : fLC = 1 2π x LOUT x COUT www.richtek.com 18 2) Design the compensator A well-designed compensator regulates the output voltage to the reference voltage VREF with fast transient response and good stability. In order to achieve fast transient response and accurate output regulation, an adequate compensator design is necessary. The goal of the compensation network is to provide adequate phase margin (usually greater than 45°C) and the highest bandwidth (0dB crossing frequency, fC) possible. It is also recommended to manipulate loop frequency response that its gain crosses over 0dB at a slope of -20dB/dec. According to Figure 10, the location of poles and zeros are : 1 fZ1 = 2π x R2 x C1 1 fZ2 = 2π x (R1 + R3) x C3 fP1 = 0 1 2π x C3 x R3 1 fP3 = C1 x C2 x R2 2π x C1 + C2 fP2 = Generally, fZ1 and fZ2 are designed to cancel the double pole of modulation. Usually, place fZ1 at a fraction of the DS8113-02 April 2011 RT8113 For given bandwith, R2, fZ1, fZ2, fP2, fP3, then 1 C1 = 2π x fZ1 x R2 C3 = R1 = R3 = C2 = GMOD@BW 2π x fC x R2 1 2π x fZ2 x C3 2.00 Maximum Power Dissipation (W)1 fLC, and place fZ2 at fLC. fP2 is usually placed at fESR to cancel the ESR zero. And fP3 is placed below switching frequency to cancel high frequency noise. 1 1.50 1.25 1.00 0.75 0.50 0.25 0.00 0 2π x fP2 x C3 2π x fP3 Four-Layer PCB 1.75 25 50 75 100 125 Ambient Temperature (°C) C1 x C1 x R2 -1 Figure 11. Derating Curves for RT8113 Package Thermal Considerations Layout Considerations For continuous operation, do not exceed absolute maximum junction temperature. The maximum power dissipation depends on the thermal resistance of IC package, PCB layout, rate of surrounding airflow and temperature difference between junction to ambient. The maximum power dissipation can be calculated by following the formula : For best performance of the RT8113, the following guidelines must be strictly followed : ` The power components should be placed first. Keep the connection between power components as short as possible. ` The shape of the phase plane (the connection plane between high side MOSFETs, low-side MOSFETs and output inductors) has to be as square as possible. Long traces, thin bars or separated islands must be avoided in the phase plane. ` Keep snubber circuits or damping elements near its objects. Phase RC snubbers have to be close to lowside MOSFETs, UGATE damping resistor has to be close to high-side MOSFETs, and boot to phase damping resistor has to be close to high-side MOSFETs and phase plane. Also, keep the traces of these snubber circuits as short as possible. ` The area of VIN plane (power stage 12V VIN) and VOUT plane (output bulk capacitors and inductor connection plane) has to be as wide as possible. Long traces or thin bars must be avoided in these planes. The plane trace width must be wide enough to carry large input/ output current (40mm/A). ` The following traces have to be wide and short : UGATE, LGATE, BOOT, PHASE, and VCC12. Make sure the widths of these traces are wide enough to carry large driving current (at least 40mm). PD(MAX) = (TJ(MAX) − TA ) / θJA where TJ(MAX) is the maximum junction temperature, TA is the ambient temperature and θJA is the junction to ambient thermal resistance. For recommended operating conditions specification of the RT8113, the maximum junction temperature is 125°C and TA is the ambient temperature. The junction to ambient thermal resistance θ JA is layout dependent. For WQFN-24L 4x4 packages, the thermal resistance θJA is 52°C/W on the standard JEDEC 51-7 four-layer thermal test board. The maximum power dissipation at TA = 25°C can be calculated by the following formula : PD(MAX) = (125°C − 25°C) / (52°C/W) = 1.923W for WQFN-24L 4x4 package The maximum power dissipation depends on operating ambient temperature for fixed T J (MAX) and thermal resistance θJA. For RT8113 package, the derating curve in Figure 11 allows the designer to see the effect of rising ambient temperature on the maximum power dissipation. DS8113-02 April 2011 www.richtek.com 19 RT8113 ` The voltage feedback loop contains two traces, VCC and VSS, which are Kelvin sensed from CPU socket or output capacitors. These two traces should have 10mm width and be placed away from high (di/dt) switching elements such as high-side MOSFETs, low-side MOSFETs, phase plane etc. The circuit elements of voltage feedback loop, such as feedback loop short resistors and voltage loop compensation RCs, have to be kept near the RT8113 and also away from switching elements. ` The current-sense mechanism of the RT8113 is fully differential Kelvin sense. Therefore, the current-sense loop of the RT8113 contain two traces : the positive trace(ISP) comes from the positive node the of output inductor (the node connecting phase plane) and the negative trace (ISN) comes from the negative node of the output inductor (the node connecting output plane). DO NOT connect the current-sense traces from the phase plane or output plane. Only connect these traces from both sides of the output inductor to achieve the goal of precise Kelvin sense. The current-sense feedback loops have to be routed away from switching elements, and the current-sense RC elements have to be put near their respective ISN or ISP pins of the RT8113 and also away from noise switching elements. At lease 10 mm width is suggested for current sense feedback loops. www.richtek.com 20 DS8113-02 April 2011 RT8113 Outline Dimension D2 D SEE DETAIL A L 1 E E2 e b 1 1 2 2 DETAIL A Pin #1 ID and Tie Bar Mark Options A A3 A1 Note : The configuration of the Pin #1 identifier is optional, but must be located within the zone indicated. Dimensions In Millimeters Dimensions In Inches Symbol Min Max Min Max A 0.700 0.800 0.028 0.031 A1 0.000 0.050 0.000 0.002 A3 0.175 0.250 0.007 0.010 b 0.180 0.300 0.007 0.012 D 3.950 4.050 0.156 0.159 D2 2.300 2.750 0.091 0.108 E 3.950 4.050 0.156 0.159 E2 2.300 2.750 0.091 0.108 e L 0.500 0.350 0.020 0.450 0.014 0.018 W-Type 24L QFN 4x4 Package Richtek Technology Corporation Richtek Technology Corporation Headquarter Taipei Office (Marketing) 5F, No. 20, Taiyuen Street, Chupei City 5F, No. 95, Minchiuan Road, Hsintien City Hsinchu, Taiwan, R.O.C. Taipei County, Taiwan, R.O.C. Tel: (8863)5526789 Fax: (8863)5526611 Tel: (8862)86672399 Fax: (8862)86672377 Email: [email protected] Information that is provided by Richtek Technology Corporation is believed to be accurate and reliable. Richtek reserves the right to make any change in circuit design, specification or other related things if necessary without notice at any time. No third party intellectual property infringement of the applications should be guaranteed by users when integrating Richtek products into any application. No legal responsibility for any said applications is assumed by Richtek. DS8113-02 April 2011 www.richtek.com 21