SANYO LV8729V

Ordering number : ENA1702C
LV8729V
Bi-CMOS LSI
PWM Constant-Current Control
Stepping Motor Driver
Overview
The LV8729V is a PWM current-controlled microstep bipolar stepping motor driver.
This driver can perform eight times of excitation of the second phase to 32W1-second phase and can drive simply by the
CLK input.
Features
• Single-channel PWM current control stepping motor driver.
• BiCDMOS process IC.
• Output on-resistance (upper side : 0.35Ω ; lower side : 0.3Ω ; total of upper and lower : 0.65Ω ; Ta = 25°C, IO = 1.8A)
• 2-phase, 1-2 phase, W1-2 phase, 2W1-2 phase, 4W1-2 phase, 8W1-2 phase, 16W1-2 phase, 32W1-2 phase excitation are
selectable.
• Advance the excitation step with the only step signal input.
• Available forward reverse control.
• Over current protection circuit.
• Thermal shutdown circuit.
• Input pull down resistance
• With reset pin and enable pin.
Specifications
Absolute Maximum Ratings at Ta = 25°C
Parameter
Maximum supply voltage
Symbol
Conditions
Ratings
Unit
VM max
36
V
Maximum output peak current
IO max
1.8
A
Maximum logic input voltage
VIN max
6
V
Maximum VREF input voltage
VREF max
6
V
Maximum MO input voltage
VMO max
6
V
Continued on next page.
Any and all SANYO Semiconductor Co.,Ltd. products described or contained herein are, with regard to
"standard application", intended for the use as general electronics equipment (home appliances, AV equipment,
communication device, office equipment, industrial equipment etc.). The products mentioned herein shall not be
intended for use for any "special application" (medical equipment whose purpose is to sustain life, aerospace
instrument, nuclear control device, burning appliances, transportation machine, traffic signal system, safety
equipment etc.) that shall require extremely high level of reliability and can directly threaten human lives in case
of failure or malfunction of the product or may cause harm to human bodies, nor shall they grant any guarantee
thereof. If you should intend to use our products for applications outside the standard applications of our
customer who is considering such use and/or outside the scope of our intended standard applications, please
consult with us prior to the intended use. If there is no consultation or inquiry before the intended use, our
customer shall be solely responsible for the use.
Specifications of any and all SANYO Semiconductor Co.,Ltd. products described or contained herein stipulate
the performance, characteristics, and functions of the described products in the independent state, and are not
guarantees of the performance, characteristics, and functions of the described products as mounted in the
customer' s products or equipment. To verify symptoms and states that cannot be evaluated in an independent
device, the customer should always evaluate and test devices mounted in the customer' s products or
equipment.
20211 SY/90110 SY/81110 SY/42110 SY 20100331-S00001 No.A1702-1/26
LV8729V
Continued from preceding page.
Parameter
Maximum DOWN input voltage
Symbol
Conditions
Ratings
Unit
VDOWN max
6
*
V
Allowable power dissipation
Pd max
3.85
W
Operating temperature
Topr
-30 to +85
°C
Storage temperature
Tstg
-55 to +150
°C
* Specified circuit board : 90.0mm×90.0mm×1.6mm, glass epoxy 2-layer board, with backside mounting.
Allowable Operating Ratings at Ta = 25°C
Parameter
Symbol
Conditions
Ratings
Unit
Supply voltage range
VM
9 to 32
V
Logic input voltage
VIN
0 to 5
V
VREF input voltage range
VREF
0 to 3
V
Electrical Characteristics at Ta = 25°C, VM = 24V, VREF = 1.5V
Parameter
Standby mode current drain
Symbol
Conditions
IMst
ST = “L”
Current drain
IM
ST = “H”, OE = “H”, no load
Thermal shutdown temperature
TSD
Design guarantee
Thermal hysteresis width
ΔTSD
Design guarantee
Logic pin input current
IINL
VIN = 0.8V
IINH
VIN = 5V
Logic high-level input voltage
VINH
Logic low-level input voltage
VINL
Chopping frequency
Fch
OSC1 pin charge/discharge current
Ratings
min
typ
100
μA
3.3
4.6
mA
180
200
°C
70
150
Unit
max
°C
40
3
8
15
μA
30
50
70
μA
2.0
V
0.8
V
70
100
130
kHz
Iosc1
7
10
13
μA
Chopping oscillation circuit
Vtup1
0.8
1
1.2
V
threshold voltage
Vtdown1
0.3
0.5
0.7
V
VREF pin input voltage
Iref
DOWN output residual voltagr
VO1DOWN
Idown = 1mA
40
100
mV
MO pin residual voltage
VO1MO
Imo = 1mA
40
100
mV
Hold current switching frequency
Fdown
Cosc2 = 1500pF
1.12
1.6
2.08
Hz
Hold current switching frequency
Vtup2
0.8
1
1.2
V
threshold voltage
Vtdown2
0.3
0.5
0.7
V
VREG1 output voltage
Vreg1
4.7
5
5.3
V
VREG2 output voltage
Vreg2
18
19
20
V
Output on-resistance
Output leakage current
Cosc1 = 100pF
VREF = 1.5V
VM
μA
-0.5
Ronu
IO = 1.8A, high-side ON resistance
0.35
0.455
Ω
Rond
IO = 1.8A, low-side ON resistance
0.3
0.39
Ω
IOleak
VM = 36V
50
μA
Diode forward voltage
VD
ID = -1.8A
Current setting reference voltage
VRF
VREF = 1.5V, Current ratio 100%
0.285
1
1.4
V
0.3
0.315
V
No.A1702-2/26
LV8729V
Package Dimensions
unit : mm (typ)
3333
TOP VIEW
SIDE VIEW
BOTTOM VIEW
15.0
44
23
(3.5)
0.5
5.6
7.6
(4.7)
0.22
0.65
22
0.2
1.7MAX
1
(0.68)
0.1 (1.5)
SIDE VIEW
SANYO : SSOP44K(275mil)
Pin Assignment
VM 1
44 OUT1A
NC 2
43 OUT1A
VREG2 3
42 PGND1
NC 4
41 NC
VREG1 5
40 NC
ST 6
39 VM1
MD1 7
38 VM1
MD2 8
37 RF1
MD3 9
36 RF1
OE 10
35 OUT1B
RST 11
NC 12
34 OUT1B
LV8729V
FR 13
33 OUT2A
32 OUT2A
STP 14
31 RF2
OSC1 15
30 RF2
OSC2 16
29 VM2
NC 17
28 VM2
EMO 18
27 NC
DOWN 19
26 NC
MO 20
25 PGND2
VREF 21
24 OUT2B
SGND 22
23 OUT2B
Top view
No.A1702-3/26
LV8729V
Pd max - Ta
Allowable power dissipation, Pd max - W
5.0
4.0
3.85
3.0
(1):Exposed Die-Padsubstrate
(2):Without Exposed Die-pad
(1)
(2)
2.70
2.00
2.0
1.40
1.0
0
—30
0
30
60
90
120
Ambient temperature, Ta - C
Substrate Specifications (Substrate recommended for operation of LV8729V)
Size
: 90mm × 90mm × 1.6mm (two-layer substrate [2S0P])
Material
: Glass epoxy
Copper wiring density : L1 = 85% / L2 = 90%
L1 : Copper wiring pattern diagram
L2 : Copper wiring pattern diagram
Cautions
1) The data for the case with the Exposed Die-Pad substrate mounted shows the values when 90% or more of the
Exposed Die-Pad is wet.
2) For the set design, employ the derating design with sufficient margin.
Stresses to be derated include the voltage, current, junction temperature, power loss, and mechanical stresses such as
vibration, impact, and tension.
Accordingly, the design must ensure these stresses to be as low or small as possible.
The guideline for ordinary derating is shown below :
(1)Maximum value 80% or less for the voltage rating
(2)Maximum value 80% or less for the current rating
(3)Maximum value 80% or less for the temperature rating
3) After the set design, be sure to verify the design with the actual product.
Confirm the solder joint state and verify also the reliability of solder joint for the Exposed Die-Pad, etc.
Any void or deterioration, if observed in the solder joint of these parts, causes deteriorated thermal conduction,
possibly resulting in thermal destruction of IC.
No.A1702-4/26
SGND
ISD
TSD
+
Oscllator
ST
Output pre stage
OSC2
OUT1B VM1
VM2 OUT2A
+
RF2
OSC1
Decay Mode
setting circuit
Current
select
circuit
OUT2B
MD1 MD2 MD3 FR STP RST OE
Output control logic
Output pre stage
Current
select
circuit
+
OUT1A
Output pre stage
VREF
Regulator 1
Regulator 2
RF1
Output pre stage
VREG1
PGND2
PGND1
+
-
VM
VREG2
EMO
DOWN
MO
LV8729V
Block Diagram
No.A1702-5/26
LV8729V
Pin Functions
Pin No.
Pin Name
Pin Functtion
7
MD1
Excitation mode switching pin
8
MD2
Excitation mode switching pin
9
MD3
Excitation mode switching pin
10
OE
Output enable signal input pin
11
RST
Reset signal input pin
13
FR
Forward / Reverse signal input pin
14
STP
Step clock pulse signal input pin
Equivalent Circuit
VREG1
GND
6
ST
Chip enable pin.
VREG1
GND
23, 24
OUT2B
Channel 2 OUTB output pin.
25
PGND2
Channel 2 Power system ground
28, 29
VM2
Channel 2 motor power supply
30, 31
RF2
32, 33
OUT2A
Channel 2 OUTA output pin.
34, 35
OUT1B
Channel 1 OUTB output pin.
36, 37
RF1
Channel 1 current-sense resistor
38, 39
Channel 1 motor power supply pin.
42
VM1
PGND1
43, 44
OUT1A
Channel 1 OUTA output pin.
38 39
28 29
connection pin.
Channel 2 current-sense resistor
connection pin.
34 35
23 24
43 44
32 33
connection pin.
Channel 1 Power system ground
25 42
36 37
30 31
GND
21
VREF
Constant-current control reference
voltage input pin.
VREG1
GND
Continued on next page.
No.A1702-6/26
LV8729V
Continued from preceding page.
Pin No.
3
Pin Name
VREG2
Pin Functtion
Internal regulator capacitor connection
pin.
Equivalent Circuit
VM
GND
5
VREG1
Internal regulator capacitor connection
pin.
VM
GND
18
EMO
Over-current detection alarm output pin.
19
DOWN
Holding current output pin.
20
MO
Position detecting monitor pin.
VREG1
GND
15
OSC1
Copping frequency setting capacitor
connection pin.
16
OSC2
VREG5
Holding current detection time setting
capacitor connection pin.
GND
No.A1702-7/26
LV8729V
Reference describing operation
(1) Stand-by function
When ST pin is at low levels, the IC enters stand-by mode, all logic is reset and output is turned OFF.
When ST pin is at high levels, the stand-by mode is released.
(2) STEP pin function
Operating mode
Input
ST
STP
Low
*
Standby mode
High
Excitation step proceeds
High
Excitation step is kept
(3) Excitation setting method
Set the excitation setting as shown in the following table by setting MD1 pin, MD2 pin and MD3 pin.
Input
Initial position
Mode
MD3
MD2
MD1
(Excitation)
1ch current
2ch current
Low
Low
Low
2 phase
100%
-100%
0%
Low
Low
High
1-2 phase
100%
Low
High
Low
W1-2 phase
100%
0%
Low
High
High
2W1-2 phase
100%
0%
High
Low
Low
4W1-2 phase
100%
0%
0%
High
Low
High
8W1-2 phase
100%
High
High
Low
16W1-2 phase
100%
0%
High
High
High
32W1-2 phase
100%
0%
The initial position is also the default state at start-up and excitation position at counter-reset in each excitation mode.
(4) Output current setting
Output current is set shown below by the VREF pin (applied voltage) and a resistance value between RF1(2) pin and
GND.
IOUT = ( VREF / 5 ) / RF1 (2) resistance
* The setting value above is a 100% output current in each excitation mode.
(Example) When VREF = 1.1V and RF1 (2) resistance is 0.22Ω, the setting is shown below.
IOUT = ( 1.1V / 5 ) / 0.22Ω = 1.0A
(5) Output enable function
When the OE pin is set Low, the output is forced OFF and goes to high impedance. However, the internal logic circuits
are operating, so the excitation position proceeds when the STP is input. Therefore, when OE pin is returned to High,
the output level conforms to the excitation position proceeded by the STP input.
OE
Power save mode
STEP
MONI
1ch output
0%
2ch output
Output is high-impedance
No.A1702-8/26
LV8729V
(6) Reset function
When the RST pin is set Low, the output goes to initial mode and excitation position is fixed in the initial position for
STP pin and FR pin input. MO pin outputs at low levels at the initial position. (Open drain connection)
RST
RESET
STEP
MONI
1ch output
0%
2ch output
Initial state
(7) Forward / reverse switching function
FR
Operating mode
Low
Clockwise (CW)
High
Counter-clockwise (CCW)
FR
CW mode
CCW mode
CW mode
STEP
Excitation position
(1)
(2)
(3)
(4)
(5)
(6)
(5)
(4)
(3)
(4)
(5)
1ch output
2ch output
The internal D/A converter proceeds by a bit on the rising edge of the step signal input to the STP pin. In addition, CW
and CCW mode are switched by FR pin setting.
In CW mode, the channel 2 current phase is delayed by 90° relative to the channel 1 current.
In CCW mode, the channel 2 current phase is advanced by 90° relative to the channel 1 current.
(8) EMO, DOWN, MO output pin
The output pin is open -drain connection. When it becomes prescribed, it turns on, and each pin outputs the Low level.
Pin state
EMO
DOWN
MO
Low
At detection of over-current
Holding current state
Initial position
OFF
Normal state
Normal state
Non initial position
No.A1702-9/26
LV8729V
(9) Chopping frequency setting function
Chopping frequency is set as shown below by a capacitor between OSC1 pin and GND.
Fcp = 1 / ( Cosc1 / 10 х 10-6 ) (Hz)
(Example) When Cosc1 = 200pF, the chopping frequency is shown below.
Fcp = 1 / ( 200 х 10-12 / 10 х 10-6 ) = 50(kHz)
(10) Output current vector locus (one step is normalized to 90 degrees)
Channel 1 current ratio (%)
100.0
66.7
33.3
0.0
0.0
33.3
66.7
100.0
Channel 2 current ratio (%)
Current setting ratio in each excitation mode
STEP
θ0
θ1
θ2
θ3
θ4
θ5
θ6
θ7
θ8
θ9
θ10
θ11
θ12
θ13
θ14
θ15
θ16
θ17
θ18
θ19
θ20
θ21
θ22
θ23
θ24
θ25
32W1-2 phase(%)
1ch
2ch
100
0
100
1
100
2
100
4
100
5
100
6
100
7
100
9
100
10
99
11
99
12
99
13
99
15
99
16
99
17
98
18
98
20
98
21
98
22
97
23
97
24
97
25
96
27
96
28
96
29
95
30
16W1-2 phase(%)
1ch
2ch
100
0
100
2
100
5
100
7
100
10
99
12
99
15
99
17
98
20
98
22
97
24
96
27
96
29
8W1-2 phase(%)
1ch
2ch
100
0
100
5
100
10
99
15
98
20
97
24
96
29
4W1-2 phase(%)
1ch
2ch
100
0
100
10
98
20
96
29
2W1-2 phase (%)
1ch
2ch
100
0
98
W1-2 phase (%)
1ch
2ch
100
0
1-2 phase (%)
1ch
2ch
100
0
2 phase (%)
1ch
2ch
20
Continued on next page.
No.A1702-10/26
LV8729V
Continued from preceding page.
STEP
θ26
θ27
θ28
θ29
θ30
θ31
θ32
θ33
θ34
θ35
θ36
θ37
θ38
θ39
θ40
θ41
θ42
θ43
θ44
θ45
θ46
θ47
θ48
θ49
θ50
θ51
θ52
θ53
θ54
θ55
θ56
θ57
θ58
θ59
θ60
θ61
θ62
θ63
θ64
θ65
θ66
θ67
θ68
θ69
θ70
θ71
θ72
θ73
θ74
θ75
θ76
θ77
θ78
θ79
θ80
θ81
θ82
θ83
θ84
θ85
θ86
θ87
θ88
θ89
θ90
32W1-2 phase
1ch
2ch
95
31
95
33
94
34
94
35
93
36
93
37
92
38
92
39
91
41
91
42
90
43
90
44
89
45
89
46
88
47
88
48
87
49
86
50
86
51
85
52
84
53
84
55
83
56
82
57
82
58
81
59
80
60
80
61
79
62
78
62
77
63
77
64
76
65
75
66
74
67
73
68
72
69
72
70
71
71
70
72
69
72
68
73
67
74
66
75
65
76
64
77
63
77
62
78
62
79
61
80
60
80
59
81
58
82
57
82
56
83
55
84
53
84
52
85
51
86
50
86
49
87
48
88
47
88
46
89
45
89
16W1-2 phase
1ch
2ch
95
31
94
34
93
36
92
38
91
41
90
43
89
45
88
47
87
49
86
51
84
53
83
56
82
58
80
60
79
62
77
63
76
65
74
67
72
69
71
71
69
72
67
74
65
76
63
77
62
79
60
80
58
82
56
83
53
84
51
86
49
87
47
88
45
89
8W1-2 phase
1ch
2ch
94
34
92
38
90
43
88
47
86
51
83
56
80
60
77
63
74
67
71
71
67
74
63
77
60
80
56
83
51
86
47
88
4W1-2 phase
1ch
2ch
2W1-2 phase
1ch
2ch
92
38
92
38
88
47
83
56
83
56
77
63
71
71
71
71
63
77
56
83
56
83
47
88
W1-2 phase (%)
1ch
2ch
92
38
71
71
1-2 phase (%)
1ch
2ch
2 phase (%)
1ch
2ch
71
100
71
100
Continued on next page.
No.A1702-11/26
LV8729V
Continued from preceding page.
STEP
θ91
θ92
θ93
θ94
θ95
θ96
θ97
θ98
θ99
θ100
θ101
θ102
θ103
θ104
θ105
θ106
θ107
θ108
θ109
θ110
θ111
θ112
θ113
θ114
θ115
θ116
θ117
θ118
θ119
θ120
θ121
θ122
θ123
θ124
θ125
θ126
θ127
θ128
32W1-2 phase
1ch
2ch
44
90
43
90
42
91
41
91
39
92
38
92
37
93
36
93
35
94
34
94
33
95
31
95
30
95
29
96
28
96
27
96
25
97
24
97
23
97
22
98
21
98
20
98
18
98
17
99
16
99
15
99
13
99
12
99
11
99
10
100
9
100
7
100
6
100
5
100
4
100
2
100
1
100
0
100
16W1-2 phase
1ch
2ch
43
90
41
91
38
92
36
93
34
94
31
95
29
96
27
96
24
97
22
98
20
98
17
99
15
99
12
99
10
100
7
100
5
100
2
100
0
100
8W1-2 phase
1ch
2ch
43
90
38
92
34
94
29
96
24
97
20
98
15
99
10
100
5
100
0
100
4W1-2 phase
1ch
2ch
2W1-2 phase
1ch
2ch
38
92
38
92
29
96
20
98
20
98
10
100
0
100
0
100
W1-2 phase (%)
1ch
2ch
38
92
0
100
1-2 phase (%)
1ch
2ch
0
2 phase (%)
1ch
2ch
100
No.A1702-12/26
LV8729V
(11) Current wave example in each excitation mode ( 2 phase, 1-2 phase, 4W1-2 phase, 32W1-2 phase)
2-phase excitation (CW mode)
STP
MO
(%)
100
l1
0
-100
(%)
100
I2
0
-100
1-2 phase excitation (CW mode)
STP
MO
(%)
100
I1
0
-100
(%)
100
I2
0
-100
No.A1702-13/26
LV8729V
4W1-2 phase excitation ( CW mode )
STP
MO
(%)
100
50
I1
0
-50
-100
(%)
100
50
I2
0
-50
-100
32W1-2 phase excitation ( CW mode )
STP
MO
(%)
100
50
I1
0
-50
-100
(%)
100
50
I2
0
-50
-100
No.A1702-14/26
LV8729V
(12) Current control operation
( Sine-wave increasing direction )
STP
Setting current
Setting current
Coil current
Blanking Time
fchop
Current mode CHARGE
SLOW
FAST
CHARGE
SLOW
FAST
( Sine-wave decreasing direction )
STP
Setting current
Coil current
Setting current
Blanking Time
fchop
Current mode CHARGE
SLOW
FAST
Blanking Time
FAST
CHARGE
SLOW
Each of current modes operates with the follow sequence.
· The IC enters CHARGE mode at a rising edge of the chopping oscillation. ( A period of CHARGE mode (Blanking
Time) is forcibly present in approximately 1μs, regardless of the current value of the coil current (ICOIL) and set
current (IREF)).
· In a period of Blanking Time, the coil current (ICOIL) and the setting current (IREF) are compared.
If an ICOIL < IREF state exists during the charge period:
The IC operates in CHARGE mode until ICOIL ≥ IREF. After that, it switches to SLOW DECAY mode and
then switches to FAST DECAY mode in the last approximately 1μs of the period.
If no ICOIL < IREF state exists during the charge period:
The IC switches to FAST DECAY mode and the coil current is attenuated with the FAST DECAY operation
until the end of a chopping period.
The above operation is repeated. Normally, in the sine wave increasing direction the IC operates in SLOW (+ FAST)
DECAY mode, and in the sine wave decresing direction the IC operates in FAST DECAY mode until the current is
attenuated and reaches the set value and the IC operates in SLOW (+ FAST) DECAY mode.
No.A1702-15/26
LV8729V
(13) Output short-circuit protection circuit
Built-in output short-circuit protection circuit makes output to enter in stand-by mode. This function prevents the IC
from damaging when the output shorts circuit by a voltage short or a ground short, etc. When output short state is
detected, short-circuit detection circuit state the operating and output is once turned OFF. Subsequently, the output is
turned ON again after the timer latch period ( typ. 256μs ). If the output remains in the short-circuit state, turn OFF the
output, fix the output to the wait mode, and turn ON the EMO output.
When output is fixed in stand-by mode by output short protection circuit, output is released the latch by setting ST =
“L”.
(14) Open-drain pin for switching holding current
The output pin is an open-drain connection.
This pin is turned ON when no rising edge of STP between the input signals while a period determined by a capacitor
between OSC2 and GND, and outputs at low levels.
The open-drain output in once turned ON, is turned OFF at the next rising edge of STP.
Holding current switching time ( Tdown ) is set as shown below by a capacitor between OSC2 pin and GND.
Tdown = Cosc2 х 0.4 х 109 (s)
(Example) When Cosc2 = 1500pF, the holding current switching time is shown below.
Tdown = 1500pF х 0.4 х 109 = 0.6 (s)
No.A1702-16/26
LV8729V
Application Circuit Example
- +
Motor
power
supply
OUT1A 44
2 NC
OUT1A 43
3 VREG2
PGND1 42
4 NC
NC 41
5 VREG1
NC 40
6 ST
VM1 39
7 MD1
VM1 38
8 MD2
RF1 37
9 MD3
RF1 36
10 OE
11 RST
12 NC
13 FR
200pF
Short-circuit
state detection
monitor
- +
Current
setting
reference
voltage
LV8729V
Logic
input
1 VM
OUT1B 35
OUT1B 34
OUT2A 33
OUT2A 32
14 STP
RF2 31
15 OSC1
RF2 30
16 OSC2
VM2 29
17 NC
VM2 28
18 EMO
NC 27
19 DOWN
NC 26
20 MO
PGND2 25
21 VREF
OUT2B 24
22 SGND
OUT2B 23
M
The above sample application circuit is set to the following conditions:
· Output enable function fixed to the output state ( OE = “H” )
· Reset function fixed to the output state ( RST = “H” )
· Chopping frequency : 50kHz ( Cosc1 = 200pF )
The set current value is as follows :
IOUT = ( Current setting reference voltage / 5 ) / 0.22Ω
No.A1702-17/26
LV8729V
Measurement circuit diagram
Stand-by mode current drain : IMstn
Current drain : IM
- +
IMstn/IM
A
- +
24V
5V
1 VM
OUT1A 44
2 NC
OUT1A 43
3 VREG2
PGND1 42
4 NC
NC 41
5 VREG1
NC 40
6 ST
VM1 39
7 MD1
VM1 38
8 MD2
RF1 37
9 MD3
RF1 36
11 RST
12 NC
13 FR
100pF
LV8729V
10 OE
OUT1B 35
OUT1B 34
OUT2A 33
OUT2A 32
14 STP
RF2 31
15 OSC1
RF2 30
16 OSC2
VM2 29
17 NC
VM2 28
18 EMO
NC 27
19 DOWN
NC 26
20 MO
PGND2 25
21 VREF
OUT2B 24
22 SGND
OUT2B 23
Turn OFF SW when measuring IMstn.
Turn ON SW when measuring IM
No.A1702-18/26
LV8729V
- +
- +
Logic pin input current : IINL, IINH
VIN
A
IINL/IINH
1 VM
OUT1A 44
2 NC
OUT1A 43
3 VREG2
PGND1 42
4 NC
NC 41
5 VREG1
NC 40
6 ST
VM1 39
7 MD1
VM1 38
8 MD2
RF1 37
9 MD3
RF1 36
11 RST
12 NC
13 FR
100pF
LV8729V
10 OE
OUT1B 35
OUT1B 34
OUT2A 33
OUT2A 32
14 STP
RF2 31
15 OSC1
RF2 30
16 OSC2
VM2 29
17 NC
VM2 28
18 EMO
NC 27
19 DOWN
NC 26
20 MO
PGND2 25
21 VREF
OUT2B 24
22 SGND
OUT2B 23
Set VIN = 0.8V when measuring IINL.
Set VIN = 5V when measuring IINH
This measurement is related to the ST pin. Take the same procedure for measurement of other pins.
No.A1702-19/26
LV8729V
Logic input high-level voltage : VINH ( ST, OE )
Logic input low-level voltage : VINL ( ST, OE )
- +
VOUT1A
24V
- +
a
VIN
b
SW1
a
SW2
OUT1A 44
2 NC
OUT1A 43
3 VREG2
PGND1 42
4 NC
NC 41
5 VREG1
NC 40
6 ST
VM1 39
7 MD1
VM1 38
8 MD2
RF1 37
9 MD3
RF1 36
10 OE
- +
11 RST
5V
12 NC
13 FR
100pF
LV8729V
b
1 VM
V
OUT1B 35
OUT1B 34
OUT2A 33
OUT2A 32
14 STP
RF2 31
15 OSC1
RF2 30
16 OSC2
VM2 29
17 NC
VM2 28
18 EMO
NC 27
19 DOWN
NC 26
20 MO
PGND2 25
21 VREF
OUT2B 24
22 SGND
OUT2B 23
To measure the ST pin, set SW1 to the ”a” side and SW2 to the ”b” side.
To measure the OE pin, set SW1 to the ”b” side and SW2 to the ”a” side.
VINH : When VIN is raised gradually from 0V, the VOUT1A voltage changes from ”L” to ”H”. The VIN voltage at
which the voltage changes from ”L” to ”H” is the VINH voltage.
VINL : When VIN is raised gradually from 3V, the VOUT1A voltage changes from ”H” to ”L”. The VIN voltage at
which the voltage changes from ”H” to ”L” is the VINL voltage.
No.A1702-20/26
LV8729V
- +
Logic input high-level voltage : VINH ( MD1, MD2, MD3 )
Logic input high-level voltage : VINL ( MD1, MD2, MD3 )
5V
- +
- +
24V
VIN
1 VM
OUT1A 44
2 NC
OUT1A 43
3 VREG2
PGND1 42
4 NC
NC 41
5 VREG1
NC 40
6 ST
VM1 39
7 MD1
VM1 38
8 MD2
RF1 37
9 MD3
RF1 36
11 RST
12 NC
13 FR
100pF
LV8729V
10 OE
OUT1B 35
OUT1B 34
OUT2A 33
OUT2A 32
14 STP
RF2 31
15 OSC1
RF2 30
16 OSC2
VM2 29
17 NC
VM2 28
18 EMO
NC 27
19 DOWN
NC 26
20 MO
PGND2 25
21 VREF
OUT2B 24
22 SGND
OUT2B 23
VOUT2B
V
VINH : When VIN is raised gradually from 0V, the VOUT2B voltage changes from ”H” to ”L”. The VIN voltage at
which the voltage changes from ”H” to ”L” is the VINH voltage.
VINL : When VIN is raised gradually from 3V, the VOUT2B voltage changes from ”L” to ”H”. The VIN voltage at
which the voltage changes from ”L” to ”H” is the VINL voltage.
This measurement is related to the MD1 pin. Take the same procedure for measurement of MD2 and MD3 pins.
No.A1702-21/26
LV8729V
- +
REG1 output voltage : Vreg1
REG2 output voltage : Vreg2
VREF pin input voltage : Iref
24V
V
Vreg2
- +
V
Vreg1
5V
1 VM
OUT1A 44
2 NC
OUT1A 43
3 VREG2
PGND1 42
4 NC
NC 41
5 VREG1
NC 40
6 ST
VM1 39
7 MD1
VM1 38
8 MD2
RF1 37
9 MD3
RF1 36
11 RST
12 NC
13 FR
100pF
- +
Iref
A
1.5V
LV8729V
10 OE
OUT1B 35
OUT1B 34
OUT2A 33
OUT2A 32
14 STP
RF2 31
15 OSC1
RF2 30
16 OSC2
VM2 29
17 NC
VM2 28
18 EMO
NC 27
19 DOWN
NC 26
20 MO
PGND2 25
21 VREF
OUT2B 24
22 SGND
OUT2B 23
No.A1702-22/26
LV8729V
- +
- +
Copping frequency : Fch
MO pin residual voltage : VOlMO
1 VM
OUT1A 44
2 NC
OUT1A 43
3 VREG2
PGND1 42
4 NC
NC 41
5 VREG1
NC 40
6 ST
VM1 39
7 MD1
VM1 38
8 MD2
RF1 37
9 MD3
RF1 36
11 RST
12 NC
Fch
M
100pF
VolMO
V
1mA
13 FR
LV8729V
10 OE
OUT1B 35
OUT1B 34
OUT2A 33
OUT2A 32
14 STP
RF2 31
15 OSC1
RF2 30
16 OSC2
VM2 29
17 NC
VM2 28
18 EMO
NC 27
19 DOWN
NC 26
20 MO
PGND2 25
21 VREF
OUT2B 24
22 SGND
OUT2B 23
No.A1702-23/26
LV8729V
- +
Output on-resistance : Ronu,Rond
5V
- +
24V
1 VM
OUT1A 44
2 NC
OUT1A 43
3 VREG2
PGND1 42
4 NC
NC 41
b
5 VREG1
NC 40
a SW2
6 ST
VM1 39
7 MD1
VM1 38
8 MD2
RF1 37
9 MD3
RF1 36
11 RST
12 NC
13 FR
LV8729V
10 OE
100pF
Vds
V
SW1 a
1.8A
OUT1B 35
OUT1B 34
OUT2A 33
OUT2A 32
14 STP
RF2 31
15 OSC1
RF2 30
16 OSC2
VM2 29
17 NC
VM2 28
18 EMO
NC 27
19 DOWN
NC 26
20 MO
b
PGND2 25
21 VREF
OUT2B 24
22 SGND
OUT2B 23
b
a SW4
Vds
V
b
SW3 a
1.8A
When measuring OUT1A upper and OUT2B upper FETs, set SW1 to 4 to the ”a” side.
When measuring OUT1A lower and OUT2B lower FETs, set SW1 to 4 to the ”b” side.
This measurment is related to OUT1A and OUT2B. To measure OUT2A and OUT1B, enter two rectangular waves to
the STP pin and carry out the procedure for measurement.
No.A1702-24/26
LV8729V
- +
Current setting reference voltage : VRF
5V
- +
24V
1 VM
OUT1A 44
2 NC
OUT1A 43
3 VREG2
PGND1 42
4 NC
NC 41
5 VREG1
NC 40
6 ST
VM1 39
7 MD1
VM1 38
8 MD2
RF1 37
9 MD3
RF1 36
11 RST
12 NC
13 FR
- +
100pF
1.5V
LV8729V
10 OE
Channel 1 side monitor
M
+ VRF(1ch side)
OUT1B 35
OUT1B 34
OUT2A 33
OUT2A 32
14 STP
RF2 31
15 OSC1
RF2 30
16 OSC2
VM2 29
17 NC
VM2 28
18 EMO
NC 27
19 DOWN
NC 26
20 MO
PGND2 25
21 VREF
OUT2B 24
22 SGND
OUT2B 23
+ VRF(2ch side)
Channel 2 side monitor
M
Raise the RF1 (2) pin voltage from 0V. The RF1 (2) voltage at which tje OUT voltage changes from ”H” to ”L” is VRF.
No.A1702-25/26
LV8729V
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products at values that exceed, even momentarily, rated values (such as maximum ratings, operating condition
ranges, or other parameters) listed in products specifications of any and all SANYO Semiconductor Co.,Ltd.
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limited to protective circuits and error prevention circuits for safe design, redundant design, and structural
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SANYO Semiconductor Co.,Ltd. product that you intend to use.
Information (including circuit diagrams and circuit parameters) herein is for example only; it is not guaranteed
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This catalog provides information as of February, 2011. Specifications and information herein are subject
to change without notice.
PS No.A1702-26/26