NSC MM5483N

MM5483
Liquid Crystal Display Driver
General Description
Features
The MM5483 is a monolithic integrated circuit utilizing
CMOS metal-gate low-threshold enhancement mode devices. It is available in a 40-pin molded package. The chip
can drive up to 31 segments of LCD and can be cascaded to
increase this number. This chip is capable of driving a 41⁄2digit 7-segment display with minimal interface between the
display and the data source.
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The MM5483 stores the display data in latches after it is
latched in, and holds the data until another load pulse is
received.
Serial data input
Serial data output
Wide power supply operation
TTL compatibility
31 segment outputs
Alphanumeric and bar graph capability
Cascade capability
Applications
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COPS™ or microprocessor displays
Industrial control indicator
Digital clock, thermometer, counter, voltmeter
Instrumentation readouts
Remote displays
Block and Connection Diagrams
00614001
FIGURE 1.
COPS™ is a trademark of National Semiconductor Corporation.
© 2004 National Semiconductor Corporation
DS006140
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MM5483 Liquid Crystal Display Driver
May 2002
MM5483
Block and Connection Diagrams
(Continued)
Dual-In-Line Package
00614002
Top View
Order Number MM5483N
See NS Package Number N40A
00614007
Order Number MM5483V
See NS Package Number V44A
FIGURE 2.
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2
Storage Temperature
If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales Office/
Distributors for availability and specifications.
Power Dissipation
Operating Temperature
300 mW at +85˚C
350 mW at +25˚C
Junction Temperature
VSS to VSS +10V
Voltage at Any Pin
−65˚C to +150˚C
+150˚C
Lead Temperature
(Soldering, 10 seconds)
−40˚C to +85˚C
300˚C
DC Electrical Characteristics
TA within operating range, VDD = 3.0V to 10V, VSS = 0V, unless otherwise specified
Parameter
Conditions
Min
Max
Units
10
V
2.5
µA
VDD = 5.0V
10
µA
VDD = 10.0V
40
µA
0.9
Power Supply
Typ
3.0
Average Supply Current, IDD
All Outputs Bits = Open, Data Out = Open,
BP_Out = Open, Clock In = 0V,
Data In = 0V, Data Load = 0V,
Osc In = 0V, BP_In = 32Hz
VDD = 3.0V
1.5
Input Voltage Levels
Logic “0”
Logic “1”
Logic “0”
Logic “1”
Load, Clock, Data
VDD = 5.0V
VDD = 5.0V
VDD = 3.0V
VDD = 3.0V
2.4
2.0
V
V
V
V
Output Current Levels
Segments and Data Out
Sink
Source
VDD = 3.0V, VOUT = 0.3V
VDD = 3.0V, VOUT = 2.7V
20
20
µA
µA
BP Out Sink
BP Out Source
VDD = 3.0V, VOUT = 0.3V
VDD = 3.0V, VOUT = 2.7V
320
320
µA
µA
0.4
AC Electrical Characteristics
VDD ≥ 4.7V, VSS = 0V unless otherwise specified
Symbol
Parameter
fC
Clock Frequency, VDD = 3V
tCH
Clock Period High
tCL
tDS
Min
(Notes 2, 3)
Typ
Max
Units
500
kHz
500
ns
Clock Period Low
500
ns
Data Set-Up before Clock
300
ns
tDH
Data Hold Time after Clock
100
ns
tLW
Minimum Load Pulse Width
500
ns
tLTC
Load to Clock
400
tCDO
Clock to Data Valid
ns
400
750
ns
Note 1: “Absolute Maximum Ratings” are those values beyond which the safety of the device cannot be guaranteed. They are not meant to imply that the devices
should be operated at these limits. The table of “Electrical Characteristics” specifies conditions of device operation.
Note 2: AC input waveform specification for test purpose: tr ≤ 20 ns, tf ≤ 20 ns, f = 500 kHz, 50% ± 10% duty cycle.
Note 3: Clock input rise and fall times must not excced 300 ms.
Note 4: Output offset voltage is ± 50 mV with CSEGMENT = 250 pF, CBP = 8750 pF.
Figure 5. In the 2-wire control mode, 31 bits (or less depending on the number of segments used) of data are clocked
into the MM5483 in a short time frame (with less than 0.1
second there probably will be no noticeable flicker) with no
more clocks until new information is to be displayed. If data
was slowly clocked in, it can be seen to “walk” across the
display in the 2-wire mode. An AC timing diagram can be
seen in Figure 6. It should be noted that data out is not a
TTL-compatible output.
Functional Description
A block diagram for the MM5483 is shown in Figure 1 and a
package pinout is shown in Figure 2. Figure 3 shows a
possible 3-wire connection system with a typical signal format for Figure 3. Shown in Figure 4, the load input is an
asynchronous input and lets data through from the shift
register to the output buffers any time it is high. The load
input can be connected to VDD for 2-wire control as shown in
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MM5483
Absolute Maximum Ratings (Note 1)
MM5483
Functional Description
(Continued)
00614003
FIGURE 3. Three-Wire Control Mode
00614004
FIGURE 4. Data Format Diagram
00614005
FIGURE 5. Two-Wire Control Mode
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MM5483
Functional Description
(Continued)
00614006
FIGURE 6. Timing Diagram
5
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MM5483
Physical Dimensions
inches (millimeters) unless otherwise noted
Molded Dual-In-Line Package (N)
Order Number MM5483N
NS Package Number N40A
Order Number MM5483V
NS Package Number V44A
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MM5483 Liquid Crystal Display Driver
Notes
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