Si3000 VOICE B AND C ODEC W I T H M ICROPHONE /S P E A K E R D RIVE Features Complete voice codec solution includes the following: 84 dB ADC Dynamic Range 84 dB DAC Dynamic Range 4–12 kHz Sample Rates 30 dB Microphone Pre-Amp Programmable Input Gain/ Attenuation: –34.5 dB to 12 dB Programmable Output Gain/ Attenuation: –34.5 dB to 12 dB Support for 32 Headphones 3:1 Analog Input Mixer 3.3–5.0 V Power Supply Direct Serial Interface to DSPs Direct Connection to Si303x/44/56, serial interface DAA chipsets Low profile 16-Pin SOIC Package RoHS-compliant package available Ordering Information: See page 29. Pin Assignments Applications Modem Voice Channel (DSVD) Speech Processing Telephony General Purpose Analog I/O Companion chip for FDX ISOmodems with voice features Si3000 Description The Si3000 is a complete voice band audio codec solution that offers high integration by incorporating programmable input and output gain/ attenuation, a microphone bias circuit, handset hybrid circuit, and an output drive for 32 headphones. The Si3000 can be connected directly to the Si3034, Si3035, Si3044, and Si3056 North American and international DAA chipsets through their daisy-chaining serial interface. It also serves as a companion chip to a FAT ISOmodem chipset with voice features, providing hardware support for a handset and speaker phone. The device operates from a single 3.3 to 5 V power supply and is available in a 16-pin small outline package (SOIC). SPKRR 1 16 SPKRL MBIAS 2 15 LINEO HDST 3 14 GND SDI 4 13 VA SDO 5 12 VD FSYNC 6 11 LINEI MCLK 7 10 MIC SCLK 8 9 RESET Functional Block Diagram Si3000 MCLK Prog Gain/ Attenuator SCLK FSYNC SDI SDO High Pass Filter 0/+10/+20/+30 dB MBIAS MIC ADC 0/+10/+20 dB Digital Interface Handset Hybrid LINEI HDST 0/–6/–12/–18 dB Prog Gain/ Attenuator DAC Headphone Driver SPKRR SPKRL LINEO RESET Rev. 1.4 12/10 0/–6/–12/–18 dB Copyright © 2010 by Silicon Laboratories Si3000 Si3000 2 Rev. 1.4 Si3000 TABLE O F C ONTENTS Section Page 1. Electrical Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4 2. Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 2.1. Analog Inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14 2.2. Pre-amp/Microphone Bias Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 2.3. Programmable Input Gain/Attenuation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 2.4. Analog Outputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 2.5. Programmable Output Gain/Attenuation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 2.6. Line Output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 2.7. Speaker Output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 2.8. Digital Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 2.9. Clock Generation Subsystem . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 2.10. Sleep Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 2.11. Loopback Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 2.12. Reducing Power-on Pop Noise . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 3. Control Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19 4. Pin Descriptions: Si3000 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .27 5. Ordering Guide . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 6. Package Outline: 16-Pin SOIC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 7. 16-Pin SOIC Land Pattern . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 8. Package Markings (Top Markings) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .32 8.1. Si3000-C-GS Top Marking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 8.2. Si3000-C-FS Top Marking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 Document Change List . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .33 Contact Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .34 Rev. 1.4 3 Si3000 1. Electrical Specifications Table 1. Recommended Operating Conditions Parameter Symbol Test Condition Min1 Typ Max1 Unit TA F and K-grade 0 25 70 °C Ambient Temperature 2 VA 3.0 3.3/5.0 5.25 V 2,3 VD 3.0 3.3/5.0 5.25 V Si3000 Supply Voltage, Analog Si3000 Supply Voltage, Digital Notes: 1. All minimum and maximum specifications are guaranteed and apply across the recommended operating conditions. Typical values apply at nominal supply voltages and an operating temperature of 25°C unless otherwise stated. 2. The digital supply, VD, and analog supply, VA, can operate from either 3.3 V or 5.0 V. The Si3000 supports interface to 3.3 V logic when operating from 3.3 V. VD must be within 0.6 V of VA. 3. The Si3000 specifications are guaranteed using the typical application circuit (including component tolerance) of Figure 13. Table 2. DC Characteristics, VA/VD = 5 V (VA = 5 V ±5%, VD = 5 V ±5%, TA = 0 to 70°C) Parameter Symbol Test Condition Min Typ Max Unit High Level Input Voltage VIH 3.5 — — V Low Level Input Voltage VIL — — 0.8 V High Level Output Voltage VOH IO = –2 mA 3.5 — — V Low Level Output Voltage VOL IO = 2 mA — — 0.4 V Input Leakage Current IL –10 — 10 µA Power Supply Current, Analog1 IA VA pin — 6.5 10 mA Power Supply Current, Digital2 ID VD pin — 10 15 mA — — 1.5 mA Min Typ Max Unit 2.4 — — V Total Supply Current, Sleep Mode3 Notes: 1. No loads at DAC outputs, no load at MBIAS, Fs=12.5 kHz. 2. Slave mode operation, Fs = 12.5 kHz. 3. All inputs, except MCLK, are held static, and all outputs are unloaded. Table 3. DC Characteristics, VA/VD = 3.3 V (VA = 3.3 V ±10%, VD = 3.3 V ±10%, TA = 0 to 70°C) Parameter Symbol High Level Input Voltage Test Condition VIH Low Level Input Voltage VIL High Level Output Voltage VOH IO = –2 mA Low Level Output Voltage VOL IO = 2 mA Input Leakage Current IL — — 0.8 V 2.4 — — V — — 0.35 V –10 — 10 µA Power Supply Current, Analog IA VA pin — 6 10 mA Power Supply Current, Digital2 ID VD pin — 6 10 mA — — 1.5 mA Total Supply Current, Sleep Mode3 Notes: 1. No loads at DAC outputs, no load at MBIAS, Fs=12.5 kHz. 2. Slave mode operation, Fs = 12.5 kHz. 3. All inputs, except MCLK, are held static, and all outputs are unloaded. 4 Rev. 1.4 Si3000 Table 4. AC Characteristics (VA, VD = 5 V ±5% or 3.3 V ±10%, TA = 0 to 70°C) Parameter Symbol Test Condition ADC Resolution ADC Dynamic Range1,2 3 ADC Total Harmonic Distortion ADC Total Harmonic Distortion Unit — 16 — Bits 80 84 — dB ADCTHD VIN = 1 kHz, –3 dB, MIC/LINEI — –80 –62 dB VIN = 1 kHz, –3 dB, HDST — –80 –62 VIN = 1 kHz, –3 dB, MIC/LINEI — –80 –76 VIN = 1 kHz, –3 dB, HDST — –80 –71 Vin = 1 kHz — 1 — Vrms –34.5 — 12 dB — 1.5 — dB VA, VD = 5 V ±5% ADC Full Scale Level (0 dB gain) Max VIN = 1 kHz, –3 dB ADCTHD 4 Typ ADCDR VA, VD = 3.3 V ±10% 3 Min VRX ADC Programmable Input Gain ADC Input Gain Step Size dB ADC Freq Response5 FRR Low –3 dB corner — 33 — Hz Response5 FRR 300 Hz –0.1 — 0 dB FRR 3400 Hz –0.2 — 0 dB Line In Preamp Gain — 0/10/20 — dB Mic In Preamp Gain — 0/10/20/ 30 — dB — 20 — k — 15 — pF — 0.002 — dB/°C — 16 — Bits ADC Freq ADC Freq Response ADC Input Resistance 0 dB Preamp Gain ADC Input Capacitance ADC Gain Drift AT VIN = 1 kHz DAC Resolution DAC Dynamic Range1,2 DAC Total Harmonic Distortion3 DACDR VIN = 1 kHz, –6 dB 80 84 — dB DACTHD VIN=1 kHz,–6 dB,LINEO,600 — –76 –60 dB VIN=1 kHz,–6 dB, SPKR, 60 — –72 –60 VIN=1 kHz,–6 dB, HDST, 600 — –80 –70 VIN=1 kHz,–3 dB,LINEO,600 — –76 –65 VIN=1 kHz,–3 dB, SPKR, 60 — –72 –65 VIN=1 kHz,–3 dB, HDST, 600 — –80 –76 — 1 — Vrms –34.5 — 12 dB VA, VD = 3.3 V ±10% DAC Total Harmonic Distortion3 DACTHD VA, VD = 5 V ±5% DAC Full Scale Level (0 dB gain) VRX DAC Programmable Output Gain dB Notes: 1. DR = VIN + 20 log (RMS signal/RMS noise). Measurement bandwidth is 300 to 3400 Hz. Valid sample rate ranges between 4000 and 12000 Hz. 2. 0 dB setting for analog and digital attenuation/gain. 3. THD = 20 log (RMS distortion/RMS signal). Valid sample rate ranges between 4000 and 12000 Hz. 4. At 0 dB gain setting, 1 Vrms input corresponds to –1.5 dB of full scale digital output code. 5. These characteristics are determined by external components. See Figure 13. 6. With a 600 load. Output starts clipping with half of full scale digital input, which corresponds to a 0.5 Vrms output. Rev. 1.4 5 Si3000 Table 4. AC Characteristics (Continued) (VA, VD = 5 V ±5% or 3.3 V ±10%, TA = 0 to 70°C) Parameter Symbol Test Condition DAC Output Gain Step Size Min Typ Max Unit — 1.5 — dB DAC Freq Response5 FRR Low –3 dB corner — 33 — Hz DAC Freq Response5 FRR 300 Hz –0.01 — 0 dB DAC Freq Response FRR 3400 Hz –0.2 — 0 dB DAC Line Output Load Resistance 600 — — DAC Line Output Load Capacitance — — 40 pF DAC SPKR Output Load Resistance — 60 — — 0.002 — dB/°C Interchannel Isolation (Crosstalk) — 90 — dB HDST Full Scale Level Input — 0.5 — Vrms HDST Full Scale Level Output6 — 1.0 — Vrms — 600 — DAC Gain Drift HDST Output Resistance AT VIN = 1 kHz Rout DC MIC Bias Voltage Vmbias — 2.5 — V MIC Power Supply Rejection Ratio PSRR — 40 — dB Notes: 1. DR = VIN + 20 log (RMS signal/RMS noise). Measurement bandwidth is 300 to 3400 Hz. Valid sample rate ranges between 4000 and 12000 Hz. 2. 0 dB setting for analog and digital attenuation/gain. 3. THD = 20 log (RMS distortion/RMS signal). Valid sample rate ranges between 4000 and 12000 Hz. 4. At 0 dB gain setting, 1 Vrms input corresponds to –1.5 dB of full scale digital output code. 5. These characteristics are determined by external components. See Figure 13. 6. With a 600 load. Output starts clipping with half of full scale digital input, which corresponds to a 0.5 Vrms output. Table 5. Absolute Maximum Ratings Parameter DC Supply Voltage Input Current, Si3000 Digital Input Pins Digital Input Voltage Operating Temperature Range Storage Temperature Range Symbol Value Unit VD, VA –0.5 to 6.0 V IIN ±10 mA VIND –0.3 to (VD + 0.3) V TA –10 to 100 °C TSTG –40 to 150 °C Note: Permanent device damage may occur if the above Absolute Maximum Ratings are exceeded. Functional operation should be restricted to the conditions as specified in the operational sections of this data sheet. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. 6 Rev. 1.4 Si3000 Table 6. Switching Characteristics—General Inputs (VA, VD = 5 V ±5% or 3.3 V ±10%,TA = 0 to 70°C, CL = 20 pF) Parameter1 Symbol Test Condition Min Typ Max Unit Cycle Time, MCLK tmc 16.67 — — ns MCLK Duty Cycle tdty 40 50 60 % Rise Time, MCLK tr — — 5 ns Fall Time, MCLK tf — — 5 ns RESET Pulse Width2 trl 250 — — ns Rise Time, RESET tRr — 1 — µs Notes: 1. All timing (except Rise and Fall time) is referenced to the 50% level of the waveform. Input test levels are VIH = VD – 0.4 V, VIL = 0.4 V. Rise and Fall times are referenced to the 20% and 80% levels of the waveform. 2. The minimum RESET pulse width is the greater of 5 s or 10 MCLK cycle times. tr tmc tf MCLK VIH V IL tRr RESET trl Figure 1. General Inputs Timing Diagram Rev. 1.4 7 Si3000 Table 7. Switching Characteristics—Serial Interface (VA, VD = 5 V ±5% or 3.3 V ±10%, TA = 0 to 70°C, CL = 20 pF) Parameter Symbol Test Condition Min Typ Max Unit Cycle Time, SCLK tc 354 1/256 Fs — ns SCLK Duty Cycle tdty — 50 — % Delay Time, SCLK to FSYNC td1 — — 10 ns Delay Time, SCLK to SDO Valid td2 — — 20 ns Delay Time, SCLK to FSYNC td3 — — 10 ns Setup Time, SDI, before SCLK tsu 25 — — ns Hold Time, SDI, after SCLK th 20 — — ns Setup Time, FSYNC (mode 2) before MCLK tsu 25 — — ns Hold Time, FSYNC (mode 2) after MCLK th 20 — — ns Note: All timing is referenced to the 50% level of the waveform. Input test levels are VIH = VD – 0.4 V, VIL = 0.4 V tc V OH SCLK V OL td3 td1 FSYNC (mode 0) td3 FSYNC (mode 1) FSYNC (mode 2) t d2 16 Bit SDO High-Z D15 D14 tsu 16 Bit SDI D15 ... D2 D1 th D14 ... D2 D1 Figure 2. Serial Interface Timing Diagram 8 D0 D0 Rev. 1.4 D0 High-Z Si3000 Table 8. Digital FIR Filter Characteristics—Transmit and Receive (VA, VD = 5 V ±5% or 3.3 V ±10%, Sample Rate = 8 kHz, TA = 0 to 70°C) Parameter Symbol Min Typ Max Unit Passband (3 dB, HPFD = 1) F(3 dB) 0 — 3.6 kHz Passband (3 dB, HPFD = 0) F(3 dB) 0.01 — 3.6 kHz –0.1 — 0.1 dB — 4.4 — kHz –74 — — dB — 12/Fs — sec Passband Ripple Peak-to-Peak Stopband Stopband Attenuation tgd Group Delay Note: Typical FIR filter characteristics for Fs = 8000 Hz are shown in Figures 3, 4, 5, and 6. Table 9. Digital IIR Filter Characteristics—Transmit and Receive (VA, VD = 5 V ±5% or 3.3 V ±10%, Sample Rate = 8 kHz, TA = 70°C) Parameter Symbol Min Typ Max Unit Passband (3 dB, HPFD = 1) F(3 dB) 0 — 3.6 kHz Passband (3 dB, HPFD = 0) F(3 dB) 0.01 — 3.6 kHz –0.2 — 0.2 dB — 4.4 — kHz –40 — — dB — 1.6/Fs — sec Passband Ripple Peak-to-Peak Stopband Stopband Attenuation Group Delay tgd Note: Typical IIR filter characteristics for Fs = 8000 Hz are shown in Figures 7, 8, 9, and 10. Figures 11 and 12 show group delay versus input frequency. Rev. 1.4 9 Attenuation - dB Attenuation - dB Si3000 Input Frequency - Hz Input Frequency - Hz Figure 5. FIR Transmit Filter Response Attenuation - dB Attenuation - dB Figure 3. FIR Receive Filter Response Input Frequency - Hz Input Frequency - Hz Figure 4. FIR Receive Filter Passband Ripple Figure 6. FIR Transmit Filter Passband Ripple For Figures 3–6, all filter plots apply to a sample rate of Fs = 8 kHz. The filters scale with the sample rate as follows: F(0.1 dB) = 0.4125 Fs F(– 3 dB) = 0.45 Fs where Fs is the sample frequency. 10 Rev. 1.4 Attenuation - dB Attenuation - dB Si3000 Input Frequency - Hz Input Frequency - Hz Figure 10. IIR Transmit Filter Passband Ripple Delay - µs Attenuation - dB Figure 7. IIR Receive Filter Response Input Frequency - Hz Input Frequency - Hz Figure 11. IIR Receive Group Delay Delay - µs Attenuation - dB Figure 8. IIR Receive Filter Passband Ripple Input Frequency - Hz Input Frequency - Hz Figure 9. IIR Transmit Filter Response Figure 12. IIR Transmit Group Delay Rev. 1.4 11 12 Rev. 1.4 10 2 2 Figure 13. Si3000 Typical Application Circuit 10 = 2= TELEPHONE SET PSTN Si3000 Si3000 ‘ Table 10. Component Values—Typical Application Symbol Value C1,C3,C6,C8 0.1 µF, 16 V, ±20% C2,C4,C5,C7,C9,C10 10 µF, 16 V, ±20% D1 Motorola MMBD914L J1,J2 Phonejack Stereo JP1 4 Header K1 Relay DPDT L1,L2 Ferrite Bead R1 0 , 1/4 W ±5% R2 51 , 1/4 W ±5% R4 10 k, 1/4 W ±5% R8 2.2 k, 1/4 W, ±5% R9 10 , 1/16 W, ±5% R11,R12 30 , 1/16 W, ±5% U2 LM317LZ Q1 PNP Transistor Rev. 1.4 13 Si3000 2. Functional Description 2.2. Pre-amp/Microphone Bias Circuit The Si3000 is a highly integrated voice bandwidth audio codec which contains a single 16-bit A/D converter and D/A converter. The analog input path contains a microphone input with selectable gain, a line level input with selectable gain, and a handset input. Each of the inputs go through a mixer prior to A/D conversion. The result of this A/D conversion is a 16-bit 2s complement signed number. Following the A/D converter is a digital programmable gain amplifier. The analog output path contains a digital programmable gain amplifier feeding a single 16-bit D/A converter. The DAC output is provided to a line output, a headphone drive output, and a handset output. Control for the various functions available on the Si3000 as well as the audio data are communicated to the device over a serial interface. The Si3000 can be connected directly to the Si3035, Si3034, Si3044, or Si3056 in modem applications requiring a voice channel, or the device can be used as a stand-alone codec in other voice band applications. The Si3000 offers high integration, and it needs only a few low-cost, discrete components as shown in Figure 13. 2.1. Analog Inputs The typical connection diagram (Figure 13) shows the recommended external analog circuitry for the Si3000. The device supports three mono analog inputs—line level, microphone level, and a handset input. Each of these inputs is provided to a mixer circuit prior to A/D conversion. Each analog input may also be muted by writing the appropriate bits in the control registers. Unused analog inputs should be tied to GND through a 0.1 F capacitor. This prevents any DC current flow. An internal amplifier with a selectable gain of 0 dB, 10 dB, 20 dB, or 30 dB is provided for the MIC input and an internal amplifier with a selectable gain of 0 dB, 10 dB, or 20 dB, is provided for the LINEI input. AC coupling is required for both inputs because any DC offset on the input will be amplified if gain is selected. Gain settings for the LINEI and MIC inputs are achieved by writing the RX Gain Control 1 register 5. When gain is disabled, these inputs become line level inputs with a full-scale input of 1 Vrms. A microphone bias circuit is provided on-chip which consists of a 2.5 V reference output capable of sourcing up to 5 mA of current. This circuit can be used for active microphones requiring a bias source. 2.3. Programmable Input Gain/Attenuation The signals from the microphone, line, or handset inputs are mixed and then routed to the A/D converter and a digital programmable gain circuit which provides up to 12 dB of gain or –34.5 dB of attenuation in 1.5 dB steps. Level changes only take effect on zero crossings to minimize audible artifacts. The requested level change is implemented if no zero crossing is found after 256 frames. Write the ADC Volume Control register 6 to set digital input gain/attenuation. 2.4. Analog Outputs The analog outputs of the D/A converter are routed to a line level output (LINEO), a pair of speaker outputs (SPKRL and SPKRR), and a handset. Each analog output can be independently muted. Si3034/35/44/56 Chipsets DAA System-Side Device DAA Line-Side Device Discretes DSP SPKR Si3000 Voice Codec Handset Line Mic Figure 14. Si3000 with Silicon Labs DAA System Diagram 14 Rev. 1.4 TIP RING Si3000 2.5. Programmable Output Gain/Attenuation Prior to D/A conversion, the Si3000 contains a digital programmable gain/attenuator which provides up to 12 dB of gain or –34.5 dB of attenuation in 1.5 dB steps. Level changes only take effect on zero crossings to minimize audible artifacts. The requested level change is implemented if no zero crossing is found after 256 frames. Write the DAC Volume Control (register 7) to set digital input gain/attenuation. 2.6. Line Output LINEO is a line level analog output signal centered around a common mode voltage. The minimum recommended load impedance is 600 . This output is a fully filtered output with a 1 Vrms full scale range. The only external component required is the 10 F DC blocking capacitor shown in Figure 13 on page 12. This output may be muted through the LOM bit in register 6 or attenuated by setting the analog attenuation bits in register 9. 2.7. Speaker Output The SPKRL and SPKRR are mono, in-phase, analog outputs capable of driving a small loudspeaker whose impedance is typically 32 (see Figure 13 on page 12). The speaker outputs may be muted through the SLM and SRM bits in the DAC Gain Control register 7 or attenuated by setting the analog attenuation bits in register 9. 2.8. Digital Interface The Si3000 has two serial interface modes that support most standard modem DSPs. These modes are selected by the addition of a 50 k pull-down/up resistor on the SDO and SCLK pins as shown in Figure 13 on page 12. The key difference between these two serial modes is the operation of the FSYNC signal. Table 11 summarizes the serial mode definitions. Table 11. Serial Modes Mode SCLK* SDO* Description 0 0 0 FSYNC frames data 1 0 1 FSYNC pulse starts data frame 2 1 0 Slave mode 3 1 1 Reserved *Note: Pull-up/pull-down states The digital interface consists of a single synchronous serial link which communicates audio and control data. In slave mode, SCLK is connected only to the pullup/ pulldown resistor, and MCLK is a 256 Fs input which is internally multiplied using the on-chip phase-locked loop (PLL) to clock the A/D converter and D/A converter. In master mode, the master clock (MCLK) is an input and the serial data clock (SCLK) is an output. The MCLK frequency and the value of the sample rate control registers 3 and 4 determine the sample rate (Fs). The serial port clock, SCLK, runs at 256 bits per frame, where the frame rate is equivalent to the sample rate. Digital information is transferred between the DSP and the Si3000 in the form of 16-bit Primary Frames and 16bit Secondary Frames. There are separate pins for receive (SDO) and transmit (SDI) functions, providing simultaneous receive/transmit operation within each frame. Primary Frames are used for digital audio data samples. Primary Frames occur at the frame rate and are always present. Secondary Frames are used for accessing internal Si3000 registers. Secondary Frames are not always present and are requested on-demand. When Secondary Frames are present, they occur mid-point between Primary Frames. Hence, no Primary Frames are dropped. On Primary Frame transmits (DSP to Si3000), the Si3000 treats the LSB (16th bit) as a flag to request a Secondary Frame. Set the primary frame LSB = 1 to request a secondary frame; otherwise, set the primary frame LSB = 0. Therefore, out of 16-bits of transmit data on SDI, only 15-bits represent actual audio data. When secondary frames are not present, no transmission occurs during this time slot. On Primary Frames receives (Si3000 to DSP), the Si3000 drives SDO with 16-bits of audio data, if the Si3000 is in either Serial Mode 0 or 1. However, if the Si3000 is in SLAVE mode (Mode 2), the Si3000 supplies 15-bits of Audio Data to the DSP and always drives the LSB zero. This feature is designed to work with the Si3021 register 14 SSEL set to 10. In this system configuration, when the DSP receives Primary Frames, it can check the LSB to determine whether the receive data is from the Si3021 or from the Si3000. On Secondary Frame receives and transmits; the Si3000 treats the input and output serial stream as 16bits of data. Figure 15 shows the relative timing of the serial frames. Figure 16 and Figure 17 illustrate the secondary frame write cycle and read cycle, respectively. During a read cycle, the R/W bit is high and the 5-bit address field contains the address of the register to be read. The contents of the 8-bit control register are placed on the SDO signal. During a write cycle, the R/W bit is low and the 5-bit address field contains the address of the register to be written. The 8-bit data to be written immediately follows the address on SDI. Only one register can be read or written during each secondary frame. See "3. Control Registers" on page 19 for the register addresses and functions. Rev. 1.4 15 Si3000 FS Y NC Prim ary Secondary Prim ary D 15 – D 1 D 0 = 0 (Softw are FC Bit) S DI XM T D ata Secondary U pdate XM T D ata S DO R C V D ata Secondary U pdate R C V D ata 16 SCLKs 128 SCLKs 256 SCLKs Figure 15. Secondary Request FS Y NC (m ode 0) FS Y NC (m ode 1) D 15 D 14 D 13 D 12 D 11 D 10 D 9 S DI 0 0 0 A A A D8 A D7 D6 D5 D4 D3 D2 D D D D D D A D1 D0 D D R/W S DO Figure 16. Secondary Communication Data Format—Write Cycle FS Y NC (m ode 0) FS Y NC (m ode 1) D 15 D 14 D 13 D 12 D 11 D 10 S DI 0 0 1 A A A D9 D8 A R/W S DO D0 D7 A D7 D6 H igh Z D D D5 D4 D D D3 D D2 D D1 D0 D Figure 17. Secondary Frame Format—Read Cycle 16 Rev. 1.4 D H igh Z Si3000 F U P1 M CLK ÷ N1 F PLL1 P V CO1 D ÷ 5 or ÷ 10* 1024·Fs *Note: S ee P LL bit in Register 2. ÷ M1 8 bits Figure 18. Clock Generation Subsystem (PLL) 2.9. Clock Generation Subsystem The Si3000 contains an on-chip clock generator. Using a single MCLK input frequency, the Si3000 can generate all the desired standard modem sample rates, as well as the common 11.025 kHz rate for audio playback. Table 12. MCLK Examples for 8 kHz MCLK (MHz) N1 M1 1.8432 9 200 4.0000 25 256 The clock generator consists of a phase-locked loop (PLL1) that achieves the desired sample frequency. Figure 18 illustrates the clock generator. The architecture of the PLL allows for fast lock time on initial start-up, fast lock time when changing modem sample rates and high noise immunity. A large number of MCLK frequencies between 1 MHz and 60 MHz are supported. 4.0960 1 10 5.2800 33 256 5.7600 9 64 6.1440 3 20 8.1920 1 5 9.2160 9 40 2.9.1. Programming the Clock Generator 10.0800 63 256 10.5600 33 128 11.0592 27 100 12.288 3 10 14.7456 9 25 16.0000 25 64 18.4320 9 20 24.5760 3 5 25.8048 63 100 33.7600 211 256 44.2368 27 25 46.0800 9 8 47.9232 117 100 48.0000 75 64 56.0000 175 128 59.200 185 128 As noted in Figure 18, the clock generator must output a clock equal to 1024*Fs, where Fs is the desired sample rate. The 1024*Fs clock is determined through programming of the following registers: Register 3 - N1 divider, 8 bits. Register 4 - M1 divider, 8 bits N1 (register 3) and M1 (register 4) are 8-bit unsigned values. FMCLK is the clock provided to the MCLK pin. Table 12 lists several standard crystal rates that could be supplied to MCLK. When programming the registers of the clock generator, the order of register writes is important. For PLL updates, N1 (register 3) must always be written first, immediately followed by a write to M1 (register 4). Note: The values shown in Table 12 satisfy the equations above. However, when programming the registers for N1 and M1, the value placed in these registers must be one less than the value calculated from the equations. Rev. 1.4 17 Si3000 2.9.2. PLL Lock Times 3. Restore MCLK before initiating the power up sequence. The Si3000 changes sample rates very quickly. However, lock time will vary based on the programming of the clock generator. The following relationship describes the boundaries on PLL locking time: 4. Reset the Si3000 using the RESET pin (after MCLK is present). PLL lock time < 1 ms It is recommended that the PLL be programmed during initialization. The final design consideration for the clock generator is the update rate of PLL. The following criteria must be satisfied in order for the PLL to remain stable: F UP1 = F MCLK N1 144kHz Where FUP1 is shown in Figure 18. 2.9.3. Setting Generic Sample Rates The above clock generation description focuses on common modem sample rates. The restrictions and equations above still apply; however, a more generic relationship between MCLK and Fs (the desired sample rate) is needed. The following equation describes this relationship: M1 5 1024 Fs -------- = -------------------------------N1 MCLK where Fs is the sample frequency, and all other symbols are shown in Figure 18. Knowing the MCLK frequency and desired sample rate the values for the M1 and N1 registers can be determined. When determining these values, remember to consider the range for each register as well as the minimum update rate for the first PLL. The values determined for M1 and N1 must be adjusted by minus one when determining the value written to the respective registers. This is due to internal logic, which adds one to the value stored in the register. This addition allows the user to write a zero value in any of the registers and the effective divide-by is one. A special case occurs when both M1 and N1 are programmed with a zero value. When M1 and N1 are both zero, the PLL is bypassed. 2.10. Sleep Mode The Si3000 supports a low-power sleep mode. Sleep mode is activated by setting the Chip Power Down (CPD) bit in register 1. When the Si3000 is in sleep mode, the MCLK signal may be stopped or remain active, but it must be active before waking up the Si3000. To take the Si3000 out of sleep mode, pulse the reset pin (RESET) low. In summary, the power down/up sequence is as follows: 5. Program the registers to desired settings. 2.11. Loopback Operation The Si3000 advanced design provides the manufacturer with increased ability to determine system functionality during production line tests, as well as support for end-user diagnostics. Two loopback modes exist for this purpose, allowing increased coverage of system components. The digital loopback1 mode allows an external device to send audio data to the SDI input pin and receive the signal through the SDO output pin. In this mode, the group delay of the digital filters is present. This mode allows testing of the digital filters, DAC, and ADC. To enable this mode, set the DL1 bit of register 2, and clear DL2. The digital loopback2 mode allows an external device to send audio data to the SDI input pin and receive the signal through the SDO output pin. This mode allows testing of the digital filters, but not the ADC and DAC. To enable this mode, set the DL2 bit of register 2, and clear DL1. 2.12. Reducing Power-on Pop Noise To minimize power-on pop during initialization, a waiting period is recommended before powering up the analog output drivers. The waiting period starts when the reset signal to the Si3000 is negated. The wait time required is dependent on the external load. Typically, the load consists of an AC coupling capacitor in series with an equivalent load resistor to ground. The equivalent load resistor can either be a speaker load, or the input resistance of an external amplifier. The rule-of-thumb for the waiting period in msec is derived by C*(12+R). For example, in the case of a 10 F AC coupling capacitor and resistive load of 1.0 k the recommended waiting period is 10*(12+1) = 130 msec. If the analog outputs drive external amplifiers, another factor to consider is the voltage division ratio determined by R/(R+12), where R represents the input resistance of the external amplifier. This ratio must be kept as small as possible. A good target value is R = 1 k. If needed, add a load resistor in parallel with the amplifier input to lower the effective input resistance of the amplifier stage. 1. Set the Power Down bit (PDN, register 6, bit 3). 2. MCLK may stay active or stop. 18 Rev. 1.4 Si3000 3. Control Registers Note: Any register not listed here is reserved and should not be written. Any register bit labelled reserved should be written to zero during writes to the register. Register 0 can be read (always returns 0) and written safely. Table 13. Register Summary Register Name Bit 7 Bit 6 Bit 5 SR Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 SPD LPD HPD MPD CPD HPFD PLL DL1 DL2 MCM HIM IIR 1 Control 1 2 Control 2 3 PLL1 Divide N1 4 PLL1 Multiply M1 5 RX Gain Control 1 6 ADC Volume Control RXG LOM HOM 7 DAC Volume Control TXG SLM SRM 8 Status Report 9 Analog Attenuation Divider N1 Multiplier M1 LIG SLSC LIM SRSC MCG LOSC LOT Rev. 1.4 SOT 19 Si3000 Register 1. Control 1 Bit D7 Name Type D6 D5 D4 D3 D2 D1 D0 SR SPD LPD HPD MPD CPD R/W R/W R/W R/W R/W R/W Reset settings = 0000_0000 Bit Name Function 7 SR 6:5 Reserved 4 SPD Speaker Drive Power Down. 1= Normal operation 0 = Power down left and right speaker drive. 3 LPD Line Drive Power Down. 1 = Normal operation 0 = Power down line driver. 2 HPD Handset Drive Power Down. 1 = Normal operation 0 = Power down handset driver. 1 MPD MIC Bias Power Down. 1 = Power down MIC bias buffer. 0 = Normal operation 0 CPD Chip Power Down. 1 = Puts Si3000 into power down mode. 0 = Normal operation Software Reset. 1 = Sets all registers to their reset value. 0 = Enables chip for normal operation. Note: Bit will automatically clear after being set. 20 Read returns zero. Rev. 1.4 Si3000 Register 2. Control 2 Bit D7 D6 D5 D4 D3 D2 D1 Name HPFD PLL DL1 DL2 Type R/W R/W R/W R/W D0 Reset Settings = 0000_0000 Bit Name Function 7:5 Reserved 4 HPFD 3 PLL PLL Divide by 10. 1 = Sets final stage of PLL to divide by 10. 0 = Sets final stage of PLL to divide by 5. 2 DL1 Digital Loopback. 1 = Enables digital loopback (DAC analog out ADC analog in). 0 = Normal operation 1 DL2 Digital Loopback. 1 = Enables digital loopback (DAC one bit ADC one bit). 0 = Normal operation 0 Reserved Read returns zero. High Pass Filter (HPF) Disable. 1 = HPF disabled 0 = HPF enabled Read returns zero. Rev. 1.4 21 Si3000 Register 3. PLL1 Divide N1 Bit D7 D6 D5 D4 D3 Name Divider N1 Type R/W D2 D1 D0 Reset settings = 0000_0000 Bit Name 7:0 N1 Function N1. Contains the (value – 1) for determining the output frequency on PLL. Register 4. PLL1 Multiply M1 Bit D7 D6 D5 D4 D3 Name Multiplier M1 Type R/W D2 D1 Reset settings = 0000_0000 22 Bit Name 7:0 M1 Function M1. Contains the (value – 1) for determining the output frequency on PLL. Rev. 1.4 D0 Si3000 Register 5. RX Gain Control 1 Bit D7 D6 D5 D4 D3 D2 D1 D0 Name LIG LIM MCG MCM HIM IIR Type R/W R/W R/W R/W R/W R/W Reset settings = 0100_0111 Bit Name 7:6 LIG Function Line in Gain. 11 = 20 dB gain 10 = 10 dB gain 01 = 0 dB gain 00 = Reserved 5 LIM Line in Mute. 1 = Line input muted 0 = Line input goes to mixer 4:3 MCG MIC Input Gain. 11 = 30 dB gain 10 = 20 dB gain 01 = 10 dB gain 00 = 0 dB gain 2 MCM MIC Input Mute. 1 = Mute MIC input 0 = MIC input goes into mixer. 1 HIM Handset Input Mute. 1 = Mute handset input 0 = Handset input goes into mixer. 0 IIR IIR Enable. 1 = Enables IIR filter 0 = Enables FIR filter Rev. 1.4 23 Si3000 Register 6. ADC Volume Control Bit D7 D6 D5 D4 D3 D1 D0 Name RXG LOM HOM Type R/W R/W R/W Reset settings = 0101_1100 24 D2 Bit Name Function 7 Reserved 6:2 RXG RX PGA Gain Control. 11111 = 12 dB 10111 = 0 dB 00000 = –34.5 dB LSB = 1.5 dB 1 LOM Line Out Mute. 0 = Mute 1 = Active 0 HOM Handset Out Mute. 0 = Mute 1 = Active Read returns zero. Rev. 1.4 Si3000 Register 7. DAC Volume Control Bit D7 D6 D5 D4 D3 D2 D1 D0 Name TXG SLM SRM Type R/W R/W R/W Reset settings = 0101_1100 Bit Name Function 7 Reserved 6:2 TXG TX PGA Gain Control. 11111 = 12 dB 10111 = 0 dB 00000 = –34.5 dB LSB = 1.5 dB 1 SLM SPKR_L Mute. 0 = Mute 1 = Active 0 SRM SPKR_R Mute. 0 = Mute 1 = Active Read returns zero. Rev. 1.4 25 Si3000 Register 8. Status Report Bit D7 D6 D5 Name SLSC SRSC LOSC Type R R R D4 D3 D2 D1 D0 Reset settings = 0000_0000 Bit Name Function 7 SLSC SPK_L Short Circuit. 1 = Indicate short circuit status is detected at left speaker. 0 = Normal mode 6 SRSC SPK_R Short Circuit. 1 = Indicate short circuit status is detected at right speaker. 0 = Normal mode 5 LOSC Line Out Short Circuit. 1 = Indicate short circuit status is detected at line out. 0 = Normal mode 4:0 Reserved Read returns zero. Register 9. Analog Attenuation Bit D7 D6 D5 D4 D3 D2 D0 Name LOT SOT Type R/W R/W Reset settings = 0000_0000 26 D1 Bit Name Type 7:4 Reserved 3:2 LOT Line Out Attenuation. 11 = –18 dB analog attenuation on Line Output. 10 = –12 dB analog attenuation on Line Output. 01 = –6 dB analog attenuation on Line Output. 00 = 0 dB analog attenuation on Line Output. 2:0 SOT Speaker Out Attenuation. 11 = –18 dB analog attenuation on Speaker Output. 10 = –12 dB analog attenuation on Speaker Output. 01 = –6 dB analog attenuation on Speaker Output. 00 = 0 dB analog attenuation on Speaker Output. Read returns zero. Rev. 1.4 Si3000 4. Pin Descriptions: Si3000 SPKRR 1 16 SPKRL MBIA S 2 15 LINEO HDST 3 14 GND SDI 4 13 VA SDO 5 12 VD FSY NC 6 11 LINEI MCLK 7 10 MIC SCLK 8 9 RESET Pin # Pin Name Description 1 SPKRR Speaker Right Output. Analog output capable of driving a 60 load. 2 MBIAS Microphone bias output. 3 HDST Handset Input/Output. Handset analog input/output. 4 SDI Serial Port Data In. Serial communication and control data that is generated by the System DSP to the Si3000. 5 SDO Serial Port Data Out. Serial communication data that is provided by the Si3000 to the system DSP. 6 FSYNC Frame Sync Output. Data framing signal that is used to indicate the start and stop of a communication data frame. 7 MCLK Master Clock Input. High speed master clock input. Generally supplied by the system crystal clock or DSP. 8 SCLK Serial Port Bit Clock Input/Output. Controls the serial data on SDO and latches the data on SDI. This pin is an input in slave mode and an output in master mode. 9 RESET Reset. An active low input that is used to reset all control registers to a defined initialized state. Also used to bring the Si3000 out of sleep mode. 10 MIC 11 LINEI Line Input. Line level input with selectable gain of 0, 10, or 20 dB. The full scale input level is 1 VRMS. 12 VD Digital Supply Voltage. Provides the digital supply voltage to the Si3000. Nominally either 5 or 3.3 V and within 0.6 V of VA. MIC Input. Microphone level or line level input. This input contains selectable gain of 0, 10, 20, or 30 dB with a full scale input level of 1 VRMS. Rev. 1.4 27 Si3000 Pin # Pin Name 13 VA 14 GND 15 LINEO Line Output. Line level analog output with a 1 VRMS full scale output level. 16 SPKRL Speaker Left Output. Analog output capable of driving a 60 load. 28 Description Analog Supply Voltage. Provides the analog supply voltage to the Si3000. Nominally either 5 or 3.3 V and within 0.6 V of VD. Ground. Connects to the system digital ground. Rev. 1.4 Si3000 5. Ordering Guide Table 14. Ordering Guide Part Number Package Lead-Free Temp. Range Si3000-C-FS SOIC-16 Yes 0 to 70 °C Si3000-C-GS SOIC-16 Yes –40 to 85 °C *Note: Add an “R” at the end of the device to denote tape and reel option. Rev. 1.4 29 Si3000 6. Package Outline: 16-Pin SOIC Figure 19 illustrates the package details for the Si3000. Table 15 lists the values for the dimensions shown in the illustration. Figure 19. 16-Pin Small Outline Integrated Circuit (SOIC) Package Table 15. Package Diagram Dimensions Dimension Min Max Dimension Min Max A — 1.75 L 0.40 1.27 A1 0.10 0.25 L2 A2 1.25 — h 0.25 0.50 b 0.31 0.51 θ 0° 8° c 0.17 0.25 aaa 0.10 0.25 BSC D 9.90 BSC bbb 0.20 E 6.00 BSC ccc 0.10 E1 3.90 BSC ddd 0.25 e 1.27 BSC Notes: 1. All dimensions shown are in millimeters (mm) unless otherwise noted. 2. Dimensioning and Tolerancing per ANSI Y14.5M-1994. 3. This drawing conforms to the JEDEC Solid State Outline MS-012, Variation AC. 4. Recommended card reflow profile is per the JEDEC/IPC J-STD-020C specification for Small Body Components. 30 Rev. 1.4 Si3000 7. 16-Pin SOIC Land Pattern Figure illustrates the recommended land pattern for the Si3000 16-pin SOIC. Table 16 lists the values for the dimensions shown in the illustration. Figure 20. 16-Pin SOIC Land Pattern Diagram Table 16. 16-Pin MSOP Land Pattern Dimensions Dimension Feature mm C1 Pad Column Spacing 5.40 E Pad Row Pitch 1.27 X1 Pad Width 0.60 Y1 Pad Length 1.55 Notes: General 1. All dimensions shown are in millimeters (mm) unless otherwise noted. 2. Dimensioning and Tolerancing per ASME Y14.5M-1994. 3. This Land Pattern Design is based on the IPC-7351 guidelines. 4. All dimensions shown are at Maximum Material Condition (MMC). Least Material Condition (LMC) is calculated based on a Fabrication Allowance of 0.05 mm. Solder Mask Design 5. All metal pads are to be non-solder mask defined (NSMD). Clearance between the solder mask and the metal pad is to be 60 µm minimum, all the way around the pad. Stencil Design 6. A stainless steel, laser-cut and electro-polished stencil with trapezoidal walls should be used to assure good solder paste release. 7. The stencil thickness should be 0.125 mm (5 mils). 8. The ratio of stencil aperture to land pad size should be 1:1. Card Assembly 9. A No-Clean, Type-3 solder paste is recommended. 10. The recommended card reflow profile is per the JEDEC/IPC J-STD-020 specification for Small Body Components. Rev. 1.4 31 Si3000 8. Package Markings (Top Markings) Codes for the Si3000-C-GS and Si3000-C-FS top marks are as follows: YY = Current Year WW = Work Week R = Die Revision TTTTT = Trace Code 8.1. Si3000-C-GS Top Marking 8.2. Si3000-C-FS Top Marking 32 Rev. 1.4 Si3000 DOCUMENT CHANGE LIST Revision 1.0 to Revision 1.1 Updated Functional Block Diagram. Removed all B-grade references. Updated Table 4 (AC Characteristics). Updated Figure 14. Removed analog loopback feature description. Revision 1.1 to Revision 1.2 Updated " Features" on page 1 and "5. Ordering Guide" on page 29 to add updated support for leadfree, RoHS-compliant packages. Updated document for compatibility with Silicon Laboratories 3rd generation serial interface DAA, the Si3056. Updated Figure 13 on page 12. Updated MIC and MICBIAS pin number labels. Changed standardized minimum input/output attenuation level to –34.5 dB. In some instances, this level was incorrectly specified at –36 dB. Updated SOIC package outline drawing and dimensions table. Revision 1.2 to Revision 1.3 Updated Table 6 on page 7. Updated Figure 1 on page 7. Updated Figure 2 on page 8. Updated Figure 13 on page 12. Updated "2.8. Digital Interface" on page 15. Updated "2.11. Loopback Operation" on page 18. Updated "4. Pin Descriptions: Si3000" on page 27. Revision 1.3 to Revision 1.4 Added extended temperature Si3000-C-GS to Table 14 ordering guide. Added Section 7, 16-Pin SOIC Land Pattern. Added Section 8, Package Top Markings. Rev. 1.4 33 Si3000 CONTACT INFORMATION Silicon Laboratories Inc. 400 West Cesar Chavez Austin, TX 78701 Tel: 1+(512) 416-8500 Fax: 1+(512) 416-9669 Toll Free: 1+(877) 444-3032 Please visit the Silicon Labs Technical Support web page: https://www.silabs.com/support/pages/contacttechnicalsupport.aspx and register to submit a technical support request. The information in this document is believed to be accurate in all respects at the time of publication but is subject to change without notice. Silicon Laboratories assumes no responsibility for errors and omissions, and disclaims responsibility for any consequences resulting from the use of information included herein. Additionally, Silicon Laboratories assumes no responsibility for the functioning of undescribed features or parameters. Silicon Laboratories reserves the right to make changes without further notice. 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Other products or brandnames mentioned herein are trademarks or registered trademarks of their respective holders. 34 Rev. 1.4