54LS256/DM74LS256 Dual 4-Bit Addressable Latch General Description The ’LS256 is a dual 4-bit addressable latch with common control inputs; these include two Address inputs (A0, A1), an active LOW enable input (E) and an active LOW Clear input (CL). Each latch has a Data input (D) and four outputs (Q0 – Q3). When the Enable (E) is HIGH and the Clear input (CL) is LOW, all outputs (Q0–Q3) are LOW. Dual 4-channel demultiplexing occurs when the CL and E are both LOW. When CL is HIGH and E is LOW, the selected output (Q0 – Q3), determined by the Address inputs, follows D. When the E goes HIGH, the contents of the latch are stored. When operating in the addressable latch mode (E e LOW, CL e HIGH), changing more than one bit of the Address (A0, A1) Connection Diagram could impose a transient wrong address. Therefore, this should be done only while in the memory mode (E e CL e HIGH). Features Y Y Y Y Y Serial-to-parallel capability Output from each storage bit available Random (addressable) data entry Easily expandable Active low common clear Logic Symbol Dual-In-Line Package TL/F/9823–1 TL/F/9823 – 2 Order Number 54LS256DMQB, 54LS256FMQB or DM74LS256N See NS Package Number J16A, N16E or W16A Pin Names A0, A1 Da, Db E CL Q0a – Q3a Q0b – Q3b C1995 National Semiconductor Corporation TL/F/9823 VCC e Pin 16 GND e Pin 8 Description Common Address Inputs Data Inputs Common Enable Input (Active LOW) Conditional Clear Input (Active LOW) Side A Latch Outputs Side B Latch Outputs RRD-B30M115/Printed in U. S. A. 54LS256/DM74LS256 Dual 4-Bit Addressable Latch June 1989 Truth Table Inputs Outputs CL E A0 A1 L H X L L L L L L L L L H L H H H H H H H L L L L Mode Q0 Q1 Q2 Q3 X L L L L Clear L L H H D L L L L D L L L L D L L L L D Demultiplex X X Qtb1 Qt b 1 Qtb1 Qt b 1 Memory L H L H L L H H D Qtb1 D Qt b 1 Qt b 1 Qtb1 Qt b 1 D Qtb1 Qt b 1 Qt b 1 Qt b 1 D Addressable Latch Qtb1 Qtb1 Qtb1 t b 1 e Bit time before address change or rising edge of E H e HIGH Voltage Level L e LOW Voltage Level X e Immaterial Mode Selection E CL Mode L H L H H H L L Addressable Latch Memory Active HIGH 4-Channel Demultiplexers Clear Logic Diagram TL/F/9823 – 3 2 Absolute Maximum Ratings (Note) Note: The ‘‘Absolute Maximum Ratings’’ are those values beyond which the safety of the device cannot be guaranteed. The device should not be operated at these limits. The parametric values defined in the ‘‘Electrical Characteristics’’ table are not guaranteed at the absolute maximum ratings. The ‘‘Recommended Operating Conditions’’ table will define the conditions for actual device operation. If Military/Aerospace specified devices are required, please contact the National Semiconductor Sales Office/Distributors for availability and specifications. Supply Voltage 7V Input Voltage 7V Operating Free Air Temperature Range b 55§ C to a 125§ C 54LS DM74LS 0§ C to a 70§ C Storage Temperature Range b 65§ C to a 150§ C Recommended Operating Conditions Symbol 54LS256 Parameter DM74LS256 Units Min Nom Max Min Nom Max 4.5 5 5.5 4.75 5 5.25 VCC Supply Voltage VIH High Level Input Voltage VIL Low Level Input Voltage IOH High Level Output Current IOL Low Level Output Current TA Free Air Operating Temperature ts (H) Setup Time HIGH, Dn to E 20 20 th (H) Hold Time HIGH, Dn to E 0 0 ns ts (L) Setup Time LOW, Dn to E 15 15 ns th (L) Hold Time LOW, Dn to E 0 0 ns ts (H) ts (L) Setup Time HIGH or LOW, An to E 0 0 ns tw (L) E Pulse Width LOW 17 17 ns 2 2 V V 0.7 0.8 V b 0.4 b 0.4 mA 8 mA 70 §C 4 b 55 125 0 ns Electrical Characteristics Over recommended operating free air temperature range (unless otherwise noted) Symbol Parameter Conditions Min Typ (Note 1) Max Units b 1.5 V VI Input Clamp Voltage VCC e Min, II e b18 mA VOH High Level Output Voltage VCC e Min, IOH e Max VIL e Max Low Level Output Voltage VCC e Min, IOL e Max VIH e Min 54LS DM74 0.35 0.5 IOL e 4 mA, VCC e Min DM74 0.25 0.4 Input Current @ Max Input Voltage VCC e Max, VI e 10V Inputs 0.1 E 0.2 High Level Input Current VCC e Max, VI e 2.7V VOL II IIH IIL IOS ICC Low Level Input Current VCC e Max, VI e 0.4V Short Circuit Output Current VCC e Max (Note 2) Supply Current VCC e Max 54LS 2.5 DM74 2.7 V 3.4 0.4 Inputs 20 E 40 Inputs b 0.4 E b 0.8 54LS b 20 b 100 DM74 b 20 b 100 25 Note 1: All typicals are at VCC e 5V, TA e 25§ C. Note 2: Not more than one output should be shorted at a time, and the duration should not exceed one second. 3 V mA mA mA mA mA Switching Characteristics VCC e a 5.0V, TA e a 25§ C (See Section 1 for waveforms and load configurations) Symbol RL e 2 kX CL e 15 pF Parameter Units Max tPLH tPHL Propagation Delay E to Qn 27 24 ns tPLH tPHL Propagation Delay Dn to Qn 30 20 ns tPLH tPHL Propagation Delay An to Qn 30 29 ns tPLH Propagation Delay CL to Qn 18 ns 4 Physical Dimensions inches (millimeters) 16-Lead Ceramic Dual-In-Line Package (J) Order Number 54LS256DMQB NS Package Number J16A 16-Lead Molded Dual-In-Line Package (N) Order Number DM74LS256N NS Package Number N16E 5 54LS256/DM74LS256 Dual 4-Bit Addressable Latch Physical Dimensions inches (millimeters) (Continued) 16-Lead Ceramic Flat Package (W) Order Number 54LS256FMQB NS Package Number W16A LIFE SUPPORT POLICY NATIONAL’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF NATIONAL SEMICONDUCTOR CORPORATION. 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