9314/DM9314 Quad Latch General Description The ’9314 is a multifunctional 4-bit latch designed for general purpose storage applications in high speed digital systems. All outputs have active pull-up circuitry to provide high capacitance drive and to provide low impedance in both logic states for good noise immunity. Connection Diagram Logic Symbol Dual-In-Line Package TL/F/9788 – 2 VCC e Pin 16 GND e Pin 8 TL/F/9788 – 1 Order Number 9314DMQB, 9314FMQB or DM9314N See NS Package Number J16A, N16E or W16A Pin Names E D0–D3 S0 – S3 MR Q0–Q3 C1995 National Semiconductor Corporation TL/F/9788 Description Enable Input (Active LOW) Data Inputs Set Inputs (Active LOW) Master Reset Input (Active LOW) Latch Outputs RRD-B30M115/Printed in U. S. A. 9314/DM9314 Quad Latch June 1989 Absolute Maximum Ratings (Note) Note: The ‘‘Absolute Maximum Ratings’’ are those values beyond which the safety of the device cannot be guaranteed. The device should not be operated at these limits. The parametric values defined in the ‘‘Electrical Characteristics’’ table are not guaranteed at the absolute maximum ratings. The ‘‘Recommended Operating Conditions’’ table will define the conditions for actual device operation. If Military/Aerospace specified devices are required, please contact the National Semiconductor Sales Office/Distributors for availability and specifications. Supply Voltage Input Voltage Operating Free Air Temperature Range Military Commercial 7V b 55§ C to a 125§ C 0§ C to a 70§ C Storage Temperature Range b 65§ C to a 150§ C 5.5V Recommended Operating Conditions Symbol Military Parameter Commercial Units Min Nom Max Min Nom Max 4.5 5 5.5 4.75 5 5.25 VCC Supply Voltage VIH High Level Input Voltage VIL Low Level Input Voltage IOH High Level Output Current IOL Low Level Output Current TA Free Air Operating Temperature ts (H) ts (L) Setup Time HIGH or LOW Dn to E 5.0 18 5.0 18 ns th (H) th (L) Hold Time HIGH or LOW Dn to E 0 5.0 0 5.0 ns ts (H) Setup Time HIGH, Dn to Sn 8.0 8.0 ns th (L) Hold Time LOW, Dn to Sn 8.0 8.0 ns tw (L) E Pulse Width LOW 18 18 ns tw (L) MR Pulse Width LOW 18 18 ns trec Recovery Time, MR to E 0 0 ns 2 2 V 0.8 0.8 V b 0.8 b 0.8 mA 16 mA 70 §C 16 b 55 V 125 0 Electrical Characteristics Over recommended operating free air temperature range (unless otherwise noted) Symbol Parameter Conditions VI Input Clamp Voltage VCC e Min, II e b 12 mA VOH High Level Output Voltage VCC e Min, IOH e Max VIL e Max VOL Low Level Output Voltage VCC e Min, IOL e Max VIH e Min II Input Current @ Max Input Voltage IIH High Level Input Current IIL IOS ICC Low Level Input Current Min 2.4 Typ (Note 1) Max Units b 1.5 V 3.4 0.2 V 0.4 V VCC e Min, VI e 5.5V 1 mA VCC e Max, VI e 2.4V 40 Data Inputs 60 VCC e Max, VI e 0.4V b 1.6 Data Inputs b 2.7 Short Circuit Output Current VCC e Max (Note 2) Supply Current VCC e Max MIL b 20 b 70 COM b 20 b 70 55 Note 1: All typicals are at VCC e 5V, TA e 25§ C. Note 2: Not more than one output should be shorted at a time. 2 mA mA mA mA Switching Characteristics VCC e a 5.0V, TA e a 25§ C (See Section 1 for waveforms and load configurations) Symbol CL e 15 pF Parameter Min Units Max tPLH tPHL Propagation Delay E to Qn 24 24 ns tPLH tPHL Propagation Delay Dn to Qn 12 24 ns tPLH Propagation Delay MR to Qn 18 ns tPHL Propagation Delay Sn to Qn 24 ns Functional Description Truth Table The ’9314 consists of four latches with a common active LOW Enable input and active LOW Master Reset input. When the Enable goes HIGH, data present in the latches is stored and the state of the latch is no longer affected by the Sn and Dn inputs. The Master Reset when activated overrides all other input conditions forcing all latch outputs LOW. Each of the four latches can be operated in one of two modes: D-TYPE LATCHÐFor D-type operation the S input of a latch is held LOW. While the common Enable is active the latch output follows the D input. Information present at the latch output is stored in the latch when the Enable goes HIGH. SET/RESET LATCHÐDuring set/reset operation when the common Enable is LOW a latch is reset by a LOW on the D input, and can be set by a LOW on the S input if the D input is HIGH. If both S and D inputs are LOW, the D input will dominate and the latch will be reset. When the Enable goes HIGH, the latch remains in the last state prior to disablement. The two modes of latch operation are shown in the Truth Table. MR E D S Qn Operation H H H L L H L H X L L X L H D Mode H H H H H L L L L H L H L H X L L H H X Qnb1 Qnb1 L X X X L H e HIGH Voltage Level L e LOW Voltage Level X e Immaterial Qnb1 e Previous Output State Qn e Present Output State 3 Qnb1 L H L R/S Mode Reset Logic Diagram TL/F/9788 – 3 4 Physical Dimensions inches (millimeters) 16-Lead Ceramic Dual-In-Line Package (J) Order Number 9314DMQB NS Package Number J16A 16-Lead Molded Dual-In-Line Package (N) Order Number DM9314N NS Package Number N16E 5 9314/DM9314 Quad Latch Physical Dimensions inches (millimeters) (Continued) 16-Lead Ceramic Flat Package (W) Order Number 9314FMQB NS Package Number W16A LIFE SUPPORT POLICY NATIONAL’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF NATIONAL SEMICONDUCTOR CORPORATION. As used herein: 1. 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