TP3076 COMBO ® II Programmable PCM CODEC/Filter for ISDN and Digital Phone Applications General Description Features The TP3076 is a second-generation combined PCM CODEC and Filter devices optimized for digital switching applications on subscriber line and trunk cards and digital phone applications. Using advanced switched capacitor techniques, COMBO II combines transmit bandpass and receive lowpass channel filters with a companding PCM encoder and decoder. The devices are A-law and µ-law selectable and employ a conventional serial PCM interface capable of being clocked up to 4.096 MHz. A number of programmable functions may be controlled via a serial control port. Channel gains are programmable over a 25.4 dB range in each direction. To enable COMBO II to interface to the SLIC control leads, a number of programmable latches are included; each may be configured as either an input or an output. The TP3076 provides 4 latches. n Complete CODEC and Filter system including: — Transmit and receive PCM channel filters — µ-law or A-law companding coder and decoder — Receive power amplifier drives 300Ω — 4.096 MHz serial PCM data (max) n Programmable functions: — Transmit gain: 25.4 dB range, 0.1 dB steps — Receive gain: 25.4 dB range, 0.1 dB steps — Time-slot assignment; to 64 slots/frame — 4 interface latches — A or µ-law — Analog loopback — Digital loopback n Direct interface to solid-state SLICs n Standard serial control interface n 80 mW operating power (typ) n 1.5 mW standby power (typ) n Designed for CCITT and LSSGR specifications n TTL and CMOS compatible digital interfaces Note: See also AN-614 COMBO II application guide. Block Diagram DS009758-1 FIGURE 1. TRI-STATE ® and COMBO ® are registered trademarks of National Semiconductor Corporation. MICROWIRE/PLUS™ is a trademark of National Semiconductor Corporation. © 1999 National Semiconductor Corporation DS009758 www.national.com TP3076 COMBO II Programmable PCM CODEC/Filter for ISDN and Digital Phone Applications April 1994 Connection Diagram Pin DS009758-4 This transmit data TRI-STATE ® output remains in the high impedance state except during the assigned transmit time slot on the assigned port, during which the transmit PCM data byte is shifted out on the rising edges of BCLK. TSX1 Normally this open drain output is floating in a high impedance state except when a time-slot is active on the DX output, when the TSX1 output pulls low to enable a backplane line-driver. DR1 This receive data input is inactive except during the assigned receive time slot of the assigned port when the receive PCM data is shifted in on the falling edges of BCLK. CCLK Control Clock input. This clock shifts serial control information into CI or out from CO when the CS input is low, depending on the current instruction. CCLK may be asynchronous with the other system clocks. CI Control Data Input pin. Serial control information is shifted into COMBO II on this pin when CS is low. Byte 1 of control information is always written into COMBO II, while the direction of byte 2 data is determined by bit 2 of byte 1, as defined in Table 1. CO Control Data Output pin. Serial control or status information is shifted out of COMBO II on this pin when CS is low. CS Chip Select input. When this pin is low, control information can be written to or read from COMBO II via CI or CO. IL3–IL0 Each Interface Latch I/O pin may be individually programmed as an input or an output determined by the state of the corresponding bit in the Latch Direction Register (LDR). For pins configured as inputs, the logic state sensed on each input is latched into the Interface Latch Register (ILR) whenever control data is written to COMBO II, while CS is low, and the information is shifted out on the CO pin. When configured as outputs, control data written into the ILR appears at the corresponding IL pins. Order Number TP3076J See NS Package Number J20A Pin Descriptions Pin Description VCC +5V ± 5% power supply. VBB −5V ± 5% power supply. GND Ground. All analog and digital signals are referenced to this pin. FSX Transmit Frame Sync input. Normally a pulse or squarewave with an 8 kHz repetition rate is applied to this input to define the start of the transmit time slot assigned to this device (non-delayed data timing mode), or the start of the transmit frame (delayed data timing mode using the internal time-slot assignment counter). FSR Receive Frame Sync input. Normally a pulse or squarewave with an 8 kHz repetition rate is applied to this input to define the start of the receive time slot assigned to this device (non-delayed data timing mode), or the start of the receive frame (delayed data timing mode using the internal time-slot assignment counter). BCLK Bit clock input used to shift PCM data into and out of the DR and DX pins. BCLK may vary from 64 kHz to 4.096 MHz in 8 kHz increments, and must be synchronous with MCLK. MCLK Master clock input used by the switched capacitor filters and the encoder and decoder sequencing logic. Must be 512 kHz, 1.536/1.544 MHz, 2.048 MHz or 4.096 MHz and synchronous with BCLK. VFXI VFRO www.national.com Description DX1 Functional Description POWER-ON INITIALIZATION The Transmit analog high-impedance input. Voice frequency signals present on this input are encoded as an A-law or µ-law PCM bit stream and shifted out on the selected DX pin. When power is first applied, power-on reset circuitry initializes the COMBO II and puts it into the power-down state. The gain control registers for the transmit and receive gain sections are programmed for no output, the power amp is disabled and the device is in the non-delayed timing mode. The Latch Direction Register (LDR) is pre-set with all IL pins programmed as inputs, placing the SLIC interface pins in a high impedance state. The CO pin is in TRI-STATE condition. Other initial states in the Control Register are indicated in Section 2.0. The Receive analog power amplifier output, capable of driving load impedances as low as 300Ω (depending on the peak overload level required). PCM data received on the assigned DR pin is decoded and appears at this output as voice frequency signals. 2 Functional Description der low-pass switched capacitor filters. The A/D converter has a compressing characteristic according to the standard CCITT A or µ255 coding laws, which must be selected by a control instruction during initialization (see Table 1 and Table 2). A precision on-chip voltage reference ensures accurate and highly stable transmission levels. Any offset voltage arising in the gain-set amplifier, the filters or the comparator is canceled by an internal auto-zero circuit. Each encode cycle begins immediately following the assigned Transmit time-slot. The total signal delay referenced to the start of the time-slot is approximately 165 µs (due to the Transmit Filter) plus 125 µs (due to encoding delay), which totals 290 µs. Data is shifted out on DX1 during the selected time slot on eight rising edges of BCLK. (Continued) The desired modes for all programmable functions may be initialized via the control port prior to a Power-up command. POWER-DOWN STATE Following a period of activity in the powered-up state the power-down state may be re-entered by writing any of the control instructions into the serial control port with the “P” bit set to “1” as indicated in Table 1. It is recommended that the chip be powered down before writing any additional instructions. In the power-down state, all non-essential circuitry is de-activated and the DX1 output is in the high impedance TRI-STATE condition. The data stored in the Gain Control registers, the LDR and ILR, and all control bits remain unchanged in the power-down state unless changed by writing new data via the serial control port, which remains active. The outputs of the Interface Latches also remain active, maintaining the ability to monitor and control the SLIC. DECODER AND RECEIVER FILTER PCM data is shifted into the Decoder’s Receive PCM Register via the DR1 pin during the selected time-slot on the 8 falling edges of BCLK. The Decoder consists of an expanding DAC with either A or µ255 law decoding characteristic, which is selected by the same control instruction used to select the Encode law during initialization. Following the Decoder is a 5th order low-pass switched capacitor filter with integral Sin x/x correction for the 8 kHz sample and hold. A programmable gain amplifier, which must be set by writing to the Receive Gain Register, is included, and finally a Power Amplifier capable of driving a 300Ω load to ± 3.5V, a 600Ω load to ± 3.8V or a 15 kΩ load to ± 4.0V at peak overload. TRANSMIT FILTER AND ENCODER The Transmit section input, VFXI, is a high impedance input. No external components are necessary to set the gain. Following this is a programmable gain/attenuation amplifier which is controlled by the contents of the Transmit Gain Register (see Programmable Functions section). An active pre-filter then precedes the 3rd order high-pass and 5th or- TABLE 1. Programmable Register Instructions Function Single Byte Power-Up/Down Byte 1 (Notes 1, 2, 3) Byte 2 (Note 1) 7 6 5 4 3 2 1 0 P X X X X X 0 X 7 6 5 4 3 2 1 0 None Write Control Register P 0 0 0 0 0 1 X See Table 2 Read-Back Control Register P 0 0 0 0 1 1 X See Table 2 Write to Interface Latch Register P 0 0 0 1 0 1 X See Table 4 Read Interface Latch Register P 0 0 0 1 1 1 X See Table 4 Write Latch Direction Register P 0 0 1 0 0 1 X See Table 3 Read Latch Direction Register P 0 0 1 0 1 1 X See Table 3 Write Receive Gain Register P 0 1 0 0 0 1 X See Table 8 Read Receive Gain Register P 0 1 0 0 1 1 X See Table 8 Write Transmit Gain Register P 0 1 0 1 0 1 X See Table 7 Read Transmit Gain Register P 0 1 0 1 1 1 X See Table 7 Write Receive Time-Slot/Port P 1 0 0 1 0 1 X See Table 6 Read-Back Receive Time-Slot/Port P 1 0 0 1 1 1 X See Table 6 Write Transmit Time-Slot/Port P 1 0 1 0 0 1 X See Table 6 Read-Back Transmit Time-Slot/Port P 1 0 1 0 1 1 X See Table 6 Note 1: Bit 7 of bytes 1 and 2 is always the first bit clocked into or out from the CI or CO pin. X = don’t care. Note 2: “P” is the power-up/down control bit, see Power-up/Down Control section. (“0” = Power Up, “1” = Power Down) Note 3: Other register address codes are invalid and should not be used. PCM INTERFACE The FSX and FSR frame sync inputs determine the beginning of the 8-bit transmit and receive time-slots respectively. They may have any duration from a single cycle of BCLK HIGH to one MCLK period LOW. Two different relationships may be established between the frame sync inputs and the actual time-slots on the PCM busses by setting bit 3 in the Control Register (see Table 2). Non-delayed data mode is similar to long-frame timing on the TP3050/60 series of de- A decode cycle begins immediately after the assigned receive timeslot, and 10 µs later the Decoder DAC output is updated. The total signal delay is 10 µs plus 120 µs (filter delay) plus 62.5 µs (1⁄2 frame) which gives approximately 190 µs. 3 www.national.com Functional Description Programmable Functions (Continued) vices (COMBO); time-slots begin nominally coincident with the rising edge of the appropriate FS input. The alternative is to use Delayed Data mode, which is similar to shortframe sync timing on COMBO, in which each FS input must be high at least a half-cycle of BCLK earlier than the timeslot. The Time-Slot Assignment circuit on the device can only be used with Delayed Data timing. When using Time-Slot Assignment, the beginning of the first time-slot in a frame is identified by the appropriate FS input. The actual transmit and receive time-slots are then determined by the internal Time-Slot Assignment counters. Transmit and Receive frames and time-slots may be skewed from each other by any number of BCLK cycles. During each assigned Transmit time-slot, the DX1 output shifts data out from the PCM register on the rising edges of BCLK. TSX1 also pulls low for the first 71⁄2 bit times of the time-slot to control the TRI-STATE Enable of a backplane line-driver. Serial PCM data is shifted into the DR1 input during each assigned Receive time-slot on the falling edges of BCLK. POWER-UP/DOWN CONTROL Following power-on initialization, power-up and power-down control may be accomplished by writing any of the control instructions listed in Table 1 into COMBO II with the “P” bit set to “0” for power-up or “1” for power-down. Normally it is recommended that all programmable functions be initially programmed while the device is powered down. Power state control can then be included with the last programming instruction or the separate single-byte instruction. Any of the programmable registers may also be modified while the device is powered-up or down by setting the “P” bit as indicated. When the power-up or down control is entered as a single byte instruction, bit one (1) must be reset to a 0. When a power-up command is given, all de-activated circuits are activated, but the TRI-STATE PCM output(s), DX1 will remain in the high impedance state until the second FSX pulse after power-up. CONTROL REGISTER INSTRUCTION The first byte of a READ or WRITE instruction to the Control Register is as shown in Table 1. The second byte has the following bit functions: SERIAL CONTROL PORT Control information and data are written into or read-back from COMBO II via the serial control port consisting of the control clock CCLK, the serial data input, CI, and output, CO, and the Chip Select input, CS. All control instructions require 2 bytes, as listed Table 1, with the exception of a single byte power-up/down command. The Byte 1 bits are used as follows: bit 7 specifies power up or power down; bits 6, 5, 4 and 3 specify the register address, bit 2 specifies whether the instruction is read or write; bit 1 specifies a one or two byte instruction; and bit 0 is not used. To shift control data into COMBO II, CCLK must be pulsed high 8 times while CS is low. Data on the CI input is shifted into the serial input register on the falling edge of each CCLK pulse. After all data is shifted in, the contents of the input shift register are decoded, and may indicate that a 2nd byte of control data will follow. This second byte may either be defined by a second byte-wide CS pulse or may follow the first contiguously, i.e, it is not mandatory for CS to return high between the first and second control bytes. At the end of CCLK8 in the 2nd control byte the data is loaded into the appropriate programmable register. CS may remain low continuously when programming successive registers, if desired. However, CS must be set high when no data transfers are in progress. To readback Interface Latch data or status information from COMBO II, the first byte of the appropriate instruction is strobed while CS is low, as defined in Table 1. CS must be kept low, or be taken low again for a further 8 CCLK cycles, during which the data is shifted onto the CO pin on the rising edges of CCLK. When CS is high the CO pin is in the high-impedance TRI-STATE, enabling the CI and CO pins of many devices to be multiplexed together. If CS returns high during either byte 1 or byte 2 before all eight CCLK pulses of that byte occur, both the bit count and byte count are reset and register contents are not affected. This prevents loss of synchronization in the control interface as well as corruption of register data due to processor interrupt or other problem. When CS returns low again, the device will be ready to accept bit 1 of byte 1 of a new instruction. www.national.com TABLE 2. Control Register Byte 2 Functions Bit Number and Name 7 6 5 4 3 2 1 0 F1 F0 MA IA DN DL AL PP Function 0 0 MCLK = 512 kHz 0 1 MCLK = 1.536 MHz 1 0 MCLK = 2.048 MHz (Note 4) 1 1 or 1.544 MHz MCLK = 4.096 MHz 0 X Select µ255 Law (Note 4) 1 0 A-Law, Including Even Bit Inversion 1 1 A-Law, No Even Bit Inversion 0 Delay Data Timing 1 Non-Delayed Data Timing (Note 4) 0 0 Normal Operation (Note 4) 1 X Digital Loopback 0 1 Analog Loopback 0 Power Amp 1 Power Amp Enabled in PDN Disabled in PDN (Note 4) Note 4: state at power-on initialization. Master Clock Frequency Selection A Master clock must be provided to COMBO II for operation of the filter and coding/decoding functions. The MCLK frequency must be either 512 kHz, 1.536 MHz, 1.544 MHz, 2.048 MHz, or 4.096 MHz and must be synchronous with BCLK. Bits F1 and F0 (see Table 2) must be set during initialization to select the correct internal divider. 4 Programmable Functions Bits L3–L0 must be set by writing the specific instruction to the LDR with the L bits in the second byte set as follows: (Continued) Coding Law Selection Bits “MA” and “IA” in Table 2 permit the selection of µ255 coding or A-law coding, with or without even bit inversion. TABLE 3. Byte 2 Functions of Latch Direction Register Byte 2 Bit Number Analog Loopback Analog Loopback mode is entered by setting the “AL” and “DL” bits in the Control Register as shown in Table 2. In the analog loopback mode, the Transmit input VFXI is isolated from the input pin and internally connected to the VFRO output, forming a loop from the Receive PCM Register back to the Transmit PCM Register. The VFRO pin remains active, and the programmed settings of the Transmit and Receive gains remain unchanged, thus care must be taken to ensure that overload levels are not exceeded anywhere in the loop. 7 6 5 4 3 2 1 0 L0 L1 L2 L3 1 1 X X Ln Bit IL Direction 0 Input 1 Output X = Don’t Care INTERFACE LATCH STATES Interface Latches configured as outputs assume the state determined by the appropriate data bit in the 2-byte instruction written to the Interface Latch Register (ILR) as shown in Table 1 and Table 4. Latches configured as inputs will sense the state applied by an external source, such as the Off-Hook detect output of a SLIC. All bits of the ILR, i.e. sensed inputs and the programmed state of outputs, can be read back in the 2nd byte of a READ from the ILR. It is recommended that during initialization, the state of IL pins to be configured as outputs should be programmed first followed immediately by the Latch Direction Register. Digital Loopback Digital Loopback mode is entered by setting the “AL” and “DL” bits in the Control Register as shown in Table 2. This mode provides another stage of path verification by enabling data written into the Receive PCM Register to be read back from that register in any Transmit time-slot at DX1. PCM decoding continues and analog output appears at VFR0. The output can be disabled by programming ‘No Output’ in the Receive Gain Register (see Table 8). INTERFACE LATCH DIRECTIONS Immediately following power-on, all Interface Latches assume they are inputs, and therefore all IL pins are in a high impedance state. Each IL pin may be individually programmed as a logic input or output by writing the appropriate instruction to the LDR, see Table 1 and Table 3. For minimum power dissipation, unconnected latch pins should be programmed as outputs. For the TP3076, bits 2 and 3 should always be programmed as “1” (outputs). TABLE 4. Interface Latch Data Bit Order Bit Number 7 6 5 4 3 2 1 0 D0 D1 D2 D3 D4 D5 X X TABLE 5. Coding Law Conventions µ255 Law MSB VIN = +Full Scale VIN = 0V VIN = −Full Scale LSB True A-Law with A-Law without Even Bit Inversion Even Bit Inversion MSB LSB MSB LSB 10000000 10101010 111111111 11111111 11010101 100000000 11111111 01010101 000000000 00000000 00101010 011111111 Note 5: The MSB is always the first PCM bit shifted in or out of COMBO II. 5 www.national.com Programmable Functions (Continued) TABLE 6. Time-Slot and Port Assignment Instruction Bit Number and Name 7 EN 6 4 3 2 1 0 T4 T3 T2 T1 T0 X X X X X PS T5 (Note 6) (Note 7) 1 X 0 Function 5 Disable DX1 Output (Transmit Instruction) Disable DR1 Input (Receive Instruction) 1 1 Assign One Binary Coded Time-Slot from 0–63 Enable DX1 Output (Transmit Instruction) Assign One Binary Coded Time-Slot from 0–63 Enable DR1 Input (Transmit Instruction) Note 6: The “PS” bit MUST be set to “1” for both transmit and receive for the TP3076. Note 7: T5 is the MSB of the time-slot assignment bit field. Time-slot bits should be set to “000000” for both transmit and receive when operating in non-delayed data timing mode. and convert to the binary equivalent. Some examples are given in Table 7. A complete tabulation is given in Appendix I of AN-614. It should be noted that the Transmit (idle channel) Noise and Transmit Signal to Total Distortion are both specified with transmit gain set to 0 dB (gain register set to all ones). At high transmit gains there will be some degradation in noise performance for these parameters. See Application Note AN-614 for more information on this subject. TIME-SLOT ASSIGNMENT COMBO II can operate in either fixed time-slot or time-slot assignment mode for selecting the Transmit and Receive PCM time-slots. Following power-on, the device is automatically in Non-Delayed Timing mode, in which the time-slot always begins with the leading (rising) edge of frame sync inputs FSX and FSR. Time-Slot Assignment may only be used with Delay Data timing; see Figure 4. FSX and FSR may have any phase relationship with each other in BCLK period increments. Alternatively, the internal time-slot assignment counters and comparators can be used to access any time-slot in a frame, using the frame sync inputs as marker pulses for the beginning of transmit and receive time-slot 0. In this mode, a frame may consist of up to 64 time-slots of 8 bits each. A time-slot is assigned by a 2-byte instruction as shown in Table 1 and Table 6. The last 6 bits of the second byte indicate the selected time-slot from 0–63 using straight binary notation. When writing a time-slot and port assignment register, if the PCM interface is currently active, it is immediately deactivated to prevent possible bus clashes. A new assignment becomes active on the second frame following the end of the Chip-Select for the second control byte. Rewriting of the register contents should not be performed during the talking period of a connection to prevent waveform distortion caused by loss of a sample which will occur with each register write. The “EN” bit allows the PCM input, DR1, or output, DX1, as appropriate, to be enabled or disabled. Time-Slot Assignment mode requires that the FSX and FSR pulses conform to the delayed data timing format shown in Figure 4. TABLE 7. Byte 2 of Transmit Gain Instruction Bit Number at VFXI 00000000 No Output (Note 8) 00000001 0.074 00000010 0.075 — — 11111110 1.359 11111111 1.375 Note 8: Analog signal path is cut off, but DX remains active and will output codes representing idle noise. RECEIVE GAIN INSTRUCTION BYTE 2 The receive gain can be programmed in 0.1 dB steps by writing to the Receive Gain Register as defined in Table 1 and Table 8. Note the following restrictions on output drive capability: 1. 0 dBm0 levels ≤ 1.96 Vrms at VFRO may be driven into a load of ≥ 15 kΩ to GND; Receive Gain set to 0 dB (gain register set to all ones). PORT SELECTION On the TP3076, the “PS” bit MUST always be set to 1. Table 6 shows the format for the second byte of both transmit and receive time-slot and port assignment instructions. 2. 0 dBm0 levels ≤ 1.85 Vrms at VFRO may be driven into a load of ≥ 600Ω to GND; Receive Gain set to 0.5 dB. 0 dBm0 levels ≤ 1.71 Vrms at VFRO may be driven into a load of ≥ 300 Ω to GND. Receive Gain set to −1.2 dB. To calculate the binary code for byte 2 of this instruction for any desired output 0 dBm0 level in Vrms, take the nearest integer to the decimal number given by: 3. TRANSMIT GAIN INSTRUCTION BYTE 2 The transmit gain can be programmed in 0.1 dB steps by writing to the Transmit Gain Register as defined in Table 1 and Table 7. This corresponds to a range of 0 dBm0 levels at VFXI between 1.375 Vrms and 0.074 Vrms (equivalent to +5.0 dBm to −20.4 dBm in 600Ω). To calculate the binary code for byte 2 of this instruction for any desired input 0 dBm0 level in Vrms, take the nearest integer to the decimal number given by: 200 x log10 (V/0.07299) www.national.com 0 dBm0 Test Level (Vrms) 76543210 200 x log10 (V/0.1043) and convert to the binary equivalent. Some examples are given in Table 8. A complete tabulation is given in Appendix I or AN-614. 6 Programmable Functions POWER SUPPLIES (Continued) While the pins of the TP3076 COMBO II device are well protected against electrical misuse, it is recommended that the standard CMOS practice of applying GND to the device before any other connections are made should always be followed. In applications where the printed circuit card may be plugged into a hot socket with power and clocks already present, an extra long ground pin on the connector should be used and a Schottky diode connected between VBB and GND. TABLE 8. Byte 2 of Receive Gain Instruction Bit Number 0 dBm0 Test Level (Vrms) 76543210 at VFRO 00000000 No Output (Low Z to GND) 00000001 0.105 00000010 0.107 — — 11111110 1.941 11111111 1.964 To minimize noise sources all ground connections to each device should meet at a common point as close as possible to the GND pin in order to prevent the interaction of ground return currents flowing through a common bus impedance. Power supply decoupling capacitors of 0.1 µF should be connected from this common point to VCC and VBB as close to the device pins as possible. Applications Information Figure 2 shows a typical ISDN phone application of the TP3076 together with a TP3420 ISDN Transceiver “S” Interface Device and HPC16400 High-Performance Microcontroller with HDLC Controller. The TP3076 device is programmed over its serial control interface via the HPC16400 MICROWIRE/PLUS™ serial I/O port. Further guidelines on PCB layout techniques are provided in Application Note AN-614, “COMBO II™ Programmable PCM CODEC/Filter Family Application Guide”. 7 www.national.com www.national.com 8 Sidetone ≅ −21.5 dB for 1200Ω. Note 11: Sidetone ≅ −9.2 dB for 200Ω, Note 10: Primo type DH31 or similar. Note 9: Primo type EM80–PMI2 or similar. FIGURE 2. Typical Application in an ISDN Phone DS009758-5 Applications Information Absolute Maximum Ratings (Note 12) Storage Temperature Range VBB to GND Current at VFR0 Current at Any Digital Output Lead Temperature (Soldering, 10 sec.) If Military/Aerospace specified devices are required, please contact the National Semiconductor Sales Office/ Distributors for availability and specifications. VCC to GND Voltage at VFXI Voltage at Any Digital Input 7V VCC +0.5V to VBB −0.5V VCC +0.5V to GND −0.5V −65˚C to +150˚C −7V ± 100 mA ± 50 mA 300˚C Electrical Characteristics Unless otherwise noted, limits printed in BOLD characters are guaranteed for VCC = +5V ± 5%, VBB = −5V ± 5%; TA = 0˚C to +70˚C by correlation with 100% electrical testing at TA = 25˚C. All other limits are assured by correlation with other production tests and/or product design and characterization. All signals referenced to GND. Typicals specified at VCC = +5V, VBB = −5V, TA = 25˚C. Symbol Parameter Conditions Min Typ Max Units 0.7 V 0.4 V DIGITAL INTERFACES VIL Input Low Voltage All Digital Inputs (DC Meas.) VIH Input High Voltage VOL Output Low Voltage All Digital Inputs (DC Meas.) (Note 13) DX1, TSX1, and CO, IL = 3.2 mA, VOH Output High Voltage All Other Digital Outputs, IL = 1 mA DX1 and CO, IL = −3.2 mA, All Other Digital Outputs (except TSX), IL = −1 mA All Digital Outputs, IL = −100 µA IIL Input Low Current IIH Input High Current IOZ 2.0 2.4 −10 Any Digital Input, except MR, VIH < VIN < VCC MR Only DX1, TSX1 and CO High Impedance IL3–IL0 when Selected as Inputs State (TRI-STATE ) GND < VOUT < VCC V VCC − 0.5 Any Digital Input, GND < VIN < VIL Output Current in V V 10 µA −10 10 µA −10 100 −10 10 1.0 µA ANALOG INTERFACES IVFXI Input Current, VFXI −3.3V < VFXI < 3.3V −1.0 RVFXI Input Resistance 1.0 VOSX Input Offset Voltage −3.3V < VFXI < 3.3V Transmit Gain = 0 dB Transmit Gain = 25.40 dB Receive Gain = 0 dB Applied at VFXI RLVFRO Load Resistance Receive Gain = −0.5 dB Receive Gain = −1.2 dB CLVFRO Load Capacitance µA MΩ 200 mV 10 mV 15k Ω 600 300 RLVFRO ≥ 300Ω 200 pF CLVFRO from VFRO to GND ROVFRO Output Resistance Steady Zero PCM Code Applied to DR1 VOSR Output Offset Voltage Alternating ± Zero PCM Code Applied at VFRO DR1, Maximum Receive Gain 3.0 Ω 200 mV 0.1 0.6 mA −0.1 −0.3 mA 8.0 11.0 mA mA 1.0 −200 POWER DISSIPATION ICC0 Power Down Current CCLK, CI, CO = 0.4V, CS = 2.4V Interface Latches Set as Outputs with No Load, All Other Inputs Active, Power Amp Disabled IBB0 Power Down Current As Above ICC1 Power Up Current CCLK, CI, CO = 0.4V, CS = 2.4V No Load on Power Amp Interface Latches Set as Outputs with No Load IBB1 Power Up Current As Above −8.0 −11.0 ICC2 Power Down Current As Above, Power Amp Enabled 2.0 3.0 mA IBB2 Power Down Current As Above, Power Amp Enabled −2.0 −3.0 mA Note 12: “Absolute Maximum Ratings” indicate limits beyond which damage to the device may occur. Operating Ratings indicate conditions for which the device is functional, but do not guarantee specific performance limits. 9 www.national.com Electrical Characteristics (Continued) Note 13: See definitions and timing conventions section. Timing Specifications Unless otherwise noted, limits printed in BOLD characters are guaranteed for VCC = +5V ± 5%; VBB = −5V ± 5%; TA = 0˚C to +70˚C by correlation with 100% electrical testing at TA = 25˚C. All other limits are assured by correlation with other production tests and/or product design and characterization. All signals referenced to GND. Typicals specified at VCC = +5V, VBB = −5V, TA = 25˚C. All timing parameters are measured at VOH = 2.0V and VOL = 0.7V. See Definitions and Timing Conventions section for test methods information. Symbol Parameter Conditions Min Typ Max Units MASTER CLOCK TIMING fMCLK Frequency of MCLK Selection of Frequency is Programmable (See Table 5) tWMH Period of MCLK High Measured from VIH to VIH (Note 14) 80 tWML Period of MCLK Low Measured from VIL to VIL (Note 14) 80 tRM Rise Time of MCLK Measured from VIL to VIH tFM Fall Time of MCLK Measured from VIH to VIL tHBM HOLD Time, BCLK LOW 512 kHz 1536 kHz 1544 kHz 2048 kHz 4096 kHz ns ns 30 ns 30 ns 50 ns to MCLK HIGH tWFL Period of FSX Measured from VIL to VIL 1 MCLK or FSR Low Period PCM INTERFACE TIMING fBCLK Frequency of BCLK May Vary from 64 kHz to 4096 kHz 64 4096 kHz in 8 kHz Increments tWBH Period of BCLK High Measured from VIH to VIH 80 tWBL Period of BCLK Low Measured from VIL to VIL 80 tRB Rise Time of BCLK Measured from VIL to VIH tFB Fall Time of BCLK Measured from VIH to VIL tHBF Hold Time, BCLK Low ns ns 30 ns 30 ns 30 ns 30 ns to FSX/R High or Low tSFB Setup Time, FSX/R High to BCLK Low tDBD Delay Time, BCLK High Load = 100 pF Plus 2 LSTTL Loads 80 ns 80 ns 60 ns 60 ns to Data Valid tDBZ Delay Time, BCLK Low to DX1 DX1 disabled is measured Disabled if FSX Low, FSX Low to at VOL or VOH according DX1 disabled if 8th BCLK to Figure 5 15 Low, or BCLK High to DX1 Disabled if FSX High tDBT Delay Time, BCLK High to Load = 100 pF Plus 2 LSTTL Loads TSX Low if FSX High, or FSX High to TSX Low if BCLK High (Nondelayed mode); BCLK High to TSX Low (delayed data mode) tZBT TRI-STATE Time, BCLK Low to TSX High if FSX Low, FSX Low to TSX High if 8th BCLK Low, or 15 BCLK High to TSX High if FSX High tDFD Delay Time, FSX/R www.national.com Load = 100 pF Plus 2 LSTTL Loads, 10 Timing Specifications (Continued) Unless otherwise noted, limits printed in BOLD characters are guaranteed for VCC = +5V ± 5%; VBB = −5V ± 5%; TA = 0˚C to +70˚C by correlation with 100% electrical testing at TA = 25˚C. All other limits are assured by correlation with other production tests and/or product design and characterization. All signals referenced to GND. Typicals specified at VCC = +5V, VBB = −5V, TA = 25˚C. All timing parameters are measured at VOH = 2.0V and VOL = 0.7V. See Definitions and Timing Conventions section for test methods information. Symbol Parameter Conditions Min Typ Max Units 80 ns PCM INTERFACE TIMING High to Data Valid Applies if FSX/R Rises Later Than BCLK Rising Edge in Non-Delayed Data Mode Only tSDB Setup Time, DR1 30 ns 15 ns Valid to BCLK Low tHBD Hold Time, BCLK Low to DR1 Invalid SERIAL CONTROL PORT TIMING fCCLK Frequency of CCLK tWCH Period of CCLK High Measured from VIH to VIH 160 tWCL Period of CCLK Low Measured from VIL to VIH 160 tRC Rise Time of CCLK Measured from VIL to VIH tFC Fall Time of CCLK Measured of VIH to VIL tHCS Hold Time, CCLK Low CCLK1 10 ns CCLK8 100 ns 60 ns 60 ns 50 ns 50 ns 2048 kHz ns ns 50 ns 50 ns to CS Low tHSC Hold Time, CCLK Low to CS High tSSC Setup Time, CS Transition to CCLK Low tSSC0 tSDC Setup Time, CS To Insure CO is Not Enabled Transition to CCLK High for Single Byte Setup Time, CI Data In to CCLK Low tHCD Hold Time, CCLK Low to CO Invalid tDCD Load = 100 pF Plus 2 LSTTL Loads 80 ns Delay Time, CS Low Applies Only if Separate 80 ns to CO Valid CS Used for Byte 2 80 ns Delay Time, CCLK High to CO Data Out Valid tDSD tDDZ Delay Time, CS or 9th CCLK Applies to Earlier of CS High to CO High Impedance High or 9th CCLK High 15 INTERFACE LATCH TIMING tSLC Setup Time, IL to Interface Latch Inputs Only 100 ns 50 ns CCLK 8 of Byte 1 tHCL Hold Tme, IL Valid from 8th CCLK Low (Byte 1) tDCL Delay Time CCLK8 of Byte 2 to IL Interface Latch Outputs Only CL = 50 pF 200 ns Note 14: Applies only to MCLK Frequencies ≥ 1.536 MHz. At 512 kHz a 50:50 ± 2% Duty Cycle must be used. 11 www.national.com Timing Diagrams DS009758-6 FIGURE 3. Non-Delayed Data Timing Mode DS009758-7 FIGURE 4. Delayed Data Timing Mode www.national.com 12 DS009758-8 (Continued) FIGURE 5. Control Port Timing Timing Diagrams 13 www.national.com Transmission Characteristics Unless otherwise noted, limits printed in BOLD characters are guaranteed for VCC = +5V ± 5%, VBB = −5V ± 5%; TA = 0˚C to +70˚C by correlation with 100% electrical testing at TA = 25˚C. f = 1015.625 Hz, VFXI = 0 dBm0, DR1 = 0 dBm0 PCM code. Transmit and receive gains programmed for maximum 0 dBm0 test levels (0 dB Gain). All other limits are assured by correlation with other production tests and/or product design and characterization. All signals referenced to GND. Typicals specified at VCC = +5V, VBB = −5V, TA = 25˚C. Symbol Parameter Conditions Min Typ Max Units AMPLITUDE RESPONSE Absolute Levels The Maximum 0 dBm0 Levels Are: VFXI 1.375 Vrms VFRO (15 kΩ Load) 1.964 Vrms 73.8 mVrms 105.0 mVrms The Minimum 0 dBm0 Levels are: VFXI VFRO (Any Load ≥ 300Ω) GXA Transmit Gain Transmit Gain Programmed for Maximum Absolute Accuracy 0 dBm0 Test Level. Measure Deviation of Digital Code from GXAG Transmit Gain Ideal 0 dBm0 PCM Code at DX1. TA = 25˚C TA = 25˚C, VCC = 5V, VBB = 5V Variation with Programmed Gain from 0 dB to 19 dB Programmed Gain (0 dBm0 Levels of 1.619 Vrms to 0.182 Vrms) −0.15 0.15 dB −0.1 0.1 dB −0.3 0.3 dB −26 dB −1.8 −0.1 dB −0.15 0.15 dB 0.0 dB Programmed Gain from 19.1 dB to 25.4 dB (0 dBm0 Levels of 0.180 Vrms to 0.087 Vrms) Note: ± 0.1 dB Min/Max is Available as a Selected Part GXAF Transmit Gain Relative to 1015.625 Hz, (Note 18) Variation with Minimum Gain < GX < Maximum Gain f = 60 Hz f = 200 Hz Frequency f = 300 Hz to 3000 Hz f = 3400 Hz −0.7 f = 400 Hz −14 dB f ≥ 4600 Hz. Measure Response −32 dB at Alias Frequency from 0 kHz to 4 kHz GX = 0.0 dB, VFXI = 1.375 Vrms Relative to 1015.625 Hz f = 62.5 Hz f = 203.125 Hz f = 343.75 Hz f = 515.625 Hz f = 2140.625 Hz f = 3156.25 Hz f = 3406.250 Hz −24.9 dB −1.7 −0.1 dB −0.15 0.15 dB −0.15 0.15 dB −0.15 0.15 dB −0.15 0.15 dB −0.74 0.0 dB −13.5 dB −32 dB −32 dB −32 dB 0.1 dB f = 3984.375 Hz Relative to 1062.5 Hz (Note 18) f = 5250 Hz, Measure 2750 Hz GXAT Variation with f = 11750 Hz, Measure 3750 Hz f = 49750 Hz, Measure 1750 Hz Measured Relative to GXA, VCC = 5V, VBB = −5V, Temperature Minimum gain < GX < Maximum Gain Transmit Gain www.national.com 14 −0.1 Transmission Characteristics (Continued) Unless otherwise noted, limits printed in BOLD characters are guaranteed for VCC = +5V ± 5%, VBB = −5V ± 5%; TA = 0˚C to +70˚C by correlation with 100% electrical testing at TA = 25˚C. f = 1015.625 Hz, VFXI = 0 dBm0, DR1 = 0 dBm0 PCM code. Transmit and receive gains programmed for maximum 0 dBm0 test levels (0 dB Gain). All other limits are assured by correlation with other production tests and/or product design and characterization. All signals referenced to GND. Typicals specified at VCC = +5V, VBB = −5V, TA = 25˚C. Symbol Parameter Conditions Min Typ Max Units −0.2 0.2 dB −0.4 0.4 dB −1.2 1.2 dB −0.15 0.15 dB −0.1 0.1 dB −0.3 0.3 dB −0.1 0.1 dB −0.25 0.15 dB −0.15 0.15 dB −0.7 0.0 dB −14 dB AMPLITUDE RESPONSE GXAL Transmit Gain Variation with Signal Level GRA Sinusoidal Test Method. Reference Level = 0 dBm0 VFXI = −40 dBm0 to +3 dBm0 VFXI = −50 dBm0 to −40 dBm0 VFXI = −55 dBm0 to −50 dBm0 Receive Gain Receive Gain Programmed for Maximum Absolute Accuracy 0 dBm0 Test Level. Apply 0 dBm0 PCM Code to DR1. Measure VFR0. TA = 25˚C GRAG Receive Gain TA = 25˚C, VCC = 5V, VBB = −5V Variation with Programmed Gain from 0 dB to 19 dB Programmed Gain (0 dBm0 Levels of 1.964 Vrms to 0.220 Vrms) Programmed Gain from 19.1 dB to 25.4 dB (0 dBm0 Levels of 0.218 Vrms to 0.105 Vrms) Note: ± 0.1 dB Min/Max is Available as a Selected Part GRAT GRAF Variation with Receive Gain Measured Relative to GRA. VCC = 5V, VBB = −5V. Temperature Minimum Gain < GR < Maximum Gain Receive Gain Relative to 1015.625 Hz, (Note 18) DR1 = 0 dBm0 Code. Variation with Frequency Minimum Gain < GR < Maximum Gain f = 200 Hz f = 300 Hz to 3000 Hz f = 3400 Hz f = 4000 Hz GR = 0 dB, DR1 = 0 dBm0 Code, GX = 0 dB (Note 18) GRAL Receive Gain Variation with Signal Level f = 296.875 Hz f = 1875.00 Hz f = 2906.25 Hz −0.15 0.15 dB −0.15 0.15 dB −0.15 0.15 dB f = 2984.375 Hz f = 3406.250 Hz f = 3984.375 Hz −0.15 0.15 dB −0.74 0.0 dB −13.5 dB −0.2 0.2 dB −0.4 0.4 dB −1.2 1.2 dB Sinusoidal Test Method. Reference Level = 0 dBm0. DR1 = −40 dBm0 to +3 dBm0 DR1 = −50 dBm0 to −40 dBm0 DR1 = −55 dBm0 to −50 dBm0 DR1 = 3.1 dBm0 −0.5 RL = 600Ω, GR = −0.5 dB RL = 300Ω, GR = 1.2 dB ENVELOPE DELAY DISTORTION WITH FREQUENCY DXA Tx Delay, Absolute f = 1600 Hz 15 −0.2 0.2 dB −0.2 0.2 dB 315 µs www.national.com Transmission Characteristics (Continued) Unless otherwise noted, limits printed in BOLD characters are guaranteed for VCC = +5V ± 5%, VBB = −5V ± 5%; TA = 0˚C to +70˚C by correlation with 100% electrical testing at TA = 25˚C. f = 1015.625 Hz, VFXI = 0 dBm0, DR1 = 0 dBm0 PCM code. Transmit and receive gains programmed for maximum 0 dBm0 test levels (0 dB Gain). All other limits are assured by correlation with other production tests and/or product design and characterization. All signals referenced to GND. Typicals specified at VCC = +5V, VBB = −5V, TA = 25˚C. Symbol Parameter Conditions Min Typ Max Units 220 µs 145 µs f = 800 Hz–1000 Hz f = 1000 Hz–1600 Hz f = 1600 Hz–2600 Hz 75 µs 40 µs 75 µs f = 2600 Hz–2800 Hz f = 2800 Hz–3000 Hz f = 1600 Hz 105 µs ENVELOPE DELAY DISTORTION WITH FREQUENCY Tx Delay, Relative to DXA f = 500 Hz–600 Hz DXR f = 600 Hz–800 Hz DRA Rx Delay, Absolute DRR Rx Delay, Relative to DRA f = 500 Hz–1000 Hz f = 1000 Hz–1600 Hz f = 1600 Hz–2600 Hz f = 2600 Hz–2800 Hz 155 µs 200 µs −40 µs −30 µs 90 µs 125 µs 175 µs 12 15 dBrnC0 −74 −67 dBm0p f = 2800 Hz–3000 Hz NOISE NXC NXP NRC Transmit Noise, C Message (Note 15) 11111111 Weighted, µ-Law Selected in Gain Register Transmit Noise, P Message (Note 15) 11111111 Weighted, A-Law Selected in Gain Register Receive Noise, C Message PCM Code is Alternating Positive 8 11 dBrnC0 PCM Code Equals Positive Zero −82 −79 dBm0p −53 dBm0 Weighted, µ-Law Selected NRP Receive Noise, P Message Weighted, A-Law Selected NRS PPSRX Noise, Single Frequency Positive Power Supply Rejection, Transmit NPSRX Negative Power Supply Rejection, Transmit PPSRR Positive Power Supply Rejection, Receive NPSRR Negative Power Supply Rejection, Receive www.national.com f = 0 kHz to 100 kHz, Loop Around Measurement, VFXI = 0 Vrms VCC = 5.0 VDC + 100 mVrms f = 0 kHz–4 kHz (Note 16) f = 4 kHz–50 kHz VBB = −5.0 VDC +100 mVrms 36 dBC 30 dBC f = 0 kHz–4 kHz (Note 16) f = 4 kHz–50 kHz 36 dBC 30 dBC Measure VFRO f = 0 Hz–4000 Hz f = 4 kHz–25 kHz 36 dBC 40 dB f = 25 kHz–50 kHz 36 dB Measure VFRO f = 0 Hz–4000 Hz f = 4 kHz–25 kHz 36 dBC 40 dB f = 25 kHz–50 kHz 36 dB PCM Code Equals Positive Zero VCC = 5.0 VDC + 100 mVrms PCM Code Equals Positive Zero VBB = −5.0 VDC + 100 mVrms 16 Transmission Characteristics (Continued) Unless otherwise noted, limits printed in BOLD characters are guaranteed for VCC = +5V ± 5%, VBB = −5V ± 5%; TA = 0˚C to +70˚C by correlation with 100% electrical testing at TA = 25˚C. f = 1015.625 Hz, VFXI = 0 dBm0, DR1 = 0 dBm0 PCM code. Transmit and receive gains programmed for maximum 0 dBm0 test levels (0 dB Gain). All other limits are assured by correlation with other production tests and/or product design and characterization. All signals referenced to GND. Typicals specified at VCC = +5V, VBB = −5V, TA = 25˚C. Symbol Parameter Conditions Min Typ Max Units NOISE SOS Spurous Out-of-Band 0 dBm0 300 Hz to 3400 Hz Input PCM Code Signals Applied at the at DR1 Channel Output 4600 Hz–7600 Hz −30 dB 7600 Hz–8400 Hz −40 dB 8400 Hz–50,000 Hz −30 dB DISTORTION STDX Signal to Total Distortion STDR Transmit or Receive Half-Channel, µ-Law Selected STDRL Single to Total Distortion Receive with Resistive Load SFDX Sinusoidal Test Method Level = 3.0 dBm0 33 dBC = 0 dBm0 to −30 dBm0 = −40 dBm0 36 dBC 30 dBC = −45 dBm0 25 dBC 33 dBC Sinusoidal Test Method Level = +3.1 dBm0 RL = 600Ω, GR = −0.5 dB RL = 300Ω, GR = −1.2 dB 33 dBC Single Frequency −46 dB −46 dB −41 dB −90 −75 dB −90 −70 dB Distortion, Transmit SFDR Single Frequency Distortion, Receive IMD Intermodulation Distortion Transmit or Receive Two Frequencies in the Range 300 Hz–3400 Hz CROSSTALK CTX-R Receive to Transmit Crosstalk, f = 300 Hz–3400 Hz DR = Idle Code f = 300 Hz–3400 Hz 0 dBm0 Receive Level (Note 16) Transmit to Receive Crosstalk, 0 dBm0 Transmit Level CTR-X Note 15: Measured by grounded input at VFXI. Note 16: PPSRX, NPSRX, and CTR-X are measured with a −50 dBm0 activation signal applied to VFXI. Note 17: A signal is Valid if it is above VIHor below VIL and Invalid if it is between VIL and VIH. For the purposes of this specification the following conditions apply: a) All input signals are defined as: VIL = 0.4V, VIH = 2.7V, tR < 10 ns, tF < 10 ns. b) tR is measured from VIL to VIH. tF is measured from VIH to VIL. c) Delay Times are measured from the input signal Valid to the output signal Valid. d) Setup Times are measured from the data input Valid to the clock input Invalid. e) Hold Times are measured from the clock signal Valid to the data input Invalid. f) Pulse widths are measured from VIL to VIL or from VIH to VIH. Note 18: A multi-tone test technique is used. 17 www.national.com TP3076 COMBO II Programmable PCM CODEC/Filter for ISDN and Digital Phone Applications Physical Dimensions inches (millimeters) unless otherwise noted Ceramic Dual-In-Line Package (J) Order Number TP3076J NS Package Number J20A LIFE SUPPORT POLICY NATIONAL’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF NATIONAL SEMICONDUCTOR CORPORATION. As used herein: 2. A critical component is any component of a life support 1. Life support devices or systems are devices or sysdevice or system whose failure to perform can be reatems which, (a) are intended for surgical implant into sonably expected to cause the failure of the life support the body, or (b) support or sustain life, and whose faildevice or system, or to affect its safety or effectiveness. ure to perform when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury to the user. National Semiconductor Corporation Americas Tel: 1-800-272-9959 Fax: 1-800-737-7018 Email: [email protected] www.national.com National Semiconductor Europe Fax: +49 (0) 1 80-530 85 86 Email: [email protected] Deutsch Tel: +49 (0) 1 80-530 85 85 English Tel: +49 (0) 1 80-532 78 32 Français Tel: +49 (0) 1 80-532 93 58 Italiano Tel: +49 (0) 1 80-534 16 80 National Semiconductor Asia Pacific Customer Response Group Tel: 65-2544466 Fax: 65-2504466 Email: [email protected] National Semiconductor Japan Ltd. Tel: 81-3-5639-7560 Fax: 81-3-5639-7507 National does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and National reserves the right at any time without notice to change said circuitry and specifications.