LM3207 650mA Miniature, Adjustable, Step-Down DC-DC Converter for RF Power Amplifiers with Integrated Vref LDO General Description Features The LM3207 is a DC-DC converter optimized for powering WCDMA / CDMA RF power amplifiers (PAs) from a single Lithium-Ion cell; however they may be used in many other applications. It steps down an input voltage from 2.7V to 5.5V to a variable output voltage from 0.8V(typ.) to 3.6V(typ.). Output voltage is set using a VCON analog input for controlling power levels and efficiency of the RF PA. The LM3207 also provides a regulated reference voltage (Vref) required by linear RF power amplifiers through an integrated LDO that has a maximum Iref up to 10 mA. See Ordering Information table on page 2 for Voltage Options. The LM3207 is available in a 9-pin lead free micro SMD package. High switching frequency (2MHz) allows use of surfacemount components. Only four small external surface-mount components are required, an inductor and three ceramic capacitors. ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ 2MHz (typ.) PWM Switching Frequency Operates from a single Li-Ion cell (2.7V to 5.5V) Variable Output Voltage (0.8V to 3.6V) 650mA Maximum load capability High Efficiency (95% Typ at 3.9VIN, 3.4VOUT at 400mA) from internal synchronous rectification Integrated Vref LDO Regulated LDO Output up to 10mA max Fast 3uS Vref LDO On/Off Time 9-pin micro SMD Package Current Overload Protection Thermal Overload Protection Applications ■ ■ ■ ■ Cellular Phones Hand-Held Radios RF PC Cards Battery Powered RF Devices Typical Application 20165301 FIGURE 1. LM3207 Typical Application © 2007 National Semiconductor Corporation 201653 www.national.com LM3207 650mA Miniature, Adjustable, Step-Down DC-DC Converter for RF Power Amplifiers April 2007 LM3207 Connection Diagrams 20165399 9–Bump Thin Micro SMD Package, Large Bump NS Package Number TLA09TTA Order Information LDO Voltage Option Order Number Part Marking (Note) Supplied As 2.875 LM3207TL XVS/34 250 units, Tape-and-Reel LM3207TLX XVS/34 3000 units, Tape-and-Reel 2.53 LM3207TL-2.53 XVS/43 250 units, Tape-and-Reel LM3207TLX-2.53 XVS/43 3000 units, Tape-and-Reel Note: The actual physical placement of the package marking will vary from part to part. The package marking “X” designates the date code. “V” is a NSC internal code for die traceability. Both will vary considerably. “S” designates the device type as switcher device. “34” identifies the device part number/option. Pin Descriptions Pin # Name A1 PVIN B1 ENLDO Description Power Supply Voltage Input. LDO Enable Input. Set this digital input high to turn on LDO (EN pin must also be set high). For shutdown, set low. C1 FB C2 VCON Voltage Control Analog input. VCON controls VOUT in PWM mode. C3 LDO LDO Output Voltage. B3 SGND Analog and Control Ground. A3 PGND Power Ground. A2 SW Switch node connection to the internal PFET switch and NFET synchronous rectifier. Connect to an inductor with a saturation current rating that exceeds the maximum Switch Peak Current Limit specification of the LM3207. B2 EN PWM enable Input. Set this digital input high for normal operation. For shutdown, set low. www.national.com Feedback Analog Input. Connect to the output at the output filter capacitor. 2 If Military/Aerospace specified devices are required, please contact the National Semiconductor Sales Office/ Distributors for availability and specifications. PVIN to SGND PGND to SGND EN, FB, VCON, ENLDO, LDO SW PVIN Continuous Power Dissipation (Note 3) Junction Temperature (TJ-MAX) Operating Ratings −0.2V to +6.0V −0.2V to +0.2V (SGND −0.2V) to (VDD +0.2V) w/6.0V max (PGND −0.2V) to (PVIN +0.2V) w/6.0V max −0.2V to +0.2V −65°C to +150°C +260°C (Notes 1, 2) Input Voltage Range Recommended Load Current Junction Temperature (TJ) Range Ambient Temperature (TA) Range (Note 4) 2.7V to 5.5V 0mA to 650mA −30°C to +125°C −30°C to +85°C Thermal Properties Junction-to-Ambient Thermal 100°C/W Resistance (θJA), TLA09 Package (Note 5) Internally Limited +150°C Electrical Characteristics (Notes 2, 6, 7) Limits in standard typeface are for TA = TJ = 25°C. Limits in boldface type apply over the full operating ambient temperature range (−30°C ≤ TA = TJ ≤ +85°C). Unless otherwise noted, all specifications apply to all LM3207 LDO options with: PVIN = VIN = ENLDO = EN = 3.6V. Symbol Parameter Conditions Min VLDO LDO Output Voltage VLDO,MIN Minimum LDO Output Voltage Iout = 10mA, PVIN = 3V -2.6 ISC Short circuit current(DC) VLDO = 0 IPUT Pull-up current (transient) VLDO = VLDO(nom)/2, PVIN = 3V (Note 12) IPD DC Pull-down current (DC) VLDO = PVIN, ENLDO = 0 IPDT Pull-down current (transient) VLDO = 1.44V, PVIN = 3V (Note 12) IQ_LDO + PWM DC Bias current into PVIN VCON = 2V, FB = 0V, No Switching, ENLDO = EN = 3.6V (Note 9) IPIN,ENLDO LDO Pin pull down current Typ Max Units +2.6 % LDO Iout = 0 mA % 50 mA 150 mA -50 mA -200 mA 1.2 1.6 mA 5 10 uA Switcher VFB, MIN Feedback Voltage at minimum VCON = 0.32V setting 0.75 0.8 0.85 V VFB, MAX Feedback Voltage at maximum VCON = 1.44V, PVIN = 4.2V setting 3.537 3.6 3.683 V ISHDN Shutdown supply current EN = ENLDO= SW = VCON = 0V, (Note 8) 0.01 2 µA IQ_PWM DC bias current into PVIN VCON = 2V, FB = 0V, ENLDO = 0V , EN = 3.6V, No Switching (Note 9) 1.1 1.6 mA RDSON(P) Pin-pin resistance for PFET ISW = 200mA RDSON(N) Pin-pin resistance for NFET 140 ISW = - 200mA 300 (Note 10) 200 230 415 485 mΩ mΩ ILIM,PFET Switch peak current limit 935 1100 1200 mA FOSC Internal oscillator frequency 1.7 2 2.3 MHz VIH,EN Logic high input threshold (PWM, LDO) 1.2 VIL,EN Logic low input threshold (PWM, LDO) IPIN,EN PWM Pin pull down current V 5 3 0.5 V 10 µA www.national.com LM3207 Storage Temperature Range Maximum Lead Temperature (Soldering, 10 sec) Absolute Maximum Ratings (Notes 1, 2) LM3207 Symbol Parameter Conditions Gain VCON to VOUT Gain 0.32V ≤ VCON ≤ 1.44V ICON VCON pin leakage current VCON = 1.0V www.national.com Min Typ Max 2.5 V/V ±1 4 Units µA The following spec table entries are guaranteed by design providing the component values in the typical application circuit are used (L = 3.0µH, (DCR = 0.12Ω, FDK MIPW3226D3R0M); CIN = 10µF, (6.3V, 0805, TDK C2012X5R0J106K); COUT = 4.7µF, (6.3V, 0603, TDK C1608X5R0J475M); CLDO = 100nF, (10V, 0402, TDK C1005X5R1A104KT) (or 220nF, (6.3V, 0402, TDK C1005X5R0J224KT))) . These parameters are not guaranteed by production testing. Min and Max values are specified over the VIN range = 2.7V to 5.5V and over the ambient temp range TA = −30°C to 85°C unless otherwise specified. Typical values are specified at PVIN = EN = 3.6V and TA = 25°C unless otherwise specified. Symbol Parameter Conditions Min Typ Max Units PSRR Power Supply Rejection Ratio Offset Freq = 1Khz, Cout = 100nF, Iout = 1mA, PVin = Vout(nom) + 0.5V 50 dB VLDO(NOISE) Output Noise Voltage BW = 10Hz to 100Khz, Iout = 1mA 30 uVrms tLDO, ON Time to reach 90% of VLDO(nom) after ENLDO signal goes high. CLDO = 100nF, PWM mode assumed to be fully functional before ENLDO goes high. LDO 3 uS 5 uS PVin = 3V, RLOAD = 562 Ω (Note 12) CLDO = 220nF, PWM mode assumed to be fully functional before ENLDO goes high. PVin = 3V, RLOAD = 562 Ω (Note 12) tLDO, OFF Time to reach 10% of VLDO(nom) after ENLDO signal goes low. CLDO = 100nF, PVin = 3V, Iout = 0mA (Note 12) 3 CLDO = 220nF, PVin = 3V, Iout = 0mA (Note 12) 5 uS Switcher TRESPONSE (Rise Time for VOUT to rise from PVIN = 4.2V, COUT = 4.7uF, L = 3.0uH, time) 0.8V to 3.6V RLOAD = 5.5Ω 20 30 µs TRESPONSE (Fall time) Time for VOUT to fall from PVIN = 4.2V, COUT = 4.7uF, L = 3.0uH, 3.6V to 0.8V RLOAD = 10Ω 20 30 µs CCON VCON input capacitance VCON = 1V, Test frequency = 100 kHz 20 pF VCON Linearity Linearity in control range 0.32V to 1.44V PVIN = 3.9V, Monotonic in nature +3 % T_ON Turn on time (time for output to reach 3.6V from Enable low to high transition) EN = Low to High, PVIN = 4.2V, VO = 3.6V, COUT = 4.7µF, 70 100 µs PVIN = 3.6V, VOUT = 0.8V, IOUT = 90mA 81 % PVIN = 3.9V, VOUT = 3.4V, IOUT = 400mA 95 % η Efficiency (L = 3.0µH, DCR ≤ 100mΩ) IOUT ≤ 1mA -3 VO_ripple Ripple voltage, PWM mode PVIN = 3V to 4.5V, VOUT = 0.8V, IOUT = 10mA to 400mA, (Note 11) 10 mVp-p Line_tr Line transient response PVIN = 600mV perturbance, TRISE = TFALL = 10µs, VOUT = 0.8V, IOUT = 100mA 50 mV PVIN = 3.1/3.6/4.5V, VOUT = 0.8V, transients up to 100mA, TRISE = TFALL = 10µs 50 mV Load_tr Load transient response Note 1: Absolute Maximum Ratings indicate limits beyond which damage to the component may occur. Operating Ratings are conditions under which operation of the device is guaranteed. Operating Ratings do not imply guaranteed performance limits. For guaranteed performance limits and associated test conditions, see the Electrical Characteristics tables. Note 2: All voltages are with respect to the potential at the GND pins. The LM3207 is designed for mobile phone applications where turn-on after power-up is controlled by the system controller and where requirements for a small package size overrule increased die size for internal Under Voltage Lock-Out (UVLO) circuitry. Thus, it should be kept in shutdown by holding the EN pin low until the input voltage exceeds 2.7V. Note 3: Internal thermal shutdown circuitry protects the device from permanent damage. Thermal shutdown engages at TJ = 150°C (typ.) and disengages at TJ = 130°C (typ.). 5 www.national.com LM3207 System Characteristics LM3207 Note 4: In applications where high power dissipation and/or poor package thermal resistance is present, the maximum ambient temperature may have to be derated. Maximum ambient temperature (TA-MAX) is dependent on the maximum operating junction temperature (TJ-MAX-OP = 125°C), the maximum power dissipation of the device in the application (PD-MAX), and the junction-to ambient thermal resistance of the part/package in the application (θJA), as given by the following equation: TA-MAX = TJ-MAX-OP – (θJA × PD-MAX). Note 5: Junction-to-ambient thermal resistance (θJA) is taken from thermal measurements, performed under the conditions and guidelines set forth in the JEDEC standard JESD51-7. Note 6: Min and Max limits are guaranteed by design, test, or statistical analysis. Typical numbers are not guaranteed, but do represent the most likely norm. Due to the pulsed nature of the testing TA = TJ for the electrical characteristics table. Note 7: The parameters in the electrical characteristics table are tested under open loop conditions at PVIN = 3.6V. For performance over the input voltage range and closed loop results refer to the datasheet curves. Note 8: Shutdown current includes leakage current of PFET. Note 9: IQ specified here is when the part is operating at 100% duty cycle. Note 10: Current limit is built-in, fixed, and not adjustable. Refer to datasheet curves for closed loop data and its variation with regards to supply voltage and temperature. Electrical Characteristic table reflects open loop data (FB = 0V and current drawn from SW pin ramped up until cycle by cycle limit is activated). Closed loop current limit is the peak inductor current measured in the application circuit by increasing output current until output voltage drops by 10%. Note 11: Ripple voltage should measured at COUT electrode on good layout PC board and under condition using suggested inductors and capacitors. Note 12: Transient Pull-up current (IPUT) and Transient Pull-down Current (IPDT) will be tested which are inversely proportional to charge and discharge times tLDO, ON and tLDO, OFF respectively. Note 13: Dropout voltage is the voltage difference between the input and the output at which the output voltage drops to 100 mV below its nominal value. Typical Performance Characteristics (Circuit in Figure 3, See Operation Description Section), PVIN = EN = 3.6V, L = 3.0µH, (DCR = 0.12Ω, FDK MIPW3226D3R0M); CIN = 10µF, (6.3V, 0805, TDK C2012X5R0J106K); COUT = 4.7µF, (6.3V, 0603, TDK C1608X5R0J475M), CLDO = 100nF, 10V, (0402, TDK C1005X5R1A104KT) (or 220nF, (6.3V, 0402, TDK C1005X5R0J224KT)) can be used. TA = 25°C unless otherwise specified. LDO Typical Performance Curves (2.875 Option) LDO Voltage vs Load Current (CLDO = 100nF) LDO Dropout Voltage vs Load Current (CLDO = 100nF), (Note 13) 20165378 www.national.com 20165330 6 LM3207 LDO Short Circuit Current vs Voltage (VIN = 3.0V, CLDO = 100nF) LDO Output Noise Density (ILOAD = 1mA, CLDO = 100nF and 220nF) 20165360 20165380 LDO Power Supply Rejection Ratio (VIN = Vout(nom) + 0.5V, CLDO = 100nF) LDO Turn On Time vs VIN (CLDO = 100nF) 20165381 20165363 LDO Turn Off Time vs VIN (CLDO = 100nF) LDO Line Transient Response (VIN = 3.0V to 3.6V, ILOAD = 10mA, CLDO = 100nF) 20165365 20165364 7 www.national.com LM3207 LDO Load Transient Repsonse (VIN= 3.2V, VOUT = 0.8V, CLDO = 100nF) LDO VLDO Out vs Temperature (VIN = 3.6V,CLDO = 100nF) 20165376 20165377 www.national.com 8 LDO Voltage vs Load Current (CLDO = 100nF) LDO Dropout Voltage vs Load Current (CLDO = 100nF), (Note 13) 20165382 20165358 LDO Short Circuit Current vs Voltage (VIN = 3.0V, CLDO = 100nF) LDO Power Supply Rejection Ratio (VIN = Vout(nom) + 0.5V, CLDO = 100nF) 20165383 20165384 LDO Turn On Time vs VIN (CLDO = 100nF) LDO Turn Off Time vs VIN (CLDO = 100nF) 20165398 20165385 9 www.national.com LM3207 LDO Typical Performance Curves (2.53 Option) LM3207 LDO VLDO Out vs Temperature (VIN = 3.6V,CLDO = 100nF) 20165359 www.national.com 10 Quiescent Current vs Supply Voltage (VCON = 2V, FB = 0V, No Switching, LDO Disabled) Quiescent Current vs Supply Voltage (VCON = 2V, FB = 0V, No Switching, LDO Enabled) 20165315 20165379 Shutdown Current vs Temperature (VCON = 0V, EN = 0V) Switching Frequency vs Temperature (VOUT = 1.3V, IOUT = 200mA) 20165302 20165303 Output Voltage Regulation(%) vs Output Load (VOUT = 1.5V) Output Voltage vs Temperature (VIN = 3.6V, VOUT = 0.8V) 20165316 20165317 11 www.national.com LM3207 SWITCHER Typical Performance Curves LM3207 Output Voltage vs Temperature (VIN = 3.6V, VOUT = 3.4V) Open/Closed Loop Current Limit vs Temperature (PWM Mode) 20165319 20165318 VCON Voltage vs Output Voltage (VIN = 4.2V, RLOAD = 8Ω) Efficiency vs Output Voltage (VIN = 3.9V) 20165305 20165304 Efficiency vs Output Current (VOUT = 0.8V) Efficiency vs Output Current (VOUT = 3.4V) 20165320 www.national.com 20165321 12 LM3207 Load Transient Response (VOUT = 0.8V) Load Transient Response (VIN = 4.2V, VOUT = 3.4V) 20165322 20165323 Startup (VIN = 4.2V, VOUT = 3.4V, RLOAD = 5kΩ) Startup (VIN = 3.6V, VOUT = 1.3V, RLOAD = 1kΩ) 20165325 20165324 Shutdown Response (VIN = 4.2V, VOUT = 3.4V, RLOAD = 10Ω) Line Transient Reponse (VIN = 3.0V to 3.6V, IOUT = 100mA) 20165326 20165307 13 www.national.com LM3207 VCON Voltage Response (VIN = 4.2V, VCON = 0.32V/1.44V, RLOAD = 10Ω) VCON and Load Transient (VIN = 4.2V, VCON = 0.32V/1.44V, RLOAD = 15Ω/8Ω) 20165308 20165309 Timed Current Limit Response (VIN = 3.6V) Output Voltage Ripple (VOUT = 1.3V) 20165310 20165327 Output Voltage Ripple (VOUT = 3.4V) Output Voltage Ripple in Pulse Skip (VIN = 3.64V, VOUT = 3.4V, RLOAD = 5Ω) 20165328 www.national.com 20165329 14 LM3207 RDSON vs Temperature (microSMD) (P-ch, ISW = 200mA) RDSON vs Temperature (microSMD) (N-ch, ISW = -200mA) 20165311 20165312 EN High Threshold vs VIN 20165313 15 www.national.com LM3207 Block Diagram 20165335 FIGURE 2. Functional Block Diagram www.national.com 16 The LM3207 is a simple, step-down DC-DC converter with a VREF LDO optimized for powering RF power amplifiers (PAs) in mobile phones, portable communicators, and similar battery powered RF devices. The DC-DC converter is designed to allow the RF PA to operate at maximum efficiency over a wide range of power levels from a single Lithium-Ion battery cell. The DC-DC is based on current-mode buck architecture, with synchronous rectification for high efficiency. It is designed for a maximum load capability of 650mA in PWM mode. Maximum load range may vary from this depending on input voltage, output voltage and the inductor chosen. The device has two pin-selectable operating modes required for powering RF PAs in mobile phones and other sophisticated portable devices. Fixed-frequency PWM operation offers regulated output at high efficiency while minimizing interference with sensitive IF and data acquisition circuits. Shutdown mode turns the device off and reduces battery consumption to 0.01uA (typ). Efficiency is typically around 95% for a 400mA load with 3.9VIN, 3.4VOUT. The output voltage is dynamically programmable from 0.8V (typ) to 3.6V (typ) by adjusting the 20165336 FIGURE 3. Typical Application Circuit when the inductor current is high, and releases it when low, smoothing the voltage across the load. The output voltage is regulated by modulating the PFET switch on time to control the average current sent to the load. The effect is identical to sending a duty-cycle modulated rectangular wave formed by the switch and synchronous rectifier at SW to a low-pass filter formed by the inductor and output filter capacitor. The output voltage is equal to the average voltage at the SW pin. Circuit Operation (DC-DC Converter) Referring to Figure 1 and Figure 2, the LM3207 operates as follows. During the first part of each switching cycle, the control block in the LM3207 turns on the internal PFET (Pchannel MOSFET) switch. This allows current to flow from the input through the inductor to the output filter capacitor and load. The inductor limits the current to a ramp with a slope of around (PVIN - VOUT) / L, by storing energy in a magnetic field. During the second part of each cycle, the controller turns the PFET switch off, blocking current flow from the input, and then turns the NFET (N-channel MOSFET) synchronous rectifier on. In response, the inductor’s magnetic field collapses, generating a voltage that forces current from ground through the synchronous rectifier to the output filter capacitor and load. As the stored energy is transferred back into the circuit and depleted, the inductor current ramps down with a slope around VOUT / L. The output filter capacitor stores charge PWM Operation While in PWM (Pulse Width Modulation) mode, the output voltage is regulated by switching at a constant frequency and then modulating the energy per cycle to control power to the load. Energy per cycle is set by modulating the PFET switch on-time pulse width to control the peak inductor current. This is done by comparing the signal from the current-sense amplifier with a slope compensated error signal from the voltagefeedback error amplifier. At the beginning of each cycle, the clock turns on the PFET switch, causing the inductor current 17 www.national.com LM3207 voltage on the control pin without the need for external feedback resistors. This ensures longer battery life by being able to change the PA supply voltage dynamically depending on its transmitting power. Additional features include current overload protection, and thermal overload shutdown. The LM3207 is constructed using a chip-scale 9-pin micro SMD package. This package offers the smallest possible size, for space-critical applications such as cell phones, where board area is an important design consideration. Use of a high switching frequency (2MHz) reduces the size of external components. As shown in Figure 1, only four external power components are required for implementation. Use of a micro SMD package requires special design considerations for implementation. (See Micro SMD Package Assembly and use in the Applications Information section.) The fine bumppitch requires careful board design and precision assembly equipment. Use of this package is best suited for opaquecase applications, where its edges are not subject to highintensity ambient red or infrared light. Also, the system controller should set EN low during power-up and other low supply voltage conditions. (See Shutdown Mode in the Device Information section.) Operation Description LM3207 to ramp up. When the current sense signal ramps past the error amplifier signal, the PWM comparator turns off the PFET switch and turns on the NFET synchronous rectifier, ending the first part of the cycle. If an increase in load pulls the output down, the error amplifier output increases, which allows the inductor current to ramp higher before the comparator turns off the PFET. This increases the average current sent to the output and adjusts for the increase in the load. Before appearing at the PWM comparator, a slope compensation ramp from the oscillator is subtracted from the error signal for stability of the current feedback loop. The minimum on time of PFET in PWM mode is 50ns (typ.) handset is far away from the base station or when data is being transmitted. In other instances the transmitting power can be reduced. Hence the supply voltage to the PA can be reduced, promoting longer battery life. See Setting the Output Voltage in the Application Information section for further details. Thermal Overload Protection The LM3207 has a thermal overload protection function that operates to protect itself from short-term misuse and overload conditions. When the junction temperature exceeds 150°C, the device inhibits operation. The PFET and NFET are turned off in PWM mode. The LDO is turned off as well. When the temperature drops below 130°C, normal operation resumes. Prolonged operation in thermal overload conditions may damage the device and is considered bad practice. Shutdown Mode Setting the EN digital pin low (<0.5V) places the LM3207 in a 0.01µA (typ.) Shutdown mode. During shutdown, the PFET switch, NFET synchronous rectifier, reference voltage source, control and bias circuitry of theLM3207 are turned off. Setting EN high (>1.2V) enables normal operation. EN should be set low to turn off the LM3207 during power-up and under voltage conditions when the power supply is less than the 2.7V minimum operating voltage. The LM3207 is designed for compact portable applications, such as mobile phones. In such applications, the system controller determines power supply sequencing and requirements for small package size outweigh the additional size required for inclusion of UVLO (Under Voltage Lock-Out) circuitry. LDO Operation An LDO is used to provide a regulated Vref supply to a RF PA with a fixed voltage. The LDO can be enabled only after the PWM is running. The LDO will automatically be disabled whenever the EN or ENLDO is disabled. Included in the LDO are active charge and discharge circuits to quickly move a 100nF capacitor to meet the 3us timing requirements, or an 220nF capacitor to meet the 5us timing requirements. The charging and discharging currents are controlled to minimize supply disturbances. The LM3207 was designed specifically to work with a 100nF or a 220nF ceramic capacitor and no bypass capacitor. See Ordering Information table on page 2 for Voltage Options. Internal Synchronous Rectification While in PWM mode, the LM3207 uses an internal NFET as a synchronous rectifier to reduce rectifier forward voltage drop and associated power loss. Synchronous rectification provides a significant improvement in efficiency whenever the output voltage is relatively low compared to the voltage drop across and ordinary rectifier diode. The internal NFET synchronous rectifier is turned on during the inductor current down slope in the second part of each cycle. The synchronous rectifier is turned off prior to the next cycle. The NFET is designed to conduct through its intrinsic body diode during transient intervals before it turns on, eliminating the need for an external diode. Application Information SETTING THE DC-DC CONVERTER OUTPUT VOLTAGE The LM3207 features a pin-controlled variable output voltage to eliminate the need for external feedback resistors. It can be programmed for an output voltage from 0.8V (typ.) to 3.6V (typ.) by setting the voltage on the VCON pin, as in the following formula: VOUT = 2.5 x VCON When VCON is between 0.32V and 1.44V, the output voltage will follow proportionally by 2.5 times of VCON. If VCON is over 1.44V (VOUT = 3.6V), sub-harmonic oscillation may occur because of insufficient slope compensation. If VCON voltage is less than 0.32V (VOUT = 0.8V), the output voltage may not be regulated due to the required on-time being less than the minimum on-time (50ns). The output voltage can go lower than 0.8V providing a limited VIN range is used. Refer to datasheet curve (VCON Voltage vs Output Voltage) for details. This curve is for a typical part and there could have part-to-part variation for output voltages less than 0.8V over the limited VIN range. Current Limiting A current limit feature allows the LM3207 to protect itself and external components during overload conditions. In PWM mode, a 1200mA (max.) cycle-by-cycle current limit is normally used. If an excessive load pulls the output voltage down to approximately 0.375V, then the device switches to a timed current limit mode. In timed current limit mode the internal PFET switch is turned off after the current comparator trips and the beginning of the next cycle is inhibited for 3.5us to force the instantaneous inductor current to ramp down to a safe value. The synchronous rectifier is off in timed current limit mode. Timed current limit prevents the loss of current control evident in some products when the output voltage is pulled low in serious overload conditions. LDO CAPACITOR SELECTION The output capacitor should be connected between the LDO output and a good ground connection. This capacitor must be selected within specified capacitance range and have sufficiently low ESR. The ESR of the capacitor is generally a major factor in LDO stability. Refer to manufacturer ESR curves for more detail. Table 1 suggests acceptable capacitors and their suppliers. Dynamically Adjustable Output Voltage The LM3207 features dynamically adjustable output voltage to eliminate the need for external feedback resistors. The output can be set from 0.8V(typ.) to 3.6V(typ.) by changing the voltage on the analog VCON pin. This feature is useful in PA applications where peak power is needed only when the www.national.com 18 Model Vendor C1005X5R1A104KT, 100nF, 10V C1005X5R0J224KT, 220nF, 6.3V TABLE 3. Suggested capacitors and their suppliers Model Vendor TDK 0805ZD475KA, 4.7µF, 10V Taiyo-Yuden TDK C1608X5R0J475M, 4.7uF, 6.3V TDK C1608X5R0J106M, 10µF, 6.3V TDK C2012X5R0J106M, 10uF, 6.3V TDK C2012X5R1A475M, 4.7uF, 6.3V TDK INDUCTOR SELECTION A 3.3µH inductor with saturation current rating over 1200mA and low inductance drop at the full DC bias condition is recommended for almost all applications. The inductor’s DC resistance should be less than 0.2Ω for good efficiency. For low dropout voltage, lower DCR inductors are advantageous. The lower limit of acceptable inductance is 1.7µH at 1200mA over the operating temperature range. Full attention should be paid to this limit, because some small inductors show large inductance drops at high DC bias. These can not be used with the LM3207. Table 2 suggests some inductors and suppliers. The input filter capacitor supplies AC current drawn by the PFET switch of the LM3207 in the first part of each cycle and reduces the voltage ripple imposed on the input power source. The output filter capacitor absorbs the AC inductor current, helps maintain a steady output voltage during transient load changes and reduces output voltage ripple. These capacitors must be selected with sufficient capacitance and sufficiently low ESR (Equivalent Series Resistance) to perform these functions. The ESR of the filter capacitors is generally a factor in voltage ripple. TABLE 2. Suggested inductors and their suppliers Model Size (WxLxH) [mm] Vendor NR3015T3R3M 3.0 x 3.0 x 1.5 Taiyo-Yuden DO3314-332MXC 3.3 x 3.3 x 1.4 Coilcraft MIPW3226D3R0M 3.2 x 2.6 x 1.0 FDK EN PIN CONTROL Drive the EN and ENLDO pins using the system controller to turn the LM3207 ON and OFF. Use a comparator, Schmidt trigger or logic gate to drive the EN and ENLDO pins. Set EN high (>1.2V) for normal operation and low (<0.5V) for a 0.01µA (typ.) shutdown mode. Set EN low to turn off the LM3207 during power-up and under voltage conditions when the power supply is less than the 2.7V minimum operating voltage. The part is out of regulation when the input voltage is less than 2.7V. The LM3207 is designed for mobile phones where the system controller controls operation mode for maximizing battery life and requirements for small package size outweigh the additional size required for inclusion of UVLO (Under Voltage Lock-Out) circuitry. If a smaller inductance inductor is used in the application, the LM3207 may become unstable during line and load transients and VCON transient response times may be affected. For lowcost applications, an unshielded bobbin inductor is suggested. For noise critical applications, a toroidal or shieldedbobbin inductor is recommended. A good practice is to layout the board with footprints accommodating both types for design flexibility. This allows substitution of a low-noise toroidal inductor, in the event that noise from low-cost bobbin models is unacceptable. Saturation occurs when the magnetic flux density from current through the windings of the inductor exceeds what the inductor’s core material can support with a corresponding magnetic field. This can result in poor efficiency, regulation errors or stress to DC-DC converter like the LM3207. Micro SMD PACKAGE ASSEMBLY AND USE Use of the Micro SMD package requires specialized board layout, precision mounting and careful re-flow techniques, as detailed in National Semiconductor Application Note 1112. Refer to the section Surface Mount Technology (SMD) Assembly Considerations. For best results in assembly, alignment ordinals on the PC board should be used to facilitate placement of the device. The pad style used with Micro SMD package must be the NSMD (non-solder mask defined) type. This means that the solder-mask opening is larger than the pad size. This prevents a lip that otherwise forms if the soldermask and pad overlap, from holding the device off the surface of the board and interfering with mounting. See Application Note 1112 for specific instructions. The 9-Bump package used for LM3207 has 300 micron solder balls and requires 10.82mil pads for mounting the circuit board. The trace to each pad should enter with a 90° entry angle to prevent debris from being caught in deep corners. Initially, the trace to each pad should be 6-7mil wide, for a section approximately 6mil long or longer, to provide thermal relief. Each trace should then neck up or down to its optimal width. The important criterion is symmetry. This ensures the solder bumps re-flow evenly and that the device solders level to the board. In particular, special attention must be paid to the pads for bumps A1, A3 and B3. Because PGND and PVIN are typically connected to large copper planes, inadequate thermal relief’s may result in late or inadequate re-flow of these bumps. The Micro SMD package is optimized for the smallest possible size in applications with red or infrared opaque cases. Because the Micro SMD package lacks the DC-DC CONVERTER CAPACITOR SELECTION The LM3207 is designed with a ceramic capacitor for its input and output filters. Use a 10µF ceramic capacitor for input and a 4.7µF ceramic capacitor for output. They should maintain at least 50% capacitance at DC bias and temperature conditions. Ceramic capacitors types such as X5R, X7R are recommended for both filters. These provide an optimal balance between small size, cost, reliability and performance for cell phones and similar applications. Table 3 lists suggests acceptable part numbers and their suppliers. DC bias characteristics of the capacitors must be considered when selecting the voltage rating and case size of the capacitor. If it is necessary to choose a 0603-size capacitor for VIN, the operation of the LM3207should be carefully evaluated on the system board. Output capacitors with smaller case sizes mitigate piezo electric vibrations when the output voltage is stepped up and down at fast rates. However, they have a larger percentage drop in value with dc bias. Use of multiple 2.2µF or 1µF capacitors in parallel may also be considered. 19 www.national.com LM3207 TABLE 1. Suggested capacitors and their suppliers LM3207 plastic encapsulation characteristic of larger devices, it is vulnerable to light. Backside metalization and/or epoxy coating, along with front-side shading by the printed circuit board, reduce this sensitivity. However, the package has exposed die edges. Micro SMD devices are sensitive to light, in the red and infrared range, shining on the package’s exposed die edges. BOARD LAYOUT CONSIDERATIONS 20165354 FIGURE 4. Current Loop Referring to Figure 4, the LM3207 has two major current loops where pulse and ripple current flow. The loop shown in the left hand side is most important, because pulse current shown in Figure 4 flows in this path. The right hand side is next. The current waveform in this path is triangular, as shown in Figure 4. Pulse current has many high-frequency components due to fast di/dt. Triangular ripple current also has wide high-fre- www.national.com quency components. Board layout and circuit pattern design of these two loops are the key factors for reducing noise radiation and stable operation. Other lines, such as from battery to C1(+) and C2(+) to load, are almost DC current, so it is not necessary to take so much care. Only pattern width (current capability) and DCR drop considerations are needed. 20 LM3207 20165357 FIGURE 5. Evaluation Board Layout BOARD LAYOUT FLOW 1. Minimize C1, PVIN, and PGND loop. These traces should be as wide and short as possible. This is most important. 2. Minimize L1, C2, SW and PGND loop. These traces also should be wide and short. This is the second priority. 3. Above layout patterns should be placed on the component side of the PCB to minimize parasitic inductance and resistance due to via-holes. It may be a good idea that the SW to L1 path is routed between C2 (+) and C2(-) land patterns. If vias are used in these large current paths, multiple via-holes should be used if possible. 4. Connect C1(-), C2(-) and PGND with wide GND pattern. This pattern should be short, so C1(-), C2(-), and PGND should be as close as possible. Then connect to a PCB 5. 6. 7. common GND pattern with as many via-holes as possible. SGND should not connect directly to PGND. Connecting these pins under the device should be avoided. (If possible, connect SGND to the common port of C1(-), C2 (-) and PGND.) FB line should be protected from noise. It is a good idea to use an inner GND layer (if available) as a shield. The LDO Cap C7 (CLDO) should be placed as close to the PA as possible and as far away from the switcher to suppress high frequency switch noises. Note: The evaluation board shown in Figure 5 for the LM3207 was designed with these considerations, and it shows good performance. However some aspects have not been optimized because of limitations due to evaluation-specific requirements. Please refer questions to a National representative. 21 www.national.com LM3207 Physical Dimensions inches (millimeters) unless otherwise noted 9-Bump Thin Micro SMD, Large Bump X1 = 1.946mm ± 0.030mm X2 = 1.946mm ±0.030mm X3 = 0.600mm ±0.075mm www.national.com 22 LM3207 Notes 23 www.national.com LM3207 650mA Miniature, Adjustable, Step-Down DC-DC Converter for RF Power Amplifiers Notes THE CONTENTS OF THIS DOCUMENT ARE PROVIDED IN CONNECTION WITH NATIONAL SEMICONDUCTOR CORPORATION (“NATIONAL”) PRODUCTS. NATIONAL MAKES NO REPRESENTATIONS OR WARRANTIES WITH RESPECT TO THE ACCURACY OR COMPLETENESS OF THE CONTENTS OF THIS PUBLICATION AND RESERVES THE RIGHT TO MAKE CHANGES TO SPECIFICATIONS AND PRODUCT DESCRIPTIONS AT ANY TIME WITHOUT NOTICE. NO LICENSE, WHETHER EXPRESS, IMPLIED, ARISING BY ESTOPPEL OR OTHERWISE, TO ANY INTELLECTUAL PROPERTY RIGHTS IS GRANTED BY THIS DOCUMENT. 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