WINBOND W83877

W83877F
WINBOND I/O
GENERAL DESCRIPTION
One of Winbond's popular series of I/O chips, the W83877F integrates a disk drive adapter, serial
port (UART), parallel port, IDE bus interface, and game port decoder onto a single chip. The
W83877F is an enhanced version of the W83777F, with additional powerful features such as
configurable plug-and-play registers for the whole chip and infrared support in one of the serial ports.
The disk drive adapter functions of the W83877F include a floppy disk drive controller compatible
with the industry standard 82077/765, data separator, write pre-compensation circuit, decode logic,
data rate selection, clock generator, drive interface control logic, and interrupt and DMA logic. The
wide range of functions integrated onto the W83877F greatly reduces the number of components
required for interfacing with floppy disk drives. The W83877F supports four 360K, 720K, 1.2M, 1.44M,
or 2.88M disk drives and data transfer rates of 250 Kb/S, 300 Kb/S, 500 Kb/S, and 1 Mb/S.
The W83877F provides two high-speed serial communication ports (UARTs), one of which supports
serial Infrared communication. Each UART includes a 16-byte send/receive FIFO, a programmable
baud rate generator, complete modem control capability, and a processor interrupt system.
The W83877F supports one PC-compatible printer port. Additional bidirectional I/O capability is
available by hardware control or software programming. The parallel port also supports the Enhanced
Parallel Port (EPP) and Extended Capabilities Port (ECP).
The W83877F supports two embedded hard disk drive (AT bus) interfaces and a game port with
decoded read/write output. The chip's Extension FDD Mode and Extension 2FDD Mode allow one or
two external floppy disk drives to be connected to the computer through the printer interface pins in
notebook computer applications.
The Extension Adapter Mode of the W83877F allows pocket devices to be installed through the
printer interface pins in notebook computer applications according to a protocol set by Winbond, but
with upgraded performance. The JOYSTICK mode allows a joystick to be connected to a parallel port
with a signal switching cable.
The configuration registers support mode selection, function enable/disable, and power down function
selection. Moreover, the configurable PnP registers are compatible with the plug-and-play feature in
Windows 95TM , which makes system resource allocation more efficient than ever.
-1-
Publication Release Date: January 1996
Revision A2
W83877F
FEATURES
FDC:
•
Compatible with IBM PC AT disk drive systems
•
Variable write pre-compensation with track selectable capability
•
DMA enable logic
•
Non-burst mode DMA option
•
Supports floppy disk drives and tape drives
•
Detects all overrun and underrun conditions
•
Data rate and drive control registers
•
Built-in address mark detection circuit to simplify the read electronics
•
IBM PC system address decoder
•
Supports up to two embedded hard disk drives (IDE AT BUS)
•
Single 24 MHz crystal input
•
FDD anti-virus functions with software write protect and FDD write enable signal, write data signal
force inactive
•
Supports up to four 3.5-inch or 5.25-inch floppy disk drives
•
Completely compatible with industry standard 82077
•
360K/720K/1.2M/1.44M/2.88M format
•
250K, 300K, 500K, 1M bps data transfer rate
•
Supports vertical recording format
•
16-byte data FIFOs
UART:
•
Two high-speed 16550 compatible UARTs with 16-byte send/receive FIFOs
•
MIDI compatible
•
Fully programmable serial-interface characteristics:
− 5, 6, 7 or 8-bit characters
− Even, odd or no parity bit generation/detection
− 1, 1.5 or 2 stop bits generation
•
Internal diagnostic capabilities:
− Loop-back controls for communications link fault isolation
− Break, parity, overrun, framing error simulation
•
Programmable baud generator allows division of 1.8461 MHz and 24 MHz by 1 to (216-1)
Parallel Port:
-2-
W83877F
•
Compatible with IBM parallel port
•
Supports parallel port with bidirectional lines
•
Supports Enhanced Parallel Port (EPP)
− Compatible with IEEE 1284 specification
•
Supports Extended Capabilities Port (ECP)
− Compatible with IEEE 1284 specification
•
Extension FDD mode supports disk drive B through parallel port
•
Extension Adapter Mode supports pocket devices through parallel port
•
Extension 2FDD mode supports disk drives A and B through parallel port
•
JOYSTICK mode supports joystick through parallel port
Others:
•
Programmable configuration settings
•
Immediate or automatic power-down mode for power management
•
All hardware power-on settings have internal pull-up or pull-down resistors as default value
•
Packaged in 100-pin QFP
•
Configurable Plug and Play registers
•
Infrared communication port
-3-
Publication Release Date: January 1996
Revision A2
W83877F
PIN CONFIGURATION
/
D
/
S
T
K
/ / R
M M A N C A
O
W
H 1
O
K
B A 0 P G 0
X
X
X
X
X
/
R
D
/ /
A
V
G I I A
T D D D D D D D D N O O E A A A A A D A A A A A
A 7 6 5 4 3 2 1 0 D W R N 9 8 7 6 5 D 4 3 2 1 0
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51
INDEX
STEP
DSA
DSB
WE
WD
RWC
HEAD
DIR
GND
IDBEN
IRQ_B
IRQIN
CS0
CS1
IRQ_A
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
TC
X
DACK_B
IRQ_F
DRQ_B
X
X
X
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30
X
X
/ /
R C
E S
S
I
D
E
X
X
P
D
C
I
N
D
R
Q
|
C
X
X
X
X
X
X
X
X
X
X
X
X
X
X
I M X X P P P P P P V P P /
O R T T D D D D D D D D D D
A A 0 1 2 3 4 5 D 6 7 A
C
C
L L
H
K
1 2
R
|
D
C
Y
-4-
X
X
X
X
X
/
S
T
B
/
A
F
D
/
I
N
I
T
/
S
L
I
N
I
R
Q
|
E
X
X
X
X
X
X
X
B G / P S / S
U N A E L E I
C R N
S D C
K
T R A
Y
X
X
X
X
RIB
DCDB
DSRB
CTSB
X
DTRB
X
RTSB
IRQ_C
SOUTB
SINB
X
X
X
X
X
X
X
X
X
X
X
X
GMRD
GND
GMWR
SOUTA
IRQ_D
RTSA
DTRA
CTSA
DSRA
X
DCDA
X
RIA
W83877F
1.0 PIN DESCRIPTION
Note: Refer to section 9.2 DC CHARACTERISTICS for details.
I/O8t - TTL level bidirectional pin with 8 mA source-sink capability
I/O12t - TTL level bidirectional pin with 12 mA source-sink capability
I/O24t - TTL level bidirectional pin with 24 mA source-sink capability
OUT8t - TTL level output pin with 8 mA source-sink capability
OUT12t
- TTL level output pin with 12 mA source-sink capability
OD12 - Open-drain output pin with 12 mA sink capability
OD24 - Open-drain output pin with 24 mA sink capability
INt
- TTL level input pin
INc
- CMOS level input pin
INcs - CMOS level schmitt-triggered input pin
1.1 Host Interface
SYMBOL
PIN
I/O
FUNCTION
D0−D7
66-73
I/O24t
A0−A9
51-55
INc
System address bus bits 0-9
In ECP Mode, this pin is the A10 address input.
System data bus bits 0-7
57-61
A10
75
INc
IOCHRDY
5
OD24
In EPP Mode, this pin is the IO Channel Ready output to extend
the host read/write cycle.
MR
6
INcs
Master Reset. Active high. MR is low during normal operations.
CS
2
INt
Active low chip select signal
AEN
62
INc
System address bus enable
IOR
63
INcs
CPU I/O read signal
IOW
64
INcs
CPU I/O write signal
DRQ_B
100
OUT12t
DACK_B
98
INc
DRQ_C
4
OUT12t
DACK_ C
18
INc
DMA Acknowledge signal C
TC
97
INc
Terminal Count. When active, this pin indicates termination of a
DMA transfer.
IRQIN
93
INc
Interrupt request input
DMA request signal B
DMA Acknowledge signal B
DMA request signal C
-5-
Publication Release Date: January 1996
Revision A2
W83877F
1.1 Host Interface, continued
SYMBOL
IRQ_ A /
PIN
I/O
96
OUT12t
I/O12t
GIO1
IRQ_ B /
92
OUT12t
I/O12t
GIO0
FUNCTION
When CR16 Bit 4 (GOIQSEL) = 0: Interrupt request signal A;
When CR16 Bit 4 (GOIQSEL) = 1: General Purpose I/O port 1.
When CR16 Bit 4 (GOIQSEL) = 0: Interrupt request signal B;
When CR16 Bit 4 (GOIQSEL) = 1: General Purpose I/O port 0.
IRQ_C
44
OUT12t
Interrupt request signal C
IRQ_D
37
OUT12t
Interrupt request signal D
IRQ_E
23
OUT12t
Interrupt request signal E
IRQ_F
99
OUT12t
Interrupt request signal F
XTAL1
7
INc
XTAL oscillator input
XTAL2
8
OUT8t
XTAL oscillator output
1.2 Serial Port Interface
SYMBOL
PIN
I/O
CTSA
34
INt
CTSB
47
DSRA
33
DSRB
48
DCDA
32
DCDB
49
RIA
31
RIB
50
SINA
SINB/IRRX1
30
SOUTA/
38
PIRIDE
FUNCTION
Clear To Send is the modem control input.
The function of these pins can be tested by reading Bit 4 of the
handshake status register.
INt
Data Set Ready. An active low indicates the modem or data set
is ready to establish a communication link and transfer data to
the UART.
INt
Data Carrier Detect. An active low indicates the modem or data
set has detected a data carrier.
INt
Ring Indicator. An active low indicates that a ring signal is being
received by the modem or data set.
INt
Serial Input. Used to receive serial data from the communication
link.
42
I/O8t
UART A Serial Output. Used to transmit serial data out to the
communication link.
During power-on reset, this pin is pulled up internally and is
defined as PIRIDE, which provides the power-on value for CR16
bit 1 (IRIDE). A 47 kΩ is recommended when intends to pull
down at power-on reset.
-6-
W83877F
1.2 Serial Port Interface, continued
SYMBOL
SOUTB/
PIN
I/O
43
I/O8t
IRTX1/
UART B Serial Output. Used to transmit serial data out to the
communication link.
During power-on reset, this pin is pulled up internally and is
defined as PGMDRQ, which provides the power-on value for
CR16 bit 3 (GMDRQ). A 47 kΩ is recommended when intends
to pull down at power-on reset.
PGMDRQ
DTRA
FUNCTION
35
I/O8t
PHEFRAS
UART A Data Terminal Ready. An active low informs the
modem or data set that the controller is ready to communicate.
During power-on reset, this pin is pulled down internally and is
defined as PHEFRAS, which provides the power-on value for
CR16 bit 0 (HEFRAS). A 47 kΩ is recommended when intends
to pull up at power-on reset.
DTRB
46
O8t
UART B Data Terminal Ready. An active low informs the
modem or data set that controller is ready to communicate.
RTSA
36
I/O8t
UART A Request To Send. An active low informs the modem or
data set that the controller is ready to send data.
PPNPCVS
During power-on reset, this pin is pulled up internally and is
defined as PPNPCVS, which provides the power-on value for
CR16 bit 2 (PNPCVS). A 47 kΩ is recommended when intends
to pull down at power-on reset.
RTSB
PGOIQSEL
45
I/O8t
UART B Request To Send. An active low informs the modem or
data set that the controller is ready to send data.
During power-on reset, this pin is pulled down internally and is
defined as PGOIQSEL, which provides the power-on value for
CR16 bit 4 (GOIQSEL). A 47 kΩ is recommended when intends
to pull up at power-on reset.
-7-
Publication Release Date: January 1996
Revision A2
W83877F
1.3 Game Port/Power Down Interface
If Bit 3 of CR16 (GMDRQ) is 1, Bit 4 of CR3 (GMODS0) determines whether the game port is in
Adapter mode or Portable mode (default is Adapter mode). If Bit 3 of CR16 is 0, pin 39 and 41 are
used for DMA A operation.
SYMBOL
GMRD
PIN
I/O
41
OUT8t
When CR16 Bit 3 (GMDRQ) = 1:
OUT8t
Adapter mode: Game port read control signal.
OUT8t
Portable mode: When parallel port is selected as Extension
FDD/Extension 2FDD mode, this pin will be active. The active
state is dependent on bit 7 of CRA (PFDCACT), and default is
low active.
PFDCEN
DACK_ A
FUNCTION
When CR16 Bit 3 (GMDRQ) = 0:
DMA acknowledge signal A.
GMWR
39
PEXTEN
OUT8t
When CR16 Bit 3 (GMDRQ) = 1:
OUT8t
Adapter mode: Game port write control signal.
Portable mode: When a particular extended mode is selected for
the parallel port, this pin will be active. The extended modes
include Extension Adapter mode, EPP mode, ECP mode, and
ECP/EPP mode, which are selected using bit 3 - bit 0 of CRA.
The active state is dependent on bit 6 of CRA (PEXTACT); the
default is low active.
When CR16 Bit 3 (GMDRQ) = 0:
DRQ_A
PDCIN
3
INt
DMA request signal A.
INc
This input pin controls the chip power down. When this pin is
active, the clock supply to the chip will be inhibited and the
output pins will be tri-stated as defined in CR4 and CR6. The
PDCIN is pulled down internally. Its active state is defined by bit
4 of CRA (PDCHACT). Default is high active.
-8-
W83877F
1.4 Multi-Mode Parallel Port
The following pins have eight functions, which are controlled by bits PRTMOD0, PRTMOD1, and
PRTMOD2 of CR0 and CR9 (refer to section 8.0, Extended Functions).
SYMBOL
BUSY
PIN
I/O
24
INt
OD12
FUNCTION
PRINTER MODE: BUSY
An active high input indicates that the printer is not ready to
receive data. This pin is pulled high internally. Refer to the
description of the parallel port for the definition of this pin in ECP
and EPP mode.
EXTENSION FDD MODE: MOB2
INt
This pin is for Extension FDD B; the function of this pin is the
same as that of the MOB pin.
EXTENSION ADAPTER MODE: XIRQ
OD12
This pin is an interrupt request generated by the Extension
Adapter and is an active high input.
EXTENSION 2FDD MODE: MOB2
_
This pin is for Extension FDD A and B; the function of this pin is
the same as that of the MOB pin.
JOYSTICK MODE: NC pin.
ACK
26
INt
PRINTER MODE: ACK
An active low input on this pin indicates that the printer has
received data and is ready to accept more data. This pin is
pulled high internally. Refer to the description of the parallel port
for the definition of this pin in ECP and EPP mode.
OD12
EXTENSION FDD MODE: DSB2
This pin is for the Extension FDD B; its functions are the same
as those of the DSB pin.
INt
EXTENSION ADAPTER MODE: XDRQ
DMA request generated by the Extension Adapter. An active
high input.
OD12
EXTENSION 2FDD MODE: DSB2
This pin is for Extension FDD A and B; this function of this pin is
the same as that of the DSB pin.
_
JOYSTICK MODE: NC pin.
-9-
Publication Release Date: January 1996
Revision A2
W83877F
1.4 Multi-Mode Parallel Port, continued
SYMBOL
PE
PIN
I/O
27
INt
FUNCTION
PRINTER MODE: PE
An active high input on this pin indicates that the printer has
detected the end of the paper. This pin is pulled high internally.
Refer to the description of the parallel port for the definition of
this pin in ECP and EPP mode.
OD12
OUT12t
EXTENSION FDD MODE: WD2
This pin is for Extension FDD B; its function is the same as that
of the WD pin.
EXTENSION ADAPTER MODE: XA0
OD12
This pin is system address A0 for the Extension Adapter.
EXTENSION 2FDD MODE: WD2
_
This pin is for Extension FDD A and B; this function of this pin is
the same as that of the WD pin.
JOYSTICK MODE: NC pin.
SLCT
28
INt
OD12
PRINTER MODE: SLCT
An active high input on this pin indicates that the printer is
selected. This pin is pulled high internally. Refer to the
description of the parallel port for the definition of this pin in ECP
and EPP mode.
EXTENSION FDD MODE: WE2
OUT12t
OD12
This pin is for Extension FDD B; its functions are the same as
those of the WE pin.
EXTENSION ADAPTER MODE: XA1
This pin is system address A1 for the Extension Adapter.
EXTENSION 2FDD MODE: WE2
_
This pin is for Extension FDD A and B; this function of this pin is
the same as that of the WE pin.
JOYSTICK MODE: NC pin.
- 10 -
W83877F
1.4 Multi-Mode Parallel Port, continued
SYMBOL
ERR
PIN
I/O
29
INt
FUNCTION
PRINTER MODE: ERR
An active low input on this pin indicates that the printer has
encountered an error condition. This pin is pulled high internally.
Refer to the description of the parallel port for the definition of
this pin in ECP and EPP mode.
OD12
EXTENSION FDD MODE: HEAD2
This pin is for Extension FDD B; its function is the same as that
of the HEADpin.
OUT12t
EXTENSION ADAPTER MODE: XA2
This pin is system address A2 for the Extension Adapter.
OD12
EXTENSION 2FDD MODE: HEAD2
This pin is for Extension FDD A and B; its function is the same
as that of the HEAD pin.
_
SLIN
22
OD12
JOYSTICK MODE: NC pin.
PRINTER MODE: SLIN
Output line for detection of printer selection. This pin is pulled
high internally. Refer to the description of the parallel port for the
definition of this pin in ECP and EPP mode.
OD12
EXTENSION FDD MODE: STEP2
OUT12t
This pin is for Extension FDD B; its function is the same as that
of the STEP pin.
EXTENSION ADAPTER MODE: XTC
OD12
This pin is the DMA terminal count for the Extension Adapter.
The count is sent by TC directly.
EXTENSION 2FDD MODE: STEP2
OUT12t
This pin is for Extension FDD A and B; its function is the same
as that of the STEP pin .
JOYSTICK MODE: VDD for joystick.
- 11 -
Publication Release Date: January 1996
Revision A2
W83877F
1.4 Multi-Mode Parallel Port, continued
SYMBOL
INIT
PIN
I/O
21
OD12
FUNCTION
PRINTER MODE: INIT
Output line for the printer initialization. This pin is pulled high
internally. Refer to the description of the parallel port for the
definition of this pin in ECP and EPP mode.
OD12
OUT12t
EXTENSION FDD MODE: DIR2
This pin is for Extension FDD B; its function is the same as that
of the DIR pin.
EXTENSION ADAPTER MODE: XDACK
OD12
This pin is the DMA acknowledge output for the Extension
Adapter; the output is sent directly from PDACKX .
EXTENSION 2FDD MODE: DIR2
OUT12t
This pin is for Extension FDD A and B; its function is the same
as that of the DIR pin.
JOYSTICK MODE: VDD for joystick.
AFD
20
OD12
PRINTER MODE: AFD
An active low output from this pin causes the printer to auto feed
a line after a line is printed. This pin is pulled high internally.
Refer to the description of the parallel port for the definition of
this pin in ECP and EPP mode.
OD12
EXTENSION FDD MODE: RWC2
OUT12t
This pin is for Extension FDD B; its function is the same as that
of the RWC pin.
EXTENSION ADAPTER MODE: XRD
This pin is the I/O read command for the Extension Adapter.
OD12
When the Extension Adapter base address is written to the
Extension Adapter address register, XRD and XWR go low
simultaneously so that the command register on the Extension
Adapter can latch the same base address.
EXTENSION 2FDD MODE: RWC2
OUT12t
This pin is for Extension FDD A and B; its function is the same
as that of the RWC pin.
JOYSTICK MODE: VDD for joystick.
- 12 -
W83877F
1.4 Multi-Mode Parallel Port, continued
SYMBOL
STB
PIN
I/O
19
OD12
OUT12t
FUNCTION
PRINTER MODE: STB
An active low output is used to latch the parallel data into the
printer. This pin is pulled high internally. Refer to the description
of the parallel port for the definition of this pin in ECP and EPP
mode.
EXTENSION FDD MODE:
This pin is a tri-state output.
EXTENSION ADAPTER MODE: XWR
This pin is the I/O write command for the Extension Adapter.
OUT12t
When the Extension Adapter base address is written to the
Extension Adapter address register, XRD and XWR go low
simultaneously so that the command register on the Extension
Adapter can latch the same base address.
EXTENSION 2FDD MODE: This pin is a tri-state output.
JOYSTICK MODE: VDD for joystick.
PD0
9
I/O24t
PRINTER MODE: PD0
Parallel port data bus bit 0. Refer to the description of the
parallel port for the definition of this pin in ECP and EPP mode.
INt
EXTENSION FDD MODE: INDEX2
This pin is for Extension FDD B; the function of this pin is the
same as that of the INDEX pin. This pin is pulled high internally.
I/O24t
EXTENSION ADAPTER MODE: XD0
This pin is system data bus D0 for the Extension Adapter.
INt
EXTENSION 2FDD MODE: INDEX2
This pin is for Extension FDD A and B; this function of this pin is
the same as INDEX pin. This pin is pulled high internally.
I/O24t
JOYSTICK MODE: JP0
This pin is the paddle 0 input for joystick.
- 13 -
Publication Release Date: January 1996
Revision A2
W83877F
1.4 Multi-Mode Parallel Port, continued
SYMBOL
PD1
PIN
I/O
10
I/O24t
FUNCTION
PRINTER MODE: PD1
Parallel port data bus bit 1. Refer to the description of the
parallel port for the definition of this pin in ECP and EPP mode.
INt
EXTENSION FDD MODE: TRAK02
This pin is for Extension FDD B; the function of this pin is the
same as that of the TRAK0 pin. This pin is pulled high internally.
I/O24t
EXTENSION ADAPTER MODE: XD1
This pin is system data bus D1 for the Extension Adapter.
INt
EXTENSION. 2FDD MODE: TRAK02
This pin is for Extension FDD A and B; this function of this pin is
the same as TRAK0 pin. This pin is pulled high internally.
I/O24t
JOYSTICK MODE: JP1
This pin is the paddle 1 input for joystick.
PD2
11
I/O24t
PRINTER MODE: PD2
Parallel port data bus bit 2. Refer to the description of the
parallel port for the definition of this pin in ECP and EPP mode.
INt
EXTENSION FDD MODE: WP2
This pin is for Extension FDD B; the function of this pin is the
same as that of the WP pin. This pin is pulled high internally.
I/O24t
EXTENSION ADAPTER MODE: XD2
This pin is system data bus D2 for the Extension Adapter.
INt
-
EXTENSION. 2FDD MODE: WP2
This pin is for Extension FDD A and B; this function of this pin is
the same as that of the WP pin. This pin is pulled high
internally.
JOYSTICK MODE: NC pin
- 14 -
W83877F
1.4 Multi-Mode Parallel Port, continued
SYMBOL
PD3
PIN
12
I/O
I/O24t
INt
I/O24t
INt
-
PD4
13
I/O24t
INt
I/O24t
INt
INt
PD5
14
I/O24t
I/O24t
INt
FUNCTION
PRINTER MODE: PD3
Parallel port data bus bit 3. Refer to the description of the
parallel port for the definition of this pin in ECP and EPP mode.
EXTENSION FDD MODE: RDATA2
Motor on B for Extension FDD B; the function of this pin is the
same as that of the RDATA pin. This pin is pulled high internally.
EXTENSION ADAPTER MODE: XD3
This pin is system data bus D3 for the Extension Adapter.
EXTENSION 2FDD MODE: RDATA2
This pin is for Extension FDD A and B; this function of this pin is
the same as that of the RDATA pin. This pin is pulled high
internally.
JOYSTICK MODE: NC pin
PRINTER MODE: PD4
Parallel port data bus bit 4. Refer to the description of the
parallel port for the definition of this pin in ECP and EPP mode.
EXTENSION FDD MODE: DSKCHG2
Drive select B for Extension FDD B; the function of this pin is the
same as that of DSKCHG pin. This pin is pulled high internally.
EXTENSION ADAPTER MODE: XD4
This pin is system data bus D4 for the Extension Adapter.
EXTENSION 2FDD MODE: DSKCHG2
This pin is for Extension FDD A and B; this function of this pin is
the same as that of the DSKCHG pin. This pin is pulled high
internally.
JOYSTICK MODE: JB0
This pin is the button 0 input for the joystick.
PRINTER MODE: PD5
Parallel port data bus bit 5. Refer to the description of the
parallel port for the definition of this pin in ECP and EPP mode.
EXTENSION FDD MODE:
This pin is a tri-state output.
EXTENSION ADAPTER MODE: XD5
This pin is system data bus D5 for the Extension Adapter
EXTENSION 2FDD MODE:
This pin is a tri-state output.
JOYSTICK MODE: JB1
This pin is the button 1 input for the joystick.
- 15 -
Publication Release Date: January 1996
Revision A2
W83877F
1.4 Multi-Mode Parallel Port, continued
SYMBOL
PD6
PIN
I/O
16
I/O24t
-
FUNCTION
PRINTER MODE: PD6
Parallel port data bus bit 6. Refer to the description of the
parallel port for the definition of this pin in ECP and EPP mode.
EXTENSION FDD MODE:
I/O24t
This pin is a tri-state output.
EXTENSION ADAPTER MODE: XD6
OD24
-
This pin is system data bus D6 for the Extension Adapter
EXTENSION. 2FDD MODE: MOA2
This pin is for Extension FDD A; its function is the same as that
of the MOA pin.
JOYSTICK MODE: NC pin
PD7
17
I/O24t
PRINTER MODE: PD7
Parallel port data bus bit 7. Refer to the description of the
parallel port for the definition of this pin in ECP and EPP mode.
-
EXTENSION FDD MODE:
This pin is a tri-state output.
I/O24t
EXTENSION ADAPTER MODE: XD7
This pin is system data bus D7 for the Extension Adapter.
OD24
EXTENSION 2FDD MODE: DSA2
This pin is for Extension FDD A; its function is the same as that
of the DSA pin.
-
JOYSTICK MODE: NC pin
- 16 -
W83877F
1.5 IDE and FDC Interface
SYMBOL
PIN
1
I/O
OUT12t
OUT12t
FUNCTION
When CR16 Bit 1 (IRIDE) = 0: Active low reset signal for IDE;
When CR16 Bit 1 (IRIDE) = 1: Interrupt request signal G.
IDBEN /
IRQ_H
91
OUT12t
OUT12t
When CR16 Bit 1 (IRIDE) = 0: Active low enable signal for IDE;
When CR16 Bit 1 (IRIDE) = 1: Interrupt request signal H.
CS1/
95
OUT12t
When CR16 Bit 1 (IRIDE) = 0: This pin is used to select the IDE
RESIDE /
IRQ_G
OUT12t
IRTX2
CS0 /
94
INt
IRRX2
WE
DIR
OUT12t
85
OD24
89
24
HEAD
88
OD24
RWC
87
OD24
WD
86
OD24
STEP
82
OD24
INDEX
81
INcs
controller. CS1 decodes the HDC addresses specified in
CR22.
When CR16 Bit 1 (IRIDE) = 1: Function as a InfraRed
transmission data line.
When CR16 Bit 1 (IRIDE) = 0: This pin is used to select the IDE
controller. CS decodes HDC addresses specified in CR21.
When CR16 Bit 1 (IRIDE) = 1: Function as a InfraRed receiving
line.
Write enable. An open drain output.
Direction of the head step motor. An open drain output.
Logic 0 = inward motion
Head select. This open drain output determines which disk drive
head is active.
Logic 1 = side 0
Logic 0 = side 1
Reduced write current. This signal can be used on two-speed
disk drives to select the transfer rate. An open drain output.
Logic 0 = 250 Kb/s
Logic 1 = 500 Kb/s
When bit 5 of CR9 (EN3MODE) is set to high, the three-mode
FDD function is enabled, and the pin will have a different
definition. Refer to the EN3MODE bit in CR9.
Write data. This logic low open drain writes precompensation
serial data to the selected FDD. An open drain output.
Step output pulses. This active low open drain output produces a
pulse to move the head to another track.
This schmitt input from the disk drive is active low when the
head is positioned over the beginning of a track marked by an
index hole. This input pin is pulled up internally by an
approximately 1K ohm resistor. The resistor can be disabled by
bit 4 of CR6 (FIPURDWN).
- 17 -
Publication Release Date: January 1996
Revision A2
W83877F
1.5 IDE and FDC Interface, continued
SYMBOL
PIN
I/O
FUNCTION
TRAK0
78
INcs
Track 0. This schmitt input from the disk drive is active low when
the head is positioned over the outermost track. This input pin is
pulled up internally by an approximately 1K ohm resistor. The
resistor can be disabled by bit 4 of CR6 (FIPURDWN).
WP
77
INcs
Write protected. This active low schmitt input from the disk drive
indicates that the diskette is write-protected. This input pin is
pulled up internally by an approximately 1K ohm resistor. The
resistor can be disabled by bit 4 of CR6 (FIPURDWN).
RDATA
74
INcs
The read data input signal from the FDD. This input pin is pulled
up internally by an approximately 1K ohm resistor. The resistor
can be disabled by bit 4 of CR6 (FIPURDWN).
DSKCHG
76
INcs
Diskette change. This signal is active low at power on and
whenever the diskette is removed. This input pin is pulled up
internally by an approximately 1K ohm resistor. The resistor can
be disabled by bit 4 of CR6 (FIPURDWN).
MOA
79
OD24
Motor A On. When set to 0, this pin enables disk drive 0. This is
an open drain output.
MOB
80
OD24
Motor B On. When set to 0, this pin enables disk drive 1. This is
an open drain output.
DSA
83
OD24
Drive Select A. When set to 0, this pin enables disk drive A. This
is an open drain output.
DSB
84
OD24
Drive Select B. When set to 0, this pin enables disk drive B. This
is an open drain output.
VDD
15,
56
+5 power supply for the digital circuitry
GND
25,
40
65,
90
Ground
2.0 FDC FUNCTIONAL DESCRIPTION
2.1 W83877F FDC
The floppy disk controller of the W83877F integrates all of the logic required for floppy disk control.
The FDC implements a PC/AT or PS/2 solution. All programmable options default to compatible
values. The FIFO provides better system performance in multi-master systems. The digital data
separator supports up to 1 M bits/sec data rate.
The FDC includes the following blocks: AT interface, Precompensation, Data Rate Selection, Digital
Data Separator, FIFO, and FDC Core.
- 18 -
W83877F
2.1.1 AT interface
The interface consists of the standard asynchronous signals: RD , WR , A0-A3, IRQ, DMA control,
and a data bus. The address lines select between the configuration registers, the FIFO and
control/status registers. This interface can be switched between PC/AT, Model 30, or PS/2 normal
modes. The PS/2 register sets are a superset of the registers found in a PC/AT.
2.1.2 FIFO (Data)
The FIFO is 16 bytes in size and has programmable threshold values. All command parameter
information and disk data transfers go through the FIFO. Data transfers are governed by the RQM
and DIO bits in the Main Status Register.
The FIFO defaults to disabled mode after any form of reset. This maintains PC/AT hardware
compatibility. The default values can be changed through the CONFIGURE command. The
advantage of the FIFO is that it allows the system a larger DMA latency without causing disk errors.
The following tables give several examples of the delays with a FIFO. The data are based upon the
following formula:
THRESHOLD # × (1/DATA/RATE) *8 - 1.5 µS = DELAY
FIFO THRESHOLD
MAXIMUM DELAY TO SERVICING AT 500K BPS
Data Rate
1 Byte
1 × 16 µS - 1.5 µS = 14.5 µS
2 Byte
2 × 16 µS - 1.5 µS = 30.5 µS
8 Byte
8 × 16 µS - 1.5 µS = 6.5 µS
15 Byte
15 × 16 µS - 1.5 µS = 238.5 µS
FIFO THRESHOLD
MAXIMUM DELAY TO SERVICING AT 1M BPS
Data Rate
1 Byte
1 × 8 µS - 1.5 µS = 6.5 µS
2 Byte
2 × 8 µS - 1.5 µS = 14.5 µS
8 Byte
8 × 8 µS - 1.5 µS = 62.5 µS
15 Byte
15 × 8 µS - 1.5 µS = 118.5 µS
At the start of a command the FIFO is always disabled and command parameters must be sent based
upon the RQM and DIO bit settings in the main status register. When the FDC enters the command
execution phase, it clears the FIFO of any data to ensure that invalid data are not transferred.
An overrun and underrun will terminate the current command and the data transfer. Disk writes will
complete the current sector by generating a 00 pattern and valid CRC. Reads require the host to
remove the remaining data so that the result phase may be entered.
DMA transfers are enabled with the SPECIFY command and are initiated by the FDC by activating
the DRQ pin during a data transfer command. The FIFO is enabled directly by asserting DACK and
addresses need not be valid.
Note that if the DMA controller is programmed to function in verify mode a pseudo read is performed
by the FDC based only on DACK . This mode is only available when the FDC has been configured
- 19 -
Publication Release Date: January 1996
Revision A2
W83877F
into byte mode (FIFO disabled) and is programmed to do a read. With the FIFO enabled the above
operation is performed by using the new VERIFY command. No DMA operation is needed.¡@
2.1.3 Data Separator
The function of the data separator is to lock onto the incoming serial read data. When a lock is
achieved the serial front end logic of the chip is provided with a clock which is synchronized to the
read data. The synchronized clock, called the Data Window, is used to internally sample the serial
data portion of the bit cell, and the alternate state samples the clock portion. Serial to parallel
conversion logic separates the read data into clock and data bytes.
The Digital Data Separator (DDS) has three parts: control logic, error adjustment, and speed tracking.
The DDS circuit cycles once every 12 clock cycles ideally. Any data pulse input will be synchronized
and then adjusted by immediate error adjustment. The control logic will generate RDD and RWD for
every pulse input. During any cycle where no data pulse is present, the DDS cycles are based on
speed. A digital integrator is used to keep track of the speed changes in the input data stream.
2.1.4 Write Precompensation
The write precompensation logic is used to minimize bit shifts in the RDDATA stream from the disk
drive. Shifting of bits is a known phenomenon in magnetic media and is dependent on the disk media
and the floppy drive.
The FDC monitors the bit stream that is being sent to the drive. The data patterns that require
precompensation are well known. Depending upon the pattern, the bit is shifted either early or late
relative to the surrounding bits.
2.1.5 Perpendicular Recording Mode
The FDC is also capable of interfacing directly to perpendicular recording floppy drives. Perpendicular
recording differs from the traditional longitudinal method in that the magnetic bits are oriented
vertically. This scheme packs more data bits into the same area.
FDCs with perpendicular recording drives can read standard 3.5" floppy disks and can read and write
perpendicular media. Some manufacturers offer drives that can read and write standard and
perpendicular media in a perpendicular media drive.
A single command puts the FDC into perpendicular mode. All other commands operate as they
normally do. The perpendicular mode requires a 1 Mbps data rate for the FDC. At this data rate the
FIFO eases the host interface bottleneck due to the speed of data transfer to or from the disk.
2.1.6 FDC Core
The W83877F FDC is capable of performing twenty commands. Each command is initiated by a
multi-byte transfer from the microprocessor. The result can also be a multi-byte transfer back to the
microprocessor. Each command consists of three phases: command, execution, and result.
Command
The microprocessor issues all required information to the controller to perform a specific operation.
Execution
The controller performs the specified operation.
Result
After the operation is completed, status information and other housekeeping information is provided
to the microprocessor.
- 20 -
W83877F
2.1.7 FDC Commands
Command Symbol Descriptions:
C:
Cylinder number 0 - 256
D:
Data Pattern
DIR:
Step Direction
DIR = 0, step out
DIR = 1, step in
DS0:
Disk Drive Select 0
DS1:
Disk Drive Select 1
DTL:
Data Length
EC:
Enable Count
EOT:
End of Track
EFIFO:
Enable FIFO
EIS:
Enable Implied Seek
EOT:
End of track
FIFOTHR: FIFO Threshold
GAP:
Gap length selection
GPL:
Gap Length
H:
Head number
HDS:
Head number select
HLT:
Head Load Time
HUT:
Head Unload Time
LOCK:
Lock EFIFO, FIFOTHR, PTRTRK bits prevent affected by software reset
MFM:
MFM or FM Mode
MT:
Multitrack
N:
The number of data bytes written in a sector
NCN:
New Cylinder Number
ND:
Non-DMA Mode
OW:
Overwritten
PCN:
Present Cylinder Number
POLL:
Polling Disable
PRETRK:
Precompensation Start Track Number
R:
Record
RCN:
Relative Cylinder Number
R/W:
Read/Write
SC:
Sector/per cylinder
SK:
Skip deleted data address mark
- 21 -
Publication Release Date: January 1996
Revision A2
W83877F
SRT:
Step Rate Time
ST0:
Status Register 0
ST1:
Status Register 1
ST2:
Status Register 2
ST3:
Status Register 3
WG:
Write gate alters timing of WE
(1) Read Data
PHASE
R/W
D7
D6
Command
W
MT MFM SK
0
0
W
0
0
0 HDS DS1 DS0
0
D5
0
D4
D3
D2
1
D1
1
D0
0
W
---------------------- C ------------------------
W
---------------------- H ------------------------
W
---------------------- R ------------------------
W
---------------------- N ------------------------
W
-------------------- EOT -----------------------
W
-------------------- GPL -----------------------
W
-------------------- DTL -----------------------
Execution
Result
REMARKS
Command codes
Sector ID information prior
to command execution
Data transfer between the
FDD and system
R
R
-------------------- ST0 -----------------------
R
-------------------- ST2 -----------------------
R
---------------------- C ------------------------
R
---------------------- H ------------------------
R
---------------------- R ------------------------
R
---------------------- N ------------------------
-------------------- ST1 -----------------------
- 22 -
Status information after
command execution
Sector ID information after
command execution
W83877F
(2) Read Deleted Data
PHASE
R/W
D7
D6
D5
Command
W
MT
MFM SK
0
1
W
0
0
0
0
0
D4
D3 D2
1
D1
D0
0
0
Command codes
HDS DS1 DS0
W
---------------------- C ------------------------
W
---------------------- H ------------------------
W
---------------------- R ------------------------
W
---------------------- N ------------------------
W
-------------------- EOT -----------------------
W
-------------------- GPL -----------------------
W
-------------------- DTL -----------------------
Execution
Result
REMARKS
Sector ID information prior
to command execution
Data transfer between the
FDD and system
R
-------------------- ST0 -----------------------
R
-------------------- ST1 -----------------------
R
-------------------- ST2 -----------------------
R
---------------------- C ------------------------
R
---------------------- H ------------------------
R
---------------------- R ------------------------
R
---------------------- N ------------------------
- 23 -
Status information after
command execution
Sector ID information after
command execution
Publication Release Date: January 1996
Revision A2
W83877F
(3) Read A Track
PHASE
R/W
Command
W
W
D7
D6
D5
D4
D3
D2
D1
D0
0 MFM
0
0
0
0
1
0
0
0
0
0 HDS DS1 DS0
0
W
---------------------- C ------------------------
W
---------------------- H ------------------------
W
---------------------- R ------------------------
W
---------------------- N ------------------------
W
-------------------- EOT -----------------------
W
-------------------- GPL -----------------------
W
-------------------- DTL -----------------------
Execution
Result
REMARKS
Command codes
Sector ID information prior
to command execution
Data transfer between the
FDD and system; FDD
reads contents of all
cylinders from index hole to
EOT
R
-------------------- ST0 -----------------------
R
-------------------- ST1 -----------------------
R
-------------------- ST2 -----------------------
R
---------------------- C ------------------------
R
---------------------- H ------------------------
R
---------------------- R ------------------------
R
---------------------- N ------------------------
- 24 -
Status information after
command execution
Sector ID information after
command execution
W83877F
(4) Read ID
PHASE
R/W
D7
D6
Command
W
0 MFM
W
0
0
D5
D4
D3
D2
D1
D0
0
0
1
0
1
0
0
0
0
Command codes
HDS DS1 DS0
Execution
Result
REMARKS
The first correct ID
information on the cylinder
is stored in Data Register
R
-------------------- ST0 -----------------------
R
-------------------- ST1 -----------------------
R
-------------------- ST2 -----------------------
R
R
---------------------- C ------------------------
R
---------------------- R ------------------------
R
---------------------- N ------------------------
---------------------- H ------------------------
Status information after
command execution
Disk status after the
command has been
completed
(5) Verify
PHASE
Command
R/W
D7
D6
D5
D4
D3
D2
D1
D0
0
1
1
0
W
MT MFM
SK
1
W
EC
0
0
0
0
REMARKS
Command codes
HDS DS1 DS0
W
---------------------- C ------------------------
W
---------------------- H ------------------------
W
---------------------- R ------------------------
W
---------------------- N ------------------------
W
-------------------- EOT -----------------------
W
-------------------- GPL -----------------------
Sector ID information prior
to command execution
-------------------- DTL/SC ------------------Execution
Result
No data transfer takes
place
R
-------------------- ST0 -----------------------
R
-------------------- ST1 -----------------------
R
-------------------- ST2 -----------------------
R
---------------------- C ------------------------
R
---------------------- H ------------------------
R
---------------------- R ------------------------
R
---------------------- N ------------------------
- 25 -
Status information after
command execution
Sector ID information after
command execution
Publication Release Date: January 1996
Revision A2
W83877F
(6) Version
PHASE
R/W
D7
D6
D5
D4
D3
D2
D1
D0
REMARKS
Command
W
0
0
0
1
0
0
0
0
Command code
Result
R
1
0
0
1
0
0
0
0
Enhanced controller
D6
D5
D4
D3
D2
D1
D0
0
0
0
1
0
1
(7) Write Data
PHASE
R/W
Command
W
W
D7
MT MFM
0
0
0
0
0
Command codes
HDS DS1 DS0
W
---------------------- C ------------------------
W
---------------------- H ------------------------
W
---------------------- R ------------------------
W
---------------------- N ------------------------
W
-------------------- EOT -----------------------
W
-------------------- GPL -----------------------
W
-------------------- DTL -----------------------
Sector ID information prior
to Command execution
Execution
Result
REMARKS
Data transfer between the
FDD and system
R
-------------------- ST0 -----------------------
R
-------------------- ST1 -----------------------
R
-------------------- ST2 -----------------------
R
---------------------- C ------------------------
R
---------------------- H ------------------------
R
---------------------- R ------------------------
R
---------------------- N ------------------------
Status information after
Command execution
Sector ID information after
Command execution
(8) Write Deleted Data
PHASE
R/W
Command
W
W
D7
D6
D5
D4
D3
D2
D1
D0
MT
MFM 0
0
1
0
0
1
0
0
0
0
0
REMARKS
Command codes
HDS DS1 DS0
W
---------------------- C ------------------------
W
---------------------- H ------------------------
W
---------------------- R ------------------------
W
---------------------- N ------------------------
- 26 -
Sector ID information prior
to command execution
W83877F
Write deleted data, continued
PHASE
R/W
D7
D6
D5
D4
D3
D2
D1
D0
W
-------------------- EOT -----------------------
W
-------------------- GPL -----------------------
W
-------------------- DTL -----------------------
Execution
Result
REMARKS
Data transfer between the
FDD and system
R
-------------------- ST0 -----------------------
R
-------------------- ST1 -----------------------
R
-------------------- ST2 -----------------------
R
---------------------- C ------------------------
R
---------------------- H ------------------------
R
---------------------- R ------------------------
R
---------------------- N ------------------------
Status information after
command execution
Sector ID information after
command execution
(9) Format A Track
PHASE
Command
Execution
for Each
Sector
Repeat:
Result
R/W
D7
W
0
W
0
D6
D5
D4
D3
D2
D1
D0
MFM
0
0
1
1
0
1
0
0
0
0
REMARKS
Command codes
HDS DS1 DS0
W
---------------------- N ------------------------
Bytes/Sector
W
--------------------- SC -----------------------
Sectors/Cylinder
W
--------------------- GPL ---------------------
Gap 3
W
---------------------- D ------------------------
Filler Byte
W
---------------------- C ------------------------
Input Sector Parameters
W
---------------------- H ------------------------
W
---------------------- R ------------------------
W
---------------------- N ------------------------
R
-------------------- ST0 -----------------------
R
-------------------- ST1 -----------------------
R
-------------------- ST2 -----------------------
R
R
---------------- Undefined -------------------
R
---------------- Undefined -------------------
R
---------------- Undefined -------------------
Status information after
command execution
---------------- Undefined -------------------
- 27 -
Publication Release Date: January 1996
Revision A2
W83877F
(10) Recalibrate
PHASE
R/W
D7 D6 D5
Command
W
0
0
W
0
0
D4
D3
D2
D1
D0
0
0
0
1
1
1
0
0
0
0
REMARKS
Command codes
DS1 DS0
Execution
Head retracted to Track 0
Interrupt
(11) Sense Interrupt Status
PHASE
R/W
D7
76
D5
D4
D3
D2
D1
D0
Command
W
0
0
0
0
1
0
0
0
Result
R
---------------- ST0 -------------------------
R
---------------- PCN -------------------------
REMARKS
Command code
Status information at the end
of each seek operation
(12) Specify
PHASE
R/W
D7
D6
D5
D4
D3
D2
D1
D0
W
0
0
0
0
0
0
1
1
Command
W
| ---------SRT ----------- | --------- HUT ---------- |
W
|------------ HLT ----------------------------------| ND
REMARKS
Command codes
(13) Seek
PHASE
R/W
D7
D6
D5
D4
D3
D2
D1
D0
W
0
0
0
0
1
1
1
1
W
0
0
0
0
0
Command
W
Execution
REMARKS
Command codes
HDS DS1 DS0
-------------------- NCN -----------------------
R
Head positioned over proper
cylinder on diskette
(14) Configure
PHASE
Command
R/W
D7
D6
D5
D4
D3
D2
D1
D0
W
0
0
0
1
0
0
1
1
W
0
0
0
0
0
0
0
0
W
0 EIS EFIFO POLL | ------ FIFOTHR ----|
W
| --------------------PRETRK ---------------------- |
Execution
REMARKS
Configure information
Internal registers written
- 28 -
W83877F
(15) Relative Seek
PHASE
Command
R/W
D7
D6
W
1
W
0
W
D5
D4
D3
D2
D1
D0
DIR
0
0
1
1
1
1
0
0
0
0
REMARKS
Command codes
HDS DS1 DS0
| -------------------- RCN ---------------------------- |
(16) Dumpreg
PHASE
R/W
D7
D6
D5
D4
D3
D2
D1
D0
Command
W
0
0
0
0
1
1
1
0
Result
R
-------------------- PCN-Drive 0-----------------
R
-------------------- PCN-Drive 1 ----------------
R
-------------------- PCN-Drive 2-----------------
R
-------------------- PCN-Drive 3 ----------------
R
-------SRT ----------------- | --------- HUT --------
R
------------ HLT -------------------------------------| ND
R
REMARKS
Registers placed in FIFO
-------------------- SC/EOT --------------------
R
LOCK 0
D3
D2
D1
D0
GAP WG
R
0 EIS EFIFO POLL | ------ FIFOTHR --------
R
--------------------PRETRK ---------------------
(17) Perpendicular Mode
PHASE
Command
R/W
D7
D6
D5
D4
D3
D2
D1
D0
W
0
0
0
1
0
0
1
0
W
OW
0
D3
D2 D1
R/W
D7
D6
D5
D4
D3
D2
D1
D0
LOCK 0
0
1
0
1
0
0
LOCK 0
0
0
0
REMARKS
Command Code
D0 GAP WG
(18) Lock
PHASE
Command
W
Result
R
0
0
0
D7
D6
D5
D4
D3
D2
D1
D0
W
0
0
0
0
0
1
0
0
W
0
0
0
0
0 HDS DS1 DS0
REMARKS
Command Code
(19) Sense Drive Status
PHASE
Command
Result
R/W
R
---------------- ST3 -------------------------
- 29 -
REMARKS
Command Code
Status information about
disk drive
Publication Release Date: January 1996
Revision A2
W83877F
(20) Invalid
PHASE
R/W
D7
D6
D5
D4
D3
D2
D1
D0
Command
W
------------- Invalid Codes -----------------
Result
R
-------------------- ST0 ----------------------
REMARKS
Invalid codes (no operation
- FDC goes into standby
state)
ST0 = 80H
2.2 Register Descriptions
There are several status, data, and control registers in W83877F. These registers are defined below:
ADDRESS
OFFSET
base address + 0
base address + 1
base address + 2
base address + 3
base address + 4
base address + 5
base address + 7
REGISTER
READ
SA REGISTER
SB REGISTER
WRITE
DO REGISTER
TD REGISTER
DR REGISTER
DT (FIFO) REGISTER
CC REGISTER
TD REGISTER
MS REGISTER
DT (FIFO) REGISTER
DI REGISTER
2.2.1 Status Register A (SA Register) (Read base address + 0)
This register is used to monitor several disk interface pins in PS/2 and Model 30 modes. In PS/2
mode, the bit definitions for this register are as follows:
7
6
5
4
3
2
1
0
DIR
WP
INDEX
HEAD
TRAK0
STEP
DRV2
INIT PENDING
INIT PENDING (Bit 7):
This bit indicates the value of the floppy disk interrupt output.
DRV2 (Bit 6):
0
A second drive has been installed
1
A second drive has not been installed
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W83877F
STEP (Bit 5):
This bit indicates the complement of STEP output.
TRAK0 (Bit 4):
This bit indicates the value of TRAK0 input.
HEAD (Bit 3):
This bit indicates the complement of HEAD output.
0
side 0
1
side 1
INDEX (Bit 2):
This bit indicates the value of INDEX output.
WP (Bit 1):
0disk is write-protected
1disk is not write-protected
DIR (Bit 0)
This bit indicates the direction of head movement.
0
outward direction
1
inward direction
In PS/2 Model 30 mode, the bit definitions for this register are as follows:
7
6
5
4
3
2
1
0
DIR
WP
INDEX
HEAD
TRAK0
STEP F/F
DRQ
INIT PENDING
INIT PENDING (Bit 7):
This bit indicates the value of the floppy disk interrupt output.
DRQ (Bit 6):
This bit indicates the value of DRQ output pin.
STEP F/F (Bit 5):
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Publication Release Date: January 1996
Revision A2
W83877F
This bit indicates the complement of latched STEP output.
TRAK0 (Bit 4):
This bit indicates the complement of TRAK0 input.
HEAD (Bit 3):
This bit indicates the value of HEAD output.
0
side 1
1
side 0
INDEX (Bit 2):
This bit indicates the complement of INDEX output.
WP (Bit 1):
0
disk is not write-protected
1
disk is write-protected
DIR (Bit 0)
This bit indicates the direction of head movement.
0
inward direction
1
outward direction
2.2.2 Status Register B (SB Register) (Read base address + 1)
This register is used to monitor several disk interface pins in PS/2 and Model 30 modes. In PS/2
mode, the bit definitions for this register are as follows:
7
6
1
1
5
4
3
2
1
0
MOT EN A
MOT EN B
WE
RDATA Toggle
WDATA Toggle
Drive SEL0
Drive SEL0 (Bit 5):
This bit indicates the status of DO REGISTER bit 0 (drive select bit 0).
WDATA Toggle (Bit 4):
This bit changes state at every rising edge of the WD output pin.
RDATA Toggle (Bit 3):
This bit changes state at every rising edge of the RDATA output pin.
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W83877F
WE (Bit 2):
This bit indicates the complement of the WE output pin.
MOT EN B (Bit 1)
This bit indicates the complement of the MOB output pin.
MOT EN A (Bit 0)
This bit indicates the complement of the MOA output pin.
In PS/2 Model 30 mode, the bit definitions for this register are as follows:
7
6
5
4
3
2
1
0
DSC
DSD
WE F/F
RDATA F/F
WD F/F
DSA
DSB
DRV2
DRV2 (Bit 7):
0
A second drive has been installed
1
A second drive has not been installed
DSB (Bit 6):
This bit indicates the status of DSB output pin.
DSA (Bit 5):
This bit indicates the status of DSA output pin.
WD F/F(Bit 4):
This bit indicates the complement of the latched WD output pin at every rising edge of the WD
output pin.
RDATA F/F(Bit 3):
This bit indicates the complement of the latched RDATA output pin .
WE F/F (Bit 2):
This bit indicates the complement of latched WE output pin.
DSD (Bit 1):
0
Drive D has been selected
1
Drive D has not been selected
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Publication Release Date: January 1996
Revision A2
W83877F
DSC (Bit 0):
0
Drive C has been selected
1
Drive C has not been selected
2.2.3 Digital Output Register (DO Register) (Write base address + 2)
The Digital Output Register is a write-only register controlling drive motors, drive selection, DRQ/IRQ
enable, and FDC resetting. All the bits in this register are cleared by the MR pin. The bit definitions
are as follows:
7
6
5
3
4
1-0
2
Drive Select: 00 select drive A
01 select drive B
10 select drive C
11 select drive D
Floppy Disk Controller Reset
Active low resets FDC
DMA and INT Enable
Active high enable DRQ/IRQ
Motor Enable A. Motor A on when active high
Motor Enable B. Motor B on when active high
Motor Enable C. Motor C on when active high
Motor Enable D. Motor D on when active high
2.2.4 Tape Drive Register (TD Register) (Read base address + 3)
This register is used to assign a particular drive number to the tape drive support mode of the data
separator. This register also holds the media ID, drive type, and floppy boot drive information of the
floppy disk drive. In normal floppy mode, this register includes only bit 0 and 1. The bit definitions are
as follows:
7
6
5
4
3
2
X
X
X
X
X
X
1
0
Tape sel 0
Tape sel 1
If three mode FDD function is enabled (EN3MODE = 1 in CR9), the bit definitions are as follows:
7
6
5
4
3
2
1
0
Tape Sel 0
Tape Sel 1
Floppy boot drive 0
Floppy boot drive 1
Drive type ID0
Drive type ID1
Media ID0
Media ID1
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W83877F
Media ID1 Media ID0 (Bit 7, 6):
These two bits are read only. These two bits reflect the value of CR8 bit 3, 2.
Drive type ID1 Drive type ID0 (Bit 5, 4):
These two bits reflect two of the bits of CR7. Which two bits are reflected depends on the last drive
selected in the DO REGISTER.
Floppy Boot drive 1, 0 (Bit 3, 2):
These two bits reflect the value of CR8 bit 1, 0.
Tape Sel 1, Tape Sel 0 (Bit 1, 0):
These two bits assign a logical drive number to the tape drive. Drive 0 is not available as a tape drive
and is reserved as the floppy disk boot drive.
TAPE SEL 1
TAPE SEL 0
DRIVE SELECTED
0
0
None
0
1
1
1
0
2
1
1
3
2.2.5 Main Status Register (MS Register) (Read base address + 4)
The Main Status Register is used to control the flow of data between the microprocessor and the
controller. The bit definitions for this register are as follows:
7
6
5
4
3
2
1
0
FDD 0 Busy, (D0B = 1), FDD number 0 is in the SEEK mode.
FDD 1 Busy, (D1B = 1), FDD number 1 is in the SEEK mode.
FDD 2 Busy, (D2B = 1), FDD number 2 is in the SEEK mode.
FDD 3 Busy, (D3B = 1), FDD number 3 is in the SEEK mode.
FDC Busy, (CB). A read or write command is in the process when CB = HIGH.
Non-DMA mode, the FDC is in the non-DMA mode, this bit is set only during the
execution phase in non-DMA mode.
Transition to LOW state indicates execution phase has ended.
DATA INPUT/OUTPUT, (DIO). If DIO= HIGH then transfer is from Data Register to the processor.
If DIO = LOW then transfer is from processor to Data Register.
Request for Master (RQM). A high on this bit indicates Data Register is ready to send or receive data to or from the processor.
2.2.6 Data Rate Register (DR Register) (Write base address + 4)
The Data Rate Register is used to set the transfer rate and write precompensation. The data rate of
the FDC is programmed by the CC REGISTER for PC-AT and PS/2 Model 30 and PS/2 mode, and
not by the DR REGISTER. The real data rate is determined by the most recent write to either of the
DR REGISTER or CC REGISTER.
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Publication Release Date: January 1996
Revision A2
W83877F
7
6
5
4
3
2
1
0
0
DRATE0
DRATE1
PRECOMP0
PRECOMP1
PRECOMP2
POWER DOWN
S/W RESET
S/W RESET (Bit 7):
This bit is the software reset bit.
POWER-DOWN (Bit 6):
0
FDC in normal mode
1
FDC in power-down mode
PRECOMP2 PRECOMP1 PRECOMP0 (Bit 4, 3, 2):
These three bits select the value of write precompensation. The following tables show the
precompensation values for the combination of these bits.
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W83877F
PRECOM
PRECOMPENSATION DELAY
2
1
0
0
0
0
Default Delays
0
0
1
41.67 nS
0
1
0
83.34 nS
0
1
1
125.00 nS
1
0
0
166.67 nS
1
0
1
208.33 nS
1
1
0
250.00 nS
1
1
1
0.00 nS (disabled)
DATA RATE
DEFAULT PRECOMPENSATION DELAYS
250 KB/S
125 nS
300 KB/S
125 nS
500 KB/S
125 nS
1 MB/S
41.67 nS
DRATE1 DRATE0 (Bit 1, 0):
These two bits select the data rate of the FDC and reduced write current control.
00 500 KB/S (MFM), 250 KB/S (FM), RWC = 1.
01 300 KB/S (MFM), 150 KB/S (FM), RWC = 0.
10 250 KB/S (MFM), 125 KB/S (FM), RWC = 0.
11 1 MB/S (MFM), Illegal (FM), RWC = 1.
2.2.7 FIFO Register (R/W base address + 5)
The Data Register consists of four status registers in a stack with only one register presented to the
data bus at a time. This register stores data, commands, and parameters and provides diskette-drive
status information. Data bytes are passed through the data register to program or obtain results after
a command. In the W83877F, this register defaults to FIFO disabled mode after reset. The FIFO can
change its value and enable its operation through the CONFIGURE command.
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Publication Release Date: January 1996
Revision A2
W83877F
Status Register 0 (ST0)
7-6
5
3
4
2
1-0
US1, US0 Drive Select:
00 Drive A selected
01 Drive B selected
10 Drive C selected
11 Drive D selected
HD Head address:
1 Head selected
0 Head selected
NR Not Ready:
1 Drive is not ready
0 Drive is ready
EC Equipment Check:
1 When a fault signal is received from the FDD or the track
0 signal fails to occur after 77 step pulses
0 No error
SE Seek end:
1 seek end
0 seek error
IC Interrupt Code:
00 Normal termination of command
01 Abnormal termination of command
10 Invalid command issue
11 Abnormal termination because the ready signal from FDD changed state during command execution
Status Register 1 (ST1)
7
6
5
4
3
2
1
0
Missing Address Mark. 1 When the FDC cannot detect the data address mark
or the data address mark has been deleted.
NW (Not Writable). 1 If a write Protect signal is detected from the diskette drive during
execution of write data.
ND (No DATA). 1 If specified sector cannot be found during execution of a read, write or verifly data.
Not used. This bit is always 0.
OR (Over Rum). 1 If the FDC is not serviced by the host system within a certain time interval during data transfer.
DE (data Error).1 When the FDC detects a CRC error in either the ID field or the data field.
Not used. This bit is always 0.
EN (End of track). 1 When the FDC tries to access a sector beyond the final sector of a cylinder.
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W83877F
Status Register 2 (ST2)
7
6
4
5
3
1
2
0
MD (Missing Address Mark in Data Field).
1 If the FDC cannot find a data address mark
(or the address mark has been deleted)
when reading data from the media
0 No error
BC (Bad Cylinder)
1 Bad Cylinder
0 No error
SN (Scan Not satisfied)
1 During execution of the Scan command
0 No error
SH (Scan Equal Hit)
1 During execution of the Scan command, if the equal condition is satisfied
0 No error
WC (Wrong Cylinder)
1 Indicates wrong Cylinder
DD (Data error in the Data field)
1 If the FDC detects a CRC error in the data field
0 No error
CM (Control Mark)
1 During execution of the read data or scan command
0 No error
Not used. This bit is always 0
Status Register 3 (ST3)
6
7
4
5
2
3
1
0
US0 Unit Select 0
US1 Unit Select 1
HD Head Address
TS Two-Side
TO Track 0
RY Ready
WP Write Protected
FT Fault
2.2.8 Digital Input Register (DI Register) (Read base address + 7)
The Digital Input Register is an 8-bit read-only register used for diagnostic purposes. In a PC/XT or
AT only Bit 7 is checked by the BIOS. When the register is read, Bit 7 shows the complement of
DSKCHG , while other bits of the data bus remain in tri-state. Bit definitions are as follows:
7
6
5
4
3
2
x x
x
x
x x x
for the hard disk controller
x Reserved
During a read of this register, these bits are in tri-state
1
0
DSKCHG
In the PS/2 mode, the bit definitions are as follows:
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Publication Release Date: January 1996
Revision A2
W83877F
7
6
1
5
4
3
1
1
1
2
0
1
HIGH DENS
DRATE0
DRATE1
DSKCHG
DSKCHG (Bit 7):
This bit indicates the complement of the DSKCHG input.
Bit 6-3: These bits are always a logic 1 during a read.
DRATE1 DRATE0 (Bit 2, 1):
These two bits select the data rate of the FDC. Refer to the DR register bits 1 and 0 for the settings
corresponding to the individual data rates.
HIGH DENS (Bit 0):
0
500 KB/S or 1 MB/S data rate (high density FDD)
1
250 KB/S or 300 KB/S data rate
In the PS/2 Model 30 mode, the bit definitions are as follows:
7
6
5
4
0
0
0
3
2
1
0
DRATE0
DRATE1
NOPREC
DMAEN
DSKCHG
DSKCHG (Bit 7):
This bit indicates the status of DSKCHG input.
Bit 6-4: These bits are always a logic 1 during a read.
DMAEN (Bit 3):
This bit indicates the value of DO REGISTER bit 3.
NOPREC (Bit 2):
- 40 -
W83877F
This bit indicates the value of CC REGISTER NOPREC bit.
DRATE1 DRATE0 (Bit 1, 0):
These two bits select the data rate of the FDC.
2.2.9 Configuration Control Register (CC Register) (Write base address + 7)
This register is used to control the data rate. In the PC/AT and PS/2 mode, the bit definitions are as
follows:
7
6
5
4
3
2
x
x
x
x
x
x
1
0
DRATE0
DRATE1
X: Reserved
Bit 7-2: Reserved. These bits should be set to 0.
DRATE1 DRATE0 (Bit 1, 0):
These two bits select the data rate of the FDC.
In the PS/2 Model 30 mode, the bit definitions are as follows:
7
6
5
4
3
X
X
X
X
X
2
1
0
DRATE0
DRATE1
NOPREC
X: Reserved
Bit 7-3: Reserved. These bits should be set to 0.
NOPREC (Bit 2):
This bit indicates no precompensation. It has no function and can be set by software.
DRATE1 DRATE0 (Bit 1, 0):
These two bits select the data rate of the FDC.
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Publication Release Date: January 1996
Revision A2
W83877F
3.0 IDE
The IDE interface is essentially the AT bus ported to the hard disk drive. The hard disk controller
resides on the IDE hard disk drive. So the IDE interface provides only chip select signals and AT bus
signals between the IDE hard disk drive and ISA slot. Table 3-1 shows the IDE registers and their ISA
addresses.
Table 3-1
I/O ADDRESS
REGISTERS
OFFSET
READ
WRITE
CS0 base address + 0
Data Register
Data Register
CS0 base address + 1
Error Register
Write-Precomp
CS0 base address + 2
Sector Count
Sector Count
CS0 base address + 3
Sector Number
Sector Number
CS0 base address + 4
Cylinder LOW
Cylinder LOW
CS0 base address + 5
Cylinder HIGH
Cylinder HIGH
CS0 base address + 6
SDH Register
SDH Register
CS0 base address + 7
Status Register
Command Register
CS1 base address + 6
Alternate Status
Fixed Disk Control
3.1 IDE Decode Description
When the processor selects the addresses which match the ones specified in CR 21, the chip system
enables CS0 = LOW; otherwise, CS0 = HIGH. When the processor selects the address which
matches the one specified in CR22, the chip system enables CS1 = LOW; otherwise, CS1 = HIGH.
4.0 UART PORT
4.1 Universal Asynchronous Receiver/Transmitter (UART A, UART B)
The UARTs are used to convert parallel data into serial format on the transmit side and convert serial
data to parallel format on the receiver side. The serial format, in order of transmission and reception,
is a start bit, followed by five to eight data bits, a parity bit (if programmed) and one, one and half
(five-bit format only) or two stop bits. The UARTs are capable of handling divisors of 1 to 65535 and
producing a 16x clock for driving the internal transmitter logic. Provisions are also included to use this
16x clock to drive the receiver logic. The UARTs also support the MIDI data rate. Furthermore, the
UARTs also include complete modem control capability and a processor interrupt system that may be
software trailed to the computing time required to handle the communication link. The UARTs have a
FIFO mode to reduce the number of interrupts presented to the CPU. In each UART, there are 16byte FIFOs for both receive and transmit mode.
4.2 Register Address
- 42 -
W83877F
TABLE 4-1 UART Register Bit Map
Bit Number
Register Address Base
8
BDLAB = 0
8
BDLAB = 0
9
BDLAB = 0
A
Receiver
Buffer
Register
(Read Only)
RBR
Transmitter
Buffer Register
(Write Only)
TBR
Interrupt Control
Register
ICR
0
1
2
3
4
5
6
7
RX Data
RX Data
RX Data
RX Data
RX Data
RX Data
RX Data
RX Data
Bit 0
Bit 1
Bit 2
Bit 3
Bit 4
Bit 5
Bit 6
Bit 7
TX Data
TX Data
TX Data
TX Data
TX Data
TX Data
TX Data
TX Data
Bit 0
Bit 1
Bit 2
Bit 3
Bit 4
Bit 5
Bit 6
Bit 7
RBR Data
Ready
Interrupt
Enable
(ERDRI)
TBR
Empty
Interrupt
Enable
(ETBREI)
USR
Interrupt
Enable
HSR
Interrupt
Enable
0
0
0
0
(EUSRI)
(EHSRI)
"0" if
Interrupt
Pending
Interrupt
Status
Interrupt
Status
Interrupt
Status
0
0
Bit (0)
Bit (1)
Bit (2)**
Interrupt Status
Register
(Read Only)
ISR
A
UART FIFO
Control
Register
(Write Only)
UFR
FIFO
Enable
RCVR
FIFO
Reset
XMIT
FIFO
Reset
DMA
Mode
Select
Reserved
B
UART Control
Register
UCR
Data
Length
Select
Bit 0
(DLS0)
Data
Length
Select
Bit 1
(DLS1)
Multiple
Stop Bits
Enable
Parity
Bit
Enable
(MSBE)
FIFOs
FIFOs
Enabled
Enabled
**
**
Reversed
RX
Interrupt
Active Level
(LSB)
RX
Interrupt
Active Level
(MSB)
Even
Parity
Enable
Parity
Bit Fixed
Enable
Set
Silence
Enable
(PBE)
(EPE)
PBFE)
(SSE)
Baudrate
Divisor
Latch
Access Bit
(BDLAB)
C
Handshake
Control
Register
HCR
Data
Terminal
Ready
(DTR)
Request
to
Send
(RTS)
Loopback
RI
Input
IRQ
Enable
Internal
Loopback
Enable
0
0
0
D
UART Status
Register
USR
RBR Data
Ready
Overrun
Error
Parity Bit
Error
TSR
Empty
(OER)
(PBER)
Silent
Byte
Detected
(SBD)
TBR
Empty
(RDR)
No Stop
Bit
Error
(NSER)
(TBRE)
(TSRE)
RX FIFO
Error
Indication
(RFEI) **
CTS
Toggling
DSR
Toggling
RI Falling
Edge
DCD
Toggling
Clear
to Send
Data Set
Ready
Ring
Indicator
E
Handshake
Status Register
HSR
(TCTS)
(TDSR)
(FERI)
(TDCD)
(CTS)
(DSR)
(RI)
Data Carrier
Detect
(DCD)
F
User Defined
Register
UDR
Bit 0
Bit 1
Bit 2
Bit 3
Bit 4
Bit 5
Bit 6
Bit 7
8
Baudrate Divisor
Latch Low
BLL
Bit 0
Bit 1
Bit 2
Bit 3
Bit 4
Bit 5
Bit 6
Bit 7
Baudrate
Divisor Latch
High
BHL
Bit 8
Bit 9
Bit 10
Bit 11
Bit 12
Bit 13
Bit 14
Bit 15
BDLAB = 1
9
BDLAB = 1
*: Bit 0 is the least significant bit. The least significant bit is the first bit serially transmitted or received.
**: These bits are always 0 in 16450 Mode.
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Publication Release Date: January 1996
Revision A2
W83877F
4.2.1 UART Control Register (UCR) (Read/Write)
The UART Control Register controls and defines the protocol for asynchronous data communications,
including data length, stop bit, parity, and baud rate selection.
7
6
5
4
3
2
1
0
Data length select bit 0 (DLS0)
Data length select bit 1(DLS1)
Multiple stop bits enable (MSBE)
Parity bit enable (PBE)
Even parity enable (EPE)
Parity bit fixed enable (PBFE)
Set silence enable (SSE)
Baudrate divisor latch access bit (BDLAB)
Bit 7: BDLAB. When this bit is set to a logical 1, designers can access the divisor (in 16-bit
binary format) from the divisor latches of the baudrate generator during a read or write
operation. When this bit is reset, the Receiver Buffer Register, the Transmitter Buffer Register,
or the Interrupt Control Register can be accessed.
Bit 6:
SSE. A logical 1 forces the Serial Output (SOUT) to a silent state (a logical 0). Only SOUT
is affected by this bit; the transmitter is not affected.
Bit 5: PBFE. When PBE and PBFE of UCR are both set to a logical 1,
(1) if EPE is a logical 1, the parity bit is fixed as a logical 0 to transmit and check.
(2) if EPE is a logical 0, the parity bit is fixed as a logical 1 to transmit and check.
Bit 4:
EPE. This bit describes the number of logic 1's in the data word bits and parity bit only when
bit 3 is programmed. When this bit is set, an even number of logic 1's are sent or checked.
When the bit is reset, an odd number of logic 1's are sent or checked.
Bit 3:
PBE. When this bit is set, the position between the last data bit and the stop bit of the SOUT
will be stuffed with the parity bit at the transmitter. For the receiver, the parity bit in the same
position as the transmitter will be detected.
Bit 2:
MSBE. This bit defines the number of stop bits in each serial character that is transmitted or
received.
(1) If MSBE is set to a logical 0, one stop bit is sent and checked.
(2) If MSBE is set to a logical 1, and data length is 5 bits, one and a half stop bits are sent and
checked.
(3) If MSBE is set to a logical 1, and data length is 6, 7, or 8 bits, two stop bits are sent and
checked.
Bits 0 and 1: DLS0, DLS1. These two bits define the number of data bits that are sent or checked in
each serial character.
TABLE 4-2 WORD LENGTH DEFINITION
- 44 -
W83877F
DLS1
DLS0
DATA LENGTH
0
0
5 bits
0
1
6 bits
1
0
7 bits
1
1
8 bits
4.2.2 UART Status Register (USR) (Read/Write)
This 8-bit register provides information about the status of the data transfer during communication.
7
6
5
4
3
2
1
0
RBR Data ready (RDR)
Overrun error (OER)
Parity bit error (PBER)
No stop bit error (NSER)
Silent byte detected (SBD)
Transmitter Buffer Register empty (TBRE)
Transmitter Shift Register empty (TSRE)
RX FIFO Error Indication (RFEI)
Bit 7: RFEI. In 16450 mode, this bit is always set to a logic 0. In 16550 mode, this bit is set to a logic
1 when there is at least one parity bit error, no stop bit error or silent byte detected in the FIFO.
In 16550 mode, this bit is cleared by reading from the USR if there are no remaining errors left
in the FIFO.
Bit 6: TSRE. In 16450 mode, when TBR and TSR are both empty, this bit will be set to a logical 1. In
16550 mode, if the transmit FIFO and TSR are both empty, it will be set to a logical 1. Other
thanthese two cases, this bit will be reset to a logical 0.
Bit 5: TBRE. In 16450 mode, when a data character is transferred from TBR to TSR, this bit will be
set to a logical 1. If ETREI of ICR is a logical 1, an interrupt will be generated to notify the CPU
to write the next data. In 16550 mode, this bit will be set to a logical 1 when the transmit FIFO is
empty. It will be reset to a logical 0 when the CPU writes data into TBR or FIFO.
Bit 4: SBD. This bit is set to a logical 1 to indicate that received data are kept in silent state for a full
word time, including start bit, data bits, parity bit, and stop bits. In 16550 mode, it indicates the
same condition for the data on top of the FIFO. When the CPU reads USR, it will clear this bit
to a logical 0.
Bit 3: NSER. This bit is set to a logical 1 to indicate that the received data have no stop bit. In 16550
mode, it indicates the same condition for the data on top of the FIFO. When the CPU reads
USR, it will clear this bit to a logical 0.
Bit 2: PBER. This bit is set to a logical 1 to indicate that the parity bit of received data is wrong. In
16550 mode, it indicates the same condition for the data on top of the FIFO. When the CPU
reads USR, it will clear this bit to a logical 0.
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Publication Release Date: January 1996
Revision A2
W83877F
Bit 1: OER. This bit is set to a logical 1 to indicate received data have been overwritten by the next
received data before they were read by the CPU. In 16550 mode, it indicates the same
condition instead of FIFO full. When the CPU reads USR, it will clear this bit to a logical 0.
Bit 0: RDR. This bit is set to a logical 1 to indicate received data are ready to be read by the CPU in
the RBR or FIFO. After no data are left in the RBR or FIFO, the bit will be reset to a logical 0.
4.2.3 Handshake Control Register (HCR) (Read/Write)
This register controls the pins of the UART used for handshaking peripherals such as modem, and
controls the diagnostic mode of the UART.
7
6
5
0
0
0
4
3
2
1
0
Data terminal ready (DTR)
Request to send (RTS)
Loopback RI input
IRQ enable
Internal loopback enable
Bit 4: When this bit is set to a logical 1, the UART enters diagnostic mode by an internal loopback, as
follows:
(1) SOUT is forced to a logical 1, and SIN is isolated from the communication link instead of
the
TSR.
(2) Modem output pins are set to their inactive state.
(3) Modem input pins are isolated from the communication link and connect internally as DTR
(bit 0 of HCR) → DSR, RTS ( bit 1 of HCR) → CTS, Loopback RI input ( bit 2 of HCR) →
RI and IRQ enable ( bit 3 of HCR) → DCD .
Aside from the above connections, the UART operates normally. This method allows the
CPU to test the UART in a convenient way.
Bit 3: The UART interrupt output is enabled by setting this bit to a logic 1. In the diagnostic mode this
bit is internally connected to the modem control input DCD .
Bit 2: This bit is used only in the diagnostic mode. In the diagnostic mode this bit is internally
connected to the modem control input RI .
Bit 1: This bit controls the RTS output. The value of this bit is inverted and output to RTS .
Bit 0: This bit controls the DTR output. The value of this bit is inverted and output to DTR .
- 46 -
W83877F
4.2.4 Handshake Status Register (HSR) (Read/Write)
This register reflects the current state of four input pins for handshake peripherals such as a modem
and records changes on these pins.
7
6
5
4
3
2
1
0
CTS toggling (TCTS)
DSR toggling (TDSR)
RI falling edge (FERI)
DCD toggling (TDCD)
Clear to send (CTS)
Data set ready (DSR)
Ring indicator (RI)
Data carrier detect (DCD)
Bit 7: This bit is the opposite of the DCD input. This bit is equivalent to bit 3 of HCR in loopback
mode.
Bit 6: This bit is the opposite of the RI input. This bit is equivalent to bit 2 of HCR in loopback mode.
Bit 5: This bit is the opposite of the DSR input. This bit is equivalent to bit 0 of HCR in loopback
mode.
Bit 4: This bit is the opposite of the CTS input. This bit is equivalent to bit 1 of HCR in loopback
mode.
Bit 3: TDCD. This bit indicates that the DCD pin has changed state after HSR was read by the CPU.
Bit 2: FERI. This bit indicates that the RI pin has changed from low to high state after HSR was read
by the CPU.
Bit 1: TDSR. This bit indicates that the DSR pin has changed state after HSR was read by the CPU.
Bit 0: TCTS. This bit indicates that the CTS pin has changed state after HSR was read by the CPU.
4.2.5 UART FIFO Control Register (UFR) (Write only)
This register is used to control the FIFO functions of the UART.
- 47 -
Publication Release Date: January 1996
Revision A2
W83877F
7
6
5
4
3
2
1
0
FIFO enable
Receiver FIFO reset
Transmitter FIFO reset
DMA mode select
Reserved
Reserved
RX interrupt active level (LSB)
RX interrupt active level (MSB)
Bit 6, 7: These two bits are used to set the active level for the receiver FIFO interrupt. For example, if
the interrupt active level is set as 4 bytes, once there are more than 4 data characters in the
receiver FIFO, the interrupt will be activated to notify the CPU to read the data from the
FIFO.
TABLE 4-3 FIFO TRIGGER LEVEL
BIT 7
BIT 6
RX FIFO INTERRUPT ACTIVE LEVEL (BYTES)
0
0
01
0
1
04
1
0
08
1
1
14
Bit 4, 5: Reserved
Bit 3: When this bit is programmed to logic 1, the DMA mode will change from mode 0 to mode 1 if
UFR bit 0 = 1.
Bit 2: Setting this bit to a logical 1 resets the TX FIFO counter logic to initial state. This bit will clear to
a logical 0 by itself after being set to a logical 1.
Bit 1: Setting this bit to a logical 1 resets the RX FIFO counter logic to initial state. This bit will clear to
a logical 0 by itself after being set to a logical 1.
Bit 0: This bit enables the 16550 (FIFO) mode of the UART. This bit should be set to a logical 1
before
other bits of UFR are programmed.
4.2.6 Interrupt Status Register (ISR) (Read only)
This register reflects the UART interrupt status, which is encoded by different interrupt sources into 3
bits.
- 48 -
W83877F
7
6
5
4
0
0
3
2
1
0
0 if interrupt pending
Interrupt Status bit 0
Interrupt Status bit 1
Interrupt Status bit 2
FIFOs enabled
FIFOs enabled
Bit 7, 6: These two bits are set to a logical 1 when UFR bit 0 = 1.
Bit 5, 4: These two bits are always logic 0.
Bit 3: In 16450 mode, this bit is 0. In 16550 mode, both bit 3 and 2 are set to a logical 1 when a
time-out interrupt is pending.
Bit 2, 1: These two bits identify the priority level of the pending interrupt, as shown in the table below.
Bit 0: This bit is a logical 1 if there is no interrupt pending. If one of the interrupt sources has
occurred, this bit will be set to a logical 0.
TABLE 4-4 INTERRUPT CONTROL FUNCTION
ISR
INTERRUPT SET AND FUNCTION
Bit
3
Bit
2
Bit
1
Bit
0
Interrupt
priority
0
0
0
1
-
0
1
1
0
First
0
1
0
0
Second
Interrupt Type
-
Interrupt Source
Clear Interrupt
No Interrupt pending
2. PBER =1
-
UART Receive
Status
1. OER = 1
Read USR
RBR Data Ready
1. RBR data ready
1. Read RBR
2. FIFO interrupt active level
reached
2. Read RBR until FIFO
data under active level
3. NSER = 1 4. SBD = 1
1
1
0
0
Second
FIFO Data Timeout
Data present in RX FIFO for 4
characters period of time since last
access of RX FIFO.
Read RBR
0
0
1
0
Third
TBR Empty
TBR empty
1. Write data into TBR
2. Read ISR (if priority is
third)
0
0
0
0
Fourth
Handshake status
1. TCTS = 1
2. TDSR = 1
3. FERI = 1
4. TDCD = 1
Read HSR
** Bit 3 of ISR is enabled when bit 0 of UFR is logical 1.
- 49 -
Publication Release Date: January 1996
Revision A2
W83877F
4.2.7 Interrupt Control Register (ICR) (Read/Write)
This 8-bit register allows the five types of controller interrupts to activate the interrupt output signal
separately. The interrupt system can be totally disabled by resetting bits 0 through 3 of the Interrupt
Control Register (ICR). A selected interrupt can be enabled by setting the appropriate bits of this
register to a logical 1.
7
6
5
4
0
0
0
0
3
2
1
0
RBR data ready interrupt enable (ERDRI)
TBR empty interrupt enable (ETBREI)
UART receive status interrupt enable (EUSRI)
Handshake status interrupt enable (EHSRI)
Bit 7-4: These four bits are always logic 0.
Bit 3: EHSRI. Setting this bit to a logical 1 enables the handshake status register interrupt.
Bit 2: EUSRI. Setting this bit to a logical 1 enables the UART status register interrupt.
Bit 1: ETBREI. Setting this bit to a logical 1 enables the TBR empty interrupt.
Bit 0: ERDRI. Setting this bit to a logical 1 enables the RBR data ready interrupt.
4.2.8 Programmable Baud Generator (BLL/BHL) (Read/Write)
Two 8-bit registers, BLL and BHL, compose a programmable baud generator that uses 24 MHz to
generate a 1.8461 MHz frequency and divides it by a divisor from 1 to 216-1. The output frequency of
the baud generator is the baud rate multiplied by 16, and this is the base frequency for the transmitter
and receiver. The table below illustrates the use of the baud generator with a frequency of 1.8461
MHz. In high-speed UART mode (refer to CR0C bit7 and CR0C bit6), the programmable baud
generator directly uses 24 MHz and the same divisor as the normal speed divisor. In high-speed
mode, the data transmission rate can be as high as 1.5M bps.
4.2.9 User-defined Register (UDR) (Read/Write)
This is a temporary register that can be accessed and defined by the user.
- 50 -
W83877F
TABLE 4-5 BAUD RATE TABLE
BAUD RATE USING 24 MHZ TO GENERATE 1.8461 MHZ
Desired Baud Rate
Decimal divisor used to
generate 16X clock
Percent error difference between
desired and actual
50
2304
**
75
1536
**
110
1047
0.18%
134.5
857
0.099%
150
768
**
300
384
**
600
192
**
1200
96
**
1800
64
**
2000
58
0.53%
2400
48
**
3600
32
**
4800
24
**
7200
16
**
9600
12
**
19200
6
**
38400
3
**
57600
2
**
115200
1
**
230400
104*
**
460800
52*
**
921600
26*
**
1.5M
1*
0%
* Only use in high speed mode (refer CR0C bit7 and CR0C bit6).
** The percentage error for all baud rates, except where indicated otherwise, is 0.16%.
- 51 -
Publication Release Date: January 1996
Revision A2
W83877F
5.0 PARALLEL PORT
5.1 Printer Interface Logic
The parallel port of the W83877F makes possible the attachment of various devices that accept eight
bits of parallel data at standard TTL level. The W83877F supports an IBM XT/AT compatible parallel
port (SPP), bi-directional parallel port (BPP), Enhanced Parallel Port (EPP), Extended Capabilities
Parallel Port (ECP), Extension FDD mode (EXTFDD), Extension 2FDD mode (EXT2FDD), Extension
Adapter mode (EXTADP), and JOYSTICK mode on the parallel port. Refer to the configuration
registers for more information on disabling, power-down, and on selecting the mode of operation.
Table 5-1 shows the pin definitions for different modes of the parallel port.
TABLE 5-1 PARALLEL PORT CONNECTOR AND PIN DEFINITIONS
HOST
CONNECTOR
PIN NUMBER
OF W83877F
PIN
ATTRIBUTE
SPP
EPP
ECP
1
19
O
nSTB
nWrite
2−9
9−14, 16−17
I/O
PD<0:7>
PD<0:7>
10
26
I
nACK
Intr
11
24
I
BUSY
nWait
12
27
I
PE
PE
13
28
I
SLCT
Select
SLCT
14
20
O
nAFD
nDStrb
nAFD, HostAck2
15
29
I
nERR
nError
nFault1, nPeriphRequest2
16
21
O
nINIT
nInit
17
22
O
nSLIN
nAStrb
nSTB
PD<0:7>
nACK
BUSY, PeriphAck2
PEerror, nAckReverse2
nINIT1, nReverseRqst2
nSLIN1, 2
Notes:
n<name > : Active Low
1. Compatible Mode
2. High Speed Mode
3. For more information, refer to the IEEE 1284 standard.
HOST
CONNECTOR
PIN NUMBER
OF W83877
PIN
ATTRIBUTE
SPP
PIN
ATTRIBUTE
EXT2FDD
PIN
ATTRIBUTE
EXTFDD
1
2
19
O
nSTB
---
---
---
---
9
I/O
PD0
I
INDEX 2
I
INDEX 2
3
10
I/O
PD1
I
TRAK02
I
TRAK02
4
11
I/O
PD2
I
WP2
I
WP2
5
12
I/O
PD3
I
RDATA2
I
RDATA2
6
13
I/O
PD4
I
DSKCHG2
I
DSKCHG2
7
14
I/O
PD5
---
---
---
---
8
15
I/O
PD6
OD
MOA2
---
---
- 52 -
W83877F
TABLE 5-1, continued
HOST
CONNECTOR
PIN NUMBER
OF W83877
PIN
ATTRIBUTE
SPP
PIN
ATTRIBUTE
EXT2FDD
PIN
ATTRIBUTE
EXTFDD
9
16
I/O
PD7
OD
DSA2
---
---
10
26
I
nACK
OD
DSB2
OD
DSB2
11
24
I
BUSY
OD
MOB2
OD
MOB2
12
27
I
PE
OD
WD2
OD
WD2
13
28
I
SLCT
OD
WE2
OD
WE2
14
20
O
nAFD
OD
RWC2
OD
RWC2
15
29
I
nERR
OD
NERR2
OD
NERR2
16
21
O
nINIT
OD
DIR2
OD
DIR2
17
22
O
nSLIN
OD
STEP2
OD
STEP2
HOST
CONNECTOR
PIN NUMBER
OF W83877
PIN
ATTRIBUTE
SPP
PIN
ATTRIBUTE
EXTADP
MODE
PIN
ATTRIBUTE
JOYSTICK
MODE
1
19
O
nSTB
O
XWR
O
VDD
2
9
I/O
PD0
I/O
XD0
I
JP0
3
10
I/O
PD1
I/O
XD1
I
JP1
4
11
I/O
PD2
I/O
XD2
I
---
5
12
I/O
PD3
I/O
XD3
I
---
6
13
I/O
PD4
I/O
XD4
I
JB0
7
14
I/O
PD5
I/O
XD5
I
JB1
8
15
I/O
PD6
I/O
XD6
I
---
9
16
I/O
PD7
I/O
XD7
I
---
10
26
I
nACK
I
XDRQ
I
---
11
24
I
BUSY
I
XIRQ
I
---
12
27
I
PE
O
XA0
I
---
13
28
I
SLCT
O
XA1
I
---
14
20
O
nAFD
O
XRD
O
VDD
15
29
I
nERR
O
XA2
I
---
16
21
O
nINIT
O
XDACK
O
VDD
17
22
O
nSLIN
O
TC
O
VDD
- 53 -
Publication Release Date: January 1996
Revision A2
W83877F
5.2 Enhanced Parallel Port (EPP)
TABLE 5-2 PRINTER MODE AND EPP REGISTER ADDRESS
A2
0
0
0
0
0
1
1
1
1
A1
0
0
1
1
1
0
0
1
1
A0
0
1
0
0
1
0
1
0
1
REGISTER
Data port (R/W)
Printer status buffer (Read)
Printer control latch (Write)
Printer control swapper (Read)
EPP address port (R/W)
EPP data port 0 (R/W)
EPP data port 1 (R/W)
EPP data port 2 (R/W)
EPP data port 2 (R/W)
NOTE
1
1
1
1
2
2
2
2
2
Notes:
1. These registers are available in all modes.
2. These registers are available only in EPP mode.
5.2.1 Data Swapper
The system microprocessor can read the contents of the printer's data latch by reading the data
swapper.
5.2.2 Printer Status Buffer
The system microprocessor can read the printer status by reading the address of the printer status
buffer. The bit definitions are as follows:
7
6
5
4
3
2
1
1
1
0
TMOUT
ERROR
SLCT
PE
ACK
BUSY
Bit 7: This signal is active during data entry, when the printer is off-line during printing, when the print
head is changing position, or during an error state. When this signal is active, the printer is
busy
and cannot accept data.
Bit 6: This bit represents the current state of the printer's ACK signal. A 0 means the printer has
received a character and is ready to accept another. Normally, this signal will be active for
approximately 5 microseconds before BUSY stops.
Bit 5: A 1 means the printer has detected the end of paper.
Bit 4: A 1 means the printer is selected.
Bit 3: A 0 means the printer has encountered an error condition.
- 54 -
W83877F
Bit 1, 2: These two bits are not implemented and are logic one during a read of the status register.
Bit 0: This bit is valid in EPP mode only. It indicates that a 10 µS timeout has occurred on the EPP
bus. A logic 0 means that no time-out error has occurred; a logic 1 means that a time-out error
has been detected. Writing a logic 1 to this bit will clear the time-out status bit; writing a logic 0
has no effect.
5.2.3 Printer Control Latch and Printer Control Swapper
The system microprocessor can read the contents of the printer control latch by reading the printer
control swapper. Bit definitions are as follows:
7
6
1
1
5
4
3
2
1
0
STROBE
AUTO FD
INIT
SLCT IN
IRQ ENABLE
DIR
Bit 7, 6: These two bits are a logic one during a read. They can be written.
Bit 5: Direction control bit
W83757 (SPP) mode: When this bit is a logic 1, pin PRTOE is high, and PRTBEN (CR3 bit 7)
is low, the parallel port is in input mode (read); when this bit is a logic 0, the parallel port is in
output mode (write). This bit is write-only.
BPP mode: When this bit is a logic 1, the parallel port is in input mode (read); when it is a logic
0, the parallel port is in output mode (write). This bit can be read and written.
Bit 4: A 1 in this position allows an interrupt to occur when ACK changes from low to high.
Bit 3: A 1 in this bit position selects the printer.
Bit 2: A 0 starts the printer (50 microsecond pulse, minimum).
Bit 1: A 1 causes the printer to line-feed after a line is printed.
Bit 0: A 0.5 microsecond minimum high active pulse clocks data into the printer. Valid data must be
present for a minimum of 0.5 microseconds before and after the strobe pulse.
5.2.4 EPP Address Port
The address port is available only in EPP mode. Bit definitions are as follows:
- 55 -
Publication Release Date: January 1996
Revision A2
W83877F
7
6
5
4
3
2
1
0
PD0
PD1
PD2
PD3
PD4
PD5
PD6
PD7
The contents of DB0-DB7 are buffered (non-inverting) and output to ports PD0-PD7 during a write
operation. The leading edge of IOW causes an EPP address write cycle to be performed, and the
trailing edge of IOW latches the data for the duration of the EPP write cycle.
PD0-PD7 ports are read during a read operation. The leading edge of IOR causes an EPP address
read cycle to be performed and the data to be output to the host CPU.
5.2.5 EPP Data Port 0-3
These four registers are available only in EPP mode. Bit definitions of each data port are as follows:
7
6
5
4
3
2
1
0
PD0
PD1
PD2
PD3
PD4
PD5
PD6
PD7
When accesses are made to any EPP data port, the contents of DB0-DB7 are buffered (noninverting) and output to the ports PD0-PD7 during a write operation. The leading edge of IOW causes
an EPP data write cycle to be performed, and the trailing edge of IOW latches the data for the
duration of the EPP write cycle.
During a read operation, ports PD0-PD7 are read, and the leading edge of IOR causes an EPP read
cycle to be performed and the data to be output to the host CPU.
- 56 -
W83877F
5.2.6 Bit Map of Parallel Port and EPP Registers
REGISTER
7
6
5
4
3
2
1
0
PD7
PD6
PD5
PD4
PD3
PD2
PD1
PD0
BUSY
ACK
PE
SLCT
ERROR
1
1
TMOUT
Control Swapper (Read)
1
1
1
IRQEN
SLIN
INIT
AUTOFD
STROBE
Control Latch (Write)
1
1
DIR
IRQ
SLIN
INIT
AUTOFD
STROBE
EPP Address Port
(R/W)
PD7
PD6
PD5
PD4
PD3
PD2
PD1
PD0
EPP Data Port 0 (R/W)
PD7
PD6
PD5
PD4
PD3
PD2
PD1
PD0
EPP Data Port 1 (R/W)
PD7
PD6
PD5
PD4
PD3
PD2
PD1
PD0
EPP Data Port 2 (R/W)
PD7
PD6
PD5
PD4
PD3
PD2
PD1
PD0
EPP Data Port 3 (R/W)
PD7
PD6
PD5
PD4
PD3
PD2
PD1
PD0
Data Port (R/W)
Status Buffer (Read)
5.2.7 EPP Pin Descriptions
EPP NAME
TYPE
EPP DESCRIPTION
nWrite
O
Denotes an address or data read or write operation.
PD<0:7>
I/O
Bi-directional EPP address and data bus.
Intr
I
Used by peripheral device to interrupt the host.
nWait
I
Inactive to acknowledge that data transfer is completed. Active to
indicate that the device is ready for the next transfer.
PE
I
Paper end; same as SPP mode.
Select
I
Printer selected status; same as SPP mode.
nDStrb
O
This signal is active low. It denotes a data read or write operation.
nError
I
Error; same as SPP mode.
nInits
O
This signal is active low. When it is active, the EPP device is reset to its
initial operating mode.
nAStrb
O
This signal is active low. It denotes an address read or write operation.
- 57 -
Publication Release Date: January 1996
Revision A2
W83877F
5.2.8 EPP Operation
When the EPP mode is selected in the configuration register, the standard and bi-directional modes
are also available. The PDx bus is in the standard or bi-directional mode when no EPP read, write, or
address cycle is currently being executed. In this condition all output signals are set by the SPP
Control Port and the direction is controlled by DIR of the Control Port.
A watchdog timer is required to prevent system lockup. The timer indicates that more than 10 µS
have elapsed from the start of the EPP cycle to the time WAIT is deasserted. The current EPP cycle
is aborted when a time-out occurs. The time-out condition is indicated in Status bit 0.
EPP Operation
The EPP operates on a two-phase cycle. First, the host selects the register within the device for
subsequent operations. Second, the host performs a series of read and/or write byte operations to the
selected register. Four operations are supported on the EPP: Address Write, Data Write, Address
Read, and Data Read. All operations on the EPP device are performed asynchronously.
EPP Version 1.9 Operation
The EPP read/write operation can be completed under the following conditions:
a. If the nWait is active low, when the read cycle (nWrite inactive high, nDStrb/nAStrb active low) or
write cycle (nWrite active low, nDStrb/nAStrb active low) starts, the read/write cycle proceeds
normally and will be completed when nWait goes inactive high.
b. If nWait is inactive high, the read/write cycle will not start. It must wait until nWait changes to
active low, at which time it will start as described above.
EPP Version 1.7 Operation
The EPP read/write cycle can start without checking whether nWait is active or inactive. Once the
read/write cycle starts, however, it will not terminate until nWait changes from active low to inactive
high.
5.3 Extended Capabilities Parallel (ECP) Port
This port is software and hardware compatible with existing parallel ports, so it may be used as a
standard printer mode if ECP is not required. It provides an automatic high burst-bandwidth channel
that supports DMA for ECP in both the forward (host to peripheral) and reverse (peripheral to host)
directions.
Small FIFOs are used in both forward and reverse directions to improve the maximum bandwidth
requirement. The size of the FIFO is 16 bytes. The ECP port supports an automatic handshake for
the standard parallel port to improve compatibility mode transfer speed.
The ECP port supports run-length-encoded (RLE) decompression (required) in hardware.
Compression is accomplished by counting identical bytes and transmitting an RLE byte that indicates
how many times the next byte is to be repeated. Hardware support for compression is optional.
For more information about the ECP Protocol, refer to the Extended Capabilities Port Protocol and
ISA Interface Standard.
- 58 -
W83877F
5.3.1 ECP Register and Mode Definitions
NAME
ADDRESS
I/O
ECP MODES
FUNCTION
data
Base+000h
R/W
000-001
ecpAFifo
Base+000h
R/W
011
ECP FIFO (Address)
dsr
Base+001h
R
All
Status Register
dcr
Base+002h
R/W
All
Control Register
cFifo
Base+400h
R/W
010
Parallel Port Data FIFO
ecpDFifo
Base+400h
R/W
011
ECP FIFO (DATA)
tFifo
Base+400h
R/W
110
Test FIFO
cnfgA
Base+400h
R
111
Configuration Register A
cnfgB
Base+401h
R/W
111
Configuration Register B
ecr
Base+402h
R/W
All
Extended Control Register
Data Register
Note: The base addresses are specified by CR23, which are determined by configuration register or hardware setting.
MODE
DESCRIPTION
000
SPP mode
001
PS/2 Parallel Port mode
010
Parallel Port Data FIFO mode
011
ECP Parallel Port mode
100
EPP mode (If this option is enabled in the CR9 and CR0 to select ECP/EPP mode)
101
Reserved
110
Test mode
111
Configuration mode
Note: The mode selection bits are bit 7-5 of the Extended Control Register.
5.3.2 Data and ecpAFifo Port
Modes 000 (SPP) and 001 (PS/2) (Data Port)
During a wite operation, the Data Register latches the contents of the data bus on the rising edge of
the input. The contents of this register are output to the PD0-PD7 ports. During a read operation,
ports PD0-PD7 are read and output to the host. The bit definitions are as follows:
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7
6
5
4
3
2
1
0
PD0
PD1
PD2
PD3
PD4
PD5
PD6
PD7
Mode 011 (ECP FIFO-Address/RLE)
A data byte written to this address is placed in the FIFO and tagged as an ECP Address/RLE. The
hardware at the ECP port transmits this byte to the peripheral automatically. The operation of this
register is defined only for the forward direction. The bit definitions are as follows:
7
6
5
4
3
2
1
0
Address or RLE
Address/RLE
5.3.3 Device Status Register (DSR)
These bits are at low level during a read of the Printer Status Register. The bits of this status register
are defined as follows:
7
6
5
4
3
2
1
1
1
0
1
nFault
Select
PError
nAck
nBusy
Bit 7: This bit reflects the complement of the Busy input.
Bit 6: This bit reflects the nAck input.
Bit 5: This bit reflects the PError input.
Bit 4: This bit reflects the Select input.
Bit 3: This bit reflects the nFault input.
Bit 2-0: These three bits are not implemented and are always logic one during a read.
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W83877F
5.3.4 Device Control Register (DCR)
The bit definitions are as follows:
7
1
6
5
4
3
2
1
0
1
strobe
autofd
nInit
SelectIn
ackIntEn
Direction
Bit 6, 7: These two bits are logic one during a read and cannot be written.
Bit 5: This bit has no effect and the direction is always out if mode = 000 or mode = 010. Direction is
valid in all other modes.
0
the parallel port is in output mode.
1
the parallel port is in input mode.
Bit 4: Interrupt request enable. When this bit is set to a high level, it may be used to enable interrupt
requests from the parallel port to the CPU due to a low to high transition on the ACK input.
Bit 3: This bit is inverted and output to the SLIN output.
0
The printer is not selected.
1
The printer is selected.
Bit 2: This bit is output to the INIT output.
Bit 1: This bit is inverted and output to the AFD output.
Bit 0: This bit is inverted and output to the STB output.
5.3.5 cFifo (Parallel Port Data FIFO) Mode = 010
This mode is defined only for the forward direction. The standard parallel port protocol is used by a
hardware handshake to the peripheral to transmit bytes written or DMAed from the system to this
FIFO. Transfers to the FIFO are byte aligned.
5.3.6 ecpDFifo (ECP Data FIFO) Mode = 011
When the direction bit is 0, bytes written or DMAed from the system to this FIFO are transmitted by a
hardware handshake to the peripheral using the ECP parallel port protocol. Transfers to the FIFO are
byte aligned.
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When the direction bit is 1, data bytes from the peripheral are read under automatic hardware
handshake from ECP into this FIFO. Reads or DMAs from the FIFO will return bytes of ECP data to
the system.
5.3.7 tFifo (Test FIFO Mode) Mode = 110
Data bytes may be read, written, or DMAed to or from the system to this FIFO in any direction.
Data in the tFIFO will not be transmitted to the parallel port lines. However, data in the tFIFO may be
displayed on the parallel port data lines.
5.3.8 cnfgA (Configuration Register A) Mode = 111
This register is a read-only register. When it is read, 10H is returned. This indicates to the system that
this is an 8-bit implementation.
5.3.9 cnfgB (Configuration Register B) Mode = 111
The bit definitions are as follows:
7
6
5
4
3
2
1
1
0
1
1
IRQx 0
IRQx 1
IRQx 2
intrValue
compress
Bit 7: This bit is read-only. It is at low level during a read. This means that this chip does not support
hardware RLE compression.
Bit 6: Returns the value on the ISA IRQ line to determine possible conflicts.
Bit 5-3: Reflect the IRQ resource assigned for ECP port.
cnfgB[5:3]
000
001
010
011
100
101
110
111
IRQ resource
reflect other IRQ resources selected by PnP register (default)
IRQ7
IRQ9
IRQ10
IRQ11
IRQ14
IRQ15
IRQ5
Bit 2-0: These five bits are at high level during a read and can be written.
5.3.11 ecr (Extended Control Register) Mode = all
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W83877F
This register controls the extended ECP parallel port functions. The bit definitions are follows:
7
6
5
4
3
2
1
0
empty
full
service Intr
dmaEn
nErrIntrEn
MODE
MODE
MODE
Bit 7-5: These bits are read/write and select the mode.
000
Standard Parallel Port mode. The FIFO is reset in this mode.
001
PS/2 Parallel Port mode. This is the same as 000 except that direction may be
used to tri-state the data lines and reading the data register returns the value on the
data lines and not the value in the data register.
010
Parallel Port FIFO mode. This is the same as 000 except that bytes are written or
DMAed to the FIFO. FIFO data are automatically transmitted using the standard
parallel port protocol. This mode is useful only when direction is 0.
011
ECP Parallel Port Mode. When the direction is 0 (forward direction), bytes placed
into the ecpDFifo and bytes written to the ecpAFifo are placed in a single FIFO and
transmitted automatically to the peripheral using ECP Protocol. When the direction
is 1 (reverse direction) bytes are moved from the ECP parallel port and packed into
bytes in the ecpDFifo.
100
Selects EPP Mode. In this mode, EPP is selected if the EPP supported option is
selected.
101
Reserved.
110
Test Mode. The FIFO may be written and read in this mode, but the data will not be
transmitted on the parallel port.
111
Configuration Mode. The confgA and confgB registers are accessible at 0x400 and
0x401 in this mode.
Bit 4: Read/Write (Valid only in ECP Mode)
1
Disables the interrupt generated on the asserting edge of nFault.
0
Enables an interrupt pulse on the high to low edge of nFault. If nFault is asserted
(interrupt) an interrupt will be generated and this bit is written from a 1 to 0.
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Bit 3: Read/Write
1
0
Enables DMA.
Disables DMA unconditionally.
Bit 2: Read/Write
1
0
Disables DMA and all of the service interrupts.
Enables one of the following cases of interrupts. When one of the service interrupts
has occurred, the serviceIntr bit is set to a 1 by hardware. This bit must be reset to
0 to re-enable the interrupts. Writing a 1 to this bit will not cause an interrupt.
(a) dmaEn = 1:
During DMA this bit is set to a 1 when terminal count is reached.
(b) dmaEn = 0 direction = 0:
This bit is set to 1 whenever there are writeIntr Threshold or more bytes free in the
FIFO.
(c) dmaEn = 0 direction = 1:
This bit is set to 1 whenever there are readIntr Threshold or more valid bytes to be
read from the FIFO.
Bit 1: Read only
0
1
The FIFO has at least 1 free byte.
The FIFO cannot accept another byte or the FIFO is completely full.
Bit 0: Read only
0
The FIFO contains at least 1 byte of data.
1
The FIFO is completely empty.
5.3.11 Bit Map of ECP Port Registers
data
ecpAFifo
dsr
dcr
cFifo
ecpDFifo
tFifo
cnfgA
cnfgB
ecr
D7
D6
D5
D4
D3
D2
D1
D0
PD7
PD6
PD5
PD4
PD3
PD2
PD1
PD0
Addr/RLE
Address or RLE field
NOTE
2
nBusy
nAck
PError
Select
nFault
1
1
1
1
1
1
Directio
ackIntEn
SelectIn
nInit
autofd
strobe
1
Parallel Port Data FIFO
2
ECP Data FIFO
2
Test FIFO
0
compress
2
0
0
intrValue
1
MODE
1
0
0
0
0
1
1
1
1
1
nErrIntrEn
dmaEn
serviceIntr
full
empty
Notes:
1. These registers are available in all modes.
2. All FIFOs use one common 16-byte FIFO.
5.3.12 ECP Pin Descriptions
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W83877F
NAME
TYPE
DESCRIPTION
nStrobe (HostClk)
O
The nStrobe registers data or address into the slave on the
asserting edge during write operations. This signal
handshakes with Busy.
PD<7:0>
I/O
These signals contains address or data or RLE data.
nAck (PeriphClk)
I
This signal indicates valid data driven by the peripheral when
asserted. This signal handshakes with nAutoFd in reverse.
Busy (PeriphAck)
I
This signal deasserts to indicate that the peripheral can
accept data. It indicates whether the data lines contain ECP
command information or data in the reverse direction. When
in reverse direction, normal data are transferred when Busy
(PeriphAck) is high and an 8-bit command is transferred when
it is low.
PError (nAckReverse)
I
This signal is used to acknowledge a change in the direction
of the transfer (asserted = forward). The peripheral drives this
signal low to acknowledge nReverseRequest. The host relies
upon nAckReverse to determine when it is permitted to drive
the data bus.
Select (Xflag)
I
Indicates printer on line.
nAutoFd (HostAck)
O
Requests a byte of data from the peripheral when it is
asserted. This signal indicates whether the data lines contain
ECP address or data in the forward direction. When in forward
direction, normal data are transferred when nAutoFd
(HostAck) is high and an 8-bit command is transferred when it
is low.
nFault (nPeriphRequest)
I
Generates an error interrupt when it is asserted. This signal is
valid only in the forward direction. The peripheral is permitted
(but not required) to drive this pin low to request a reverse
transfer during ECP Mode.
nInit (nReverseRequest)
O
This signal sets the transfer direction (asserted = reverse,
deasserted = forward). This pin is driven low to place the
channel in the reverse direction.
nSelectIn (ECPMode)
O
This signal is always deasserted in ECP mode.
5.3.13 ECP Operation
The host must negotiate on the parallel port to determine if the peripheral supports the ECP protocol
before ECP operation. After negotiation, it is necessary to initialize some of the port bits. The
following are required:
(a) Set direction = 0, enabling the drivers.
(b) Set strobe = 0, causing the nStrobe signal to default to the deasserted state.
(c) Set autoFd = 0, causing the nAutoFd signal to default to the deasserted state.
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(d) Set mode = 011 (ECP Mode)
ECP address/RLE bytes or data bytes may be sent automatically by writing the ecpAFifo or ecpDFifo,
respectively.
Mode Switching
Software will execute P1284 negotiation and all operation prior to a data transfer phase under
programmed I/O control (mode 000 or 001). Hardware provides an automatic control line handshake,
moving data between the FIFO and the ECP port only in the data transfer phase (mode 011 or 010).
If the port is in mode 000 or 001 it may switch to any other mode. If the port is not in mode 000 or 001
it can only be switched into mode 000 or 001. The direction can be changed only in mode 001.
When in extended forward mode, the software should wait for the FIFO to be empty before switching
back to mode 000 or 001. In ECP reverse mode the software waits for all the data to be read from the
FIFO before changing back to mode 000 or 001.
Command/Data
ECP mode allows the transfer of normal 8-bit data or 8-bit commands. In the forward direction,
normal data are transferred when HostAck is high and an 8-bit command is transferred when HostAck
is low. The most significant bits of the command indicate whether it is a run-length count (for
compression) or a channel address.
In the reverse direction, normal data are transferred when PeriphAck is high and an 8-bit command is
transferred when PeriphAck is low. The most significant bit of the command is always zero.
Data Compression
The W83877F supports run length encoded (RLE) decompression in hardware and can transfer
compressed data to a peripheral. Note that the odd (RLE) compression in hardware is not supported.
In order to transfer data in ECP mode, the compression count is written to the ecpAFifo and the data
byte is written to the ecpDFifo.
5.3.14 FIFO Operation
The FIFO threshold is set in configuration register 5. All data transfers to or from the parallel port can
proceed in DMA or Programmed I/O (non-DMA) mode, as indicated by the selected mode. The FIFO
is used by selecting the Parallel Port FIFO mode or ECP Parallel Port Mode. After a reset, the FIFO
is disabled.
5.3.15 DMA Transfers
DMA transfers are always to or from the ecpDFifo, tFifo, or CFifo. The DMA uses the standard PC
DMA services. The ECP requests DMA transfers from the host by activating the PDRQ pin. The DMA
will empty or fill the FIFO using the appropriate direction and mode. When the terminal count in the
DMA controller is reached, an interrupt is generated and serviceIntr is asserted, which will disable the
DMA.
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W83877F
5.3.16 Programmed I/O (NON-DMA) Mode
The ECP or parallel port FIFOs can also be operated using interrupt driven programmed I/O.
Programmed I/O transfers are to the ecpDFifo at 400H and ecpAFifo at 000H or from the ecpDFifo
located at 400H, or to/from the tFifo at 400H. The host must set the direction, state, dmaEn = 0 and
serviceIntr = 0 in the programmed I/O transfers.
The ECP requests programmed I/O transfers from the host by activating the IRQ pin. The
programmed I/O will empty or fill the FIFO using the appropriate direction and mode.
5.4 Extension FDD Mode (EXTFDD)
In this mode, the W83877F changes the printer interface pins to FDC input/output pins, allowing the
user to install a second floppy disk drive (FDD B) through the DB-25 printer connector. The pin
assignments for the FDC input/output pins are shown in Table 5-1.
After the printer interface is set to EXTFDD mode, the following occur:
(1) Pins MOB and DSB will be forced to inactive state.
(2) Pins DSKCHG, RDATA , WP, TRAK0, INDEX will be logically ORed with pins PD4-PD0 to
serve as input signals to the FDC.
(3) Pins PD4-PD0 each will have an internal resistor of about 1K ohm to serve as pull-up resistor for
FDD open drain/collector output.
(4) If the parallel port is set to EXTFDD mode after the system has booted DOS or another operating
system, a warm reset is needed to enable the system to recognize the extension floppy drive.
5.5 Extension 2FDD Mode (EXT2FDD)
In this mode, the W83877F changes the printer interface pins to FDC input/output pins, allowing the
user to install two external floppy disk drives through the DB-25 printer connector to replace internal
floppy disk drives A and B. The pin assignments for the FDC input/output pins are shown in Table 51.
After the printer interface is set to EXTFDD mode, the following occur:
(1) Pins MOA ,
, MOB, and DSB
(2) Pins DSKCHG, RDATA , WP, TRAK , and INDEX will be logically ORed with pins PD4-PD0 to
serve as input signals to the FDC.
(3) Pins PD4-PD0 each will have an internal resistor of about 1K ohm to serve as pull-up resistor for
FDD open drain/collector output.
(4) If the parallel port is set to EXT2FDD mode after the system has booted DOS or another operating
system, a warm reset is needed to enable the system to recognize the extension floppy drive.
5.6 Extension Adapter Mode (EXTADP) (Patent pending)
In this mode, the W83877F redefines the printer interface pins for use as an extension adapter,
allowing a pocket peripheral adapter card to be installed through the DB-25 printer connector. The pin
assignments for the extension adapter are shown in table 5-1.
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XDO-XD7 are the system data bus for the extension adapter.
XA0-XA2 are the system address bus.
XWR and XRD are the I/O read/write commands with address comparing match or in DMA
access mode.
XDACK , XTC, and XDRQ are used in conjunction with PDACKX , TC, and PDRQX to execute
a DMA cycle.
The extension adapter can issue a DMA request by setting pin XDRQ high, thus sending the
W83877F output to the host system by pin PDRQX. The DMA controller should recognize the DMA
request and output a relative DACK to pin PDACKX of the W83877F, which will output the DACK
without any change from pin XDACK to the extension adapter. Once the DMA transfer is completed,
a terminal count (TC) should be issued from the DMA controller to pin TC of W83877F and output to
the extension adapter via pin XTC. XIRQ is the interrupt request of the extension adapter. The value
of XIRQ coming from the extension adapter will directly pass through pin IRQ7 to the host system.
XIRQ and IRQ7, XDACK and PDACKX , and XDRQ and PDRQX are three input/output pairs of
W83877F pins. Although these pins are defined as DMA and interrupt functions, they can be
redefined by users for other specific functions.
5.6.1 Operation
The idea behind EXTADP mode is to treat the parallel port DB-25 connector as an ISA slot, except
that its addresses are not issued to the extension adapter. The operation of EXTADP mode is
described below:
1. Set the W83877F to EXTADP mode by programming bit 7 of CR7 as low and bit 3 and bit 2 of CR0
as high and low, respectively.
2. The W83877F CR2 is an address register that records the address of the extension adapter. When
the desired address is written into CR2, pins XWR and XRD of the W83877F will simultaneously
go low and the desired address will also appear on the printer data bus PD7-PD0. Users can
logically OR these two signals as an initial reset.
3. After the above two steps, every time the host system issues an IOR or IOW command, the
W83877F will compare the I/O address with the CR2 register. If the comparision matches, the
data, low bits addresses (XA2-XA0), and XWR / XRD will be presented on the parallel port DB-25
connector.
4. DMA operations are handled in the same way as item 3, except that the relevant PDACKX ,
PDRQX will be active on the DB-25 connector.
5.7 Joystick Mode (Patent pending)
The joystick mode allows users to plug a joystick into the parallel port DB-25 connector. The pin
definitions are shown in Table 5-1.
Pins NSTB , AFD , NSLIN, and INIT output high as a voltage supply to the joystick.
Pins PD5 and PD4 are the button input of the joystick.
Pins PD1 and PD0 are the X/Y axis paddle input of the joystick.
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W83877F
There are two one-shot timers (556) inside the W83877F for use with the joystick.
6.0 Game Port Decoder
The W83877F provides GMRD and GMWR pins that decode game port address as specified in CR1E
and I/O read/write commands.
If the host issues IOR and the specified address, the GMRD pin is low active; if it issues IOW and the
specified address, the GMWR pin is low active.
7.0 Plug and Play Configuration
A powerful new plug-and-play function has been built into the W83877F to help simplify the task of
setting up a computer environment. With appropriate support from BIOS manufacturers, the system
designer can freely allocate Winbond I/O devices (i.e., the FDC, PRT, UART, IDE, and game port) in
the PC's I/O space (100H - 3FFH). In addition, the W83877F also provides 8 interrupt requests and 3
DMA pairs for designers to assign in interfacing FDCs, UARTs, and PRTs. Hence this powerful I/O
chip offers greater flexibility for system designers.
The PnP feature is implemented through a set of Extended Function Registers (CR1E and CR20 to
29). Details on configuring these registers are given in Section 8. The default values of these PnPrelated registers set the system to a configuration compatible with environments designed with
previous Winbond I/O chips.
8.0 Extended Function Registers
The W83877F provides many configuration registers for setting up different types of configurations.
After power-on reset, the state of the hardware setting of each pin will be latched by the relevant
configuration register to allow the W83877F to enter the proper operating configuration. To protect
the chip from invalid reads or writes, the configuration registers cannot be accessed by the user.
There are four ways to enable the configuration registers to be read or written. HEFERE (CR0C bit 5)
and HEFRAS (CR16 bit 0) can be used to select one out of these four methods of entering the
Extended Function mode as follows:
HEFRAS
HEFERE
address and value
0
0
write 88H to the location 250H
0
1
write 89H to the location 250H (power-on default)
1
0
write 86H to the location 3F0H twice
1
1
write 87H to the location 3F0H twice
First, a specific value must be written once (88H/89H) or twice (86H/87H) to the Extended Functions
Enable Register (I/O port address 250H or 3F0H). Second, an index value (00H-17H, 1EH, 20H-29H)
must be written to the Extended Functions Index Register (I/O port address 251H or 3F0H) to identify
which configuration register is to be accessed. The designer can then access the desired
configuration register through the Extended Functions Data Register (I/O port address 252H or 3F1H).
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After programming of the configuration register is finished, an additional value should be written to
EFERs to exit the Extended Function mode to prevent unintentional access to those configuration
registers. In the case of EFER at 250H, this additional value can be any value other than 88H if
HEFERE = 0 and 89H if HEFERE = 1. While EFER is at 3F0H, this additional value must be AAH.
The designer can also set bit 6 of CR9 (LOCKREG) to high to protect the configuration registers
against accidental accesses.
The configuration registers can be reset to their default or hardware settings only by a cold reset (pin
MR = 1). A warm reset will not affect the configuration registers.
8.1 Extended Functions Enable Registers (EFERs)
After a power-on reset, the W83877F enters the default operating mode. Before the W83877F enters
the extended function mode, a specific value must be programmed into the Extended Function
Enable Register (EFER) so that the extended function register can be accessed. The Extended
Function Enable Registers are write-only registers. On a PC/AT system, their port addresses are
250H or 3F0H (as described in the above section).
8.2 Extended Function Index Registers (EFIRs), Extended Function Data Registers
(EFDRs)
After the extended function mode is entered, the Extended Function Index Register (EFIR) must be
loaded with an index value (0H, 1H, 2H, ..., or 29H) to access Configuration Register 0 (CR0),
Configuration Register 1 (CR1), Configuration Register 2 (CR2), and so forth through the Extended
Function Data Register (EFDR). The EFIRs are write-only registers with port address 251H or 3F0H
(as described in section 8.0) on PC/AT systems; the EFDRs are read/write registers with port address
252H or 3F1H (as described in section 8.0) on PC/AT systems. The function of each configuration
register is described below.
8.2.1 Configuration Register 0 (CR0), default = 00H
When the device is in Extended Function mode and EFIR is 0H, the CR0 register can be accessed
through EFDR. The bit definitions for CR0 are as follows:
7
6
5
4
3
2
1
0
OCSS0
OCSS1
PRTMODS0
PRTMODS1
reserved
reserved
reserved
reserved
Bit 7-Bit 4: Reserved.
PRTMOD1 PRTMOD0 (Bit 3, Bit 2):
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W83877F
These two bits and PRTMOD2 (CR9 bit7) determine the parallel port mode of the W83877 (see Table
7-1 on next page ).
Table 7-1
PRTMODS2
(BIT 7 OF CR9)
PRTMOD1
(BIT 3 OF CR0)
PRTMODS0
(BIT 2 OF CR0)
0
0
0
W83757
0
0
1
EXTFDC
0
1
0
EXTADP
0
1
1
EXT2FDD
1
0
0
JOYSTICK
1
0
1
EPP/SPP
1
1
0
ECP
1
1
1
ECP/EPP
00
W83757 Mode (Default), PRTMOD2 = 0
Default state after power-on reset. In this mode, the W83877F is fully compatible with
the W83757F/W83757AF.
01
Extension FDD Mode (EXTFDD), PRTMOD2 = 0
10
Extension Adapter Mode (EXTADP), PRTMOD2 = 0
11
Extension 2FDD Mode (EXT2FDD), PRTMOD2 = 0
00
JOYSTICK Mode, PRTMOD2 = 1
01
EPP Mode and SPP Mode, PRTMOD2 = 1
10
ECP Mode, PRTMOD2 = 1
11
ECP Mode and EPP Mode, PRTMOD2 = 1
OSCS1, OSCS0 (Bit 1, Bit 0):
These two bits and OSCS2 (CR6 bit 6) are used to select one of the W83877F's power-down
functions. These bits may be programmed in four different ways:
00
Default power-on state after power-on reset (OSCS2 = 0).
00
OSC on, 24 MHz clock is stopped internally (OSCS2 = 1). Clock can be restarted by
clearing OSCS2.
01
Immediate power-down (IPD) state, OSCS2 = 0
When bit 0 is 1 and bit 1 is set to 0, the W83877F will stop its oscillator and enter power-down mode
immediately. The W83877F will not leave the power-down mode until either a system power-on reset
from the MR pin or these two bits are used to program the chip back to power-on state. After leaving
the power-down mode, the W83877F must wait 128 mS for the oscillator to stabilize.
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10
Standby for automatic power-down (APD), OSCS2 = 0
When bit 1 is set to 1 and bit 0 is set to 0, the W83877F will stand by for automatic power-down. A
power-down will occur when the following conditions obtain:
• FDC
not busy
• FDD
motor off
• Interrupt
source of line status, modem status, and data ready is inactive (neglecting IER
enable/disable)
• Master
Reset inactive
• SOUTA
• SINA
• No
and SOUTB in idle state
and SINB in idle state
register read or write to chip
If all of these conditions are met, a counter begins to count down. While the timer is counting down,
the W83877F remains in normal operating mode, and if any of the above conditions changes, the
counter will be reset. If the set time (set by bit 7 and bit 6 of CR8) elapses without a change in any of
the above conditions, bits 1 and 0 will be set to (1, 1) and the chip will enter automatic power-down
mode. The oscillator of the W83877F will remain running, but the internal clock will be disabled to
save power. Once the above conditions are no longer met, the internal clock will be resupplied and
the chip will return to normal operation.
11
Automatic power-down (ADP) state, OSCS2 = 0
The W83877F enters this state automatically after the counter described above has counted down. If
there is a change in any of the conditions listed above, the W83877F 's clock will be restarted and bits
1 and 0 will be set to (1, 0), i.e., standby for automatic power-down. When the clock is restarted, the
chip is ready for normal operation, with no need to wait for the oscillator to stabilize.
8.2.2 Configuration Register 1 (CR1), default = 00H
When the device is in Extended Function mode and EFIR is 01H, the CR1 register can be accessed
through EFDR. The bit definitions are as follows:
7
6
5
4
3
2
1
0
reserved
reserved
reserved
reserved
reserved
reserved
reserved
ABCHG
Bit 0-bit 6: Reserved.
ABCHG (Bit 7):
This bit enables the FDC AB Change Mode. Default to be enabled at power-on reset.
- 72 -
W83877F
0
Drives A and B assigned as usual
1
Drive A and drive B assignments exchanged
8.2.3 Configuration Register 2 (CR2), default = 00H
When the device is in Extended Function mode and EFIR is 02H, the CR2 register can be accessed
through EFDR. The bit definitions are as follows:
7
6
5
4
3
2
1
0
CEA
EA3
EA4
EA5
EA6
EA7
EA8
EA9
When the W83877F is programmed into extension adapter mode, the contents of this register are a
base address for the extension adapter. When base addresses EA3-EA9 are written into CR2, both
the XRD and XWR pins will be active low simultaneously and an adapter connected to the parallel
port can latch the same base address through pins XD1-XD7. After the base address is latched into
CR2, a subsequent read/write cycle to this same base address will generate an XRD or XWR signal.
If CEA is set to 0, then the W83877F will compare system addresses SA9-SA3 with EA9-EA3 to
generate a compare-equal signal for this read/write command to access the Extension adapter. If
CEA is set to 1, then only EA9-EA4 are used in this comparison.
- 73 -
Publication Release Date: January 1996
Revision A2
W83877F
8.2.4 Configuration Register 3 (CR3), default = 30H
When the device is in Extended Function mode and EFIR is 03H, the CR3 register can be accessed
through EFDR. The bit definitions are as follows:
7
6
5
4
3
2
1
0
SUBMIDI
SUAMIDI
reserved
reserved
GMODS
EPPVER
GMENL
reserved
SUBMIDI (Bit 0):
This bit selects the clock divide rate of UARTB.
0
disables MIDI support, UARTB clock = 24 MHz divided by 13 (default)
1
enables MIDI support, UARTB clock = 24 MHz divided by 12
SUAMIDI (Bit 1):
This bit selects the clock divide rate of UARTA.
0
Disables MIDI support, UARTA clock = 24 MHz divided by 13 (default)
1
Enables MIDI support, UARTA clock = 24 MHz divided by 12
Bit 2-bit 3: Reserved.
GMODS (Bit 4):
This bit selects the adapter mode or portable mode.
0
Selects the portable mode. Pins 41 and 39 will function as PFDCEN and PEXTEN
1
Selects the adapter mode. Pins 41 and 39 will function as GMRD and GMWR
Note: GMDRQ (CR16 bit 3) has higher precedence over this bit. That is, GMODS selection is only valid when GMGRQ = 0.
EPPVER (Bit 5):
This bit selects the EPP version of parallel port:
0
Selects the EPP 1.9 version
1
Selects the EPP 1.7 version (default)
Bit 7-bit 6: Reserved.
- 74 -
W83877F
8.2.5 Configuration Register 4 (CR4), default = 00H
When the device is in Extended Function mode and EFIR is 04H, the CR4 register can be accessed
through EFDR. The bit definitions are as follows:
7
6
5
4
3
2
1
0
URBTRI
URATRI
GMTRI
PRTTRI
URBPWD
URAPWD
GMPWD
PRTPWD
PRTPWD (Bit 7):
0
Supplies power to the parallel port (default)
1
Puts the parallel port in power-down mode
GMPWD (Bit 6):
0
Supplies power to the game port (default)
1
Puts the game port in power-down mode
URAPWD (Bit 5):
0
Supplies power to COMA (default)
1
Puts COMA in power-down mode
URBPWD (Bit 4):
0
Supplies power to COMB (default)
1
Puts COMB in power-down mode
PRTTRI (Bit 3):
This bit enables or disables the tri-state outputs of parallel port in power-down mode.
0
The output pins of the parallel port will not be tri-stated when parallel port is in powerdown mode. (default)
1
The output pins of the parallel port will be tri-stated when parallel port is in powerdown mode.
GMTRI (Bit 2):
This bit enables or disables the tri-state outputs of the game port in power-down mode.
0
The output pins of the game port will not be tri-stated when game port is in powerdown mode. (default)
1
The output pins of the game port will be tri-stated when game port is in power-down
mode.
URATRI (Bit 1):
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Publication Release Date: January 1996
Revision A2
W83877F
This bit enables or disables the tri-state outputs of UARTA in power-down mode.
0
The output pins of UARTA will not be tri-stated when UARTA is in power-down mode.
1
The output pins of UARTA will be tri-stated when UARTA is in power-down mode.
URBTRI (Bit 0):
This bit enables or disables the tri-state outputs of UARTB in power-down mode.
0
The output pins of UARTB will not be tri-stated when UARTB is in power-down mode.
1
The output pins of UARTB will be tri-stated when UARTB is in power-down mode.
8.2.6 Configuration Register 5 (CR5), default = 00H
When the device is in Extended Function mode and EFIR is 05H, the CR5 register can be accessed
through EFDR. The bit definitions are as follows:
7
6
5
4
3
2
1
0
ECPFTHR0
ECPFTHR1
ECPFTHR2
ECPFTHR3
Reserved
Reserved
Reserved
Reserved
Bit 7-4: Reserved
ECPFTHR3-0 (bit 3-0): These four bits define the FIFO threshold for the ECP mode parallel port. The
default value is 0000 after power-up.
8.2.7 Configuration Register 6 (CR6), default = 00H
When the device is in Extended Function mode and EFIR is 06H, the CR6 register can be accessed
through EFDR. The bit definitions are as follows:
7
6
5
4
3
2
1
0
IDETRI
FDCTRI
IDEPWD
FDCPWD
FIPURDWM
SEL4FDD
OSCS2
Reserved
- 76 -
W83877F
Bit 7: Reserved
OSCS2 (Bit 6): This bit and OSCS1, OSCS0 (bit 1, 0 of CR0) select one of the W83877F's
power-down functions. Refer to descriptions of CR0. (Default to be 0)
SEL4FDD (Bit 5): Selects four FDD mode
0
Selects two FDD mode (default, see Table 7-2)
1
Selects four FDD mode
DSA , DSB , MOA and MOB output pins are encoded as show in Table 7-3 to select
four drives.
Table 7-2
DO REGISTER ( 3F2H )
MOB
MOA
DSB
DSA
DRIVE
Bit 7
Bit 6
Bit 5
Bit 4
Bit 1
Bit 0
SELECTED
0
0
0
0
0
0
1
1
1
1
--
0
0
0
1
0
0
1
0
1
0
FDD A
0
0
1
0
0
1
0
1
0
1
FDD B
0
1
0
0
0
1
1
1
1
1
--
1
0
0
0
1
1
1
1
1
1
--
MOB
MOA
DSB
DSA
DRIVE
Table 7-3
DO REGISTER ( 3F2H )
Bit 7
Bit 6
Bit 5
Bit 4
Bit 1
Bit 0
0
0
0
0
X
X
1
1
x
x
--
0
0
0
1
0
0
0
0
0
0
FDD A
0
0
1
0
0
1
0
0
0
1
FDD B
0
1
0
0
1
0
0
0
1
0
FDD C
1
0
0
0
1
1
0
0
1
1
FDD D
SELECTED
FIPURDWN (Bit 4):
This bit controls the internal pull-up resistors of the FDC input pins RDATA , INDEX , TRAK0,
DSKCHG, and WP.
0
The internal pull-up resistors of FDC are turned on. (default)
1
The internal pull-up resistors of FDC are turned off.
FDCPWD (Bit 3):
This bit controls the power to the FDC.
0
Power is supplied to the FDC. (default)
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Publication Release Date: January 1996
Revision A2
W83877F
1
Puts the FDC in power-down mode.
IDEPWD (Bit 2):
This bit controls the power of the IDE.
0
Power is supplied to the IDE. (default)
1
Puts the IDE in power-down mode.
FDCTRI (Bit 1):
This bit enables or disables the tri-state outputs of the FDC in power-down mode.
0
The output pins of the FDC will not be tri-stated when FDC is in power-down mode.
1
The output pins of the FDC will be tri-stated when FDC is in power-down mode.
IDETRI (BIt 0):
This bit enables or disables the tri-state outputs of the IDE in power-down mode.
0
The output pins of the IDE will not be tri-stated when IDE is in power-down mode.
1
The output pins of the IDE will be tri-stated when IDE is in power-down mode.
8.2.8 Configuration Register 7 (CR7), default = 00H
When the device is in Extended Function mode and EFIR is 07H, the CR7 register can be accessed
through EFDR. The bit definitions are as follows:
7
6
5
4
3
2
1
0
FDD A type 0
FDD A type 1
FDD B type 0
FDD B type 1
FDD C type 0
FDD C type 1
FDD D type 0
FDD D type 1
FDD A type 1, 0 (Bit 1, 0):
These two bits select the type of FDD A.
00
RWC
Selects normal mode. When RWC = 0, the data transfer rate is 250 Kb/s. When
= 1, the data transfer rate is 500 Kb/s.
Three mode FDD select (EN3MODE = 1):
01
RWC = 0, selects 1.2 MB high-density FDD.
10
RWC = 1, selects 1.44 MB high-density FDD.
11
Don't care RWC , selects 720 KB double-density FDD.
FDD B type 1, 0 (Bit 3, 2):
- 78 -
W83877F
These two bits select the type of FDD B.
00
RWC
Selects normal mode. When RWC = 0, the data transfer rate is 250 Kb/s. When
= 1, the data transfer rate is 500 Kb/s.
Three mode FDD select (EN3MODE = 1):
01
RWC = 0, selects 1.2 MB high-density FDD.
10
RWC = 1, selects 1.44 MB high-density FDD.
11
Don't care RWC, selects 720 KB double-density FDD.
FDD C type 1, 0 (Bit 5, 4):
These two bits select the type of FDD C.
00
Selects normal mode. When RWC = 0, the data transfer rate is 250 kb/s. When
RWC = 1, he data transfer rate is 500 kb/s.
Three mode FDD select (EN 3 MODE = 1):
01
RWC = 0, selects 1.2 MB high-density FDD.
10
RWC = 1, selects 1.44 MB high-density FDD.
11
Don't care RWC, selects 720 KB double-density FDD.
FDD D type 1, 0 (Bit 7, 6):
These two bits select the type of FDD D.
00
Selects normal mode. When RWC = 0, the data transfer rate is 250 Kb/s. When
RWC = 1, the data transfer rate is 500 Kb/s.
Three mode FDD select (EN3MODE = 1):
01
RWC = 0, selects 1.2 MB high-density FDD.
10
RWC = 1, selects 1.44 MB high-density FDD.
11
Don't care RWC, selects 720 KB double-density FDD.
8.2.9 Configuration Register 8 (CR8), default = 00H
When the device is in Extended Function mode and EFIR is 08H, the CR8 register can be accessed
through EFDR. The bit definitions are as follows:
7
6
5
4
3
2
1
0
Floppy Boot Drive 0
Floppy Boot Drive 1
Media ID 0
Media ID 1
SWWP
DISFDDWR
APDTMS2
APDTMS1
- 79 -
Publication Release Date: January 1996
Revision A2
W83877F
APDTMS2 APDTMS1 (Bit 6, 7):
These two bits select the count-down time of the automatic power-down mode counter.
00
4 seconds
01
32 seconds
10
64 seconds
11
4 minutes
DISFDDWR (Bit 5):
This bit enables or disables FDD write data.
0
Enables FDD write
1
Disables FDD write (forces pins WE, WD to stay high)
Once this bit is set high, the FDC operates normally, but because pin WE is inactive, the FDD will not
write data to diskettes. For example, if a diskette is formatted with DISFDDWR = 1, after the format
command has been executed, messages will be displayed that appear to indicate that the format is
complete. If the diskette is removed from the disk drive and inserted again, however, typing the DIR
command will reveal that the contents of the diskette have not been modified and the diskette was
not actually reformatted.
This is because as the operating system (e.g., DOS) reads the diskette files, it keeps the files in
memory. If there is a write operation, DOS will write data to the diskette and memory simultaneously.
When DOS wants to read the diskette, it will first search the files in memory. If DOS finds the file in
memory, it will not issue a read command to read the diskette. When DISFDDWR = 1, DOS still
writes data to the diskette and memory, but only the data in memory are updated. If a read operation
is performed, data are read from memory first, and not from the diskette. The action of removing the
diskette from the drive and inserting it again forces the DSKCHG pin active. DOS will then read the
contents of the diskette and will show that the contents have not been modified. The same holds true
with write commands.
The disable FDD write function allows users to protect diskettes against computer viruses by ensuring
that no data are written to the diskette.
SWWP (Bit 4):
0
Normal, use WP to determine whether the FDD is write-protected or not
1
FDD is always write-protected
Media ID 1 Media ID 0 (Bit 3, 2):
These two bits hold the media ID bit 1, 0 for three mode
Floppy Boot Drive 1 Floppy Boot Drive 0 (bit 1, 0)
These two bits hold the value of floppy boot drive 1 and drive 0 for three mode
8.2.10 Configuration Register 9 (CR9), default = 0AH
- 80 -
W83877F
When the device is in Extended Function mode and EFIR is 09H, the CR9 register can be accessed
through EFDR. The bit definitions are as follows:
7
6
5
4
3
2
1
0
CHIP ID0
CHIP ID1
CHIP ID2
CHIP ID3
Reserved
EN3MODE
LOCKREG
PRTMODS2
PRTMODS2 (Bit 7):
This bit and PRTMODS1, PRTMODS0 (bits 3, 2 of CR0) select the operating mode of the W83877.
Refer to the descriptions of CR0.
LOCKREG (Bit 6):
This bit enables or disables the reading and writing of all configuration registers.
0
Enables the reading and writing of CR0-CR29
1
Disables the reading and writing of CR0-CR29 (locks W83877F extension functions)
EN3MODE (Bit 5):
This bit enables or disables three mode FDD selection. When this bit is high, it enables the read/write
3F3H register.
0
Disables 3 mode FDD selection
1
Enables 3 mode FDD selection
When three mode FDD function is enabled, the value of RWC depends on bit 5 and bit 4 of
TDR(3F3H). The values of RWC and their meaning are shown in Table 7-4.
Table 7-4
BIT 5 OF TDR
BIT 4 OF TDR
RWC
RWC = 0
RWC = 1
0
0
Normal
250K bps
500K bps
0
1
0
1.2 M FDD
X
1
0
1
X
1.4M FDD
1
1
X
X
X
Bit 4: Reserved.
CHIP ID 3, CHIP ID 2, CHIP ID 1, CHIP ID 0 (Bit 3-0):
These four bits are read-only bits that contain chip identification information. The value is 0AH for
W83877F during a read.
- 81 -
Publication Release Date: January 1996
Revision A2
W83877F
8.2.11 Configuration Register A (CRA), default = 1FH
When the device is in Extended Function mode and EFIR is 0AH, the CRA register can be accessed
through EFDR. The bit definitions are as follows:
7
6
5
4
3
2
1
0
PEXTECPP
PEXT ECP
PEXT EPP
PEXT ADP
PDCACT
PDIRHOP
PEXT ACT
PFDCACT
PFDCACT (Bit 7):
This bit controls whether PFDCEN (pin 41) is active high or low in portable mode.
0
PFDCEN is active low
1
PFDCEN is active high
PEXTACT (Bit 6):
This bit controls whether PEXTEN (pin 39) is active high or low in portable mode. This pin can also
reflect the mode of the parallel port: EXTADP mode, EPP mode, ECP mode, or ECP/EPP mode, or
any combination of these modes.
0
PEXTEN is active low
1
PEXTEN is active high
Bit 5: Reserved.
PDCACT (Bit 4):
This bit controls whether the PDCIN pin is active high or low.
0
PDCIN is active low
1
PDCIN is active high
PEXTADP (Bit 3):
This bit controls whether the PEXTEN pin is active in EXTADP mode.
0
PEXTEN is not active in EXTADP mode
1
PEXTEN is active in EXTADP mode
PEXTEPP (Bit 2):
This bit controls whether the PEXTEN pin is active in EPP mode.
0
PEXTEN is not active in EPP mode
- 82 -
W83877F
1
PEXTEN is active in EPP mode
PEXTECP (Bit 1):
This bit controls whether the PEXTEN pin is active in ECP mode.
0
PEXTEN is not active in ECP mode
1
PEXTEN is active in ECP mode
PEXTECPP (Bit 0):
This bit controls whether the PEXTEN pin is active in ECP/EPP mode.
0
PEXTEN is not active in ECP/EPP mode
1
PEXTEN is active in ECP/EPP mode
8.2.12 Configuration Register B (CR0B), default = 0CH
When the device is in Extended Function mode and EFIR is 0BH, the CRB register can be accessed
through EFDR. The bit definitions are as follows:
7
6
5
0
0
0
4
3
2
1
0
DRV2EN
INVERTZ
MFM
IDENT
ENIFCHG
Bit 7-5: These bits are reserved and are logic 0 during a read.
ENIFCHG (Bit 4):
This bit is active high. When active, it enables host interface mode change, which is determined by
IDENT (Bit 3) and MFM (Bit 2).
IDENT (Bit 3):
This bit indicates the type of drive being accessed and changes the level on RWC (pin 87).
0
RWC will be active low for high data rates (typically used for 3.5" drives)
1
RWC will be active high for high data rates (typically used for 5.25" drives)
When hardware reset or ENIFCHG is a logic 1, IDENT and MFM select one of three interface modes,
as shown in Table 7-5.
Table 7- 5
IDENT
MFM
INTERFACE
- 83 -
Publication Release Date: January 1996
Revision A2
W83877F
0
0
Model 30 mode
0
1
PS/2 mode
1
0
AT mode
1
1
AT mode
MFM (Bit 2):
This bit and IDENT select one of the three interface modes (PS/2 mode, Model 30, or PC/AT mode).
INTVERTZ (Bit 1):
This bit determines the polarity of all FDD interface signals.
0
FDD interface signals are active low
1
FDD interface signals are active high
DRV2EN (Bit 0): PS/2 mode only
When this bit is a logic 0, indicates a second drive is installed and is reflected in status register A.
8.2.13 Configuration Register C (CR0C), default = 28H
When the device is in Extended Function mode and EFIR is 0CH, the CR0C register can be accessed
through EFDR. The bit definitions are as follows:
7
6
5
4
3
2
1
0
TX2INV
RX2INV
Reserved
URIRSEL
Reserved
HEFERE
TURB
TURA
TURA (bit 7):
0
the clock source of UART A is 1.8462 MHZ (24 MHz divide 13) (default)
1
the clock source of UART A is 24 MHz, it can make the baudrate of UART A up to 1.5
MHz
TURB (bit 6):
0
the clock source of UART B is 1.8462 MHz (24 MHz divide 13) (default)
1
the clock source of UART B is 24 MHz, it can make the baudrate of UART A up to 1.5
MHz
- 84 -
W83877F
HEFERE (bit 5): this bit combines with HEFRAS (CR16 bit 0) to define how to enable Extended
Function Registers.
HEFRAS
0
0
1
1
HEFERE
0
1
0
1
address and value
write 88H to the location 250H
write 89H to the location 250H (default)
write 86H to the location 3F0H twice
write 87H to the location 3F0H twice
The default value of HEFERE is 1.
Bit 4: Reserved.
URIRSEL (bit 3):
0
select UART B as IR function.
1
select UART B as normal function.
The default value of URIRSEL is 1.
Bit 2: Reserved.
RX2INV (bit 1):
0
the SINB pin of UART B function or IRRX pin of IR function in normal condition.
1
inverse the SINB pin of UART B function or IRRX pin of IR function
TX2INV (bit 0):
0
the SOUTB pin of UART B function or IRTX pin of IR function in normal condition.
1
inverse the SOUTB pin of UART B function or IRTX pin of IR function.
8.2.14 Configuration Register D (CR0D), default = a3H
When the device is in Extended Function mode and EFIR is 0DH, the CR0D register can be accessed
through EFDR. The bit definitions are as follows:
7
6
5
4
3
2
1
0
IRMODE0
IRMODE1
IRMODE2
HDUPLX
SIRRX0
SIRRX1
SIRTX0
SIRTX1
SIRTX1 (bit 7): IRTX pin selection bit 1
SIRTX0 (bit 6): IRTX pin selection bit 0
- 85 -
Publication Release Date: January 1996
Revision A2
W83877F
SIRTX1
SIRTX0
IRTX output on pin
0
0
disabled
0
1
IRTX1 (pin 43)
1
0
IRTX2 (pin 95)
1
1
disabled
SIRRX1 (bit 5): IRRX pin selection bit 1
SIRRX0 (bit 4): IRRX pin selection bit 0
SIRRX1
SIRRX0
IRRX input on pin
0
0
disabled
0
1
IRRX1 (pin 42)
1
0
IRRX2 (pin 94)
1
1
disabled
HDUPLX (bit 3):
0
The IR function is Full Duplex.
1
The IR function is Half Duplex.
IRMODE2 (bit 2): IR function mode selection bit 2
IRMODE1 (bit 1): IR function mode selection bit 1
IRMODE0 (bit 0): IR function mode selection bit 0
IR MODE
IR FUNCTION
IRTX
IRRX
00X
Disable
tri-state
high
010*
IrDA
Active pulse 1.6 µS
Demodulation into SINB
011*
IrDA
Active pulse 3/16 bit time
Demodulation into SINB
100
ASK-IR
Inverting IRTX pin
routed to SINB
101
ASK-IR
Inverting IRTX & 500 KHZ clock
routed to SINB
110
ASK-IR
Inverting IRTX
Demodulation into SINB
111*
ASK-IR
Inverting IRTX & 500 KHZ clock
Demodulation into SINB
Note: The notation is normal mode in the IR function.
The SIR schematic diagram for registers CRC and CRD is shown below.
8.2.15 Configuration Register E (CR0E), Configuration Register F (CR0F)
Reserved for testing. Should be kept all 0's.
- 86 -
W83877F
HUPLX
(CRD.bit3)
Transmission
Time Frame
IRRX1
SIN2
16550A
Demodulation
IR-DA
1
SIN
1
MUX 0
1
MUX 0
UART2
SOUT
RX2INV URIRSEL
(CRC.bit1) (CRC.bit3)
IRDA Mod.
3/16
ASK_IR
MUX 0
IRMODE2
(CRD.bit2)
IRRX2
10
MUX11
IRMODE2,1=00
+5V
SIRRX1~0
CR0D.bit5,4
1
0
0 MUX
11,00
0
1 MUX
01
IRMODE0
(CRD.bit0)
1 MUX
IRMODE2
(CRD.bit2)
1
500KHZ
+5V
NCS0 (default)
IRMODE1
(CRD.bit1)
IRDA
IRDA Mod.
Mod1.6u
01
00
Demodulation
10
MUX
TX2INV
URIRSEL CRC.bit0
(CRC,bit3)
0 MUX
disable
IRTX1 SOUT2
IRTX2
NCS1 (default)
SIRTX1~0
CRD.bit7,6
IRMODE0
(CRD.bit0)
8.2.16 Configuration Register 10 (CR10), default = 00H
When the device is in Extended Function mode and EFIR is 10H, the CR10 register can be accessed
through EFDR. The bit definitions are as follows:
7
6
5
4
3
2
1
0
GIO0AD0
GIO0AD1
GIO0AD2
GIO0AD3
GIO0AD4
GIO0AD5
GIO0AD6
GIO0AD7
GIO0AD7-GIO0AD0 (bit 7-bit 0): GIOP0 (pin 92) address bit 7 - bit 0.
8.2.17 Configuration Register 11 (CR11), default = 00H
When the device is in Extended Function mode and EFIR is 11H, the CR11 register can be accessed
through EFDR. The bit definitions are as follows:
- 87 -
Publication Release Date: January 1996
Revision A2
W83877F
7
6
5
4
3
2
1
0
GIO0AD8
GIO0AD9
GIO0AD10
Reserved
Reserved
Reserved
G0CADM0
G0CADM1
G0CADM1-G0CADM0 (bit 7-bit 6): GIOP0 address bit compare mode selection
G0CADM1
G0CADM0
GIOP0 pin
0
0
compare GIO0AD10-GIO0AD0 with SA10-SA0
0
1
compare GIO0AD10-GIO0AD1 with SA10-SA1
1
0
compare GIO0AD10-GIO0AD2 with SA10-SA2
1
1
compare GIO0AD10-GIO0AD3 with SA10-SA3
Bit 5-bit 3: Reserved
GIO0AD10-GIO0AD8 (bit 2-bit 0): GIOP0 (pin 92) address bit 10-bit 8
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W83877F
8.2.18 Configuration Register 12 (CR12), default = 00H
When the device is in Extended Function mode and EFIR is 12H, the CR12 register can be accessed
through EFDR. The bit definitions are as follows:
7
6
5
4
2
3
1
0
GIO1AD0
GIO1AD1
GIO1AD2
GIO1AD3
GIO1AD4
GIO1AD5
GIO1AD6
GIO1AD7
GIO1AD7-GIO1AD0 (bit 7-bit 0): GIOP1 (pin 96) address bit 7-bit 0.
8.2.19 Configuration Register 13 (CR13), default = 00H
When the device is in Extended Function mode and EFIR is 13H, the CR13 register can be accessed
through EFDR. The bit definitions are as follows:
7
6
5
4
3
2
1
0
GIO1AD8
GIO1AD9
GIO1AD10
Reserved
Reserved
Reserved
G1CADM0
G1CADM1
G1CADM1-G1CADM0 (bit 7-bit 6): GIOP1 address bit compare mode selection
G1CADM1
G1CADM0
GIOP1 pin
0
0
compare GIO1AD10-GIO1AD0 with SA10-SA0
0
1
compare GIO1AD10-GIO1AD1 with SA10-SA1
1
0
compare GIO1AD10-GIO1AD2 with SA10-SA2
1
1
compare GIO1AD10-GIO1AD3 with SA10-SA3
Bit 5- bit 3: Reserved
GIO1AD10-GIO1AD8 (bit 2-it 0): GIOP1 (pin 96) address bit 10-bit 8
8.2.20 Configuration Register 14 (CR14), default = 00H
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Publication Release Date: January 1996
Revision A2
W83877F
When the device is in Extended Function mode and EFIR is 14H, the CR14 register can be accessed
through EFDR. The bit definitions are as follows:
7
6
5
4
3
2
1
0
GDA0IPI
GDA0OPI
GCS0IOW
GCS0IOR
GIO0CSH
GIOP0MD0
GIOP0MD1
GIOP0MD2
GIOP0MD2-GIOP0MD0 (bit 7-bit 5): GIOP0 pin mode selection
GIOP0MD2
GIOP0MD1
GIOP0MD0
GIOP0 pin
0
0
0
inactive (tri-state)
0
0
1
as a data output pin (SD0→GIOP0), when (AEN = L)
AND (NIOW = L) AND (SA10-0 = GIO0AD10-0), the
value of SD0 will be present on GIOP0
0
1
0
as a data input pin (GIOP0→SD0), when (AEN = L)
AND (NIOR = L) AND (SA10-0 = GIO0AD10-0), the
value of GIOP0 will be present on SD0
0
1
1
as a data input/output pin (GIOP0↔SD0).
When (AEN = L) AND (NIOW = L) AND (SA10-0 =
GIO0AD10-0), the value of SD0 will be present on
GIOP0 When (AEN = L) AND (NIOR = L) AND (SA100 = GIO0AD10-0), the value of GIOP0 will be present
on SD0
1
X
X
as a Chip Select pin, the pin will be active at (AEN =
L) AND (SA10-0 = GIO0AD10-0) OR (NIOR = L) OR
(NIOW = L)
GIO0CSH(bit 4):
0
the Chip Select pin will be active LOW when (AEN = L) AND (SA10-0 = GIO0AD100) OR (NIOR = L) OR (NIOW = L)
1
the Chip Select pin will be active HIGH when (AEN = L) AND (SA10-0 = GIO0AD100) OR (NIOR = L) OR (NIOW = L)
GCS0IOR (bit 3): See below.
- 90 -
W83877F
GCS0IOW (bit 2): See below.
GCS0IOR
GCS0IOW
0
0
GIOP0 functions as a Chip Select pin, and will be active when
(AEN = L) AND (SA10-0 = GIO0AD10-0)
0
1
GIOP0 functions as a Chip Select pin, and will be active when
(AEN = L) AND (SA10-0 = GIO0AD10-0) AND (NIOW = L)
1
0
GIOP0 functions as a Chip Select pin, and will be active when
(AEN = L) AND (SA10-0 = GIO0AD10-0) AND (NIOR = L)
1
1
GIOP0 functions as a Chip Select pin, and will be active when
(AEN = L) AND (SA10-0 = GIO0AD10-0) AND (NIOW = L OR
NIOR = L)
GDA0OPI (bit 1): See below.
GDA0IPI (bit 0): See below.
GDA0OPI
GDA0IPI
0
0
GIOP0 functions as a data pin, and GIOP0→SD0, SD0→GIOP0
0
1
GIOP0 functions as a data pin, and inverse GIOP0→SD0,
SD0→GIOP0
1
0
GIOP0 functions as a data pin, and GIOP0→SD0, inverse
SD0→GIOP0
1
1
GIOP0 functions as a data pin, and inverse GIOP0→SD0, inverse
SD0→GIOP0
8.2.21 Configuration Register 15 (CR15), default = 00H
When the device is in Extended Function mode and EFIR is 15H, the CR15 register can be accessed
through EFDR. The bit definitions are as follows:
7
6
5
4
3
2
1
0
GDA0IPI
GDA0OPI
GCS0IOW
GCS0IOR
GIO0CSH
GIOP0MD0
GIOP0MD1
GIOP0MD2
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Publication Release Date: January 1996
Revision A2
W83877F
GIOP1MD2-GIOP1MD0 (bit 7-bit 5): GIOP1 pin mode selection
GIOP1MD2
GIOP1MD1
GIOP1MD0
GIOP1 pin
0
0
0
inactive (tri-state)
0
0
1
as a data output pin (SD1→GIOP1), when (AEN = L)
AND (NIOW = L) AND (SA10-0 = GIO1AD10-0), the
value of SD1 will be present on GIOP1
0
1
0
as a data input pin (GIOP1→SD1), when (AEN = L)
AND (NIOR = L) AND (SA10-0 = GIO1AD10-0), the
value of GIOP1 will be present on SD1
0
1
1
as a data input/output pin (GIOP1↔SD1).
When (AEN = L) AND (NIOW = L) AND (SA10-0 =
GIO1AD10-0), the value of SD1 will be present on
GIOP1 When (AEN = L) AND (NIOR = L) AND (SA100 = GIO1AD10-0), the value of GIOP1 will be present
on SD1
1
X
X
as a Chip Select pin, the pin will be active at (AEN =
L) AND (SA10-0 = GIO1AD10-0) OR (NIOR = L) OR
(NIOW = L)
GIO1CSH (bit 4):
0
the Chip Select pin will active LOW when (AEN = L) AND (SA10-0 = GIOAD10-0)
OR (NIOR = L) OR (NIOW = L)
1
the Chip Select pin will active HIGH when (AEN = L) AND (SA10-0 = GIOAD10-0)
OR (NIOR = L) OR (NIOW = L)
GCS1IOR (bit 3): See below.
GCS1IOW (bit 2): See below.
GCS1IOR
GCS1IOW
0
0
GIOP1 functions as a Chip Select pin, and will be active when
(AEN = L) AND (SA10-0 = GIO1AD10-0)
0
1
GIOP1 functions as a Chip Select pin, and will be active when
(AEN = L) AND (SA10-0 = GIO1AD10-0) AND (NIOW = L)
1
0
GIOP1 functions as a Chip Select pin, and will be active when
(AEN = L) AND (SA10-0 = GIO1AD10-0) AND (NIOR = L)
1
1
GIOP1 functions as a Chip Select pin, and will be active when
(AEN = L) AND (SA10-0 = GIO1AD10-0) AND (NIOW = L OR
NIOR = L)
GDA0OPI (bit 1): See below.
- 92 -
W83877F
GDA1IPI (bit 0): See below.
GDA1OPI
GDA1IPI
0
0
GIOP1 functions as a data pin, and GIOP1→SD1, SD1→GIOP1
0
1
GIOP1 functions as a data pin, and inverse GIOP1→SD1,
SD1→GIOP1
1
0
GIOP1 functions as a data pin, and GIOP1→SD1, inverse
SD1→GIOP1
1
1
GIOP1 functions as a data pin, and inverse GIOP1→ SD1, inverse
SD1→GIOP1
8.2.22 Configuration Register 16 (CR16), default = 0eH
When the device is in Extended Function mode and EFIR is 16H, the CR16 register can be accessed
through EFDR. The bit definitions are as follows:
7
6
5
4
3
2
1
0
HEFRAS
IRIDE
PNPCVS
GMDRQ
GOIQSEL
Reserved
Reserved
Reserved
Bit 7-bit 5: Reserved.
GOIQSEL (bit 4):
0
pins 92, 96 function as IRQ_B, IRQ_A, respectively.
0
pins 92, 96 function as GIO0, GIO1, respectively.
The corresponding power-on setting pin is NRTSB (pin 45).
GMDRQ (bit 3):
0
pins 39, 41 function as DRQ_A, NDACK_A, respectively.
1
pins 39, 41 function as NGMWR, NGMRD, respectively.
The corresponding power-on setting pin is SOUTB (pin 43).
PNPCVS (bit 2):
0
PnP-related registers (CR1E, CR20-29) reset to be all 0s.
1
default settings for these registers.
The corresponding power-on setting pin is NRTSA (pin 36).
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Publication Release Date: January 1996
Revision A2
W83877F
PnP register
PNPCVS = 1
PNPCVS = 0
CR1E
81H
00H
CR20
FCH
00H
CR21
7CH
00H
CR22
FDH
00H
CR23
DEH
00H
CR24
FEH
00H
CR25
BEH
00H
CR26
23H
00H
CR27
65H
00H
CR28
43H
00H
CR29
62H
00H
Note: The new value of PNPCVS must be complementary to the old one to make an effective change. For example, the user
set PNPCVS to 1 first and then reset it to 0 to reset these PnP registers if the present value of PNPCVS is 0.
must
IRIDE (bit 1):
0
pins 1, 91, 94, 95 function as IDE ports.
1
pins 1, 91, 94, 95 function as IR ports.
The corresponding power-on setting pin is SOUTA (pin 38).
pin
IRIDE = 0
IRIDE = 1
1
NRSTIDE
IRQ_G
91
NIDBEN
IRQ_H
94
NCS0
IRRX2
95
NCS1
IRTX2
HEFRAS (bit 0): combines with HEFERE (CR0C bit 5) to define how to access Extended Function
Registers (refer to CR0C bit 5 description). The corresponding power-on setting pin
is NDTRA (pin 35).
8.2.23 Configuration Register 17 (CR17), default = 00H
When the device is in Extended Function mode and EFIR is 17H, the CR17 register can be accessed
through EFDR. The bit definitions are as follows:
- 94 -
W83877F
7
6
5
4
3
2
1
0
DSUBLGRQ
DSUALGRQ
DSPRLGRQ
DSFDLGRQ
PRIRQOD
Reserved
Reserved
Reserved
Bit 7-bit 5: Reserved.
PRIRQOD (bit4):
0
printer IRQ ports are totem-poles in SPP mode and open-drains in ECP/EPP mode.
1
printer IRQ ports are totem-poles in all modes.
DSFDLGRQ (bit 3):
0
enable FDC legacy mode on IRQ and DRQ selections. DO register bit 3 has effect on
selecting IRQ.
1
disable FDC legacy mode on IRQ and DRQ selections. DO register bit 3 has no effect
on selecting IRQ.
DSPRLGRQ (bit 2):
0
enable PRT legacy mode on IRQ and DRQ selections. DCR bit 4 has effect on
selecting IRQ.
1
disable PRT legacy mode on IRQ and DRQ selections. DCR bit 4 has no effect on
selecting IRQ.
DSUALGRQ (bit 1):
0
enable UART A legacy mode on IRQ selection. MCR bit 3 has effect on selecting IRQ.
1
disable UART A legacy mode on IRQ selection. MCR bit 3 has no effect on selecting
IRQ.
DSUBLGRQ (bit 0):
0
enable UART B legacy mode on IRQ selection. MCR bit 3 has effect on selecting IRQ.
1
disable UART B legacy mode on IRQ selection. MCR bit 3 has no effect on selecting
IRQ.
- 95 -
Publication Release Date: January 1996
Revision A2
W83877F
8.2.24 Configuration Register 1E (CR1E)
When the device is in Extended Function mode and EFIR is 1EH, the CR1E register can be accessed
through EFDR. Default = 81H if CR16 bit 2 = 1; default = 00H if CR16 bit 2 = 0. The bit definitions
are as follows:
7
6
5
4
2
3
1
0
GMAS0
GMAS1
GMAD2
GMAD3
GMAD4
GMAD5
GMAD6
GMAD7
This register is used to select the base address of Game Chip Select Decoder (GAMECS) from 100H3F0H on 16-byte boundaries. NCS = 0 and A10 = 0 are required to qualify the GAMECS output.
GMAD7-GMAD2 (bit 7-bit 2): match A[9:4].
GMAS1-GMAS0 (bit 1-bit 0): CAMECS configuration.
00
01
10
11
GAMECS disable
1-byte decode, A[3:0] = 0001b
8-byte decode, A[3:0] = 0xxxb
16-byte decode, A[3:0] = xxxxb
8.2.25 Configuration Register 20 (CR20)
When the device is in Extended Function mode and EFIR is 20H, the CR20 register can be accessed
through EFDR. Default = FCH if CR16 bit 2 = 1; default = 00H if CR16 bit 2 = 0. The bit definitions
are as follows:
7
6
5
4
3
2
1
0
Reserved
Reserved
FDCAD2
FDCAD3
FDCAD4
FDCAD5
FDCAD6
FDCAD7
This register is used to select the base address of the Floppy Disk Controller (FDC) from 100H-3F0H
on 16-byte boundaries. NCS = 0 and A10 = 0 are required to access the FDC registers. A[3:0] are
always decoded as 0xxxb.
FDCAD7-FDCAD2 (bit 7-bit 2): match A[9:4]. Bit 7 = 0 and bit 6 = 0 disable this decode.
Bit 1-bit 0: Reserved, fixed at zero.
8.2.26 Configuration Register 21 (CR21)
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W83877F
When the device is in Extended Function mode and EFIR is 21H, the CR21 register can be accessed
through EFDR. Default = 7CH if CR16 bit 2 = 1; default = 00H if CR16 bit 2 = 0. The bit definitions
are as follows:
7
6
5
4
3
2
1
0
Reserved
Reserved
IDE0AD2
IDE0AD3
IDE0AD4
IDE0AD5
IDE0AD6
IDE0AD7
This register is used to select the base address of the IDE Interface Control Registers from 100H3F0H on 16-byte boundaries. NCS = 0 and A10 = 0 are required to access the IDE registers. A[3:0]
are always decoded as 0xxxb.
IDE0AD7-IDE0AD2 (bit 7-bit 2): match A[9:4]. Bit 7 = 0 and bit 6 = 0 disable this decode.
Bit 1-bit 0: Reserved, fixed at zero.
8.2.27 Configuration Register 22 (CR22)
When the device is in Extended Function mode and EFIR is 22H, the CR22 register can be accessed
through EFDR. Default = FDH if CR16 bit 2 = 1; default = 00H if CR16 bit 2 = 0. The bit definitions
are as follows:
7
6
5
4
3
2
1
0
Reserved
Reserved
IDE1AD2
IDE1AD3
IDE1AD4
IDE1AD5
IDE1AD6
IDE1AD7
This register is used to select the base address of the IDE Interface Alternate Status Register from
106H-3F6H on 16-byte boundaries + 6. NCS = 0 and A10 = 0 are required to access the IDE
Alternate Status register. A[3:0] must be 0110b.
IDE1AD7-IDE1AD2 (bit 7-bit 2): match A[9:4]. Bit 7 = 0 and bit 6 = 0 disable this decode.
Bit 1: Reserved, fixed at zero.
Bit 0: Reserved, fixed at one.
8.2.28 Configuration Register 23 (CR23)
- 97 -
Publication Release Date: January 1996
Revision A2
W83877F
When the device is in Extended Function mode and EFIR is 23H, the CR23 register can be accessed
through EFDR. Default = DEH if CR16 bit 2 = 1; default = 00H if CR16 bit 2 = 0. The bit definitions
are as follows:
7
6
5
4
3
2
1
0
PRTAD0
PRTAD1
PRTAD2
PRTAD3
PRTAD4
PRTAD5
PRTAD6
PRTAD7
This register is used to select the base address of the parallel port. If EPP is disable, the parallel port
can be set from 100H-3FCH on 4-byte boundaries. If EPP is enable, the parallel port can be set from
100H-3F8H on 8-byte boundaries. NCS = 0 and A10 = 0 are required to access the parallel port when
in compatible, bi-directional, or EPP modes. A10 is active in ECP mode.
PRTAD7-PRTAD0 (bit 7-bit 0): match A[9:2]. Bit 7 = 0 and bit 6 = 0 disable this decode.
8.2.29 Configuration Register 24 (CR24)
When the device is in Extended Function mode and EFIR is 24H, the CR24 register can be accessed
through EFDR. Default = FEH if CR16 bit 2 = 1; default = 00H if CR16 bit 2 = 0. The bit definitions
are as follows:
7
6
5
4
3
2
1
0
Reserved
URAAD1
URAAD2
URAAD3
URAAD4
URAAD5
URAAD6
URAAD7
This register is used to select the base address of the UART A from 100H-3F8H on 8-byte
boundaries. NCS = 0 and A10 = 0 are required to access the UART A registers. A[2:0] are don't-care
conditions.
URAAD7-URAAD1 (bit 7-bit 1): match A[9:3]. Bit 7 = 0 and bit 6 = 0 disable this decode.
Bit 0: Reserved, fixed at zero.
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W83877F
8.2.30 Configuration Register 25 (CR25)
When the device is in Extended Function mode and EFIR is 25H, the CR25 register can be accessed
through EFDR. Default = BEH if CR16 bit 2 = 1; default = 00H if CR16 bit 2 = 0. The bit definitions
are as follows:
7
6
5
4
3
2
1
0
Reserved
URBAD1
URBAD2
URBAD3
URBAD4
URBAD5
URBAD6
URBAD7
This register is used to select the base address of the UART B from 100H-3F8H on 8-byte
boundaries. NCS = 0 and A10 = 0 are required to access the UART B registers. A[2:0] are don't-care
conditions.
URBAD7-URBAD1 (bit 7-bit 1): match A[9:3]. Bit 7 = 0 and bit 6 = 0 disable this decode.
Bit 0: Reserved, fixed at zero.
8.2.31 Configuration Register 26 (CR26)
When the device is in Extended Function mode and EFIR is 26H, the CR26 register can be accessed
through EFDR. Default = 23H if CR16 bit 2 = 1; default = 00H if CR16 bit 2 = 0. The bit definitions are
as follows:
7
6
5
4
3
2
1
0
PRTDQS0
PRTDQS1
PRTDQS2
PRTDQS3
FDCDQS0
FDCDQS1
FDCDQS2
FDCDQS3
FDCDQS3-FDCDQS0 (bit 7-bit 4): Allocate DMA resource for FDC.
PRTDQS3-PRTDQS0 (bit 3-bit 0): Allocate DMA resource for PRT.
bit 7- bit4, bit 3 - bit 0
0000
0001
0010
0011
DMA selected
None
DMA_A
DMA_B
DMA_C
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Publication Release Date: January 1996
Revision A2
W83877F
8.2.32 Configuration Register 27 (CR27)
When the device is in Extended Function mode and EFIR is 27, the CR27 register can be accessed
through EFDR. Default = 05H if CR6 bit 2 = 1; default = 00H if CR16 bit 2 = 0. The bit definitions are
as follows:
7
6
5
4
3
2
1
0
PRTIQS0
PRTIQS1
PRTIQS2
PRTIQS3
Reserved
ECPIRQx0
ECPIRQx1
ECPIRQx2
ECPIRQx2-ECPIRQx0 (bit7-bit 5): These bits are configurable equivalents to bit[5:3] of cnfgB register
in ECP mode except that cnfgB[5:3] are read-only bits. They indicate the IRQ resource assigned for
the ECP printer port. It is the software designer's responsibility to ensure that CR27[7:5] and
CR27[3:0] are consistent. For example, CR27[7:5] should be filled with 001 (select IRQ 7) if
CR27[3:0] are to be programmed as 0101 (select IRQ_E) while IRQ_E is connected to IRQ 7.
CR27[7:5]
000
001
010
011
100
101
110
111
IRQ resource
reflect other IRQ resources selected by CR27[3:0] (default)
IRQ 7
IRQ 9
IRQ 10
IRQ 11
IRQ 14
IRQ 15
IRQ 5
Bit 4: Reserved.
PRTIQS3-PRTIQS0 (bit 3-bit 0): Select IRQ resource for the parallel port. Any unselected IRQ is in
tristate.
CR27[3:0]
IRQ selected
0000
None
0001
IRQ_A
0010
IRQ_B
0011
IRQ_C
0100
IRQ_D
0101
IRQ_E
0110
IRQ_F
0111
IRQ_G
1000
IRQ_H
- 100 -
W83877F
8.2.33 Configuration Register 28 (CR28)
When the device is in Extended Function mode and EFIR is 28, the CR28 register can be accessed
through EFDR. Default = 43H if CR6 bit 2 = 1; default = 00H if CR16 bit 2 = 0. The bit definitions are
as follows:
7
6
5
4
3
2
1
0
URBIQS0
URBIQS1
URBIQS2
URBIQS3
URAIQS0
URAIQS1
URAIQS2
URAIQS3
URAIQS3-URAIQS0 (bit 7-bit 4): Allocate interrupt resource for UART A.
URBIQS3-URBIQS0 (bit 3-bit 0): Allocate interrupt resource for UART B.
8.2.34 Configuration Register 29 (CR29)
When the device is in Extended Function mode and EFIR is 29, the CR29 register can be accessed
through EFDR. Default = 62H if CR6 bit 2 = 1; default = 00H if CR16 bit 2 = 0. The bit definitions are
as follows:
7
6
5
4
3
2
1
0
IQNIQS0
IQNIQS1
IQNIQS2
IQNIQS3
FDCIQS0
FDCIQS1
FDCIQS2
FDCIQS3
FDCIQS3-FDCIQS0 (bit 7-bit 4): Allocate interrupt resource for FDC.
IQNIQS3-IQNIQS0 (bit 3-bit 0): Allocate interrupt resource for IRQIN.
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Publication Release Date: January 1996
Revision A2
W83877F
8.2.35 Bit Map Configuration Registers
Table 7-6
Register
Power-on
Reset Value
D7
D6
D5
D4
D3
D2
D1
D0
PRTMODS0
OSCS1
OSCS0
CR0
0000 0000
0
0
0
0
PRTMODS1
CR1
0000 0000
ABCHG
0
0
0
0
0
0
0
CR2
0000 0000
RA9
RA8
RA7
RA6
RA5
RA4
RA3
CEA
CR3
0011 0000
0
GMENL
EPPVER
GMODS
0
0
SUAMIDI
SUBMIDI
CR4
0000 0000
PRTPWD
GMPWD
URAPWD
URBPWD
PRTTRI
GMTRI
URATRI
URBTRI
CR5
0000 0000
0
0
0
0
ECPFTHR3
ECPFTHR2
ECPFTHR1
ECPFTHR0
CR6
0000 0000
0
OSCS2
SEL4FDD
FIPURDWN
FDCPWD
IDEPWD
FDCTRI
IDETRI
CR7
0000 0000
FDD D T1
FDD D T0
FDD C T1
FDD C T0
FDD B T1
FDD B T0
FDD A T1
FDD A T0
CR8
0000 0000
APDTMS1
APDTMS0
DISFDDWR
SWWP
MEDIA 1
MEDIA 0
BOOT 1
BOOT 0
CR9
0000 1010
PRTMODS2
LOCKREG
EN3MODE
CRA
0001 1111
PFDCACT
PEXTACT
PDIRHISOP
PDCHACT
0
CHIP ID 3
CHIP ID 2
CHIP ID 1
CHIP ID 0
PEXTADP
PEXTEPP
PEXTECP
PEXTECPP
CRB
0000 0000
0
0
0
ENIFCHG
IDENT
MFM
INVERTZ
DRV2EN
CRC
0010 1000
TURA
TURB
HEFERE
0
URIRSEL
0
RX2INV
TX2INV
CRD
1010 0011
SIRTX1
SIRTX0
SIRRX1
SIRRX0
HDUPLX
IRMODE2
IRMODE1
IRMODE0
CR10
0000 0000
GIO0AD7
GIO0AD6
GIO0AD5
GIO0AD4
GIO0AD3
GIO0AD2
GIO0AD1
GIO0AD0
CR11
0000 0000
0
0
0
0
0
GIO0AD10
GIO0AD9
GIO0AD8
CR12
0000 0000
GIO1AD7
GIO1AD6
GIO1AD5
GIO1AD4
GIO1AD3
GIO1AD2
GIO1AD1
GIO1AD0
CR13
0000 0000
0
0
0
0
0
GIO1AD10
GIO1AD9
GIO1AD8
CR14
0000 0000
GIOP0MD2
GIOP0MD1
GIOP0MD0
GIO0CSH
GCS0IOR
GCS0IOW
GDA0OPI
GDA0IPI
CR15
0000 0000
GIOP1MD2
GIOP1MD1
GIOP1MD0
GIO1CSH
GCS1IOR
GCS1IOW
GDA1OPI
GDA1IPI
CR16
000s ssss
1
0
0
0
GOIQSEL
GMDRQ
PNPCVS
IRIDE
HEFRAS
CR17
0000 0000
0
0
0
PRIRQOD
DSFDLGRQ
DSPRLGRQ
DSUALGRQ
DSUBLGRQ
CR1E
2
1000 0001
GMAD7
GMAD6
GMAD5
GMAD4
GMAD3
GMAD2
GMAS1
GMAS0
CR20
1111 1100
2
FDCAD7
FDCAD6
FDCAD5
FDCAD4
FDCAD3
FDCAD2
0
0
2
IDE0AD7
IDE0AD6
IDE0AD5
IDE0AD4
IDE0AD3
IDE0AD2
0
0
2
IDE1AD7
IDE1AD6
IDE1AD5
IDE1AD4
IDE1AD3
IDE1AD2
0
1
CR21
0111 1100
CR22
1111 1101
2
PRTAD7
PRTAD6
PRTAD5
PRTAD4
PRTAD3
PRTAD2
PRTAD1
PRTAD0
2
URAAD7
URAAD6
URAAD5
URAAD4
URAAD3
URAAD2
URAAD1
0
CR23
1101 1110
CR24
1111 1110
2
URBAD7
URBAD6
URBAD5
URBAD4
URBAD3
URBAD2
URBAD1
0
2
FDCDQS3
FDCDQS2
FDCDQS1
FDCDQS0
PRTDQS3
PRTDQS2
PRTDQS1
PRTDQS0
2
ECPIRQx2
ECPIRQx1
ECPIRQx0
0
PRTIQS3
PRTIQS2
PRTIQS1
PRTIQS0
2
URAIQS3
URAIQS2
URAIQS1
URAIQS0
URBIQS3
URBIQS2
URBIQS1
URBIQS0
2
FDCIQS3
FDCIQS2
FDCIQS1
FDCIQS0
IQNIQS3
IQNIQS2
IQNIQS1
IQNIQS0
CR25
1011 1110
CR26
0010 0011
CR27
0000 0101
CR28
0100 0011
CR29
0110 0010
Notes:
1. 's' means its value depends on corresponding power-on setting pin.
2. These default values are valid when CR16 bit 2 is 1 during power-on reset; They will be all 0's if CR16 bit 2 is 0.
- 102 -
W83877F
9.0 SPECIFICATIONS
9.1 ABSOLUTE MAXIMUM RATINGS
PARAMETER
RATING
UNIT
-0.5 to 7.0
V
-0.5 to VDD+0.5
V
0 to +70
°C
-55 to+ 150
°C
Power Supply Voltage
Input Voltage
Operating Temperature
Storage Temperature
Note: Exposure to conditions beyond those listed under Absolute Maximum Ratings may adversely affect the life and reliability of the
device.
9.2 DC CHARACTERISTICS
(Ta = 0° C to 70° C, VDD = 5V ± 10%, VSS = 0V)
PARAMETER
SYM.
MIN.
MAX.
UNIT
CONDITIONS
I/O8t - TTL level bi-directional pin with source-sink capabilities of 8 mA
Input Low Voltage
VIL
-0.5
0.8
V
Input High Voltage
VIH
2.0
VDD+0.5
V
Output Low Voltage
VOL
0.4
V
IOL = 8 mA
Output High Voltage
VOH
V
IOH = -8 mA
Input High Leakage
ILIH
+10
µA
VIN = VDD
Input Low Leakage
ILIL
-10
µA
VIN = 0V
2.4
I/O12t - TTL level bi-directional pin with source-sink capabilities of 12 mA
Input Low Voltage
VIL
-0.5
0.8
V
Input High Voltage
VIH
2.0
VDD+0.5
V
Output Low Voltage
VOL
0.4
V
IOL = 12 mA
Output High Voltage
VOH
V
IOH = -12 mA
Input High Leakage
ILIH
+10
µA
VIN = VDD
Input Low Leakage
ILIL
-10
µA
VIN = 0V
2.4
I/O24t - TTL level bi-directional pin with source-sink capabilities of 24 mA
Input Low Voltage
VIL
-0.5
0.8
V
Input High Voltage
VIH
2.0
VDD+0.5
V
Output Low Voltage
VOL
0.4
V
IOL = 24 mA
Output High Voltage
VOH
V
IOH = -24 mA
2.4
- 103 -
Publication Release Date: January 1996
Revision A2
W83877F
9.2 DC Characteristics continued
PARAMETER
SYM.
MIN.
MAX.
UNIT
CONDITIONS
Input High Leakage
ILIH
+10
µA
VIN = VDD
Input Low Leakage
ILIL
-10
µA
VIN = 0V
OUT8t - TTL level output pin with source-sink capabilities of 8 mA
Output Low Voltage
VOL
Output High Voltage
VOH
0.4
2.4
V
IOL = 8 mA
V
IOH = -8 mA
OUT12t - TTL level output pin with source-sink capabilities of 12 mA
Output Low Voltage
VOL
Output High Voltage
VOH
0.4
2.4
V
IOL = 12 mA
V
IOH = -12 mA
OD12 - Open-drain output pin with sink capabilities of 12 mA
Output Low Voltage
VOL
0.4
V
IOL = 12 mA
OD24 - Open-drain output pin with sink capabilities of 24 mA
Output Low Voltage
VOL
0.4
V
IOL = 24 mA
INt - TTL level input pin
Input Low Voltage
VIL
-0.5
0.8
V
Input High Voltage
VIH
2.0
VDD+0.5
V
Input High Leakage
ILIH
+10
µA
VIN = VDD
Input Low Leakage
ILIL
-10
µA
VIN = 0V
INc - CMOS level input pin
Input Low Voltage
VIL
-0.5
0.3×VDD
V
Input High Voltage
VIH
0.7×VDD
VDD+0.5
V
Input High Leakage
ILIH
+10
µA
VIN = VDD
Input Low Leakage
ILIL
-10
µA
VIN = 0V
INcs - CMOS level schmitt-triggered input pin
Input Low Voltage
VIL
-0.5
1.8
V
Input High Voltage
VIH
3.0
VDD+0.5
V
Input High Leakage
ILIH
+10
µA
VIN = VDD
Input Low Leakage
ILIL
-10
µA
VIN = 0V
- 104 -
W83877F
9.3 AC CHARACTERISTICS
9.3.1 FDC: Data rate = 1 MB/500 KB/300 KB/250 KB/sec.
PARAMETER
SYM.
TEST
CONDITIONS
MIN.
TYP.
(NOTE 1)
MAX.
UNIT
SA9-SA0, AEN, DACK ,
CS, setup time to IOR ¡õ
TAR
25
nS
SA9-SA0, AEN, DACK ,
hold time for IOR ¡ô
TAR
0
nS
IOR width
TRR
80
nS
Data access time from
IOR ¡õ
TFD
CL = 100 pf
Data hold from IOR ¡õ
TDH
CL = 100 pf
10
SD to from IOR ¡ô
TDF
CL = 100 pf
10
IRQ delay from IOR ¡ô
TRI
SA9-SA0, AEN, DACK ,
setup time to IOW ¡õ
TAW
25
nS
SA9-SA0, AEN, DACK ,
hold time for IOW ¡ô
TWA
0
nS
IOW width
TWW
60
nS
Data setup time to IOW ¡ô
TDW
60
nS
Data hold time from
IOW ¡ô
TWD
0
nS
IRQ delay from IOW ¡ô
TWI
80
nS
nS
50
nS
360/570
/675
nS
360/570
/675
nS
µS
DRQ cycle time
TMCY
27
DRQ delay time DACK ¡õ
TAM
DRQ to DACK delay
TMA
0
nS
DACK width
TAA
260/430
/510
nS
IOR delay from DRQ
TMR
0
nS
IOW delay from DRQ
TMW
0
nS
50
- 105 -
nS
Publication Release Date: January 1996
Revision A2
W83877F
9.3 AC Characteristics, FDC continued
PARAMETER
SYM.
IOW or IOR response time
from DRQ
TMRW
TEST
CONDITIONS
MIN.
TYP.
(NOTE 1)
MAX.
UNIT
µS
6/12
/20/24
TC width
TTC
135/220
/260
nS
RESET width
TRST
1.8/3/3.
5
µS
INDEX width
TIDX
0.5/0.9
/1.0
µS
DIR setup time to STEP
TDST
1.0/1.6
/2.0
µS
DIR hold time from STEP
TSTD
24/40/48
µS
STEP pulse width
TSTP
6.8/11.5
/13.8
7/11.7
/14
7.2/11.9
/14.2
µS
STEP cycle width
TSC
Note 2
Note 2
Note 2
µS
WD pulse width
TWDD
100/185
/225
125/210
/250
150/235
/275
µS
Write precompensation
TWPC
100/138
/225
125/210
/250
150/235
/275
µS
Notes:
1. Typical values for T = 25° C and normal supply voltage.
2. Programmable from 2 mS through 32 mS in 2 mS increments.
9.3.2 IDE
PARAMETER
SYMBOL
MAX.
UNIT
CS0 , CS1 delay from SA valid
T1
50
nS
DBENL, DBENH delay from AEN, IOCS16, SA
T2
50
nS
IDED7 to D7 delay (read cycle)
T4
50
nS
D7 to IDED7 delay (write cycle)
T3
50
nS
- 106 -
W83877F
9.3.3 UART/Parallel Port
PARAMETER
SYMBOL
Delay from Stop to Set Interrupt
TSINT
Delay from IOR Reset Interrupt
TRINT
Delay from Initial IRQ Reset to
Transmit Start
TIRS
Delay from to Reset interrupt
THR
Delay from Initial IOW to interrupt
TSI
Delay from Stop to Set Interrupt
TSTI
Delay from IOR to Reset Interrupt
TIR
TMWO
Delay from IOR to Output
TEST
CONDITIONS
MIN.
MAX.
9/16
UNIT
Baud
Rate
1
µS
8/16
Baud
Rate
175
nS
16/16
Baud
Rate
1/2
Baud
Rate
100 pF Loading
250
nS
100 pF Loading
200
nS
100 pF Loading
1/16
100 pF Loading
9/16
Set Interrupt Delay from Modem
Input
TSIM
250
nS
Reset Interrupt Delay from IOR
TRIM
250
nS
Interrupt Active Delay
TIAD
100 pF Loading
25
nS
Interrupt Inactive Delay
TIID
100 pF Loading
30
nS
100 pF Loading
16
N
Baud Divisor
2 -1
9.3.4 Extension Adapter Mode
PARAMETER
SYM.
XRD , XWR Delay from IOR , IOW
TEST
CONDITIONS
MAX.
UNIT
tx1
50
nS
XA<0:2> Delay from SA<0:2>
tx2
50
nS
XD<0:7> Setup time
tx3
50
nS
XD<0:7> Hold time
tx4
0
nS
IRQ & Delay from XIRQ
tx5
50
nS
DRQX Delay from XDRQ
tx6
50
nS
XDACK Delay from DACKX
tx7
50
nS
XTC Delay from TC
tx8
50
nS
- 107 -
MIN.
TYP.
Publication Release Date: January 1996
Revision A2
W83877F
9.3.5 Parallel Port Mode Parameters
PARAMETER
SYM.
MIN.
TYP.
MAX.
UNIT
PD0-7, INDEX , STROBE, AUTOFD Delay from
IOW
t1
100
nS
IRQ Delay from ACK , nFAULT
t2
60
nS
IRQ Delay from IOW
t3
105
nS
IRQ Active Low in ECP and EPP Modes
t4
300
nS
ERROR Active to IRQ Active
t5
105
nS
MAX.
UNIT
200
9.3.6 EPP Data or Address Read Cycle Timing Parameters
PARAMETER
SYM.
MIN.
40
Ax Valid to IOR Asserted
nS
t2
IOR Deasserted
nS
IOR Deasserted to Ax Valid
t3
10
10
nS
IOR Deasserted to IOW or IOR Asserted
t4
40
IOR Asserted to IOCHRDY Asserted
t5
0
24
nS
PD Valid to SD Valid
t6
0
75
nS
IOR Deasserted to SD Hi-Z (Hold Time)
t7
0
40
µS
SD Valid to IOCHRDY Deasserted
t8
0
85
nS
WAIT Deasserted to IOCHRDY Deasserted
t9
60
160
nS
PD Hi-Z to PDBIR Set
t10
0
nS
WRITE Deasserted to IOR Asserted
t13
0
nS
WAIT Asserted to WRITE Deasserted
t14
0
185
nS
WAIT Deasserted to WRITE Modified
t15
60
190
nS
IOR Asserted to PD Hi-Z
t16
0
50
nS
WAIT Asserted to PD Hi-Z
t17
60
180
nS
Command Asserted to PD Valid
t18
0
nS
Command Deasserted to PD Hi-Z
t19
0
nS
WAIT Deasserted to PD Drive
t20
60
WRITE Deasserted to Command
t21
1
- 108 -
190
nS
nS
W83877F
9.3.6 EPP Data or Address Read Cycle Timing Parameters, continued
PARAMETER
SYM.
MIN.
MAX.
UNIT
PBDIR Set to Command
t22
0
20
nS
PD Hi-Z to Command Asserted
t23
0
30
nS
WAIT Asserted to Command Asserted
t24
0
195
nS
WAIT Deasserted to Command Deasserted
t25
60
180
nS
Time out
t26
10
12
nS
PD Valid to WAIT Deasserted
t27
0
nS
PD Hi-Z to WAIT Deasserted
t28
0
µS
9.3.7 EPP Data or Address Write Cycle Timing Parameters
PARAMETER
SYM.
MIN.
Ax Valid to IOW Asserted
t1
40
nS
SD Valid to IOW Asserted
t2
10
nS
IOW Deasserted to Ax Invalid
t3
10
nS
WAIT Deasserted to IOCHRDY Deasserted
t4
0
nS
Command Asserted to WAIT Deasserted
t5
10
nS
IOW Deasserted to IOW or IOR Asserted
t6
40
nS
IOCHRDY Deasserted to IOW Deasserted
t7
0
24
nS
WAIT Asserted to Command Asserted
t8
60
160
nS
IOW Asserted to WAIT Asserted
t9
0
70
nS
PBDIR Low to WRITE Asserted
t10
0
WAIT Asserted to WRITE Asserted
t11
60
185
nS
WAIT Asserted to WRITE Change
t12
60
185
nS
IOW Asserted to PD Valid
t13
0
50
nS
WAIT Asserted to PD Invalid
t14
0
nS
PD Invalid to Command Asserted
t15
10
nS
IOW to Command Asserted
t16
5
35
nS
WAIT Asserted to Command Asserted
t17
60
210
nS
WAIT Deasserted to Command Deasserted
t18
60
190
nS
Command Asserted to WAIT Deasserted
t19
0
10
µS
- 109 -
MAX.
UNIT
nS
Publication Release Date: January 1996
Revision A2
W83877F
9.3.7 EPP Data or Address Write Cycle Timing Parameters, continued
PARAMETER
SYM.
MIN.
MAX.
UNIT
Time out
t20
10
12
µS
Command Deasserted to WAIT Asserted
t21
0
nS
IOW Deasserted to WRITE Deasserted and PD
invalid
t22
0
nS
9.3.8 Parallel Port FIFO Timing Parameters
PARAMETER
SYMBOL
MIN.
MAX.
UNIT
DATA Valid to nSTROBE Active
t1
600
nS
nSTROBE Active Pulse Width
t2
600
nS
DATA Hold from nSTROBE Inactive
t3
450
nS
BUSY Inactive to PD Inactive
t4
80
nS
BUSY Inactive to nSTROBE Active
t5
680
nS
nSTROBE Active to BUSY Active
t6
500
nS
9.3.9 ECP Parallel Port Forward Timing Parameters
PARAMETER
SYMBOL
MIN.
MAX.
UNIT
nAUTOFD Valid to nSTROBE Asserted
t1
0
60
nS
PD Valid to nSTROBE Asserted
t2
0
60
nS
BUSY Deasserted to nAUTOFD Changed
t3
80
180
nS
BUSY Deasserted to PD Changed
t4
80
180
nS
nSTROBE Deasserted to BUSY Deasserted
t5
0
BUSY Deasserted to nSTROBE Asserted
t6
80
nSTROBE Asserted to BUSY Asserted
t7
0
BUSY Asserted to nSTROBE Deasserted
t8
80
180
nS
SYMBOL
MIN.
MAX.
UNIT
PD Valid to nACK Asserted
t1
0
nS
nAUTOFD Deasserted to PD Changed
t2
0
nS
nAUTOFD Asserted to nACK Asserted
t3
0
nS
nAUTOFD Deasserted to nACK Deasserted
t4
0
nS
nACK Deasserted to nAUTOFD Asserted
t5
80
200
nS
PD Changed to nAUTOFD Deasserted
t6
80
200
nS
nS
200
nS
nS
9.3.10 ECP Parallel Port Reverse Timing Parameters
PARAMETER
10.0 TIMING WAVEFORMS
- 110 -
W83877F
10.1 FDC
Write Date
Processor Read Operation
WD
SA0-SA9
TWDD
AEN
CS
TAR
TRA
DACK
TRR
IOR
TDH
Index
TFD
TDF
D0-D7
INDEX
TR
IRQ
TIDX
Processor Write Operation
TIDX
Terminal Count
SA0-SA9
AEN
DACK
TAW
TC
TWA
TTC
TWW
IOW
TWD
Reset
TDW
D0-D7
RESET
TWI
TRST
IRQ
DMA Operation
Drive Seek operation
TAM
DRQ
DIR
TMCY
DACK
TAA
TMA
TDST
TMRW
IOW or
TSTP
TSTD
STEP
IOR
TMW (IOW)
TMR (IOR)
TSC
- 111 -
Publication Release Date: January 1996
Revision A2
W83877F
10.2 IDE
SA<0:9>
IOR
IOW
DATA READ
IDED7
T4
D7
DATA WRITE
IDED7
T3
D7
CS0
CS1
T1
IOCS16
DBENL
DBENH
T2
- 112 -
W83877F
10.3 UART/Parallel
Receiver Timing
SIN
(RECEIVER
STAR
INPUT DATA)
DATA BITS
PARITY
(5-8)
STOP
TSINT
IRQ3 or IRQ4
IOR
(READ RECEIVER
TRINT
BUFFER REGISTER)
Transmitter Timing
SERIAL OUT
STAR
(SOUT)
STAR
DATA
(5-8)
PARITY
THRS
STOP
(1-2)
TSTI
IRQ3 or IRQ4
THR
IOW
(WRITE THR)
THR
TSI
TIR
IOR
(READ TIR)
- 113 -
Publication Release Date: January 1996
Revision A2
W83877F
10.3.1 Modem Control Timing
MODEM Control Timing
IOW
(WRITE MCR)
¢x
¢x
¢x
¢x¢
¡÷
RTS,DTR
CTS,DSR
DCD
IRQ3 or
IRQ4
¢x
¢x¢
IOR
(READ MSR)
¡÷
¡ö TMWO
¢x
¢x
¢x
¢x
¢
¢x
¢x
¢x¢
¢x¢
¢x
¡÷
¡÷ ¡ö TSIM
¢x
¢x
¢x
¢x¢
¢x
¢x
¢x¢
¡÷¢x ¡öTRIM
¢x
¢x
¢x¢
¡ö TSIM
¢x
¢x
¢x¢
¢x
¢x
¢x¢
RI
Printer Interrupt Timing
ACK
IRQ7
¡÷
¢x
¢x
¢x¢
¢x
¢x
¢x
¡ö TLAD
¢x
¢x
¢x¢
¢x
¢x
- 114 -
¡öTMWO
¢x
¢x
¢x
¢x¢
¢x
¢x
¢x¢
¢x¢x
TRIM
¢x
¢x¢
TSIM
¢x
¢x
¢x
¢x
¢x
¢x
¢x
¢x
¢x
¢
¢x
¢x
¢x¢
¢x
¢x ¢x
TLID
¢x
¢x¢
¢x
¢x
¢x
¢x
¢x¢
¢x
¢x
¢x
¢x¢
¡÷ ¡ö
¡ö ¡÷
¡÷
¡ö
W83877F
10.4 Parallel Port
10.4.1 Parallel Port Timing
IOW
t1
INIT, STROBE
AUTOFD, SLCTIN
PD<0:7>
ACK
t2
IRQ (SPP)
IRQ
(EPP or ECP)
t3
t4
nFAULT
(ECP)
ERROR
(ECP)
t5
t2
t4
IRQ
- 115 -
Publication Release Date: January 1996
Revision A2
W83877F
10.4.2 EPP Data or Address Read Cycle (EPP Version 1.9)
t3
A<0:10>
IOR
t1
t2
t6
t4
t7
SD<0:7>
t8
t5
t9
IOCHRDY
t10
t13
t15
t14
WRITE
t16
t18
t19
t20
t17
PD<0:7>
t21
ADDRSTB
t22
t23 t24
t25
DATASTB
t26
t27
WAIT
- 116 -
t28
W83877F
10.4.3 EPP Data or Address Write Cycle (EPP Version 1.9)
t3
t4
A10-A0
SD<0:7>
t1
t5
t2
IOW
IOCHRDY
t7
t6
t8
t9
t10
t11
WRITE
t12
t13
t14
PD<0:7>
t15
t16
t17
t18
DATAST
ADDRSTB
t19
t20
t21
WAIT
t22
PBDIR
- 117 -
Publication Release Date: January 1996
Revision A2
W83877F
10.4.4 EPP Data or Address Read Cycle (EPP Version 1.7)
t3
A<0:10>
IOR
t1
t2
t4
t6
t7
SD<0:7>
t8
t5
t9
IOCHRDY
t10
t13
t15
t14
WRITE
t16
t18
t19
t17
t20
PD<0:7>
t21
ADDRSTB
t22
t23
t25
t24
DATASTB
t26
t27
WAIT
- 118 -
t28
W83877F
10.4.5 EPP Data or Address Write Cycle (EPP Version 1.7)
t3
t4
A10-A0
SD<0:7>
t1
t5
t2
IOW
t7
t6
t8
IOCHRDY
WRITE
t9
t10
t11
t13
t22
t22
PD<0:7>
t15
t16
t17
t18
DATAST
ADDRSTB
t19
t20
WAIT
10.4.6 Parallel Port FIFO Timing
t4
t3
>|
>|
PD<0:7>
t1
nSTROBE
t2
>|
t6
>
t5
>|
>|
BUSY
- 119 -
Publication Release Date: January 1996
Revision A2
W83877F
10.4.7 ECP Parallel Port Forward Timing
t3
nAUTOFD
t4
PD<0:7>
t1
t2
t6
t8
nSTROBE
t5
t5
t7
BUSY
10.4.8 ECP Parallel Port Reverse Timing
t2
PD<0:7>
t1
t3
t4
nACK
t5
t6
nAUTOFD
- 120 -
t5
W83877F
10.4.9 Extension Adapter Mode Command Cycle
IOR
IOW
XRD
XWR
tx1
SA<0:2>
XA<0:2>
tx2
XD<0:7>
tx3
tx4
10.4.10 Extension Adapter Mode Interrupt Cycle
XIRQ
IRQ7
tx5
- 121 -
Publication Release Date: January 1996
Revision A2
W83877F
10.4.11 Extension Adapter Mode DMA Cycle
XDRQ
tx6
DRQX
DACKX
XDACK
tx7
TC
XTC
tx8
11.0 APPLICATION CIRCUITS
11.1 Parallel Port Extension FDD
JP13
WE2/SLCT
WD2/PE
MOB2/BUSY
DSB2/ACK
PD7
PD6
PD5
DCH2/PD4
RDD2/PD3
STEP2/SLIN
WP2/PD2
DIR2/INIT
TRK02/PD1
HEAD2/ERR
IDX2/PD0
RWC2/AFD
STB
13
25
12
24
11
23
10
22
9
21
8
20
7
19
6
18
5
17
4
16
3
15
2
14
1
JP 13A
DCH2
HEAD2
RDD2
WP2
TRK02
WE2
WD2
STEP2
DIR2
MOB2
DSB2
IDX2
RWC2
34
32
30
28
26
24
22
20
18
16
14
12
10
8
6
4
2
33
31
29
27
25
23
21
19
17
15
13
11
9
7
5
3
1
EXT FDC
PRINTER PORT
Parallel Port Extension FDD Mode Connection Diagram
- 122 -
W83877F
11.2 Parallel Port Extension 2FDD
JP13
WE2/SLCT
WD2/PE
MOB2/BUSY
DSB2/ACK
DSA2/PD7
MOA2/PD6
PD5
DCH2/PD4
RDD2/PD3
STEP2/SLIN
WP2/PD2
DIR2/INIT
TRK02/PD1
HEAD2/ERR
IDX2/PD0
RWC2/AFD
STB
13
25
12
24
11
23
10
22
9
21
8
20
7
19
6
18
5
17
4
16
3
15
2
14
1
JP 13A
DCH2
HEAD2
RDD2
WP2
TRK02
WE2
WD2
STEP2
DIR2
MOB2
DSA2
DSB2
MOA2
IDX2
RWC2
34
32
30
28
26
24
22
20
18
16
14
12
10
8
6
4
2
33
31
29
27
25
23
21
19
17
15
13
11
9
7
5
3
1
EXT FDC
PRINTER PORT
Parallel Port Extension 2FDD Connection Diagram
- 123 -
Publication Release Date: January 1996
Revision A2
W83877F
11.3 Parallel Port Joystick Mode
13
25
12
24
8
11
15
23
7
10
14
22
9
8
7
6
5
4
3
81K
21
20
81K
19
Joystick
15-pin
Connector
Printer Port
25-pin
Connector
VDD
1,8,9,15
1,14,15,16,17
GND
4,5,12
18~25
6
13
D0
3
2
5
12
D1
6
3
4
11
D2
NC
4
D3
NC
5
D4
D5
2
7
6
7
D6
NC
8
D7
NC
9
3
18
2
17
1
10
9
16
Joystick 15-pin connector
15
Signal
2
1
14
Printer Port
25-pin Connector
Parallel Port Joystick Mode Connection Diagram
11.4 Four FDD Mode
74LS139
7407(2)
W83777F
DSA
DSB
G1
A1
B1
MOA
MOB
G2
A2
B2
1Y0
1Y1
1Y2
1Y3
2Y0
2Y1
2Y2
2Y3
- 124 -
DSA
DSB
DSC
DSD
MOA
MOB
MOC
MOD
W83877F
12.0 PACKAGE DIMENSIONS
(100-pin QFP)
HD
D
100
81
Symbol
1
A
A1
A2
b
c
D
E
e
HD
HE
L
L1
y
θ
80
E HE
51
30
Dimension in inches
Min. Nom. Max.
Dimension in mm
Min. Nom. Max.
0.130
0.004
3.30
0.10
0.107
0.112
0.117
2.73
2.85
2.97
0.010
0.012
0.016
0.25
0.30
0.40
0.004
0.006
0.010
0.10
0.15
0.25
0.546
0.551
0.556
13.87
14.00
14.13
0.782
0.787
0.792
19.87
20.00
20.13
0.020
0.026
0.032
0.50
0.65
0.80
0.728
0.740
0.752
18.49
18.80
19.10
0.964
0.976
0.988
24.49
24.80
25.10
0.039
0.047
0.055
1.00
1.20
1.40
0.087
0.094
0.103
2.21
2.40
2.62
0.004
0
12
0.10
0
12
Notes:
31
e
b
50
1. Dimension D & E do not include interlead
flash.
2. Dimension b does not include dambar
protrusion/intrusion.
3. Controlling dimension: Millimeters
4. General appearance spec. should be based
on final visual inspection spec.
c
A2
Seating Plane
See Detail F
A
A1
θ
L
y
L1
Detail F
Headquarters
Winbond Electronics (H.K.) Ltd.
No. 4, Creation Rd. III,
Science-Based Industrial Park,
Hsinchu, Taiwan
TEL: 886-3-5770066
FAX: 886-3-5792646
http://www.winbond.com.tw/
Voice & Fax-on-demand: 886-2-7197006
Rm. 803, World Trade Square, Tower II,
123 Hoi Bun Rd., Kwun Tong,
Kowloon, Hong Kong
TEL: 852-27516023
FAX: 852-27552064
Winbond Electronics North America Corp.
Winbond Memory Lab.
Winbond Microelectronics Corp.
Winbond Systems Lab.
2730 Orchard Parkway, San Jose,
CA 95134, U.S.A.
TEL: 1-408-9436666
FAX: 1-408-9436668
Taipei Office
11F, No. 115, Sec. 3, Min-Sheng East Rd.,
Taipei, Taiwan
TEL: 886-2-7190505
FAX: 886-2-7197502
Note: All data and specifications are subject to change without notice.
- 125 -
Publication Release Date: January 1996
Revision A2