WINBOND W83627HF-AW

W83627HF/F
WINBOND I/O
W83627HF/F Data Sheet Revision History
Version
Pages
Dates
Version
09/25/98
0.50
on Web
Main Contents
Not released
For internal use only
1
n.a.
2
88-93,102,105,
139,151,153
11/10/9
8
0.51
3
90-93;113-115
01/11/9
9
0.52
Pinout and register correction.
4
90,91,113-115,
119-123,133,136,
137,140,141
07/26/9
9
0.53
Typo and data correction.
H/W Monitor register explanation.
First published.
Explanation of H/W Monitor function
and
register correction.
5
6
7
8
9
1
0
Please note that all data and specifications are subject to change without notice. All
the trade marks of products and companies mentioned in this data sheet belong to
their respective owners.
LIFE SUPPORT APPLICATIONS
These products are not designed for use in life support appliances, devices, or
systems where malfunction of these products can reasonably be expected to result
in personal injury. Winbond customers using or selling these products for use in such
W83627HF/F
PRELIMINARY
applications do so at their own risk and agree to fully indemnify Winbond for any
damages resulting from such improper use or sales.
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Publication Release Date:Sep 1998
Revision 0.50
W83627HF/F
PRELIMINARY
TABLE OF CONTENTS
GENERAL DESCRIPTION ....................................................................................................... 1
PIN CONFIGURATION FOR 627F.......................................................................................... 5
PIN CONFIGURATION FOR 627HF ...................................................................................... 6
1. PIN DESCRIPTION................................................................................................................ 7
1.1 LPC INTERFACE...................................................................................................................................................7
1.2 FDC INTERFACE ...................................................................................................................................................8
1.3 MULTI-MODE PARALLEL PORT......................................................................................................................9
1.4 SERIAL PORT INTERFACE ..............................................................................................................................14
1.5 KBC INTERFACE................................................................................................................................................15
1.6 ACPI INTERFACE...............................................................................................................................................15
1.7 HARDWARE MONITOR INTERFACE............................................................................................................15
(FOR W83627HF ONLY, ALL THESE PINS IN W83627F ARE NC.)........................................................15
1.8 GAME PORT & MIDI PORT..............................................................................................................................16
1.9 GENERAL PURPOSE I/O PORT.....................................................................................................................18
1.9.1 General Purpose I/O Port 1 (Power source is Vcc)......................................................................................18
1.9.2 General Purpose I/O Port 2 (Power source is Vcc)......................................................................................18
1.9.3 General Purpose I/O Port 3 (Power souce is VSB) .....................................................................................19
1.10 POWER PINS .....................................................................................................................................................19
2. LPC (LOW PIN COUNT) INTERFACE............................................................................20
3. FDC FUNCTIONAL DESCRIPTION ................................................................................21
3.1 W83627HF FDC ...................................................................................................................................................21
3.1.1 AT interface .....................................................................................................................................................21
3.1.2 FIFO (Data).....................................................................................................................................................21
3.1.3 Data Separator...............................................................................................................................................22
3.1.4 Write Precompensation..................................................................................................................................22
3.1.5 Perpendicular Recording Mode....................................................................................................................22
3.1.6 FDC Core .......................................................................................................................................................23
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W83627HF/F
PRELIMINARY
3.1.7 FDC Commands ............................................................................................................................................23
3.2 REGISTER DESCRIPTIONS..............................................................................................................................34
3.2.1 Status Register A (SA Register) (Read base address + 0)...........................................................................34
3.2.2 Status Register B (SB Register) (Read base address + 1)...........................................................................36
3.2.3 Digital Output Register (DO Register) (Write base address + 2) ..............................................................38
3.2.4 Tape Drive Register (TD Register) (Read base address + 3) .....................................................................38
3.2.5 Main Status Register (MS Register) (Read base address + 4) ...................................................................39
3.2.6 Data Rate Register (DR Register) (Write base address + 4) ......................................................................39
3.2.7 FIFO Register (R/W base address + 5) ........................................................................................................41
3.2.8 Digital Input Register (DI Register) (Read base address + 7) ...................................................................43
3.2.9 Configuration Control Register (CC Register) (Write base address + 7) .................................................44
4. UART PORT...........................................................................................................................45
4.1 UNIVERSAL ASYNCHRONOUS RECEIVER/TRANSMITTER (UART A, UART B) ............................45
4.2 REGISTER ADDRESS ........................................................................................................................................45
4.2.1 UART Control Register (UCR) (Read/Write)................................................................................................45
4.2.2 UART Status Register (USR) (Read/Write) ...................................................................................................47
4.2.3 Handshake Control Register (HCR) (Read/Write) ......................................................................................48
4.2.4 Handshake Status Register (HSR) (Read/Write)..........................................................................................49
4.2.5 UART FIFO Control Register (UFR) (Write only) ......................................................................................50
4.2.6 Interrupt Status Register (ISR) (Read only) .................................................................................................51
4.2.7 Interrupt Control Register (ICR) (Read/Write) ............................................................................................52
4.2.8 Programmable Baud Generator (BLL/BHL) (Read/Write)........................................................................52
4.2.9 User-defined Register (UDR) (Read/Write)..................................................................................................53
5. CIR RECEIVER PORT ........................................................................................................54
5.1 CIR REGISTERS ...................................................................................................................................................54
5.1.1 Bank0.Reg0 - Receiver Buffer Registers (RBR) (Read)................................................................................54
5.1.2 Bank0.Reg1 - Interrupt Control Register (ICR) ...........................................................................................54
5.1.3 Bank0.Reg2 - Interrupt Status Register (ISR)...............................................................................................54
5.1.4 Bank0~3.Reg3 - CIR Control Register 0/Bank Select Register (CTR0/BSR) (BANK0~3)........................55
5.1.5 Bank0.Reg4 - CIR Control Register (CTR)...................................................................................................55
5.1.6 Bank0.Reg5 - UART Line Status Register (USR) ........................................................................................56
5.1.7 Bank0.Reg6 - Remote Infrared Config Register (RIR_CFG) ......................................................................57
5.1.8 Bank0.Reg7 - User Defined Register (UDR/AUDR)....................................................................................58
5.1.9 Bank1.Reg0~1 - Baud Rate Divisor Latch (BLL/BHL) ...............................................................................59
5.1.10 Bank1.Reg2 - Version ID Regiister I (VID) ...............................................................................................60
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Revision 0.50
W83627HF/F
PRELIMINARY
5.1.11 Bank0~3.Reg3 - CIR Control Register 0/Bank Select Register (CTR0/BSR) (BANK0~3).....................60
5.1.12 Bank1.Reg4 - Timer Low Byte Register (TMRL).......................................................................................60
5.1.13 Bank1.Reg5 - Timer High Byte Register (TMRH) .....................................................................................60
6. PARALLEL PORT ...............................................................................................................61
6.1 PRINTER INTERFACE LOGIC ..........................................................................................................................61
6.2 ENHANCED PARALLEL PORT (EPP) .............................................................................................................62
6.2.1 Data Swapper.................................................................................................................................................63
6.2.2 Printer Status Buffer .......................................................................................................................................63
6.2.3 Printer Control Latch and Printer Control Swapper..................................................................................64
6.2.4 EPP Address Port............................................................................................................................................64
6.2.5 EPP Data Port 0-3 ..........................................................................................................................................65
6.2.6 Bit Map of Parallel Port and EPP Registers.................................................................................................65
6.2.7 EPP Pin Descriptions ....................................................................................................................................66
6.2.8 EPP Operation ................................................................................................................................................66
6.3 EXTENDED CAPABILITIES PARALLEL (ECP) PORT ...............................................................................67
6.3.1 ECP Register and Mode Definitions..............................................................................................................67
6.3.2 Data and ecpAFifo Port ................................................................................................................................68
6.3.3 Device Status Register (DSR) ........................................................................................................................68
6.3.4 Device Control Register (DCR)......................................................................................................................69
6.3.5 cFifo (Parallel Port Data FIFO) Mode = 010.............................................................................................70
6.3.6 ecpDFifo (ECP Data FIFO) Mode = 011.....................................................................................................70
6.3.7 tFifo (Test FIFO Mode) Mode = 110 ...........................................................................................................70
6.3.8 cnfgA (Configuration Register A) Mode = 111...........................................................................................70
6.3.9 cnfgB (Configuration Register B) Mode = 111..........................................................................................70
6.3.10 ecr (Extended Control Register) Mode = all..............................................................................................71
6.3.11 Bit Map of ECP Port Registers ...................................................................................................................72
6.3.12 ECP Pin Descriptions..................................................................................................................................73
6.3.13 ECP Operation.............................................................................................................................................74
6.3.14 FIFO Operation ...........................................................................................................................................74
6.3.15 DMA Transfers.............................................................................................................................................75
6.3.16 Programmed I/O (NON-DMA) Mode ........................................................................................................75
6.4 EXTENSION FDD MODE (EXTFDD) ..............................................................................................................75
6.5 EXTENSION 2FDD MODE (EXT2FDD)..........................................................................................................75
7. KEYBOARD CONTROLLER ............................................................................................76
7.1 OUTPUT BUFFER................................................................................................................................................77
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7.2 INPUT BUFFER ....................................................................................................................................................77
7.3 STATUS REGISTER ............................................................................................................................................77
7.4 COMMANDS.........................................................................................................................................................78
7.5 HARDWARE GATEA20/KEYBOARD RESET CONTROL LOGIC.............................................................80
7.5.1 KB Control Register (Logic Device 5, CR-F0) .............................................................................................80
7.5.2 Port 92 Control Register (Default Value = 0x24)........................................................................................80
8. GENERAL PURPOSE I/O....................................................................................................81
9. PLUG AND PLAY CONFIGURATION ............................................................................84
9.1 COMPATIBLE PNP ..............................................................................................................................................84
9.1.1 Extended Function Registers..........................................................................................................................84
9.1.2 Extended Functions Enable Registers (EFERs)............................................................................................85
9.1.3 Extended Function Index Registers (EFIRs), Extended Function Data Registers(EFDRs) ......................85
9.2 CONFIGURATION SEQUENCE........................................................................................................................85
9.2.1 Enter the extended function mode..................................................................................................................85
9.2.2 Configurate the configuration registers........................................................................................................85
9.2.3 Exit the extended function mode ....................................................................................................................86
9.2.4 Software programming example....................................................................................................................86
10. ACPI REGISTERS FEATURES .......................................................................................87
11. HARDWARE MONITOR...................................................................................................88
11.1 GENERAL DESCRIPTION ...............................................................................................................................88
11.2 ACCESS INTERFACE .......................................................................................................................................88
11.2.1 LPC interface.................................................................................................................................................88
11.2.2 I2C interface..................................................................................................................................................90
11.3 ANALOG INPUTS..............................................................................................................................................94
11.3.1 Monitor over 4.096V voltage:......................................................................................................................94
11.3.2 Monitor negative voltage: ............................................................................................................................95
11.3.3 Temperature Measurement Machine...........................................................................................................96
11.4 FAN SPEED COUNT AND FAN SPEED CONTROL...................................................................................97
11.4.1 Fan speed count ............................................................................................................................................97
11.4.2 Fan speed control .........................................................................................................................................99
11.5 SMI# INTERRUPT MODE ................................................................................................................................99
11.5.1 Voltage SMI# mode :....................................................................................................................................99
11.5.2 Fan SMI# mode : ..........................................................................................................................................99
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11.5.3 The W83627HF temperature sensor 1 SMI# interrupt has two modes: ............................................... 100
11.5.4 The W83627HF temperature sensor 2 and sensor 3 SMI# interrupt has two modes and it is
programmed at CR[4Ch] bit 6. ............................................................................................................. 101
11.6 OVT# INTERRUPT MODE............................................................................................................................ 102
11.6.1 The W83627HF temperature sensor 2 and 3 Over-Temperature (OVT#) has the following modes. 102
11.7 REGISTERS AND RAM ................................................................................................................................. 103
11.7.1 Address Register (Port x5h) ...................................................................................................................... 103
11.7.2 Data Register (Port x6h) ........................................................................................................................... 106
11.7.3 Configuration Register ¾ Index 40h ......................................................................................................... 106
11.7.4 Interrupt Status Register 1¾ Index 41h ..................................................................................................... 107
11.7.5 Interrupt Status Register 2 ¾ Index 42h .................................................................................................... 108
11.7.6 SMI# Mask Register 1 ¾ Index 43h ........................................................................................................... 108
11.7.7 SMI# Mask Register 2 ¾ Index 44h ........................................................................................................... 109
11.7.8 Reserved Register ¾ Index 45h................................................................................................................... 109
11.7.9 Chassis Clear Register -- Index 46h......................................................................................................... 109
11.7.10 VID/Fan Divisor Register ¾ Index 47h ................................................................................................... 110
11.7.11 Serial Bus Address Register ¾ Index 48h................................................................................................ 110
11.7.12 Value RAM ¾ Index 20h- 3Fh or 60h - 7Fh (auto-increment) ............................................................. 111
11.7.13 Voltage ID (VID4) & Device ID Register - Index 49h .......................................................................... 112
11.7.14 Temperature 2 and Temperature 3 Serial Bus Address Register--Index 4Ah .................................... 113
11.7.15 Pin Control Register - Index 4Bh ........................................................................................................... 113
11.7.16 IRQ/OVT# Property Select Register- Index 4Ch ................................................................................... 114
11.7.17 FAN IN/OUT and BEEP Control Register- Index 4Dh........................................................................ 115
11.7.18 Register 50h ~ 5Fh Bank Select Register - Index 4Eh (No Auto Increase)......................................... 116
11.7.19 Winbond Vendor ID Register - Index 4Fh (No Auto Increase)............................................................ 116
11.7.20 Winbond Test Register -- Index 50h - 55h (Bank 0) ............................................................................ 117
11.7.21 BEEP Control Register 1-- Index 56h (Bank 0) .................................................................................... 117
11.7.22 BEEP Control Register 2-- Index 57h (Bank 0) .................................................................................... 117
11.7.23 Chip ID -- Index 58h (Bank 0)................................................................................................................ 118
11.7.24 Reserved Register -- Index 59h (Bank 0) .............................................................................................. 119
11.7.25 PWMOUT1 Control -- Index 5Ah (Bank 0)........................................................................................... 119
11.7.26 PWMOUT2 Control -- Index 5Bh (Bank 0)........................................................................................... 119
11.7.27 PWMOUT1/2 Clock Select -- Index 5Ch (Bank 0)................................................................................ 120
11.7.28 VBAT Monitor Control Register -- Index 5Dh (Bank 0) ...................................................................... 120
11.7.29 Reserved Register -- 5Eh (Bank 0) ....................................................................................................... 121
11.7.30 Reserved Register -- Index 5Fh (Bank 0) .............................................................................................. 121
11.7.31 Temperature Sensor 2 Temperature (High Byte) Register - Index 50h (Bank 1) ............................... 121
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PRELIMINARY
11.7.32 Temperature Sensor 2 Temperature (Low Byte) Register - Index 51h (Bank 1) ................................ 122
11.7.33 Temperature Sensor 2 Configuration Register - Index 52h (Bank 1) ................................................. 122
11.7.34 Temperature Sensor 2 Hysteresis (High Byte) Register - Index 53h (Bank 1).................................... 123
11.7.35 Temperature Sensor 2 Hysteresis (Low Byte) Register - Index 54h (Bank 1) ..................................... 123
11.7.36 Temperature Sensor 2 Over-temperature (High Byte) Register - Index 55h (Bank 1)....................... 124
11.7.37 Temperature Sensor 2 Over-temperature (Low Byte) Register - Index 56h (Bank 1) ........................ 124
11.7.38 Temperature Sensor 3 Temperature (High Byte) Register - Index 50h (Bank 2) ............................... 125
11.7.39 Temperature Sensor 3 Temperature (Low Byte) Register - Index 51h (Bank 2) ................................ 125
11.7.40 Temperature Sensor 3 Configuration Register - Index 52h (Bank 2) ................................................. 125
11.7.41 Temperature Sensor 3 Hysteresis (High Byte) Register - Index 53h (Bank 2).................................... 126
11.7.42 Temperature Sensor 3 Hysteresis (Low Byte) Register - Index 54h (Bank 2) ..................................... 126
11.7.43 Temperature Sensor 3 Over-temperature (High Byte) Register - Index 55h (Bank 2)....................... 127
11.7.44 Temperature Sensor 3 Over-temperature (Low Byte) Register - Index 56h(Bank 2) ......................... 127
11.7.45 Interrupt Status Register 3 -- Index 50h (BANK4)................................................................................ 128
11.7.46 SMI# Mask Register 3 -- Index 51h (BANK 4) ..................................................................................... 128
11.7.47 Reserved Register -- Index 52h (Bank 4) ............................................................................................... 128
11.7.48 BEEP Control Register 3-- Index 53h (Bank 4) .................................................................................... 129
11.7.49 Temperature Sensor 1 Offset Register -- Index 54h (Bank 4) .............................................................. 129
11.7.50 Temperature Sensor 2 Offset Register -- Index 55h (Bank 4) .............................................................. 130
11.7.51 Temperature Sensor 3 Offset Register -- Index 56h (Bank 4) .............................................................. 130
11.7.52 Reserved Register -- Index 57h--58h...................................................................................................... 130
11.7.53 Real Time Hardware Status Register I -- Index 59h (Bank 4) ............................................................. 131
11.7.54 Real Time Hardware Status Register II -- Index 5Ah (Bank 4)............................................................ 131
11.7.55 Real Time Hardware Status Register III -- Index 5Bh (Bank 4) .......................................................... 132
11.7.56 Reserved Register -- Index 5Ch-5Dh (Bank 4) ...................................................................................... 133
11.7.57 Value RAM 2¾ Index 50h - 5Ah (auto-increment) (BANK 5) .............................................................. 133
11.7.58 Winbond Test Register -- Index 50h (Bank 6) ....................................................................................... 133
12. SERIAL IRQ .......................................................................................................................134
12.1 START FRAME................................................................................................................................................ 134
12.2 IRQ/DATA FRAME......................................................................................................................................... 134
12.3 STOP FRAME .................................................................................................................................................. 135
13. CONFIGURATION REGISTER....................................................................................136
13.1 CHIP (GLOBAL) CONTROL REGISTER ................................................................................................... 136
13.2 LOGICAL DEVICE 0 (FDC).......................................................................................................................... 142
13.3 LOGICAL DEVICE 1 (PARALLEL PORT) ................................................................................................. 145
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13.4 LOGICAL DEVICE 2 (UART A)¢)................................................................................................................ 146
13.5 LOGICAL DEVICE 3 (UART B)................................................................................................................... 147
13.6 LOGICAL DEVICE 5 (KBC) ......................................................................................................................... 148
13.7 LOGICAL DEVICE 6 (CIR) ........................................................................................................................... 149
13.8 LOGICAL DEVICE 7 (GAME PORT AND MIDI PORT AND GPIO PORT 1) .................................... 150
13.9 LOGICAL DEVICE 8 (GPIO PORT 2) .......................................................................................................... 150
13.10 LOGICAL DEVICE 9 (GPIO PORT 3 THIS POWER OF THE PORT IS STANDBY SOURCE (VSB) )152
13.11 LOGICAL DEVICE A (ACPI) ..................................................................................................................... 153
13.12 LOGICAL DEVICE B (HARDWARE MONITOR) .................................................................................. 160
14. SPECIFICATIONS ...........................................................................................................161
14.1 ABSOLUTE MAXIMUM RATINGS............................................................................................................ 161
14.2 DC CHARACTERISTICS .............................................................................................................................. 161
15. APPLICATION CIRCUITS............................................................................................164
15.1 PARALLEL PORT EXTENSION FDD ........................................................................................................ 164
15.2 PARALLEL PORT EXTENSION 2FDD...................................................................................................... 165
15.3 FOUR FDD MODE ......................................................................................................................................... 165
16. ORDERING INSTRUCTION .........................................................................................166
17. HOW TO READ THE TOP MARKING .....................................................................166
18. PACKAGE DIMENSIONS..............................................................................................167
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Revision 0.50
W83627HF/F
PRELIMINARY
GENERAL DESCRIPTION
The W83627HF and W83627F are evolving product from Winbond's most popular I/O family. They
feature a whole new interface, namely LPC (Low Pin Count) interface, which will be supported in the
next generation Intel chip-set. This interface as its name suggests is to provide an economical
implementation of I/O's interface with lower pin count and still maintains equivalent performance as its
ISA interface counterpart. Approximately 40 pin counts are saved in LPC I/O comparing to ISA
implementation. With this additional freedom, we can implement more devices on a single chip as
demonstrated in W83627F/HF's integration of Game Port and MIDI Port. It is fully transparent in terms of
software which means no BIOS or device driver update is needed except chip-specific configuration.
The disk drive adapter functions of W83627F/HF include a floppy disk drive controller compatible with
the industry standard 82077/ 765, data separator, write pre-compensation circuit, decode logic, data rate
selection, clock generator, drive interface control logic, and interrupt and DMA logic. The wide range of
functions integrated onto the W83627F/HF greatly reduces the number of components required for
interfacing with floppy disk drives. The W83627F/HF supports four 360K, 720K, 1.2M, 1.44M, or 2.88M
disk drives and data transfer rates of 250 Kb/s, 300 Kb/s, 500 Kb/s,1 Mb/s, and 2 Mb/s.
The W83627F/HF provides two high-speed serial communication ports (UARTs), one of which supports
serial Infrared communication. Each UART includes a 16-byte send/receive FIFO, a programmable
baud rate generator, complete modem control capability, and a processor interrupt system. Both
UARTs provide legacy speed with baud rate up to 115.2k bps and also advanced speed with baud rates
of 230k, 460k, or 921k bps which support higher speed modems. In addition, the W83627F/HF
provides IR functions: IrDA 1.0 (SIR for 1.152K bps) and TV remote IR (Consumer IR, supporting NEC,
RC-5, extended RC-5, and RECS-80 protocols).
The W83627F/HF supports one PC-compatible printer port (SPP), Bi-directional Printer port (BPP) and
also Enhanced Parallel Port (EPP) and Extended Capabilities Port (ECP). Through the printer port
interface pins, also available are: Extension FDD Mode and Extension 2FDD Mode allowing one or two
external floppy disk drives to be connected.
The configuration registers support mode selection, function enable/disable, and power down function
selection. Furthermore, the configurable PnP features are compatible with the plug-and-play feature
TM
demand of Windows 95/98 , which makes system resource allocation more efficient than ever.
The W83627F/HF provides functions that complies with ACPI (Advanced Configuration and Power
Interface), which includes support of legacy and ACPI power management through PME# or PSOUT#
function pins. For OnNow keyboard Wake-Up, OnNow mouse Wake-Up, and OnNow CIR Wake-Up.
The W83627F/HF also has auto power management to reduce the power consumption.
The keyboard controller is based on 8042 compatible instruction set with a 2K Byte programmable
ROM
TM
-2, Phoenix
and a 256-Byte
RAM
bank.
Keyboard
BIOS
firmware
are
available
with
optional
AMIKEY
TM
MultiKey/42 , or customer code.
The W83627F/HF provides a set of flexible I/O control functions to the system designer through a set of
General Purpose I/O ports. These GPIO ports may serve as simple I/O or may be individually configured
to provide a predefined alternate function. General Purpose Port 1 is designed to be functional even in
power down mode (VCC is off).
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Publication Release Date: Jul 1999
Revision 0.53
W83627HF/F
PRELIMINARY
The W83627F/HF is made to fully comply with Microsoft PC98 and PC99 Hardware Design Guide.
Moreover W83627F/HF is made to meet the specification of PC98/PC99's requirement in the power
management: ACPI and DPM (Device Power Management).
The W83627F/HF contains a game port and a MIDI port. The game port is designed to support 2
joysticks and can be applied to all standard PC game control devices, They are very important for a
entertainment or consumer computer.
Only the W83627HF support hardware status monitoring for personal computers. It can be used to
monitor several critical hardware parameters of the system, including power supply voltages, fan
speeds, and temperatures, which are very important for a high-end computer system to work stably and
properly.
FEATURES
General
£» Meet LPC Spec. 1.0
£» Support LDRQ#(LPC DMA), SERIRQ (serial IRQ)
£» Include all the features of Winbond I/O W83977TF and W83977EF
£» Integrate Hardware Monitor functions
£» Compliant with Microsoft PC98/PC99 Hardware Design Guide
£» Support DPM (Device Power Management), ACPI
£» Programmable configuration settings
£» Single 24 or 48 MHz clock input
FDC
£» Compatible with IBM PC AT disk drive systems
£» Variable write pre-compensation with track selectable capability
£» Support vertical recording format
£» DMA enable logic
£» 16-byte data FIFOs
£» Support floppy disk drives and tape drives
£» Detects all overrun and underrun conditions
£» Built-in address mark detection circuit to simplify the read electronics
£» FDD anti-virus functions with software write protect and FDD write enable signal (write data signal
was forced to be inactive)
£» Support up to four 3.5-inch or 5.25-inch floppy disk drives
£» Completely compatible with industry standard 82077
£» 360K/720K/1.2M/1.44M/2.88M format; 250K, 300K, 500K, 1M, 2M bps data transfer rate
£» Support 3-mode FDD, and its Win95/98 driver
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Revision 0.53
W83627HF/F
PRELIMINARY
UART
£» Two high-speed 16550 compatible UARTs with 16-byte send/receive FIFOs
£» MIDI compatible
£» Fully programmable serial-interface characteristics:
--- 5, 6, 7 or 8-bit characters
--- Even, odd or no parity bit generation/detection
--- 1, 1.5 or 2 stop bits generation
£» Internal diagnostic capabilities:
--- Loop-back controls for communications link fault isolation
--- Break, parity, overrun, framing error simulation
£» Programmable baud generator allows division of 1.8461 MHz and 24 MHz by 1 to (216-1)
£» Maximum baud rate up to 921k bps for 14.769 MHz and 1.5M bps for 24 MHz
Infrared
£» Support IrDA version 1.0 SIR protocol with maximum baud rate up to 115.2K bps
£» Support SHARP ASK-IR protocol with maximum baud rate up to 57,600 bps
£» Support Consumer IR
Parallel Port
£» Compatible with IBM parallel port
£» Support PS/2 compatible bi-directional parallel port
£» Support Enhanced Parallel Port (EPP) − Compatible with IEEE 1284 specification
£» Support Extended Capabilities Port (ECP) − Compatible with IEEE 1284 specification
£» Extension FDD mode supports disk drive B; and Extension 2FDD mode supports disk drives A and B
through parallel port
£» Enhanced printer port back-drive current protection
Keyboard Controller
TM
TM
£» 8042 based with optional F/W from AMIKKEY -2, Phoenix MultiKey/42
bytes of programmable ROM, and 256 bytes of RAM
£» Asynchronous Access to Two Data Registers and One status Register
£» Software compatibility with the 8042
£» Support PS/2 mouse
£» Support port 92
£» Support both interrupt and polling modes
£» Fast Gate A20 and Hardware Keyboard Reset
£» 8 Bit Timer/ Counter
£» Support binary and BCD arithmetic
£» 6 MHz, 8 MHz, 12 MHz, or 16 MHz operating frequency
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or customer code with 2K
Publication Release Date: Jul 1999
Revision 0.53
W83627HF/F
PRELIMINARY
Game Port
£» Support two separate Joysticks
£» Support every Joystick two axis (X,Y) and two button (A,B) controllers
MIDI Port
£» The baud rate is 31.25 Kbaud
£» 16-byte input FIFO
£» 16-byte output FIFO
General Purpose I/O Ports
£» 22 programmable general purpose I/O ports
£» General purpose I/O ports can serve as simple I/O ports, interrupt steering inputs, watch dog timer
output, power LED output, infrared I/O pins, KBC control I/O pins, suspend LED output, RSMRST#
signal, PWROK signal, Beep output
£» Functional in power down mode (GP1 only)
OnNow Functions
£» Keyboard Wake-Up by programmable keys
£» Mouse Wake-Up by programmable buttons
£» CIR Wake-Up by programmable keys
£» On Now Wake-Up from all of the ACPI sleeping states (S1-S5)
Hardware Monitor Functions ( Only for W83627HF)
£» 5 VID input pins for CPU Vcore identification
TM
£» 3 thermal inputs from optionally remote thermistors or 2N3904 transistors or Pentium
II
(Deschutes) thermal diode output
£» 7 positive voltage inputs (typical for +12V, -12V, +5V, -5V, +3.3V, VcoreA, VcoreB)
£» 2 intrinsic voltage monitoring (typical for Vbat, +5VSB)
£» 3 fan speed monitoring inputs
£» 2 fan speed control
£» Build in Case open detection circuit
£» WATCHDOG comparison of all monitored values
£» Programmable hysteresis and setting points for all monitored items
£» Over temperature indicate output
£» Automatic Power On voltage detection Beep
£» Issue SMI#, IRQ, OVT# to activate system protection
TM
TM
£» Intel LDCM / Acer ADM compatible
Package
£» 128-pin PQFP
-4-
Publication Release Date: Jul 1999
Revision 0.53
W83627HF/F
PRELIMINARY
PIN CONFIGURATION FOR 627F
A GG
A
GP P
V
N N N N N C NN N N 2 2
C C C C C C CC C D 1 2
P WI I
L DRR
E T RT
D OX X
/ / / /
G GGG
P PPP V
2 222 S
3 456 S
DS
R C OS
I D UI
BB T N
# # BB
D
T
R
B
#
S
U
S
C
RDC
L V
TST
KB
S RSV
BBBC N I A
###C C NT
SP R
LW S
P R P MC
_ C WR I
STRSR
XL OT R
##K# X P
S
/ / / / /
G G G G GP O M M
P P P P PS UD C
3 33 3 3I TAL
0 12 3 4N#TK
11 199 9 9 999 99 9 88 8 88888 8877 77 7777 7 766 66 6
00 098 7 6 543 21 0 98 7 65432 1098 76 5432 1 098 76 5
21 0
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
VCC
NC
NC
VSS
NC
MSI/GP20
MSO/IRQIN0
GPSA2/GP17
GPSB2/GP16
GPY1/GP15
GPY2/P16/GP14
GPX2/P15/GP13
GPX1/P14/GP12
GPSB1/P13/GP11
GPSA1/P12/GP10
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
64
63
62
61
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
W83627F
SUSLED/GP35
KDAT
KCLK
VSB
KBRST
A20GATE
KBLOCK#
RIA#
DCDA#
VSS
SOUTA
SINA
DTRA#
RTSA#
DSRA#
CTSA#
VCC
STB#
AFD#
ERR#
INIT#
SLIN#
PD0
PD1
PD2
PD3
1 1 1 1 1 1 1 1 112 2 22 2 22 2 2 2 3 33 3 3 33 33
1 23 4 5 67 8 9 0 1 2 3 4 5 6 7 890 1 23 4 56 7 8 9 0 12 3 4 56 78
D
R
V
D
E
N
0
D I M D D MD
R N OSS OI
V D A BA B R
DE# ## ##
E X
N#
1
/
S
M
I
#
/
G
P
2
7
S WW V
T DE C
E# # C
P
#
T WR H
RP D E
A# A A
K TD
0 A#
# #
D CP V P L S L L L L
S L MS C D E AA A A
K K E S I R R DD D D
C I # C QI 3 2 1 0
L #R
HN
K Q
G
#
-5-
VLLSP
CF RL E
CREC
3 AST
V ME
ET
##
B AP PP P
U C D DD D
S K7 6 5 4
Y#
Publication Release Date: Jul 1999
Revision 0.53
W83627HF/F
PRELIMINARY
PIN CONFIGURATION FOR 627HF
V
T
I
N
3
V
R
E
F
+
VV3 +
1
CC.
OO3 A 2
RRVV V
EEI CI
A B NC N
S S
CD
L A
1/ /
25 AGG
VV GP P
I I N2 2
NN D 1 2
P WI I
L DRR
E T RT
D OX X
/ / / /
DS
G G G G R C OS
P P P P V I D UI
2 2 2 2 S BBTN
3 4 5 6 S # # BB
C
A
S
E
D R DC O
T T ST P
R S RS V E
B B BBC N
# ###C #
S
U
S
C
L V
KB
I A
NT
SP R
LW S
P R P MC
_ C WR I
STRSR
X L OT R
##K# X
/ / / / /
G G G G GP
P P P P PS
3 33 3 3I
0 12 3 4N
P
S
OMM
UD C
TAL
#TK
11 199 9 9 999 99 9 8 8 8 888 88 8 877 777 777 7 766 66 6
00 098 7 6 543 21 0 9 8 7 654 32 1 098 765 432 1 098 76 5
21 0
VTIN2
VTIN1
OVT#
VID4
VID3
VID2
VID1
VID0
FANIO3
FANIO2
FANIO1
VCC
FANPWM2
FANPWM1
VSS
BEEP
MSI/GP20
MSO/IRQIN0
GPSA2/GP17
GPSB2/GP16
GPY1/GP15
GPY2/P16/GP14
GPX2/P15/GP13
GPX1/P14/GP12
GPSB1/P13/GP11
GPSA1/P12/GP10
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
64
63
62
61
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
W83627HF
SUSLED/GP35
KDAT
KCLK
VSB
KBRST
A20GATE
KBLOCK#
RIA#
DCDA#
VSS
SOUTA
SINA
DTRA#
RTSA#
DSRA#
CTSA#
VCC
STB#
AFD#
ERR#
INIT#
SLIN#
PD0
PD1
PD2
PD3
1 1 1 1 1 1 1 1 1122 22 2 22 2 2 2 3 33 3 3 33 33
1 2 34 5 67 8 90 1 2 3 4 5 6 7 8901 23 4 56 7 8 9 0 12 3 4 56 78
D
R
V
D
E
N
0
DI
RN
V D
DE
E X
N#
1
/
S
M
I
#
/
G
P
2
7
M D D M D S WW V
OS S OI T DE C
ABA BRE# # C
### ## P
#
T WR H
RP D E
A# A A
K TD
0 A#
# #
D CP V P L S L L L
S L M S C D E AA A
K K E S I R R DD D
C I # C QI 3 2 1
L #R
HN
K Q
G
#
-6-
L
A
D
0
V L L S P B A P PP P
C F R L E U C D DD D
C RE C S K 7 6 5 4
3 AS T Y #
V ME
ET
##
Publication Release Date: Jul 1999
Revision 0.53
W83627HF/F
PRELIMINARY
1. PIN DESCRIPTION
Note: Please refer to Section 13.2 DC CHARACTERISTICS for details.
I/O8t
- TTL level bi-directional pin with 8 mA source-sink capability
I/O12t
- TTL level bi-directional pin with 12 mA source-sink capability
I/O12tp3
- 3.3V TTL level bi-directional pin with 12 mA source-sink capability
I/OD12t
- TTL level bi-directional pin open drain output with 12 mA sink capability
I/O24t
- TTL level bi-directional pin with 24 mA source-sink capability
OUT12t
- TTL level output pin with 12 mA source-sink capability
OUT12tp3
- 3.3V TTL level output pin with 12 mA source-sink capability
OD12
- Open-drain output pin with 12 mA sink capability
OD24
- Open-drain output pin with 24 mA sink capability
INcs
- CMOS level Schmitt-trigger input pin
INt
- TTL level input pin
INtd
- TTL level input pin with internal pull down resistor
INts
- TTL level Schmitt-trigger input pin
INtsp3
- 3.3V TTL level Schmitt-trigger input pin
1.1
LPC Interface
SYMBOL
PIN
I/O
FUNCTION
CLKIN
18
INt
PME#
PCICLK
19
OD12
Generated PME event.
21
INtsp3
PCI clock input.
LDRQ#
22
O12tp3
Encoded DMA Request signal.
SERIRQ
23
I/OD12t
Serial IRQ input/Output.
LAD[3:0]
24-27
I/O12tp3
These signal lines communicate address, control, and data
information over the LPC bus between a host and a peripheral.
LFRAME#
29
INtsp3
Indicates start of a new cycle or termination of a broken cycle.
LRESET#
SUSCLKIN
30
INtsp3
Reset signal. It can connect to PCIRST# signal on the host.
75
INts
System clock input. According to the input frequency 24MHz or
48MHz, it is selectable through register. Default is 24MHz input.
32khz clock input , for CIR only.
-7-
Publication Release Date: Jul 1999
Revision 0.53
W83627HF/F
PRELIMINARY
1.2 FDC Interface
SYMBOL
PIN
I/O
DRVDEN0
1
OD24
Drive Density Select bit 0.
DRVDEN1
2
OD12
Drive Density Select bit 1. (Default)
SMI#
Int
(IRQIN1)
FUNCTION
System Management Interrupt
(Interrupt channel input. For C version only)
GP27
I/OD12
General purpose I/O port 3 bit 6.
INDEX#
3
INcs
This Schmitt-triggered input from the disk drive is active low when
the head is positioned over the beginning of a track marked by an
index hole. This input pin is pulled up internally by a 1 KΩ resistor.
The resistor can be disabled by bit 7 of L0-CRF0 (FIPURDWN).
MOA#
4
OD24
Motor A On. When set to 0, this pin enables disk drive 0. This is
an open drain output.
DSB#
5
OD24
Drive Select B. When set to 0, this pin enables disk drive B. This
is an open drain output.
DSA#
6
OD24
Drive Select A. When set to 0, this pin enables disk drive A. This
is an open drain output.
MOB#
7
OD24
Motor B On. When set to 0, this pin enables disk drive 1. This is
an open drain output.
DIR#
8
OD24
Direction of the head step motor. An open drain output.
Logic 1 = outward motion
Logic 0 = inward motion
STEP#
9
OD24
Step output pulses. This active low open drain output produces a
pulse to move the head to another track.
WD#
10
OD24
Write data. This logic low open drain writes pre-compensation
serial data to the selected FDD. An open drain output.
WE#
11
OD24
Write enable. An open drain output.
TRAK0#
13
INcs
Track 0. This Schmitt-triggered input from the disk drive is active
low when the head is positioned over the outermost track. This
input pin is pulled up internally by a 1 KΩ resistor. The resistor
can be disabled by bit 7 of L0-CRF0 (FIPURDWN).
WP#
14
INcs
Write protected. This active low Schmitt input from the disk drive
indicates that the diskette is write-protected. This input pin is
pulled up internally by a 1 KΩ resistor. The resistor can be
disabled by bit 7 of L0-CRF0 (FIPURDWN).
RDATA#
15
INcs
The read data input signal from the FDD. This input pin is pulled
up internally by a 1 KΩ resistor. The resistor can be disabled by
bit 7 of L0-CRF0 (FIPURDWN).
-8-
Publication Release Date: Jul 1999
Revision 0.53
W83627HF/F
PRELIMINARY
1.2 FDC Interface, continued
SYMBOL
HEAD#
PIN
16
I/O
OD24
DSKCHG#
17
INcs
1.3
FUNCTION
Head select. This open drain output determines which disk drive
head is active.
Logic 1 = side 0
Logic 0 = side 1
Diskette change. This signal is active low at power on and
whenever the diskette is removed. This input pin is pulled up
internally by a 1 KΩ resistor. The resistor can be disabled by bit 7
of L0-CRF0 (FIPURDWN).
Multi-Mode Parallel Port
The following pins have alternate functions, which are controlled by CR28 and L3-CRF0.
SYMBOL
SLCT
PIN
31
I/O
INt
OD12
OD12
PE
32
INt
OD12
OD12
FUNCTION
PRINTER MODE:
An active high input on this pin indicates that the printer is selected.
Refer to the description of the parallel port for definition of this pin
in ECP and EPP mode.
EXTENSION FDD MODE: WE2#
This pin is for Extension FDD B; its function is the same as the
WE# pin of FDC.
EXTENSION 2FDD MODE: WE2#
This pin is for Extension FDD A and B; its function is the same as
the WE# pin of FDC.
PRINTER MODE:
An active high input on this pin indicates that the printer has
detected the end of the paper. Refer to the description of the
parallel port for the definition of this pin in ECP and EPP mode.
EXTENSION FDD MODE: WD2#
This pin is for Extension FDD B; its function is the same as the
WD# pin of FDC.
EXTENSION 2FDD MODE: WD2#
This pin is for Extension FDD A and B; its function is the same as
the WD# pin of FDC.
-9-
Publication Release Date: Jul 1999
Revision 0.53
W83627HF/F
PRELIMINARY
1.3 Multi-Mode Parallel Port, continued
SYMBOL
BUSY
PIN
33
I/O
INt
OD12
OD12
ACK#
34
INt
OD12
OD12
ERR#
45
INt
OD12
OD12
FUNCTION
PRINTER MODE:
An active high input indicates that the printer is not ready to receive
data. Refer to the description of the parallel port for definition of
this pin in ECP and EPP mode.
EXTENSION FDD MODE: MOB2#
This pin is for Extension FDD B; its function is the same as the
MOB# pin of FDC.
EXTENSION 2FDD MODE: MOB2#
This pin is for Extension FDD A and B; its function is the same as
the MOB# pin of FDC.
PRINTER MODE: ACK#
An active low input on this pin indicates that the printer has
received data and is ready to accept more data. Refer to the
description of the parallel port for the definition of this pin in ECP
and EPP mode.
EXTENSION FDD MODE: DSB2#
This pin is for the Extension FDD B; its functions is the same as the
DSB# pin of FDC.
EXTENSION 2FDD MODE: DSB2#
This pin is for Extension FDD A and B; its function is the same as
the DSB# pin of FDC.
PRINTER MODE: ERR#
An active low input on this pin indicates that the printer has
encountered an error condition. Refer to the description of the
parallel port for the definition of this pin in ECP and EPP mode.
EXTENSION FDD MODE: HEAD2#
This pin is for Extension FDD B; its function is the same as the
HEAD#pin of FDC.
EXTENSION 2FDD MODE: HEAD2#
This pin is for Extension FDD A and B; its function is the same as
the HEAD# pin of FDC.
- 10 -
Publication Release Date: Jul 1999
Revision 0.53
W83627HF/F
PRELIMINARY
1.3 Multi-Mode Parallel Port, continued
SYMBOL
SLIN#
PIN
43
I/O
OD12
OD12
OD12
INIT#
44
OD12
OD12
OD12
AFD#
46
OD12
OD12
OD12
FUNCTION
PRINTER MODE: SLIN#
Output line for detection of printer selection. Refer to the
description of the parallel port for the definition of this pin in ECP
and EPP mode.
EXTENSION FDD MODE: STEP2#
This pin is for Extension FDD B; its function is the same as the
STEP# pin of FDC.
EXTENSION 2FDD MODE: STEP2#
This pin is for Extension FDD A and B; its function is the same as
the STEP# pin of FDC.
PRINTER MODE: INIT#
Output line for the printer initialization. Refer to the description of
the parallel port for the definition of this pin in ECP and EPP mode.
EXTENSION FDD MODE: DIR2#
This pin is for Extension FDD B; its function is the same as the
DIR# pin of FDC.
EXTENSION 2FDD MODE: DIR2#
This pin is for Extension FDD A and B; its function is the same as
the DIR# pin of FDC.
PRINTER MODE: AFD#
An active low output from this pin causes the printer to auto feed a
line after a line is printed. Refer to the description of the parallel
port for the definition of this pin in ECP and EPP mode.
EXTENSION FDD MODE: DRVDEN0
This pin is for Extension FDD B; its function is the same as the
DRVDEN0 pin of FDC.
EXTENSION 2FDD MODE: DRVDEN0
This pin is for Extension FDD A and B; its function is the same as
the DRVDEN0 pin of FDC.
- 11 -
Publication Release Date: Jul 1999
Revision 0.53
W83627HF/F
PRELIMINARY
1.3 Multi-Mode Parallel Port, continued
SYMBOL
STB#
PD0
PIN
47
I/O
OD12
42
I/O12t
INt
INt
PD1
41
I/O12t
INt
INt
PD2
40
I/O12t
INt
INt
FUNCTION
PRINTER MODE: STB#
An active low output is used to latch the parallel data into the
printer. Refer to the description of the parallel port for the definition
of this pin in ECP and EPP mode.
EXTENSION FDD MODE: This pin is a tri-state output.
EXTENSION 2FDD MODE: This pin is a tri-state output.
PRINTER MODE: PD0
Parallel port data bus bit 0. Refer to the description of the parallel
port for the definition of this pin in ECP and EPP mode.
EXTENSION FDD MODE: INDEX2#
This pin is for Extension FDD B; its function is the same as the
INDEX# pin of FDC. It is pulled high internally.
EXTENSION 2FDD MODE: INDEX2#
This pin is for Extension FDD A and B; its function is the same as
the INDEX# pin of FDC. It is pulled high internally.
PRINTER MODE: PD1
Parallel port data bus bit 1. Refer to the description of the parallel
port for the definition of this pin in ECP and EPP mode.
EXTENSION FDD MODE: TRAK02#
This pin is for Extension FDD B; its function is the same as the
TRAK0# pin of FDC. It is pulled high internally.
EXTENSION. 2FDD MODE: TRAK02#
This pin is for Extension FDD A and B; its function is the same as
the TRAK0# pin of FDC. It is pulled high internally.
PRINTER MODE: PD2
Parallel port data bus bit 2. Refer to the description of the parallel
port for the definition of this pin in ECP and EPP mode.
EXTENSION FDD MODE: WP2#
This pin is for Extension FDD B; its function is the same as the
WP# pin of FDC. It is pulled high internally.
EXTENSION. 2FDD MODE: WP2#
This pin is for Extension FDD A and B; its function is the same as
the WP# pin of FDC. It is pulled high internally.
- 12 -
Publication Release Date: Jul 1999
Revision 0.53
W83627HF/F
PRELIMINARY
1.3 Multi-Mode Parallel Port, continued
SYMBOL
PD3
PIN
39
I/O
I/O12t
INt
INt
PD4
38
I/O12t
INt
INt
PD5
37
I/O12t
PD6
36
I/OD12t
OD12
PD7
35
I/OD12t
OD12
FUNCTION
PRINTER MODE: PD3
Parallel port data bus bit 3. Refer to the description of the parallel
port for the definition of this pin in ECP and EPP mode.
EXTENSION FDD MODE: RDATA2#
This pin is for Extension FDD B; its function is the same as the
RDATA# pin of FDC. It is pulled high internally.
EXTENSION 2FDD MODE: RDATA2#
This pin is for Extension FDD A and B; its function is the same as
the RDATA# pin of FDC. It is pulled high internally.
PRINTER MODE: PD4
Parallel port data bus bit 4. Refer to the description of the parallel
port for the definition of this pin in ECP and EPP mode.
EXTENSION FDD MODE: DSKCHG2#
This pin is for Extension FDD B; the function of this pin is the same
as the DSKCHG# pin of FDC. It is pulled high internally.
EXTENSION 2FDD MODE: DSKCHG2#
This pin is for Extension FDD A and B; this function of this pin is the
same as the DSKCHG# pin of FDC. It is pulled high internally.
PRINTER MODE: PD5
Parallel port data bus bit 5. Refer to the description of the parallel
port for the definition of this pin in ECP and EPP mode.
EXTENSION FDD MODE: This pin is a tri-state output.
EXTENSION 2FDD MODE: This pin is a tri-state output.
PRINTER MODE: PD6
Parallel port data bus bit 6. Refer to the description of the parallel
port for the definition of this pin in ECP and EPP mode.
EXTENSION FDD MODE: This pin is a tri-state output.
EXTENSION. 2FDD MODE: MOA2#
This pin is for Extension FDD A; its function is the same as the
MOA# pin of FDC.
PRINTER MODE: PD7
Parallel port data bus bit 7. Refer to the description of the parallel
port for the definition of this pin in ECP and EPP mode.
EXTENSION FDD MODE: This pin is a tri-state output.
EXTENSION 2FDD MODE: DSA2#
This pin is for Extension FDD A; its function is the same as the
DSA# pin of FDC.
- 13 -
Publication Release Date: Jul 1999
Revision 0.53
W83627HF/F
PRELIMINARY
1.4
Serial Port Interface
SYMBOL
CTSA#
CTSB#
PIN
49
78
I/O
INt
DSRA#
DSRB#
50
79
INt
51
I/O8t
RTSA#
HEFRAS
RTSB#
DTRA#
80
I/O8t
52
I/O8t
81
I/O8t
53
82
54
INt
PNPCSV#
DTRB#
SINA
SINB
SOUTA
I/O8t
PENKBC
SOUTB
PEN48
83
I/O8t
DCDA#
DCDB#
RIA#
RIB#
56
84
57
85
INt
INt
FUNCTION
Clear To Send. It is the modem control input.
The function of these pins can be tested by reading bit 4 of the
handshake status register.
Data Set Ready. An active low signal indicates the modem or data
set is ready to establish a communication link and transfer data to
the UART.
UART A Request To Send. An active low signal informs the
modem or data set that the controller is ready to send data.
During power-on reset, this pin is pulled down internally and is
defined as HEFRAS, which provides the power-on value for CR26
bit 6 (HEFRAS). A 4.7 kΩ is recommended if intends to pull up.
(select 4EH as configuration I/O port′s address)
UART B Request To Send. An active low signal informs the
modem or data set that the controller is ready to send data.
UART A Data Terminal Ready. An active low signal informs the
modem or data set that the controller is ready to communicate.
During power-on reset, this pin is pulled down internally and is
defined as PNPCSV#, which provides the power-on value for CR24
bit 0 (PNPCSV#). A 4.7 kΩ is recommended if intends to pull up.
(clear the default value of FDC, UARTs, PRT, Game port and MIDI
port)
UART B Data Terminal Ready. An active low signal informs the
modem or data set that controller is ready to communicate.
Serial Input. It is used to receive serial data through the
communication link.
UART A Serial Output. It is used to transmit serial data out to the
communication link.
During power-on reset, this pin is pulled down internally and is
defined as PENKBC, which provides the power-on value for CR24
bit 2 (ENKBC). A 4.7 kΩ resistor is recommended if intends to pull
up. (enable KBC)
UART B Serial Output. During power-on reset, this pin is pulled
down internally and is defined as PEN48, which provides the
power-on value for CR24 bit 6 (EN48). A 4.7 kΩ resistor is
recommended if intends to pull up.
Data Carrier Detect. An active low signal indicates the modem or
data set has detected a data carrier.
Ring Indicator. An active low signal indicates that a ring signal is
being received from the modem or data set.
- 14 -
Publication Release Date: Jul 1999
Revision 0.53
W83627HF/F
PRELIMINARY
1.5
KBC Interface
SYMBOL
KBLOCK#
PIN
58
I/O
INt
A20GATE
KBRST
KDATA
MDATA
KCLK
MCLK
59
60
63
66
62
65
O12
O12
I/OD16
I/OD16
I/OD16
I/OD16
1.6
ACPI Interface
SYMBOL
VBAT
PSOUT#
PIN
74
67
I/O
PWR
OD12
PSIN
68
IN t d
1.7
FUNCTION
Keyboard inhibit control input. This pin is after system reset.
Internal pull high. (KBC P17)
Gate A20 output. This pin is high after system reset. (KBC P21)
Keyboard reset. This pin is high after system reset. (KBC P20)
Keyboard Data.
PS2 Mouse Data.
Keyboard Clock.
PS2 Mouse Clock.
FUNCTION
Battery voltage input.
Panel Switch Output. This signal is used for Wake-Up system from
S5c o l d state. This pin is pulse output, active low.
Panel Switch Input. This pin is high active with an internal pull
down resistor.
Hardware Monitor Interface
(For W83627HF only, all these pins in W83627F are NC.)
SYMBOL
PIN
I/O
FUNCTION
CASEOPEN#
76
INt
CASE OPEN. An active low input from an external device when
case is opened. This signal can be latched if pin VBAT is connect
to battery, even W83627HF is power off.
-5VIN
94
AIN
0V to 4.096V FSR Analog Inputs.
-12VIN
95
AIN
0V to 4.096V FSR Analog Inputs.
+12VIN
96
AIN
0V to 4.096V FSR Analog Inputs.
+3.3VIN
98
AIN
0V to 4.096V FSR Analog Inputs.
VCOREB
99
AIN
0V to 4.096V FSR Analog Inputs.
VCOREA
100
AIN
0V to 4.096V FSR Analog Inputs.
VREF
101
AOUT
VTIN3
102
AIN
Reference Voltage for temperature measuration.
Temperature sensor 3 input. It is used for CPU2 temperature
measuration.
- 15 -
Publication Release Date: Jul 1999
Revision 0.53
W83627HF/F
PRELIMINARY
1.7 Hardware Monitor Interface, continued
SYMBOL
PIN
I/O
FUNCTION
VTIN2
103
AIN
Temperature sensor 2 input. It is used for CPU1 temperature
measuration.
VTIN1
104
AIN
Temperature sensor 1 input. It is used for system temperature
measuration.
OVT#
105
OD12
Over temperature Shutdown Output. It indicated the VTIN2 or
VTIN3 is over temperature limit.
VID[4:0]
106110
INt
Voltage Supply readouts from Pentium II .
FANIO[3:1]
111113
I/O12ts
0V to +5V amplitude fan tachometer input.
Alternate Function: Fan on-off control output.
These multifunctional pins can be programmable input or output.
FANPWM1
116
FANPWM2
115
BEEP
118
1.8
O12
OD12
Fan speed control. Use the Pulse Width Modulatuion (PWM)
technic knowledge to control the Fan's RPM.
Beep function for hardware monitor. This pin is low after system
reset.
Game Port & MIDI Port
SYMBOL
GPSA1
PIN
I/O
128
INcs
FUNCTION
Active-low, Joystick I switch input 1. (Default)
GP10
I/OD12
General purpose I/O port 1 bit 0.
P12
I/OD12
Alternate Function Output:KBC P12 I/O port.
INcs
Active-low, Joystick II switch input 1. (Default)
GPSB1
127
GP11
I/OD12
General purpose I/O port 1 bit 1.
P13
I/OD12
Alternate Function Output:KBC P13 I/O port.
I/OD12
Joystick I timer pin. this pin connect to X positioning variable
resistors for the Josystick. (Default)
GP12
I/OD12
General purpose I/O port 1 bit 2.
P14
I/OD12
Alternate Function Output:KBC P14 I/O port.
GPX1
126
- 16 -
Publication Release Date: Jul 1999
Revision 0.53
W83627HF/F
PRELIMINARY
1.8
Game Port & MIDI Port, continued
SYMBOL
GPX2
PIN
I/O
125
I/OD12
FUNCTION
Joystick II timer pin. this pin connect to X positioning variable
resistors for the Josystick. (Default)
GP13
I/OD12
General purpose I/O port 1 bit 3.
P15
I/OD12
Alternate Function Output:KBC P15 I/O port.
I/OD12
Joystick II timer pin. this pin connect to Y positioning variable
resistors for the Josystick. (Default)
GP14
I/OD12
General purpose I/O port 1 bit 4.
P16
I/OD12
Alternate Function Output:KBC P16 I/O port.
I/OD12
Joystick I timer pin. this pin connect to Y positioning variable
resistors for the Josystick. (Default)
I/OD12
General purpose I/O port 1 bit 5.
GPY2
GPY1
124
123
GP15
GPSB2
122
GP16
GPSA2
INcs
I/OD12
121
INcs
Active-low, Joystick II switch input 2. This pin has an internal pullup resistor. (Default)
General purpose I/O port 1 bit 6.
Active-low, Joystick I switch input 2. This pin has an internal pullup resistor. (Default)
GP17
MSI
119
GP20
MSO
IRQIN0
120
I/OD12
General purpose I/O port 1 bit 7.
INt
MIDI serial data input .(Default)
I/OD12t
General purpose I/O port 2 bit 0.
OUT12t
INt
MIDI serial data output. (Default)
Alternate Function input: Interrupt channel input.
- 17 -
Publication Release Date: Jul 1999
Revision 0.53
W83627HF/F
PRELIMINARY
1.9
General Purpose I/O Port
1.9.1 General Purpose I/O Port 1 (Power source is Vcc)
see 1.8 Game Port
1.9.2 General Purpose I/O Port 2 (Power source is Vcc)
SYMBOL
GP20
PIN
I/O
119
I/OD12t
MSI
INt
FUNCTION
General purpose I/O port 2 bit 0.
MIDI serial data input. Schmitt trigger input with internal pull-up
register. (Default)
GP21
92
I/OD12t
General purpose I/O port 2 bit 1.
(Alternate Function: Serial Bus Clock. For W83627HF Only)
91
INts
I/OD12t
I/OD12ts
I/OD24t
(Alternate Function: Serial Bus bi-directional Data.
For W83627HF Only)
General purpose I/O port 2 bit 3.
OD24t
Power LED output, this signal is low after system reset. (Default)
I/OD12t
General purpose I/O port 2 bit 4.
OD12t
Watch dog timer output. (Default)
88
I/OD12t
General purpose I/O port 2 bit 5.
Alternate Function Input: Infrared Receiver input. (Default)
87
INts
I/OD12t
General purpose I/O port 2 bit 6.
OUT12t
Alternate Function Output: Infrared Transmitter Output. (Default)
I/OD24t
General purpose I/O port 2 bit 7.
OD24t
Drive Density Select bit 0. (Default)
(SCL)
GP22
(SDA)
GP23
90
PLED
GP24
89
WDTO
GP25
IRRX
GP26
IRTX
GP27
DRVDEN1
IRQIN1
2
INt
General purpose I/O port 2 bit 2.
Alternate Function Input: Interrupt channel input.
- 18 -
Publication Release Date: Jul 1999
Revision 0.53
W83627HF/F
PRELIMINARY
1.9.3
General Purpose I/O Port 3 (Power souce is VSB)
SYMBOL
GP30
SLP_SX#
GP31
PWRCTL#
PIN
73
GP32
PWROK
71
I/OD12t
OD12t
GP33
RSMRST#
70
I/OD12t
OD12t
GP34
CIRRX#
69
I/OD12t
OD12t
GP35
SUSLED
64
I/OD24t
OD24t
1.10
72
I/O
I/OD12t
INt
I/OD12t
OD12t
FUNCTION
General purpose I/O port 3 bit 0.
Chpset suspend C status input.
General purpose I/O port 3 bit 1.
This pin generates the PWRCTL# signal while the power failure.
(Default)
General purpose I/O port 3 bit 2.
This pin generates the PWROK signal while the VCC come in.
(Default)
General purpose I/O port 3 bit 3.
This pin generates the RSMRST signal while the VSB come in.
(Default)
General purpose I/O port 3 bit 4.
Consumer IR receiving input. This pin can Wake-Up system from
S5cold. (Default)
General purpose I/O port 3 bit 5.
Suspend LED output, it can program to flash when suspend state.
This function can work without VCC. (Default)
POWER PINS
SYMBOL
VCC
VSB
VCC3V
AVCC
AGND
PIN
12, 48, 77, 114
61
28
97
93
VSS
20, 55, 86, 117
FUNCTION
+5V power supply for the digital circuitry.
+5V stand-by power supply for the digital circuitry.
+3.3V power supply for driving 3V on host interface.
Analog VCC input. Internally supplier to all analog circuitry.
Internally connected to all analog circuitry. The ground reference
for all analog inputs..
Ground.
- 19 -
Publication Release Date: Jul 1999
Revision 0.53
W83627HF/F
PRELIMINARY
2. LPC (LOW PIN COUNT) INTERFACE
LPC interface is to replace ISA interface serving as a bus interface between host (chip-set) and
peripheral (Winbond I/O). Data transfer on the LPC bus are serialized over a 4 bit bus. The general
characteristics of the interface implemented in Winbond LPC I/O are:
• One control line, namely LFRAME#, which is used by the host to start or stop transfers.
peripherals drive this signal.
No
• The LAD[3:0] bus, which communicates information serially. The information conveyed are cycle
type, cycle direction, chip selection, address, data, and wait states.
• MR (master reset) of Winbond ISA I/O is replaced with a active low reset signal, namely LRESET#, in
Winbond LPC I/O.
• An additional 33 MHz PCI clock is needed in Winbond LPC I/O for synchronization.
• DMA requests are issued through LDRQ#.
• Interrupt requests are issued through SERIRQ.
• Power management events are issued through PME#.
Comparing to its ISA counterpart, LPC implementation saves up to 40 pin counts (see table below) free
for integrating more devices on a single chip.
Winbond I/O
Interface pins
count
W83977TF
D[7:0], SA[15:0], DRQ[3:0], DACK#[3:0], TC, IOR#, IOW#, IOCHRDY, IRQs
49
W83627HF
LAD[3:0], LFRAME#, PCICLK, LDRQ#, SERIRQ, PME#
9
save
40
The transition from ISA to LPC is transparent in terms of software which means no BIOS or device driver
update is needed except chip-specific configuration.
- 20 -
Publication Release Date: Jul 1999
Revision 0.53
W83627HF/F
PRELIMINARY
3. FDC FUNCTIONAL DESCRIPTION
3.1
W83627HF FDC
The floppy disk controller of the W83627HF integrates all of the logic required for floppy disk control.
The FDC implements a PC/AT or PS/2 solution. All programmable options default to compatible
values. The FIFO provides better system performance in multi-master systems. The digital data
separator supports up to 2 M bits/sec data rate.
The FDC includes the following blocks: AT interface, Precompensation, Data Rate Selection, Digital
Data Separator, FIFO, and FDC Core.
3.1.1 AT interface
The interface consists of the standard asynchronous signals: RD#, WR#, A0-A3, IRQ, DMA control, and
a data bus. The address lines select between the configuration registers, the FIFO and control/status
registers. This interface can be switched between PC/AT, Model 30, or PS/2 normal modes. The PS/2
register sets are a superset of the registers found in a PC/AT.
3.1.2 FIFO (Data)
The FIFO is 16 bytes in size and has programmable threshold values. All command parameter
information and disk data transfers go through the FIFO. Data transfers are governed by the RQM and
DIO bits in the Main Status Register.
The FIFO defaults to disabled mode after any form of reset. This maintains PC/AT hardware
compatibility. The default values can be changed through the CONFIGURE command. The advantage
of the FIFO is that it allows the system a larger DMA latency without causing disk errors. The following
tables give several examples of the delays with a FIFO. The data are based upon the following formula:
THRESHOLD # × (1/DATA/RATE) *8 - 1.5 µS = DELAY
FIFO THRESHOLD
1 Byte
2 Byte
8 Byte
15 Byte
FIFO THRESHOLD
1 Byte
2 Byte
8 Byte
15 Byte
MAXIMUM DELAY TO SERVICING AT 500K BPS
Data Rate
×
µS
µS
1 16
- 1.5
= 14.5 µS
2 × 16 µS - 1.5 µS = 30.5 µS
8 × 16 µS - 1.5 µS = 6.5 µS
15 × 16 µS - 1.5 µS = 238.5 µS
MAXIMUM DELAY TO SERVICING AT 1M BPS
Data Rate
1 × 8 µS - 1.5 µS = 6.5 µS
2 × 8 µS - 1.5 µS = 14.5 µS
8 × 8 µS - 1.5 µS = 62.5 µS
15 × 8 µS - 1.5 µS = 118.5 µS
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Publication Release Date: Jul 1999
Revision 0.53
W83627HF/F
PRELIMINARY
At the start of a command the FIFO is always disabled and command parameters must be sent based
upon the RQM and DIO bit settings in the main status register. When the FDC enters the command
execution phase, it clears the FIFO of any data to ensure that invalid data are not transferred.
An overrun and underrun will terminate the current command and the data transfer. Disk writes will
complete the current sector by generating a 00 pattern and valid CRC. Reads require the host to
remove the remaining data so that the result phase may be entered.
DMA transfers are enabled with the SPECIFY command and are initiated by the FDC by activating the
DRQ pin during a data transfer command. The FIFO is enabled directly by asserting DACK# and
addresses need not be valid.
Note that if the DMA controller is programmed to function in verify mode a pseudo read is performed by
the FDC based only on DACK#. This mode is only available when the FDC has been configured into
byte mode (FIFO disabled) and is programmed to do a read. With the FIFO enabled the above
operation is performed by using the new VERIFY command. No DMA operation is needed.¡@
3.1.3
Data Separator
The function of the data separator is to lock onto the incoming serial read data. When a lock is achieved
the serial front end logic of the chip is provided with a clock which is synchronized to the read data. The
synchronized clock, called the Data Window, is used to internally sample the serial data portion of the
bit cell, and the alternate state samples the clock portion. Serial to parallel conversion logic separates
the read data into clock and data bytes.
The Digital Data Separator (DDS) has three parts: control logic, error adjustment, and speed tracking.
The DDS circuit cycles once every 12 clock cycles ideally. Any data pulse input will be synchronized and
then adjusted by immediate error adjustment. The control logic will generate RDD and RWD for every
pulse input. During any cycle where no data pulse is present, the DDS cycles are based on speed. A
digital integrator is used to keep track of the speed changes in the input data stream.
3.1.4
Write Precompensation
The write precompensation logic is used to minimize bit shifts in the RDDATA stream from the disk
drive. Shifting of bits is a known phenomenon in magnetic media and is dependent on the disk media
and the floppy drive.
The FDC monitors the bit stream that is being sent to the drive. The data patterns that require
precompensation are well known. Depending upon the pattern, the bit is shifted either early or late
relative to the surrounding bits.
3.1.5
Perpendicular Recording Mode
The FDC is also capable of interfacing directly to perpendicular recording floppy drives. Perpendicular
recording differs from the traditional longitudinal method in that the magnetic bits are oriented vertically.
This scheme packs more data bits into the same area.
FDCs with perpendicular recording drives can read standard 3.5" floppy disks and can read and write
perpendicular media. Some manufacturers offer drives that can read and write standard and
perpendicular media in a perpendicular media drive.
- 22 -
Publication Release Date: Jul 1999
Revision 0.53
W83627HF/F
PRELIMINARY
A single command puts the FDC into perpendicular mode. All other commands operate as they
normally do. The perpendicular mode requires a 1 Mbps data rate for the FDC. At this data rate the
FIFO eases the host interface bottleneck due to the speed of data transfer to or from the disk.
3.1.6
FDC Core
The W83627HF FDC is capable of performing twenty commands. Each command is initiated by a multibyte transfer from the microprocessor. The result can also be a multi-byte transfer back to the
microprocessor. Each command consists of three phases: command, execution, and result.
Command
The microprocessor issues all required information to the controller to perform a specific operation.
Execution
The controller performs the specified operation.
Result
After the operation is completed, status information and other housekeeping information is provided to
the microprocessor.
3.1.7
FDC Commands
Command Symbol Descriptions:
C:
Cylinder number 0 - 256
D:
Data Pattern
DIR:
Step Direction
DIR = 0, step out
DIR = 1, step in
DS0:
Disk Drive Select 0
DS1:
Disk Drive Select 1
DTL:
Data Length
EC:
Enable Count
EOT:
End of Track
EFIFO:
Enable FIFO
EIS:
Enable Implied Seek
EOT:
End of track
FIFOTHR:
FIFO Threshold
GAP:
Gap length selection
GPL:
Gap Length
H:
Head number
HDS:
Head number select
HLT:
Head Load Time
HUT:
Head Unload Time
- 23 -
Publication Release Date: Jul 1999
Revision 0.53
W83627HF/F
PRELIMINARY
LOCK:
MFM:
MT:
N:
NCN:
ND:
OW:
PCN:
POLL:
PRETRK:
R:
RCN:
R/W:
SC:
SK:
SRT:
ST0:
ST1:
ST2:
ST3:
WG:
Lock EFIFO, FIFOTHR, PTRTRK bits prevent affected by software reset
MFM or FM Mode
Multitrack
The number of data bytes written in a sector
New Cylinder Number
Non-DMA Mode
Overwritten
Present Cylinder Number
Polling Disable
Precompensation Start Track Number
Record
Relative Cylinder Number
Read/Write
Sector/per cylinder
Skip deleted data address mark
Step Rate Time
Status Register 0
Status Register 1
Status Register 2
Status Register 3
Write gate alters timing of WE
- 24 -
Publication Release Date: Jul 1999
Revision 0.53
W83627HF/F
PRELIMINARY
(1) Read Data
PHASE
R/W
D7
D6
Command
W
MT MFM
W
0
0
D5
D4
D3
SK
0
0
0
0
0
D2
1
D1
1
0
REMARKS
Command codes
HDS DS1 DS0
W
---------------------- C ------------------------
W
---------------------- H ------------------------
W
---------------------- R ------------------------
W
---------------------- N ------------------------
W
-------------------- EOT -----------------------
W
-------------------- GPL -----------------------
W
-------------------- DTL -----------------------
Execution
Result
D0
Sector ID information prior
to command execution
Data transfer between the
FDD and system
R
R
-------------------- ST0 -----------------------
R
-------------------- ST2 -----------------------
R
---------------------- C ------------------------
R
---------------------- H ------------------------
R
---------------------- R ------------------------
R
---------------------- N ------------------------
-------------------- ST1 -----------------------
- 25 -
Status information after
command execution
Sector ID information after
command execution
Publication Release Date: Jul 1999
Revision 0.53
W83627HF/F
PRELIMINARY
(2) Read Deleted Data
PHASE
R/W
D7
D6
Command
W
MT MFM
W
0
0
D5
D4
D3
SK
0
1
0
0
0
D2
1
D1
0
D0
0
Command codes
HDS DS1 DS0
W
---------------------- C ------------------------
W
---------------------- H ------------------------
W
---------------------- R ------------------------
W
---------------------- N ------------------------
W
-------------------- EOT -----------------------
W
-------------------- GPL -----------------------
W
-------------------- DTL -----------------------
Execution
Result
REMARKS
Sector ID information prior
to command execution
Data transfer between the
FDD and system
R
-------------------- ST0 -----------------------
R
-------------------- ST1 -----------------------
R
-------------------- ST2 -----------------------
R
---------------------- C ------------------------
R
---------------------- H ------------------------
R
---------------------- R ------------------------
R
---------------------- N ------------------------
- 26 -
Status information after
command execution
Sector ID information after
command execution
Publication Release Date: Jul 1999
Revision 0.53
W83627HF/F
PRELIMINARY
(3) Read A Track
PHASE
R/W
D7
Command
W
0
W
0
D6
MFM
0
D5
D4
D3
0
0
0
0
0
0
D2
0
D1
1
D0
0
Command codes
HDS DS1 DS0
W
---------------------- C ------------------------
W
---------------------- H ------------------------
W
---------------------- R ------------------------
W
---------------------- N ------------------------
W
-------------------- EOT -----------------------
W
-------------------- GPL -----------------------
W
-------------------- DTL -----------------------
Execution
Result
REMARKS
Sector ID information prior to
command execution
Data transfer between the
FDD and system; FDD reads
contents of all cylinders from
index hole to EOT
R
-------------------- ST0 -----------------------
R
-------------------- ST1 -----------------------
R
-------------------- ST2 -----------------------
R
---------------------- C ------------------------
R
---------------------- H ------------------------
R
---------------------- R ------------------------
R
---------------------- N ------------------------
- 27 -
Status information after
command execution
Sector ID information after
command execution
Publication Release Date: Jul 1999
Revision 0.53
W83627HF/F
PRELIMINARY
(4) Read ID
PHASE
R/W
D7
Command
W
0
W
0
D6
D5
D4
D3
MFM
0
0
1
0
0
0
0
D2
0
D1
1
D0
0
Command codes
HDS DS1 DS0
Execution
Result
REMARKS
The first correct ID
information on the cylinder
is stored in Data Register
R
-------------------- ST0 -----------------------
R
-------------------- ST1 -----------------------
R
-------------------- ST2 -----------------------
R
R
---------------------- C ------------------------
R
---------------------- R ------------------------
R
---------------------- N ------------------------
Status information after
command execution
Disk status after the
command has been
completed
---------------------- H ------------------------
(5) Verify
PHASE
Command
R/W
D7
D6
D5
D4
D3
W
MT MFM SK
1
0
W
EC
0
0
0
0
D2
1
D1
1
D0
0
REMARKS
Command codes
HDS DS1 DS0
W
---------------------- C ------------------------
W
---------------------- H ------------------------
W
---------------------- R ------------------------
W
---------------------- N ------------------------
W
-------------------- EOT -----------------------
W
-------------------- GPL -----------------------
Sector ID information prior
to command execution
-------------------- DTL/SC ------------------Execution
Result
No data transfer takes
place
R
-------------------- ST0 -----------------------
R
-------------------- ST1 -----------------------
R
-------------------- ST2 -----------------------
R
---------------------- C ------------------------
R
---------------------- H ------------------------
R
---------------------- R ------------------------
R
---------------------- N ------------------------
- 28 -
Status information after
command execution
Sector ID information after
command execution
Publication Release Date: Jul 1999
Revision 0.53
W83627HF/F
PRELIMINARY
(6) Version
PHASE
R/W
D7
D6
D5
D4
D3
D2
D1
D0
REMARKS
Command
W
0
0
0
1
0
0
0
0
Command code
Result
R
1
0
0
1
0
0
0
0
Enhanced controller
PHASE
R/W
D7
D6
D5
D4
D3
Command
W
MT MFM
0
0
0
W
0
0
0
0
(7) Write Data
0
D2
1
D1
0
D0
1
Command codes
HDS DS1 DS0
W
---------------------- C ------------------------
W
---------------------- H ------------------------
W
---------------------- R ------------------------
W
---------------------- N ------------------------
W
-------------------- EOT -----------------------
W
-------------------- GPL -----------------------
W
-------------------- DTL -----------------------
Execution
Result
REMARKS
Sector ID information prior
to Command execution
Data transfer between the
FDD and system
R
-------------------- ST0 -----------------------
R
-------------------- ST1 -----------------------
R
-------------------- ST2 -----------------------
R
---------------------- C ------------------------
R
---------------------- H ------------------------
R
---------------------- R ------------------------
R
---------------------- N ------------------------
- 29 -
Status information after
Command execution
Sector ID information after
Command execution
Publication Release Date: Jul 1999
Revision 0.53
W83627HF/F
PRELIMINARY
(8) Write Deleted Data
PHASE
R/W
Command
W
W
W
D7
D6
D5
D4
MT MFM
0
0
1
0
0
0
0
0
D3
D2
0
D1
0
D0
1
Command codes
HDS DS1 DS0
---------------------- C ------------------------
W
---------------------- H ------------------------
W
---------------------- R ------------------------
W
---------------------- N ------------------------
W
-------------------- EOT -----------------------
W
-------------------- GPL -----------------------
W
-------------------- DTL -----------------------
Execution
Result
REMARKS
Sector ID information prior
to command execution
Data transfer between the
FDD and system
R
-------------------- ST0 -----------------------
R
-------------------- ST1 -----------------------
R
-------------------- ST2 -----------------------
R
---------------------- C ------------------------
R
---------------------- H ------------------------
R
---------------------- R ------------------------
R
---------------------- N ------------------------
- 30 -
Status information after
command execution
Sector ID information after
command execution
Publication Release Date: Jul 1999
Revision 0.53
W83627HF/F
PRELIMINARY
(9) Format A Track
PHASE
Command
Execution
for Each
Sector
Repeat:
R/W
D7
W
0
W
0
D6
D5
D4
D3
MFM
0
0
1
0
0
0
0
D2
D1
1
D0
0
1
REMARKS
Command codes
HDS DS1 DS0
W
---------------------- N ------------------------
W
--------------------- SC -----------------------
Sectors/Cylinder
W
--------------------- GPL ---------------------
Gap 3
W
---------------------- D ------------------------
Filler Byte
W
---------------------- C ------------------------
Input Sector Parameters
W
---------------------- H ------------------------
W
---------------------- R ------------------------
W
---------------------- N ------------------------
R
-------------------- ST0 -----------------------
R
-------------------- ST1 -----------------------
R
-------------------- ST2 -----------------------
R
R
---------------- Undefined -------------------
R
---------------- Undefined -------------------
R
---------------- Undefined -------------------
Result
Bytes/Sector
Status information after
command execution
---------------- Undefined -------------------
(10) Recalibrate
PHASE
R/W
D7
D6
D5
D4
D3
D2
Command
W
0
0
0
0
0
1
W
0
0
0
0
0
0
D1
1
D0
1
REMARKS
Command codes
DS1 DS0
Execution
Head retracted to Track 0
Interrupt
(11) Sense Interrupt Status
PHASE
R/W
D7
D6
D5
0
0
D4
Command
W
0
Result
R
---------------- ST0 -------------------------
R
---------------- PCN -------------------------
0
D3
1
D2
0
- 31 -
D1
0
D0
0
REMARKS
Command code
Status information at the end
of each seek operation
Publication Release Date: Jul 1999
Revision 0.53
W83627HF/F
PRELIMINARY
(12) Specify
PHASE
R/W
D7
W
0
W
| ---------SRT ----------- | --------- HUT ---------- |
W
|------------ HLT ----------------------------------| ND
Command
D6
0
D5
0
D4
0
D3
0
D2
0
D1
1
D0
1
REMARKS
Command codes
(13) Seek
PHASE
R/W
D7
D6
D5
D4
W
0
0
0
0
1
W
0
0
0
0
0
Command
W
Execution
D3
D2
1
D1
1
D0
1
REMARKS
Command codes
HDS DS1 DS0
-------------------- NCN -----------------------
R
Head positioned over proper
cylinder on diskette
(14) Configure
PHASE
Command
R/W
D7
D6
D5
D4
D3
W
0
0
0
1
0
0
1
1
W
0
0
0
0
0
0
0
0
W
W
0
D2
D1
D0
REMARKS
Configure information
EIS EFIFO POLL | ------ FIFOTHR ----|
| --------------------PRETRK ----------------------- |
Execution
Internal registers written
(15) Relative Seek
PHASE
Command
R/W
D7
D6
W
1
W
0
W
D5
D4
D3
DIR
0
0
1
0
0
0
0
D2
1
D1
1
D0
1
REMARKS
Command codes
HDS DS1 DS0
| -------------------- RCN ---------------------------- |
- 32 -
Publication Release Date: Jul 1999
Revision 0.53
W83627HF/F
PRELIMINARY
(16) Dumpreg
PHASE
R/W
D7
D6
D5
D4
0
0
0
Command
W
0
Result
R
----------------------- PCN-Drive 0--------------------
R
----------------------- PCN-Drive 1 -------------------
R
----------------------- PCN-Drive 2--------------------
R
----------------------- PCN-Drive 3 -------------------
R
--------SRT ------------------ | --------- HUT --------
R
----------- HLT -----------------------------------| ND
R
------------------------ SC/EOT ---------------------D3
D2
D3
1
D2
1
D1
D1
1
D0
REMARKS
0
D0 GAP
Registers placed in FIFO
R
LOCK 0
WG
R
0 EIS EFIFO POLL | ------ FIFOTHR --------
R
-----------------------PRETRK -------------------------
(17) Perpendicular Mode
PHASE
Command
R/W
D7
D6
D5
D4
D3
W
0
0
0
1
0
W
OW
0
D3
D2
D1
R/W
D7
D6
D2
0
D1
1
D0
0
REMARKS
Command Code
D0 GAP WG
(18) Lock
PHASE
Command
W
Result
R
LOCK 0
0
0
D5
D4
D3
D2
D1
D0
0
1
0
1
0
0
0
LOCK
0
0
0
0
REMARKS
Command Code
(19) Sense Drive Status
PHASE
Command
Result
R/W
W
W
R
D7
0
0
R/W
W
D7
D6 D5 D4 D3 D2 D1 D0
0
0
0
0
1
0
0
0
0
0
0 HDS DS1 DS0
---------------- ST3 -------------------------
REMARKS
Command Code
Status information about
disk drive
(20) Invalid
PHASE
Command
Result
R
D6 D5 D4 D3 D2 D1 D0
------------- Invalid Codes ------------------------------------ ST0 ----------------------
- 33 -
REMARKS
Invalid codes (no operationFDC goes to standby state)
ST0 = 80H
Publication Release Date: Jul 1999
Revision 0.53
W83627HF/F
PRELIMINARY
3.2
Register Descriptions
There are several status, data, and control registers in W83627HF. These registers are defined below:
ADDRESS
OFFSET
base address + 0
base address + 1
base address + 2
base address + 3
base address + 4
base address + 5
base address + 7
3.2.1
REGISTER
READ
SA REGISTER
SB REGISTER
WRITE
DO REGISTER
TD REGISTER
DR REGISTER
DT (FIFO) REGISTER
CC REGISTER
TD REGISTER
MS REGISTER
DT (FIFO) REGISTER
DI REGISTER
Status Register A (SA Register) (Read base address + 0)
This register is used to monitor several disk interface pins in PS/2 and Model 30 modes. In PS/2 mode,
the bit definitions for this register are as follows:
7
6
5
4
3
2
1
0
DIR
WP
INDEX
HEAD
TRAK0
STEP
DRV2
INIT PENDING
INIT PENDING (Bit 7):
This bit indicates the value of the floppy disk interrupt output.
DRV2# (Bit 6):
0
A second drive has been installed
1
A second drive has not been installed
STEP (Bit 5):
This bit indicates the complement of STEP# output.
TRAK0# (Bit 4):
This bit indicates the value of TRAK0# input.
- 34 -
Publication Release Date: Jul 1999
Revision 0.53
W83627HF/F
PRELIMINARY
HEAD (Bit 3):
This bit indicates the complement of HEAD# output.
0
side 0
1
side 1
INDEX# (Bit 2):
This bit indicates the value of INDEX# output.
WP# (Bit 1):
0
disk is write-protected
1
disk is not write-protected
DIR (Bit 0)
This bit indicates the direction of head movement.
0
outward direction
1
inward direction
In PS/2 Model 30 mode, the bit definitions for this register are as follows:
7
6
5
4
3
2
1
0
DIR
WP
INDEX
HEAD
TRAK0
STEP F/F
DRQ
INIT PENDING
INIT PENDING (Bit 7):
This bit indicates the value of the floppy disk interrupt output.
DRQ (Bit 6):
This bit indicates the value of DRQ output pin.
STEP F/F (Bit 5):
This bit indicates the complement of latched STEP# output.
TRAK0 (Bit 4):
This bit indicates the complement of TRAK0# input.
- 35 -
Publication Release Date: Jul 1999
Revision 0.53
W83627HF/F
PRELIMINARY
HEAD# (Bit 3):
This bit indicates the value of HEAD# output.
0
side 1
1
side 0
INDEX (Bit 2):
This bit indicates the complement of INDEX# output.
WP (Bit 1):
0
disk is not write-protected
1
disk is write-protected
DIR# (Bit 0)
This bit indicates the direction of head movement.
0
inward direction
1
outward direction
3.2.2
Status Register B (SB Register) (Read base address + 1)
This register is used to monitor several disk interface pins in PS/2 and Model 30 modes. In PS/2 mode,
the bit definitions for this register are as follows:
7
6
1
1
5
4
3
2
1
0
MOT EN A
MOT EN B
WE
RDATA Toggle
WDATA Toggle
Drive SEL0
Drive SEL0 (Bit 5):
This bit indicates the status of DO REGISTER bit 0 (drive select bit 0).
WDATA Toggle (Bit 4):
This bit changes state at every rising edge of the WD# output pin.
RDATA Toggle (Bit 3):
This bit changes state at every rising edge of the RDATA# output pin.
WE (Bit 2):
This bit indicates the complement of the WE# output pin.
MOT EN B (Bit 1)
- 36 -
Publication Release Date: Jul 1999
Revision 0.53
W83627HF/F
PRELIMINARY
This bit indicates the complement of the MOB# output pin.
MOT EN A (Bit 0)
This bit indicates the complement of the MOA# output pin.
In PS/2 Model 30 mode, the bit definitions for this register are as follows:
7
6
5
4
3
2
1
0
DSC
DSD
WE F/F
RDATA F/F
WD F/F
DSA
DSB
DRV2
DRV2# (Bit 7):
0
A second drive has been installed
1
A second drive has not been installed
DSB# (Bit 6):
This bit indicates the status of DSB# output pin.
DSA# (Bit 5):
This bit indicates the status of DSA# output pin.
WD F/F(Bit 4):
This bit indicates the complement of the latched WD# output pin at every rising edge of the WD# output
pin.
RDATA F/F(Bit 3):
This bit indicates the complement of the latched RDATA# output pin .
WE F/F (Bit 2):
This bit indicates the complement of latched WE# output pin.
DSD# (Bit 1):
0
Drive D has been selected
1
Drive D has not been selected
DSC# (Bit 0):
0
Drive C has been selected
1
Drive C has not been selected
- 37 -
Publication Release Date: Jul 1999
Revision 0.53
W83627HF/F
PRELIMINARY
3.2.3
Digital Output Register (DO Register) (Write base address + 2)
The Digital Output Register is a write-only register controlling drive motors, drive selection, DRQ/IRQ
enable, and FDC resetting. All the bits in this register are cleared by the MR pin. The bit definitions are
as follows:
7
6
5
3
4
1-0
2
Drive Select: 00 select drive A
01 select drive B
10 select drive C
11 select drive D
Floppy Disk Controller Reset
Active low resets FDC
DMA and INT Enable
Active high enable DRQ/IRQ
Motor Enable A. Motor A on when active high
Motor Enable B. Motor B on when active high
Motor Enable C. Motor C on when active high
Motor Enable D. Motor D on when active high
3.2.4
Tape Drive Register (TD Register) (Read base address + 3)
This register is used to assign a particular drive number to the tape drive support mode of the data
separator. This register also holds the media ID, drive type, and floppy boot drive information of the
floppy disk drive. In normal floppy mode, this register includes only bit 0 and 1. The bit definitions are as
follows:
7
X
6
5
4
3
2
X
X
X
X
X
1
0
Tape sel 0
Tape sel 1
If three mode FDD function is enabled (EN3MODE = 1 in CR9), the bit definitions are as follows:
7
6
5
4
3
2
1
0
Tape Sel 0
Tape Sel 1
Floppy boot drive 0
Floppy boot drive 1
Drive type ID0
Drive type ID1
Media ID0
Media ID1
- 38 -
Publication Release Date: Jul 1999
Revision 0.53
W83627HF/F
PRELIMINARY
Media ID1 Media ID0 (Bit 7, 6):
These two bits are read only. These two bits reflect the value of CR8 bit 3, 2.
Drive type ID1 Drive type ID0 (Bit 5, 4):
These two bits reflect two of the bits of CR7. Which two bits are reflected depends on the last drive
selected in the DO REGISTER.
Floppy Boot drive 1, 0 (Bit 3, 2):
These two bits reflect the value of CR8 bit 1, 0.
Tape Sel 1, Tape Sel 0 (Bit 1, 0):
These two bits assign a logical drive number to the tape drive. Drive 0 is not available as a tape drive
and is reserved as the floppy disk boot drive.
TAPE SEL 1
0
0
1
1
3.2.5
TAPE SEL 0
0
1
0
1
DRIVE SELECTED
None
1
2
3
Main Status Register (MS Register) (Read base address + 4)
The Main Status Register is used to control the flow of data between the microprocessor and the
controller. The bit definitions for this register are as follows:
7
6
5
4
3
2
1
0
FDD 0 Busy, (D0B = 1), FDD number 0 is in the SEEK mode.
FDD 1 Busy, (D1B = 1), FDD number 1 is in the SEEK mode.
FDD 2 Busy, (D2B = 1), FDD number 2 is in the SEEK mode.
FDD 3 Busy, (D3B = 1), FDD number 3 is in the SEEK mode.
FDC Busy, (CB). A read or write command is in the process when CB = HIGH.
Non-DMA mode, the FDC is in the non-DMA mode, this bit is set only during the
execution phase in non-DMA mode.
Transition to LOW state indicates execution phase has ended.
DATA INPUT/OUTPUT, (DIO). If DIO= HIGH then transfer is from Data Register to the processor.
If DIO = LOW then transfer is from processor to Data Register.
Request for Master (RQM). A high on this bit indicates Data Register is ready to send or receive data to or from the processor.
3.2.6
Data Rate Register (DR Register) (Write base address + 4)
The Data Rate Register is used to set the transfer rate and write precompensation. The data rate of the
FDC is programmed by the CC REGISTER for PC-AT and PS/2 Model 30 and PS/2 mode, and not by
the DR REGISTER. The real data rate is determined by the most recent write to either of the DR
REGISTER or CC REGISTER.
- 39 -
Publication Release Date: Jul 1999
Revision 0.53
W83627HF/F
PRELIMINARY
7
6
5
4
3
2
1
0
0
DRATE0
DRATE1
PRECOMP0
PRECOMP1
PRECOMP2
POWER DOWN
S/W RESET
S/W RESET (Bit 7):
This bit is the software reset bit.
POWER-DOWN (Bit 6):
0
FDC in normal mode
1
FDC in power-down mode
PRECOMP2 PRECOMP1 PRECOMP0 (Bit 4, 3, 2):
These three bits select the value of write precompensation. The following tables show the
precompensation values for the combination of these bits.
PRECOMP
PRECOMPENSATION DELAY
2
1
0
250K - 1 Mbps
2 Mbps Tape drive
0
0
0
Default Delays
Default Delays
0
0
1
41.67 nS
20.8 nS
0
1
0
83.34 nS
41.17 nS
0
1
1
125.00 nS
62.5nS
1
0
0
166.67 nS
83.3 nS
1
0
1
208.33 nS
104.2 nS
1
1
0
250.00 nS
125.00 nS
1
1
1
0.00 nS (disabled)
0.00 nS (disabled)
DATA RATE
250 KB/S
300 KB/S
500 KB/S
1 MB/S
2 MB/S
DEFAULT PRECOMPENSATION DELAYS
125 nS
125 nS
125 nS
41.67nS
20.8 nS
- 40 -
Publication Release Date: Jul 1999
Revision 0.53
W83627HF/F
PRELIMINARY
DRATE1 DRATE0 (Bit 1, 0):
These two bits select the data rate of the FDC and reduced write current control.
00 500 KB/S (MFM), 250 KB/S (FM), RWC = 1
01 300 KB/S (MFM), 150 KB/S (FM), RWC = 0
10 250 KB/S (MFM), 125 KB/S (FM), RWC = 0
11 1 MB/S (MFM), Illegal (FM), RWC = 1
The 2 MB/S data rate for Tape drive is only supported by setting 01 to DRATE1 and DRATE0 bits, as
well as setting 10 to DRT1 and DRT0 bits which are two of the Configure Register CRF4 or CRF5 bits in
logic device 0. Please refer to the function description of CRF4 or CRF5 and data rate table for
individual data rates setting.
3.2.7
FIFO Register (R/W base address + 5)
The Data Register consists of four status registers in a stack with only one register presented to the data
bus at a time. This register stores data, commands, and parameters and provides diskette-drive status
information. Data bytes are passed through the data register to program or obtain results after a
command. In the W83627HF, this register defaults to FIFO disabled mode after reset. The FIFO can
change its value and enable its operation through the CONFIGURE command.
Status Register 0 (ST0)
7-6
5
4
3
2
1-0
US1, US0 Drive Select:
00 Drive A selected
01 Drive B selected
10 Drive C selected
11 Drive D selected
HD Head address:
1 Head selected
0 Head selected
NR Not Ready:
1 Drive is not ready
0 Drive is ready
EC Equipment Check:
1 When a fault signal is received from the FDD or the track
0 signal fails to occur after 77 step pulses
0 No error
SE Seek end:
1 seek end
0 seek error
IC Interrupt Code:
00 Normal termination of command
01 Abnormal termination of command
10 Invalid command issue
11 Abnormal termination because the ready signal from FDD changed state during command execution
- 41 -
Publication Release Date: Jul 1999
Revision 0.53
W83627HF/F
PRELIMINARY
Status Register 1 (ST1)
7
6
5
4
3
2
1
0
Missing Address Mark. 1 When the FDC cannot detect the data address mark
or the data address mark has been deleted.
NW (Not Writable). 1 If a write Protect signal is detected from the diskette drive during
execution of write data.
ND (No DATA). 1 If specified sector cannot be found during execution of a read, write or verifly data.
Not used. This bit is always 0.
OR (Over Rum). 1 If the FDC is not serviced by the host system within a certain time interval during data transfer.
DE (data Error).1 When the FDC detects a CRC error in either the ID field or the data field.
Not used. This bit is always 0.
EN (End of track). 1 When the FDC tries to access a sector beyond the final sector of a cylinder.
Status Register 2 (ST2)
7
6
5
4
3
2
1
0
MD (Missing Address Mark in Data Field).
1 If the FDC cannot find a data address mark
(or the address mark has been deleted)
when reading data from the media
0 No error
BC (Bad Cylinder)
1 Bad Cylinder
0 No error
SN (Scan Not satisfied)
1 During execution of the Scan command
0 No error
SH (Scan Equal Hit)
1 During execution of the Scan command, if the equal condition is satisfied
0 No error
WC (Wrong Cylinder)
1 Indicates wrong Cylinder
DD (Data error in the Data field)
1 If the FDC detects a CRC error in the data field
0 No error
CM (Control Mark)
1 During execution of the read data or scan command
0 No error
Not used. This bit is always 0
Status Register 3 (ST3)
7
6
5
4
3
2
1
0
US0 Unit Select 0
US1 Unit Select 1
HD Head Address
TS Two-Side
TO Track 0
RY Ready
WP Write Protected
FT Fault
- 42 -
Publication Release Date: Jul 1999
Revision 0.53
W83627HF/F
PRELIMINARY
3.2.8
Digital Input Register (DI Register) (Read base address + 7)
The Digital Input Register is an 8-bit read-only register used for diagnostic purposes. In a PC/XT or AT
only Bit 7 is checked by the BIOS. When the register is read, Bit 7 shows the complement of DSKCHG#,
while other bits of the data bus remain in tri-state. Bit definitions are as follows:
7
6
5
4
3
x
x
x
x
2
1
0
x x x
for the hard disk controller
x Reserved
During a read of this register, these bits are in tri-state
DSKCHG
In the PS/2 mode, the bit definitions are as follows:
7
6
5
4
3
1
1
1
1
2
0
1
HIGH DENS
DRATE0
DRATE1
DSKCHG
DSKCHG (Bit 7):
This bit indicates the complement of the DSKCHG# input.
Bit 6-3: These bits are always a logic 1 during a read.
DRATE1 DRATE0 (Bit 2, 1):
These two bits select the data rate of the FDC. Refer to the DR register bits 1 and 0 for the settings
corresponding to the individual data rates.
HIGH DENS# (Bit 0):
0
500 KB/S or 1 MB/S data rate (high density FDD)
1
250 KB/S or 300 KB/S data rate
In the PS/2 Model 30 mode, the bit definitions are as follows:
7
6
5
4
0
0
0
3
2
1
0
DRATE0
DRATE1
NOPREC
DMAEN
DSKCHG
- 43 -
Publication Release Date: Jul 1999
Revision 0.53
W83627HF/F
PRELIMINARY
DSKCHG (Bit 7):
This bit indicates the status of DSKCHG# input.
Bit 6-4: These bits are always a logic 1 during a read.
DMAEN (Bit 3):
This bit indicates the value of DO REGISTER bit 3.
NOPREC (Bit 2):
This bit indicates the value of CC REGISTER NOPREC bit.
DRATE1 DRATE0 (Bit 1, 0):
These two bits select the data rate of the FDC.
3.2.9
Configuration Control Register (CC Register) (Write base address + 7)
This register is used to control the data rate. In the PC/AT and PS/2 mode, the bit definitions are as
follows:
7
6
5
4
3
2
x
x
x
x
x
x
1
0
DRATE0
DRATE1
X: Reserved
Bit 7-2: Reserved. These bits should be set to 0.
DRATE1 DRATE0 (Bit 1, 0):
These two bits select the data rate of the FDC.
In the PS/2 Model 30 mode, the bit definitions are as follows:
7
6
5
4
3
X
X
X
X
X
2
1
0
DRATE0
DRATE1
NOPREC
X: Reserved
Bit 7-3: Reserved. These bits should be set to 0.
NOPREC (Bit 2):
This bit indicates no precompensation. It has no function and can be set by software.
DRATE1 DRATE0 (Bit 1, 0):
These two bits select the data rate of the FDC.
- 44 -
Publication Release Date: Jul 1999
Revision 0.53
W83627HF/F
PRELIMINARY
4.
UART PORT
4.1
Universal Asynchronous Receiver/Transmitter (UART A, UART B)
The UARTs are used to convert parallel data into serial format on the transmit side and convert serial
data to parallel format on the receiver side. The serial format, in order of transmission and reception, is
a start bit, followed by five to eight data bits, a parity bit (if programmed) and one, one and half (five-bit
format only) or two stop bits. The UARTs are capable of handling divisors of 1 to 65535 and producing
a 16x clock for driving the internal transmitter logic. Provisions are also included to use this 16x clock to
drive the receiver logic. The UARTs also support the MIDI data rate. Furthermore, the UARTs also
include complete modem control capability and a processor interrupt system that may be software
trailed to the computing time required to handle the communication link. The UARTs have a FIFO
mode to reduce the number of interrupts presented to the CPU. In each UART, there are 16-byte FIFOs
for both receive and transmit mode.
4.2
Register Address
4.2.1 UART Control Register (UCR) (Read/Write)
The UART Control Register controls and defines the protocol for asynchronous data communications,
including data length, stop bit, parity, and baud rate selection.
7
6
5
4
3
2
1
0
Data length select bit 0 (DLS0)
Data length select bit 1(DLS1)
Multiple stop bits enable (MSBE)
Parity bit enable (PBE)
Even parity enable (EPE)
Parity bit fixed enable (PBFE)
Set silence enable (SSE)
Baudrate divisor latch access bit (BDLAB)
Bit 7: BDLAB. When this bit is set to a logical 1, designers can access the divisor (in 16-bit binary format)
from the divisor latches of the baudrate generator during a read or write operation. When this bit
is reset, the Receiver Buffer Register, the Transmitter Buffer Register, or the Interrupt Control
Register can be accessed.
Bit 6: SSE. A logical 1 forces the Serial Output (SOUT) to a silent state (a logical 0). Only IRTX is
affected by this bit; the transmitter is not affected.
Bit 5: PBFE. When PBE and PBFE of UCR are both set to a logical 1,
(1) if EPE is logical 1, the parity bit is fixed as logical 0 to transmit and check.
(2) if EPE is logical 0, the parity bit is fixed as logical 1 to transmit and check.
- 45 -
Publication Release Date: Sep 1998
Revision 0.50
W83627HF/F
PRELIMINARY
TABLE 4-1 UART Register Bit Map
Bit Number
Register Address Base
+0
BDLAB = 0
+0
BDLAB = 0
+1
BDLAB = 0
+2
Receiver
Buffer
Register
(Read Only)
RBR
Transmitter
Buffer Register
(Write Only)
TBR
Interrupt Control
Register
ICR
0
1
2
3
4
5
6
7
RX Data
RX Data
RX Data
RX Data
RX Data
RX Data
RX Data
RX Data
Bit 0
Bit 1
Bit 2
Bit 3
Bit 4
Bit 5
Bit 6
Bit 7
TX Data
TX Data
TX Data
TX Data
TX Data
TX Data
TX Data
TX Data
Bit 0
Bit 1
Bit 2
Bit 3
Bit 4
Bit 5
Bit 6
Bit 7
RBR Data
Ready
Interrupt
Enable
(ERDRI)
TBR
Empty
Interrupt
Enable
(ETBREI)
USR
Interrupt
Enable
HSR
Interrupt
Enable
0
0
0
0
(EUSRI)
(EHSRI)
"0" if
Interrupt
Pending
Interrupt
Status
Interrupt
Status
Interrupt
Status
0
0
Bit (0)
Bit (1)
Bit (2)**
Interrupt Status
Register
(Read Only)
ISR
FIFOs
FIFOs
Enabled
Enabled
**
**
+2
UART FIFO
Control
Register
(Write Only)
UFR
FIFO
Enable
RCVR
FIFO
Reset
XMIT
FIFO
Reset
DMA
Mode
Select
Reserved
Reversed
RX
Interrupt
Active Level
(LSB)
RX
Interrupt
Active Level
(MSB)
+3
UART Control
Register
UCR
Data
Length
Select
Bit 0
(DLS0)
Data
Length
Select
Bit 1
(DLS1)
Multiple
Stop Bits
Enable
Parity
Bit
Enable
Even
Parity
Enable
Parity
Bit Fixed
Enable
Set
Silence
Enable
(MSBE)
(PBE)
(EPE)
PBFE)
(SSE)
Baudrate
Divisor
Latch
Access Bit
(BDLAB)
+4
Handshake
Control
Register
HCR
Data
Terminal
Ready
(DTR)
Request
to
Send
(RTS)
Loopback
RI
Input
IRQ
Enable
Internal
Loopback
Enable
0
0
0
+5
UART Status
Register
USR
RBR Data
Ready
Overrun
Error
Parity Bit
Error
TSR
Empty
(OER)
(PBER)
Silent
Byte
Detected
(SBD)
TBR
Empty
(RDR)
No Stop
Bit
Error
(NSER)
(TBRE)
(TSRE)
RX FIFO
Error
Indication
(RFEI) **
CTS
Toggling
DSR
Toggling
RI Falling
Edge
DCD
Toggling
Clear
to Send
Data Set
Ready
Ring
Indicator
+6
Handshake
Status Register
HSR
(TCTS)
(TDSR)
(FERI)
(TDCD)
(CTS)
(DSR)
(RI)
Data Carrier
Detect
(DCD)
+7
User Defined
Register
UDR
Bit 0
Bit 1
Bit 2
Bit 3
Bit 4
Bit 5
Bit 6
Bit 7
+0
Baudrate Divisor
Latch Low
BLL
Bit 0
Bit 1
Bit 2
Bit 3
Bit 4
Bit 5
Bit 6
Bit 7
Baudrate
Divisor Latch
High
BHL
Bit 8
Bit 9
Bit 10
Bit 11
Bit 12
Bit 13
Bit 14
Bit 15
BDLAB = 1
+1
BDLAB = 1
*: Bit 0 is the least significant bit. The least significant bit is the first bit serially transmitted or received.
**: These bits are always 0 in 16450 Mode.
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Publication Release Date: Sep 1998
Revision 0.50
W83627HF/F
PRELIMINARY
Bit 4: EPE. This bit describes the number of logic 1's in the data word bits and parity bit only when bit 3 is
programmed. When this bit is set, an even number of logic 1's are sent or checked. When the bit
is reset, an odd number of logic 1's are sent or checked.
Bit 3: PBE. When this bit is set, the position between the last data bit and the stop bit of the SOUT will be
stuffed with the parity bit at the transmitter. For the receiver, the parity bit in the same position as
the transmitter will be detected.
Bit 2: MSBE. This bit defines the number of stop bits in each serial character that is transmitted or
received.
(1) If MSBE is set to a logical 0, one stop bit is sent and checked.
(2) If MSBE is set to a logical 1, and data length is 5 bits, one and a half stop bits are sent and
checked.
(3) If MSBE is set to a logical 1, and data length is 6, 7, or 8 bits, two stop bits are sent and
checked.
Bits 0 and 1: DLS0, DLS1. These two bits define the number of data bits that are sent or checked in
each serial character.
TABLE 4-2 WORD LENGTH DEFINITION
DLS1
DLS0
DATA LENGTH
0
0
5 bits
0
1
6 bits
1
0
7 bits
1
1
8 bits
4.2.2 UART Status Register (USR) (Read/Write)
This 8-bit register provides information about the status of the data transfer during communication.
7
6
5
4
3
2
1
0
RBR Data ready (RDR)
Overrun error (OER)
Parity bit error (PBER)
No stop bit error (NSER)
Silent byte detected (SBD)
Transmitter Buffer Register empty (TBRE)
Transmitter Shift Register empty (TSRE)
RX FIFO Error Indication (RFEI)
Bit 7: RFEI. In 16450 mode, this bit is always set to a logic 0. In 16550 mode, this bit is set to a logic 1
when there is at least one parity bit error, no stop bit error or silent byte detected in the FIFO. In
16550 mode, this bit is cleared by reading from the USR if there are no remaining errors left
in the FIFO.
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Publication Release Date: Sep 1998
Revision 0.50
W83627HF/F
PRELIMINARY
Bit 6: TSRE. In 16450 mode, when TBR and TSR are both empty, this bit will be set to a logical 1. In
16550 mode, if the transmit FIFO and TSR are both empty, it will be set to a logical 1. Other
thanthese two cases, this bit will be reset to a logical 0.
Bit 5: TBRE. In 16450 mode, when a data character is transferred from TBR to TSR, this bit will be set to
a logical 1. If ETREI of ICR is a logical 1, an interrupt will be generated to notify the CPU to write
the next data. In 16550 mode, this bit will be set to a logical 1 when the transmit FIFO is empty. It
will be reset to a logical 0 when the CPU writes data into TBR or FIFO.
Bit 4: SBD. This bit is set to a logical 1 to indicate that received data are kept in silent state for a full word
time, including start bit, data bits, parity bit, and stop bits. In 16550 mode, it indicates the same
condition for the data on top of the FIFO. When the CPU reads USR, it will clear this bit to a
logical 0.
Bit 3: NSER. This bit is set to a logical 1 to indicate that the received data have no stop bit. In 16550
mode, it indicates the same condition for the data on top of the FIFO. When the CPU reads USR,
it will clear this bit to a logical 0.
Bit 2: PBER. This bit is set to a logical 1 to indicate that the parity bit of received data is wrong. In 16550
mode, it indicates the same condition for the data on top of the FIFO. When the CPU reads USR,
it will clear this bit to a logical 0.
Bit 1: OER. This bit is set to a logical 1 to indicate received data have been overwritten by the next
received data before they were read by the CPU. In 16550 mode, it indicates the same condition
instead of FIFO full. When the CPU reads USR, it will clear this bit to a logical 0.
Bit 0: RDR. This bit is set to a logical 1 to indicate received data are ready to be read by the CPU in the
RBR or FIFO. After no data are left in the RBR or FIFO, the bit will be reset to a logical 0.
4.2.3
Handshake Control Register (HCR) (Read/Write)
This register controls the pins of the UART used for handshaking peripherals such as modem, and
controls the diagnostic mode of the UART.
7
6
5
0
0
0
4
3
2
1
0
Data terminal ready (DTR)
Request to send (RTS)
Loopback RI input
IRQ enable
Internal loopback enable
- 48 -
Publication Release Date: Sep 1998
Revision 0.50
W83627HF/F
PRELIMINARY
Bit 4: When this bit is set to a logical 1, the UART enters diagnostic mode by an internal loopback, as
follows:
(1) SOUT is forced to logical 1, and SIN is isolated from the communication link instead of the
TSR.
(2) Modem output pins are set to their inactive state.
(3) Modem input pins are isolated from the communication link and connect internally as DTR
(bit 0 of HCR) → DSR, RTS ( bit 1 of HCR) → CTS, Loopback RI input ( bit 2 of HCR) →
RI and IRQ enable ( bit 3 of HCR) → DCD .
Aside from the above connections, the UART operates normally. This method allows the
CPU to test the UART in a convenient way.
Bit 3: The UART interrupt output is enabled by setting this bit to a logic 1. In the diagnostic mode this bit
is internally connected to the modem control input DCD .
Bit 2: This bit is used only in the diagnostic mode. In the diagnostic mode this bit is internally connected
to the modem control input RI .
Bit 1: This bit controls the RTS output. The value of this bit is inverted and output to RTS .
Bit 0: This bit controls the DTR output. The value of this bit is inverted and output to DTR .
4.2.4
Handshake Status Register (HSR) (Read/Write)
This register reflects the current state of four input pins for handshake peripherals such as a modem
and records changes on these pins.
7
6
5
4
3
2
1
0
CTS toggling (TCTS)
DSR toggling (TDSR)
RI falling edge (FERI)
DCD toggling (TDCD)
Clear to send (CTS)
Data set ready (DSR)
Ring indicator (RI)
Data carrier detect (DCD)
Bit 7: This bit is the opposite of the DCD input. This bit is equivalent to bit 3 of HCR in loopback mode.
Bit 6: This bit is the opposite of the RI input. This bit is equivalent to bit 2 of HCR in loopback mode.
Bit 5: This bit is the opposite of the DSR input. This bit is equivalent to bit 0 of HCR in loopback mode.
Bit 4: This bit is the opposite of the CTS input. This bit is equivalent to bit 1 of HCR in loopback mode.
Bit 3:
TDCD. This bit indicates that the DCD pin has changed state after HSR was read by the
CPU.
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Publication Release Date: Sep 1998
Revision 0.50
W83627HF/F
PRELIMINARY
Bit 2: FERI. This bit indicates that the RI pin has changed from low to high state after HSR was read
by the CPU.
Bit 1: TDSR. This bit indicates that the DSR pin has changed state after HSR was read by the CPU.
Bit 0: TCTS. This bit indicates that the CTS pin has changed state after HSR was read.
4.2.5
UART FIFO Control Register (UFR) (Write only)
This register is used to control the FIFO functions of the UART.
7
6
5
4
3
2
1
0
FIFO enable
Receiver FIFO reset
Transmitter FIFO reset
DMA mode select
Reserved
Reserved
RX interrupt active level (LSB)
RX interrupt active level (MSB)
Bit 6, 7: These two bits are used to set the active level for the receiver FIFO interrupt. For example, if the
interrupt active level is set as 4 bytes, once there are more than 4 data characters in the receiver
FIFO, the interrupt will be activated to notify the CPU to read the data from the FIFO.
TABLE 4-3 FIFO TRIGGER LEVEL
BIT 7
BIT 6
RX FIFO INTERRUPT ACTIVE LEVEL (BYTES)
0
0
01
0
1
04
1
0
08
1
1
14
Bit 4, 5: Reserved
Bit 3: When this bit is programmed to logic 1, the DMA mode will change from mode 0 to mode 1 if
UFR bit 0 = 1.
Bit 2: Setting this bit to a logical 1 resets the TX FIFO counter logic to initial state. This bit will clear to a
logical 0 by itself after being set to a logical 1.
Bit 1: Setting this bit to a logical 1 resets the RX FIFO counter logic to initial state. This bit will clear to a
logical 0 by itself after being set to a logical 1.
Bit 0: This bit enables the 16550 (FIFO) mode of the UART. This bit should be set to a logical 1 before
other bits of UFR are programmed.
- 50 -
Publication Release Date: Sep 1998
Revision 0.50
W83627HF/F
PRELIMINARY
4.2.6
Interrupt Status Register (ISR) (Read only)
This register reflects the UART interrupt status, which is encoded by different interrupt sources into 3
bits.
7
6
5
4
0
0
3
2
1
0
0 if interrupt pending
Interrupt Status bit 0
Interrupt Status bit 1
Interrupt Status bit 2
FIFOs enabled
FIFOs enabled
Bit 7, 6: These two bits are set to a logical 1 when UFR bit 0 = 1.
Bit 5, 4: These two bits are always logic 0.
Bit 3: In 16450 mode, this bit is 0. In 16550 mode, both bit 3 and 2 are set to a logical 1 when a time-out
interrupt is pending.
Bit 2, 1: These two bits identify the priority level of the pending interrupt, as shown in the table below.
Bit 0: This bit is a logical 1 if there is no interrupt pending. If one of the interrupt sources has occurred,
this bit will be set to a logical 0.
TABLE 4-4 INTERRUPT CONTROL FUNCTION
ISR
INTERRUPT SET AND FUNCTION
Bit
3
Bit
2
Bit
1
Bit
0
Interrupt
priority
Interrupt Type
0
0
0
1
-
0
1
1
0
First
UART Receive
Status
1. OER = 1
0
1
0
0
Second
RBR Data Ready
1. RBR data ready
1. Read RBR
2. FIFO interrupt active level
reached
2. Read RBR until FIFO
data under active level
-
Interrupt Source
Clear Interrupt
No Interrupt pending
-
2. PBER =1
Read USR
3. NSER = 1 4. SBD = 1
1
1
0
0
Second
FIFO Data Timeout
Data present in RX FIFO for 4
characters period of time since last
access of RX FIFO.
Read RBR
0
0
1
0
Third
TBR Empty
TBR empty
1. Write data into TBR
2. Read ISR (if priority is
third)
0
0
0
0
Fourth
Handshake status
1. TCTS = 1
2. TDSR = 1
3. FERI = 1
4. TDCD = 1
Read HSR
** Bit 3 of ISR is enabled when bit 0 of UFR is logical 1.
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Publication Release Date: Sep 1998
Revision 0.50
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PRELIMINARY
4.2.7
Interrupt Control Register (ICR) (Read/Write)
This 8-bit register allows the five types of controller interrupts to activate the interrupt output signal
separately. The interrupt system can be totally disabled by resetting bits 0 through 3 of the Interrupt
Control Register (ICR). A selected interrupt can be enabled by setting the appropriate bits of this
register to a logical 1.
7
6
5
4
0
0
0
0
3
2
1
0
RBR data ready interrupt enable (ERDRI)
TBR empty interrupt enable (ETBREI)
UART receive status interrupt enable (EUSRI)
Handshake status interrupt enable (EHSRI)
Bit 7-4: These four bits are always logic 0.
Bit 3: EHSRI. Setting this bit to a logical 1 enables the handshake status register interrupt.
Bit 2: EUSRI. Setting this bit to a logical 1 enables the UART status register interrupt.
Bit 1: ETBREI. Setting this bit to a logical 1 enables the TBR empty interrupt.
Bit 0: ERDRI. Setting this bit to a logical 1 enables the RBR data ready interrupt.
4.2.8
Programmable Baud Generator (BLL/BHL) (Read/Write)
Two 8-bit registers, BLL and BHL, compose a programmable baud generator
that uses 24 MHz to
16
generate a 1.8461 MHz frequency and divides it by a divisor from 1 to 2 -1. The output frequency of
the baud generator is the baud rate multiplied by 16, and this is the base frequency for the transmitter
and receiver. The table in the next page illustrates the use of the baud generator with a frequency of
1.8461 MHz. In high-speed UART mode (refer to CR0C bit7 and CR0C bit6), the programmable baud
generator directly uses 24 MHz and the same divisor as the normal speed divisor. In high-speed mode,
the data transmission rate can be as high as 1.5M bps.
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Publication Release Date: Sep 1998
Revision 0.50
W83627HF/F
PRELIMINARY
4.2.9
User-defined Register (UDR) (Read/Write)
This is a temporary register that can be accessed and defined by the user.
TABLE 4-5 BAUD RATE TABLE
BAUD RATE FROM DIFFERENT PRE-DIVIDER
Pre-Div: 13
1.8461M Hz
50
Pre-Div:1.625
14.769M Hz
400
Pre-Div: 1.0
24M Hz
650
Decimal divisor used
to generate 16X clock
Error Percentage between
desired and actual
2304
**
75
600
975
1536
**
110
880
1430
1047
0.18%
134.5
1076
1478.5
857
0.099%
150
1200
1950
768
**
300
2400
3900
384
**
600
4800
7800
192
**
1200
9600
15600
96
**
1800
14400
23400
64
**
2000
16000
26000
58
0.53%
2400
19200
31200
48
**
3600
28800
46800
32
**
4800
38400
62400
24
**
7200
57600
93600
16
**
9600
76800
124800
12
**
19200
153600
249600
6
**
38400
307200
499200
3
**
57600
460800
748800
2
**
115200
921600
1497600
1
**
** The percentage error for all baud rates, except where indicated otherwise, is 0.16%.
Note. Pre-Divisor is determined by CRF0 of UART A and B.
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Publication Release Date: Sep 1998
Revision 0.50
W83627HF/F
PRELIMINARY
5. CIR RECEIVER PORT
5.1 CIR Registers
5.1.1 Bank0.Reg0 - Receiver Buffer Registers (RBR) (Read)
Receiver Buffer Register is read only. When the CIR pulse train has been detected and passed by the
internal signal filter, the data samped and shifted into shifter register will write into Receiver Buffer
Register. In the CIR, this port is only supports PIO mode and the address port is defined in the PnP.
5.1.2 Bank0.Reg1 - Interrupt Control Register (ICR)
Power on default <7:0> = 00000000 binary
Read/Write
Description
EN_GLBI
Read/Write
Enable Global Interrupt. Write 1, enable interrupt. Write 0,
disable global interrupt.
Reserved
EN_TMR_I
En_LSR_I
Read/Write
Read/Write
Reserved
Enable Timer Interrupt.
Enable Line-Status-Register interrupt.
EN_RX_I
Read/Write
Receiver Thershold-Level Interrupt Enable.
Bit
7
6-3
2
1
0
Name
5.1.3 Bank0.Reg2 - Interrupt Status Register (ISR)
Power on default <7:0> = 00000000 binary
Bit
7-3
2
Name
Description
Read/Write
Reserved
TMR_I
Read Only
1
LSR_I
Read Only
0
RXTH_I
Read Only
Reserved
Timer Interrupt. Set to 1 when timer count to 0. This bit will
be affected by (1) the timer registers are defined in
Bank4.Reg0 and Bank1.Reg0~1, (2) EN_TMR(Enable
Timer, in Bank0.Reg3.Bit2) should be set to 1, (3)
ENTMR_I (Enable Timer Interrupt, in Bank0.Reg1.Bit2)
should be set to 1.
Line-Status-Register interrupt. Set to 1 when overrun, or
parity bit, or stop bit, or silent byte detected error in the
Line Status Register (LSR) sets to 1. Clear to 0 when LSR
is read.
Receiver Thershold-Level Interrupt. Set to 1 when (1) the
Receiver Buffer Register (RBR) is equal or larger than the
threshold level, (2) RBR occurs time-out if the receiver
buffer register has valid data and below the threshold
level. Clear to 0 when RBR is less than threshold level
from reading RBR.
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Publication Release Date: Sep 1998
Revision 0.50
W83627HF/F
PRELIMINARY
5.1.4 Bank0~3.Reg3 - CIR Control Register 0/Bank Select Register (CTR0/BSR) (BANK0~3)
Power on default <7:0> = 00000000 binary
Bit
Name
Read/Write
Description
7-6
BNK_SEL<1:0>
Read/Write
Bank Select Register. These two bits are shared same
address so that Bank Select Register (BSR) can be
programmed to desired Bank in any Bank.
BNK_SEL<1:0> = 00 Select Bank 0.
BNK_SEL<1:0> = 01 Select Bank 1.
BNK_SEL<1:0> = Reserved.
BNK_SEL<1:0> = Reserved.
5-4
RXFTL1/0
Read/Write
3
TMR_TST
Read/Write
2
EN_TMR
Read/Write
Receiver FIFO Threshold Level. It is to determine the
RXTH_I to become 1 when the Receiver FIFO Threshold
Level is equal or larger than the defined value shown as
follow.
RXFTL<1:0> = 00 -- 1 byte
RXFTL<1:0> = 01 -- 4 bytes
RXFTL<1:0> = 10 -- 8 bytes
RXFTL<1:0> = 11 -- 14 bytes
Timer Test. Write to 1, then reading the TMRL/TMRH will
return the programmed values of TMRL/TMRH, that is,
does not return down count counter value. This bit is for
test timer register.
Enable timer. Write to 1, enable the timer
1
RXF_RST
Read/Write
0
TMR_CLK
Read/Write
Setting this bit to a logical 1 resets the RX FIFO counter
logic to initial state. This bit will clear to a logical 0 by itself
after being set to a logical 1.
Timer input clock.
Winbond test register
5.1.5 Bank0.Reg4 - CIR Control Register (CTR)
Power on default <7:0> = 0010,1001 binary
Bit
Name
Read/Write
Description
7-5
RX_FR<2:0>
Read/Write
Receiver Frequency Range 2~0. These bits select the
input frequency of the receiver ranges. For the input signal,
that is through a band pass filter, i.e., the frequency of the
input signal is located at this defined range then the signal
will be received.
4-0
RX_FSL<4:0>
Read/Write
Receiver Frequency Select 4~0. Select the receiver
operation frequency.
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Publication Release Date: Sep 1998
Revision 0.50
W83627HF/F
PRELIMINARY
Table: Low Frequency range select of receiver.
RX_FR2~0 (Low Frequency)
001
010
011
RX_FSL4~0
Min.
Max.
Min.
Max.
Min.
Max.
00010
26.1
29.6
24.7
31.7
23.4
34.2
00011
28.2
32.0
26.7
34.3
25.3
36.9
00100
29.4
33.3
27.8
35.7
26.3
38.4
00101
30.0
34.0
28.4
36.5
26.9
39.3
00110
31.4
35.6
29.6
38.1
28.1
41.0
00111
32.1
36.4
30.3
39.0
28.7
42.0
01000
32.8
37.2
31.0
39.8
29.4
42.9
01001
33.6*
38.1*
31.7
40.8
30.1
44.0
01011
34.4
39.0
32.5
41.8
30.8
45.0
01100
36.2
41.0
34.2
44.0
32.4
47.3
01101
37.2
42.1
35.1
45.1
33.2
48.6
01111
38.2
43.2
36.0
46.3
34.1
49.9
10000
40.3
45.7
38.1
49.0
36.1
52.7
10010
41.5
47.1
39.2
50.4
37.2
54.3
10011
42.8
48.5
40.4
51.9
38.3
56.0
10101
44.1
50.0
41.7
53.6
39.5
57.7
10111
45.5
51.6
43.0
55.3
40.7
59.6
11010
48.7
55.2
46.0
59.1
43.6
63.7
11011
50.4
57.1
47.6
61.2
45.1
65.9
11101
54.3
61.5
51.3
65.9
48.6
71.0
Note that the other non-defined values are reserved.
5.1.6 Bank0.Reg5 - UART Line Status Register (USR)
Power on default <7:0> = 0000,0000 binary
Bit
7-3
Name
Read/Write
Description
Reserved
-
-
2
RX_TO
Read/Write
Set to 1 when receiver FIFO or frame status FIFO occurs
time-out. Read this bit will be cleared.
1
0
OV_ERR
RDR
Read/Write
Read/Write
Received FIFO overrun. Read to clear.
This bit is set to a logical 1 to indicate received data are
ready to be read by the CPU in the RBR or FIFO. After no
data are left in the RBR or FIFO, the bit will be reset to a
logical 0.
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Publication Release Date: Sep 1998
Revision 0.50
W83627HF/F
PRELIMINARY
5.1.7 Bank0.Reg6 - Remote Infrared Config Register (RIR_CFG)
Power on default <7:0> = 0000,0000 binary
Bit
7-6
Name
SMPSEL<1:0>
Read/Write
Description
Read/Write
Sampling Mode Select. Select internal decoder
methodology from the internal filter. Selected decoder
mode will determine the receive data format. The
sampling mode is shown as bellow:
SMPSEL<1:0> = 00 T-Period Sample Mode.
SMPSEL<1:0> = 01 Over-Sampling Mode.
SMPSEL<1:0> = 10 Over-Sampling with re-sync.
SMPSEL<1:0> = 11 FIFO Test Mode.
The T-period code format is defined as follows.
(Number of bits) - 1
B7 B6 B5 B4 B3 B2 B1 B0
Bit value
5-4
LP_SL<1:0>
Read/Write
3-2
RXDMSL<1:0>
Read/Write
1
PRE_DIV
Read/Write
0
RXINV
Read/Write
The Bit value is set to 0, then the high pulse will be
received. The Bit value is set to 1, then no energy will be
received. The opposite results will be generated when the
bit RXINV (Bank0.Reg6.Bit0) is set to 1.
Low pass filter source selcetion.
LP_SL<1:0> = 00 Select raw IRRX signal.
LP_SL<1:0> = 01 Select R.B.P. signal
LP_SL<1:0> = 10 Select D.B.P. signal.
LP_SL<1:0> = 11 Reserved.
Receiver Demodulation Source Selection.
RXDMSL<1:0> = 00 select B.P. and L.P. filter.
RXDMSL<1:0> = 01 select B.P. but not L.P.
RXDMSL<1:0> = 10 Reserved.
RXDMSL<1:0> = 11 do not pass demodulation.
Baud Rate Pre-divisor. Set to 1, the baud rate generator
input clock is set to 1.8432M Hz which is set to pre-divisor
into 13. When set to 0, the pre-divisor is set to 1, that is, the
input clock of baud rate generator is set to 24M Hz.
Receiving Signal Invert. Write to 1, Invert the receiving
signal.
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Publication Release Date: Sep 1998
Revision 0.50
W83627HF/F
PRELIMINARY
5.1.8 Bank0.Reg7 - User Defined Register (UDR/AUDR)
Power on default <7:0> = 0000,0000 binary
Bit
Name
Read/Write
Description
7
RXACT
Read/Write
Receive Active. Set to 1 whenever a pulse or pulse-train is
detected by the receiver. If a 1 is written into the bit
position, the bit is cleared and the receiver is de-actived.
When this bit is set, the receiver samples the IR input
continuously at the programmed baud rate and transfers
the data to the receiver FIFO.
6
RX_PD
Read Only
Set to 1 whenever a pulse or pulse-train (modulated pulse)
is detected by the receiver. Can be used by the sofware to
detect idle condition Cleared Upon Read.
5
Reserved
-
-
4-0
FOLVAL
Read Only
FIFO Level Value. Indicate that how many bytes are there
in the current received FIFO. Can read these bits then get
the FIFO level value and successively read RBR by the
prior value.
- 58 -
Publication Release Date: Sep 1998
Revision 0.50
W83627HF/F
PRELIMINARY
5.1.9 Bank1.Reg0~1 - Baud Rate Divisor Latch (BLL/BHL)
The two registers of BLL and BHL are baud rate divisor latch in the legacy UART/SIR/ASK-IR mode.
Read/Write these registers, if set in Advanced UART mode, will occur backward operation, that is, will
go to legacy UART mode and clear some register values shown table as follows.
TABLE :BAUD RATE TABLE
BAUD RATE USING 24 MHZ TO GENERATE 1.8461 MHZ
Desired Baud Rate
Decimal divisor used to
generate 16X clock
Percent error difference between
desired and actual
50
2304
**
75
1536
**
110
1047
0.18%
134.5
857
0.099%
150
768
**
300
384
**
600
192
**
1200
96
**
1800
64
**
2000
58
0.53%
2400
48
**
3600
32
**
4800
24
**
7200
16
**
9600
12
**
19200
6
**
38400
3
**
57600
2
**
115200
1
**
1.5M
1
Note 1
0%
Note 1: Only use in high speed mode, when Bank0.Reg6.Bit7 is set.
** The percentage error for all baud rates, except where indicated otherwise, is 0.16%
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PRELIMINARY
5.1.10 Bank1.Reg2 - Version ID Regiister I (VID)
Power on default <7:0> = 0001,0000 binary
Bit
7-0
Name
VID
Read/Write
Read Only
Description
Version ID, default is set to 0x10.
5.1.11 Bank0~3.Reg3 - CIR Control Register 0/Bank Select Register (CTR0/BSR) (BANK0~3)
This register is defined same as in Bank0.Reg3.
5.1.12 Bank1.Reg4 - Timer Low Byte Register (TMRL)
Power on default <7:0> = 0000,0000 binary
Bit
7-0
Name
TMRL
Read/Write
Description
Read/Write
Timer Low Byte Register. This is a 12-bit timer (another 4bit is defined in Bank1.Reg5) which resolution is 1 ms, that
12
is, the programmed maximum time is 2 -1 ms. The timer
is a down-counter. The timer start down count when the bit
EN_TMR (Enable Timer) of Bank0.Reg2. is set to 1. When
the timer down count to zero and EN_TMR=1, the TMR_I
is set to 1. When the counter down count to zero, a new
initial value will be re-loaded into timer counter.
5.1.13 Bank1.Reg5 - Timer High Byte Register (TMRH)
Power on default <7:0> = 0000,0000 binary
Bit
7-4
3-0
Name
Reserved
TMRH
Read/Write
Read/Write
Description
Reserved.
Timer High Byte Register. See Bank1.Reg4.
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PRELIMINARY
6. PARALLEL PORT
6.1 Printer Interface Logic
The parallel port of the W83627HF makes possible the attachment of various devices that accept eight
bits of parallel data at standard TTL level. The W83627HF supports an IBM XT/AT compatible parallel
port (SPP), bi-directional parallel port (BPP), Enhanced Parallel Port (EPP), Extended Capabilities
Parallel Port (ECP), Extension FDD mode (EXTFDD), Extension 2FDD mode (EXT2FDD) on the
parallel port. Refer to the configuration registers for more information on disabling, power-down, and on
selecting the mode of operation.
Table 6-1 shows the pin definitions for different modes of the parallel port.
TABLE 6-1-1 PARALLEL PORT CONNECTOR AND PIN DEFINITIONS
HOST
CONNECTOR
PIN NUMBER
OF W83627HF
PIN
ATTRIBUTE
SPP
EPP
ECP
1
36
O
nSTB
nWrite
2-9
31-26, 24-23
I/O
PD<0:7>
PD<0:7>
10
22
I
nACK
Intr
nACK, PeriphClk2
11
21
I
BUSY
nWait
BUSY, PeriphAck2
12
19
I
PE
PE
13
18
I
SLCT
Select
SLCT, Xflag2
14
35
O
nAFD
nDStrb
nAFD, HostAck2
15
34
I
nERR
nError
nFault1, nPeriphRequest2
16
33
O
nINIT
nInit
17
32
O
nSLIN
nAStrb
nSTB, HostClk 2
PD<0:7>
PEerror, nAckReverse2
nINIT1, nReverseRqst2
nSLIN1 , ECPMode2
Notes:
n<name > : Active Low
1. Compatible Mode
2. High Speed Mode
3. For more information, refer to the IEEE 1284 standard.
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PRELIMINARY
TABLE 6-1-2 PARALLEL PORT CONNECTOR AND PIN DEFINITIONS
HOST
CONNECTOR
PIN NUMBER OF
W83627HF
PIN
ATTRIBUTE
SPP
PIN
ATTRIBUTE
EXT2FDD
PIN
ATTRIBUTE
EXTFDD
1
36
O
nSTB
---
---
---
---
2
31
I/O
PD0
I
INDEX2#
I
INDEX2#
3
30
I/O
PD1
I
TRAK02#
I
TRAK02#
4
29
I/O
PD2
I
WP2#
I
WP2#
5
28
I/O
PD3
I
RDATA2#
I
RDATA2#
6
27
I/O
PD4
I
DSKCHG2#
I
DSKCHG2#
7
26
I/O
PD5
---
---
---
---
8
24
I/O
PD6
OD
MOA2#
---
---
9
23
I/O
PD7
OD
DSA2#
---
---
10
22
I
nACK
OD
DSB2#
OD
DSB2#
11
21
I
BUSY
OD
MOB2#
OD
MOB2#
12
19
I
PE
OD
WD2#
OD
WD2#
13
18
I
SLCT
OD
WE2#
OD
WE2#
14
35
O
nAFD
OD
RWC2#
OD
RWC2#
15
34
I
nERR
OD
HEAD2#
OD
HEAD2#
16
33
O
nINIT
OD
DIR2#
OD
DIR2#
17
32
O
nSLIN
OD
STEP2#
OD
STEP2#
6.2 Enhanced Parallel Port (EPP)
TABLE 6-2 PRINTER MODE AND EPP REGISTER ADDRESS
A2
0
0
0
0
0
1
1
1
1
A1
0
0
1
1
1
0
0
1
1
A0
0
1
0
0
1
0
1
0
1
REGISTER
Data port (R/W)
Printer status buffer (Read)
Printer control latch (Write)
Printer control swapper (Read)
EPP address port (R/W)
EPP data port 0 (R/W)
EPP data port 1 (R/W)
EPP data port 2 (R/W)
EPP data port 2 (R/W)
NOTE
1
1
1
1
2
2
2
2
2
Notes:
1. These registers are available in all modes.
2. These registers are available only in EPP mode.
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6.2.1 Data Swapper
The system microprocessor can read the contents of the printer's data latch by reading the data
swapper.
6.2.2 Printer Status Buffer
The system microprocessor can read the printer status by reading the address of the printer status
buffer. The bit definitions are as follows:
7
6
5
4
3
2
1
1
1
0
TMOUT
ERROR
SLCT
PE
ACK
BUSY
Bit 7: This signal is active during data entry, when the printer is off-line during printing, when the print
head is changing position, or during an error state. When this signal is active, the printer is busy
and cannot accept data.
Bit 6: This bit represents the current state of the printer's ACK# signal. A 0 means the printer has
received a character and is ready to accept another. Normally, this signal will be active for
approximately 5 microseconds before BUSY# stops.
Bit 5: Logical 1 means the printer has detected the end of paper.
Bit 4: Logical 1 means the printer is selected.
Bit 3: Logical 0 means the printer has encountered an error condition.
Bit 1, 2: These two bits are not implemented and are logic one during a read of the status register.
Bit 0: This bit is valid in EPP mode only. It indicates that a 10 µS time-out has occurred on the EPP bus.
A logic 0 means that no time-out error has occurred; a logic 1 means that a time-out error has
been detected. Writing a logic 1 to this bit will clear the time-out status bit; writing a logic 0 has no
effect.
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6.2.3 Printer Control Latch and Printer Control Swapper
The system microprocessor can read the contents of the printer control latch by reading the printer
control swapper. Bit definitions are as follows:
7
6
1
1
5
4
3
2
1
0
STROBE
AUTO FD
INIT
SLCT IN
IRQ ENABLE
DIR
Bit 7, 6: These two bits are a logic one during a read. They can be written.
Bit 5: Direction control bit
When this bit is a logic 1, the parallel port is in input mode (read); when it is a logic 0, the parallel
port is in output mode (write). This bit can be read and written. In SPP mode, this bit is invalid
and fixed at zero.
Bit 4: A 1 in this position allows an interrupt to occur when ACK# changes from low to high.
Bit 3: A 1 in this bit position selects the printer.
Bit 2: A 0 starts the printer (50 microsecond pulse, minimum).
Bit 1: A 1 causes the printer to line-feed after a line is printed.
Bit 0: A 0.5 microsecond minimum high active pulse clocks data into the printer. Valid data must be
present for a minimum of 0.5 microseconds before and after the strobe pulse.
6.2.4 EPP Address Port
The address port is available only in EPP mode. Bit definitions are as follows:
7
6
5
4
3
2
1
0
PD0
PD1
PD2
PD3
PD4
PD5
PD6
PD7
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The contents of DB0-DB7 are buffered (non-inverting) and output to ports PD0-PD7 during a write
operation. The leading edge of IOW# c auses an EPP address write cycle to be performed, and the
trailing edge of IOW# latches the data for the duration of the EPP write cycle.
PD0-PD7 ports are read during a read operation. The leading edge of IOR# causes an EPP address
read cycle to be performed and the data to be output to the host CPU.
6.2.5 EPP Data Port 0-3
These four registers are available only in EPP mode. Bit definitions of each data port are as follows:
7
6
5
4
3
2
1
0
PD0
PD1
PD2
PD3
PD4
PD5
PD6
PD7
When accesses are made to any EPP data port, the contents of DB0-DB7 are buffered (non-inverting)
and output to the ports PD0-PD7 during a write operation. The leading edge of IOW# causes an EPP
data write cycle to be performed, and the trailing edge of IOW# latches the data for the duration of the
EPP write cycle.
During a read operation, ports PD0-PD7 are read, and the leading edge of IOR# causes an EPP read
cycle to be performed and the data to be output to the host CPU.
6.2.6 Bit Map of Parallel Port and EPP Registers
REGISTER
7
6
5
4
3
2
1
0
PD7
PD6
PD
5
PD4
PD3
PD2
PD1
PD0
BUSY#
ACK#
PE
SLCT
ERROF#
1
1
TMOUT
Control Swapper (Read)
1
1
1
IRQEN
SLIN
INIT#
AUTOFD#
STROBE
#
Control Latch (Write)
1
1
DIR
IRQ
SLIN
INIT#
AUTOFD#
STROBE
#
EPP Address Port R/W)
PD7
PD6
PD
5
PD4
PD3
PD2
PD1
PD0
EPP Data Port 0 (R/W)
PD7
PD6
PD
5
PD4
PD3
PD2
PD1
PD0
EPP Data Port 1 (R/W)
PD7
PD6
PD
5
PD4
PD3
PD2
PD1
PD0
Data Port (R/W)
Status Buffer (Read)
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EPP Data Port 2 (R/W)
PD7
PD6
PD
5
PD4
PD3
PD2
PD1
PD0
EPP Data Port 3 (R/W)
PD7
PD6
PD
5
PD4
PD3
PD2
PD1
PD0
6.2.7 EPP Pin Descriptions
EPP NAME
nWrite
PD<0:7>
TYPE
O
I/O
Intr
nWait
I
I
PE
Select
I
I
nDStrb
nError
nInits
O
I
O
nAStrb
O
EPP DESCRIPTION
Denotes an address or data read or write operation.
Bi-directional EPP address and data bus.
Used by peripheral device to interrupt the host.
Inactive to acknowledge that data transfer is completed. Active to indicate
that the device is ready for the next transfer.
Paper end; same as SPP mode.
Printer selected status; same as SPP mode.
This signal is active low. It denotes a data read or write operation.
Error; same as SPP mode.
This signal is active low. When it is active, the EPP device is reset to its
initial operating mode.
This signal is active low. It denotes an address read or write operation.
6.2.8 EPP Operation
When the EPP mode is selected in the configuration register, the standard and bi-directional modes are
also available. The PDx bus is in the standard or bi-directional mode when no EPP read, write, or
address cycle is currently being executed. In this condition all output signals are set by the SPP Control
Port and the direction is controlled by DIR of the Control Port.
A watchdog timer is required to prevent system lockup. The timer indicates that more than 10 µS have
elapsed from the start of the EPP cycle to the time WAIT# is deasserted. The current EPP cycle is
aborted when a time-out occurs. The time-out condition is indicated in Status bit 0.
6.2.8.1 EPP Operation
The EPP operates on a two-phase cycle. First, the host selects the register within the device for
subsequent operations. Second, the host performs a series of read and/or write byte operations to the
selected register. Four operations are supported on the EPP: Address Write, Data Write, Address Read,
and Data Read. All operations on the EPP device are performed asynchronously.
6.2.8.2 EPP Version 1.9 Operation
The EPP read/write operation can be completed under the following conditions:
a. If the nWait is active low, when the read cycle (nWrite inactive high, nDStrb/nAStrb active low) or write
cycle (nWrite active low, nDStrb/nAStrb active low) starts, the read/write cycle proceeds normally and
will be completed when nWait goes inactive high.
b. If nWait is inactive high, the read/write cycle will not start. It must wait until nWait changes to active
low, at which time it will start as described above.
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6.2.8.3 EPP Version 1.7 Operation
The EPP read/write cycle can start without checking whether nWait is active or inactive. Once the
read/write cycle starts, however, it will not terminate until nWait changes from active low to inactive high.
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6.3 Extended Capabilities Parallel (ECP) Port
This port is software and hardware compatible with existing parallel ports, so it may be used as a
standard printer mode if ECP is not required. It provides an automatic high burst-bandwidth channel that
supports DMA for ECP in both the forward (host to peripheral) and reverse (peripheral to host)
directions.
Small FIFOs are used in both forward and reverse directions to improve the maximum bandwidth
requirement. The size of the FIFO is 16 bytes. The ECP port supports an automatic handshake for the
standard parallel port to improve compatibility mode transfer speed.
The ECP port supports run-length-encoded (RLE) decompression (required) in hardware. Compression
is accomplished by counting identical bytes and transmitting an RLE byte that indicates how many times
the next byte is to be repeated. Hardware support for compression is optional.
For more information about the ECP Protocol, refer to the Extended Capabilities Port Protocol and ISA
Interface Standard.
6.3.1 ECP Register and Mode Definitions
NAME
ADDRESS
I/O
ECP MODES
FUNCTION
data
ecpAFifo
Base+000h
Base+000h
R/W
R/W
000-001
011
dsr
dcr
cFifo
Base+001h
Base+002h
Base+400h
R
R/W
R/W
All
All
010
Status Register
Control Register
Parallel Port Data FIFO
ecpDFifo
tFifo
cnfgA
Base+400h
Base+400h
Base+400h
R/W
R/W
R
011
110
111
ECP FIFO (DATA)
Test FIFO
Configuration Register A
cnfgB
ecr
Base+401h
Base+402h
R/W
R/W
111
All
Configuration Register B
Extended Control Register
Data Register
ECP FIFO (Address)
Note: The base addresses are specified by CR23, which are determined by configuration register or hardware setting.
MODE
DESCRIPTION
000
001
010
SPP mode
PS/2 Parallel Port mode
Parallel Port Data FIFO mode
011
100
101
ECP Parallel Port mode
EPP mode (If this option is enabled in the CR9 and CR0 to select ECP/EPP mode)
Reserved
110
111
Test mode
Configuration mode
Note: The mode selection bits are bit 7-5 of the Extended Control Register.
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6.3.2 Data and ecpAFifo Port
Modes 000 (SPP) and 001 (PS/2) (Data Port)
During a write operation, the Data Register latches the contents of the data bus on the rising edge of the
input. The contents of this register are output to the PD0-PD7 ports. During a read operation, ports PD0PD7 are read and output to the host. The bit definitions are as follows:
7
6
5
4
3
2
1
0
PD0
PD1
PD2
PD3
PD4
PD5
PD6
PD7
Mode 011 (ECP FIFO-Address/RLE)
A data byte written to this address is placed in the FIFO and tagged as an ECP Address/RLE. The
hardware at the ECP port transmits this byte to the peripheral automatically. The operation of this
register is defined only for the forward direction. The bit definitions are as follows:
7
6
5
4
3
2
1
0
Address or RLE
Address/RLE
6.3.3 Device Status Register (DSR)
These bits are at low level during a read of the Printer Status Register. The bits of this status register are
defined as follows:
7
6
5
4
3
2
1
1
1
0
1
nFault
Select
PError
nAck
nBusy
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Bit 7: This bit reflects the complement of the Busy input.
Bit 6: This bit reflects the nAck input.
Bit 5: This bit reflects the PError input.
Bit 4: This bit reflects the Select input.
Bit 3: This bit reflects the nFault input.
Bit 2-0: These three bits are not implemented and are always logic one during a read.
6.3.4 Device Control Register (DCR)
The bit definitions are as follows:
7
1
6
5
4
3
2
1
0
1
strobe
autofd
nInit
SelectIn
ackIntEn
Direction
Bit 6, 7: These two bits are logic one during a read and cannot be written.
Bit 5: This bit has no effect and the direction is always out if mode = 000 or mode = 010. Direction is
valid in all other modes.
0
the parallel port is in output mode.
1
the parallel port is in input mode.
Bit 4: Interrupt request enable. When this bit is set to a high level, it may be used to enable interrupt
requests from the parallel port to the CPU due to a low to high transition on the ACK# input.
Bit 3: This bit is inverted and output to the SLIN# output.
0
The printer is not selected.
1
The printer is selected.
Bit 2: This bit is output to the INIT# output.
Bit 1: This bit is inverted and output to the AFD# output.
Bit 0: This bit is inverted and output to the STB# output.
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6.3.5 cFifo (Parallel Port Data FIFO) Mode = 010
This mode is defined only for the forward direction. The standard parallel port protocol is used by a
hardware handshake to the peripheral to transmit bytes written or DMAed from the system to this FIFO.
Transfers to the FIFO are byte aligned.
6.3.6 ecpDFifo (ECP Data FIFO) Mode = 011
When the direction bit is 0, bytes written or DMAed from the system to this FIFO are transmitted by a
hardware handshake to the peripheral using the ECP parallel port protocol. Transfers to the FIFO are
byte aligned.
When the direction bit is 1, data bytes from the peripheral are read under automatic hardware
handshake from ECP into this FIFO. Reads or DMAs from the FIFO will return bytes of ECP data to the
system.
6.3.7 tFifo (Test FIFO Mode) Mode = 110
Data bytes may be read, written, or DMAed to or from the system to this FIFO in any direction. Data in
the tFIFO will not be transmitted to the parallel port lines. However, data in the tFIFO may be displayed
on the parallel port data lines.
6.3.8 cnfgA (Configuration Register A) Mode = 111
This register is a read-only register. When it is read, 10H is returned. This indicates to the system that
this is an 8-bit implementation.
6.3.9
cnfgB (Configuration Register B) Mode = 111
The bit definitions are as follows:
7
6
5
4
3
2
1
0
1
1
1
IRQx 0
IRQx 1
IRQx 2
intrValue
compress
Bit 7: This bit is read-only. It is at low level during a read. This means that this chip does not support
hardware RLE compression.
Bit 6: Returns the value on the ISA IRQ line to determine possible conflicts.
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Bit 5-3: Reflect the IRQ resource assigned for ECP port.
cnfgB[5:3]
IRQ resource
000
reflect other IRQ resources selected by PnP register (default)
001
IRQ7
010
IRQ9
011
IRQ10
100
IRQ11
101
IRQ14
110
IRQ15
111
IRQ5
Bit 2-0: These five bits are at high level during a read and can be written.
6.3.10 ecr (Extended Control Register) Mode = all
This register controls the extended ECP parallel port functions. The bit definitions are follows:
7
6
5
4
3
2
1
0
empty
full
service Intr
dmaEn
nErrIntrEn
MODE
MODE
MODE
Bit 7-5: These bits are read/write and select the mode.
000
001
010
011
100
101
110
111
Standard Parallel Port mode. The FIFO is reset in this mode.
PS/2 Parallel Port mode. This is the same as 000 except that direction may be used
to tri-state the data lines and reading the data register returns the value on the data
lines and not the value in the data register.
Parallel Port FIFO mode. This is the same as 000 except that bytes are written or
DMAed to the FIFO. FIFO data are automatically transmitted using the standard
parallel port protocol. This mode is useful only when direction is 0.
ECP Parallel Port Mode. When the direction is 0 (forward direction), bytes placed into
the ecpDFifo and bytes written to the ecpAFifo are placed in a single FIFO and auto
transmitted to the peripheral using ECP Protocol. When the direction is 1 (reverse
direction), bytes are moved from the ECP parallel port and packed into bytes in the
ecpDFifo.
Selects EPP Mode. In this mode, EPP is activated if the EPP mode is selected.
Reserved.
Test Mode. The FIFO may be written and read in this mode, but the data will not be
transmitted on the parallel port.
Configuration Mode. The confgA and confgB registers are accessible at 0x400 and
0x401 in this mode.
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Bit 4: Read/Write (Valid only in ECP Mode)
1
Disables the interrupt generated on the asserting edge of nFault.
0
Enables an interrupt pulse on the high to low edge of nFault. If nFault is asserted
(interrupt) an interrupt will be generated and this bit is written from a 1 to 0.
Bit 3: Read/Write
1
Enables DMA.
0
Disables DMA unconditionally.
Bit 2: Read/Write
1
Disables DMA and all of the service interrupts.
0
Enables one of the following cases of interrupts. When one of the service interrupts
has occurred, the serviceIntr bit is set to a 1 by hardware. This bit must be reset to 0
to re-enable the interrupts. Writing a 1 to this bit will not cause an interrupt.
(a) dmaEn = 1: During DMA this bit is set to a 1 when terminal count is reached.
(b) dmaEn = 0 direction = 0: This bit is set to 1 whenever there are writeIntr
Threshold or more bytes free in the FIFO.
(c) dmaEn = 0 direction = 1: This bit is set to 1 whenever there are readIntr
Threshold or more valid bytes to be read from the FIFO.
Bit 1: Read only
0
The FIFO has at least 1 free byte.
1
The FIFO cannot accept another byte or the FIFO is completely full.
Bit 0: Read only
0
The FIFO contains at least 1 byte of data.
1
The FIFO is completely empty.
6.3.11 Bit Map of ECP Port Registers
data
ecpAFifo
dsr
dcr
cFifo
ecpDFifo
tFifo
cnfgA
cnfgB
ecr
D7
D6
D5
D4
D3
D2
D1
D0
PD7
PD6
PD5
PD4
PD3
PD2
PD1
PD0
Addr/RLE
Address or RLE field
NOTE
2
nBusy
nAck
PError
Select
nFault
1
1
1
1
1
1
Directio
ackIntEn
SelectIn
nInit
autofd
strobe
1
Parallel Port Data FIFO
2
ECP Data FIFO
2
Test FIFO
2
0
compress
0
0
intrValue
1
MODE
1
0
0
0
0
1
1
1
1
1
nErrIntrEn
dmaEn
serviceIntr
full
empty
Notes:
1. These registers are available in all modes.
2. All FIFOs use one common 16-byte FIFO.
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PRELIMINARY
6.3.12 ECP Pin Descriptions
NAME
TYPE
DESCRIPTION
nStrobe (HostClk)
O
The nStrobe registers data or address into the slave on the
asserting edge during write operations. This signal handshakes
with Busy.
PD<7:0>
I/O
These signals contains address or data or RLE data.
nAck (PeriphClk)
I
This signal indicates valid data driven by the peripheral when
asserted. This signal handshakes with nAutoFd in reverse.
Busy (PeriphAck)
I
This signal deasserts to indicate that the peripheral can accept
data. It indicates whether the data lines contain ECP command
information or data in the reverse direction. When in reverse
direction, normal data are transferred when Busy (PeriphAck) is
high and an 8-bit command is transferred when it is low.
PError (nAckReverse)
I
This signal is used to acknowledge a change in the direction of
the transfer (asserted = forward). The peripheral drives this
signal low to acknowledge nReverseRequest. The host relies
upon nAckReverse to determine when it is permitted to drive the
data bus.
Select (Xflag)
I
Indicates printer on line.
nAutoFd (HostAck)
O
Requests a byte of data from the peripheral when it is asserted.
This signal indicates whether the data lines contain ECP address
or data in the forward direction. When in forward direction,
normal data are transferred when nAutoFd (HostAck) is high and
an 8-bit command is transferred when it is low.
nFault (nPeriphRequest)
I
Generates an error interrupt when it is asserted. This signal is
valid only in the forward direction. The peripheral is permitted
(but not required) to drive this pin low to request a reverse
transfer during ECP Mode.
nInit (nReverseRequest)
O
This signal sets the transfer direction (asserted = reverse,
deasserted = forward). This pin is driven low to place the
channel in the reverse direction.
nSelectIn (ECPMode)
O
This signal is always deasserted in ECP mode.
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PRELIMINARY
6.3.13 ECP Operation
The host must negotiate on the parallel port to determine if the peripheral supports the ECP protocol
before ECP operation. After negotiation, it is necessary to initialize some of the port bits. The following
are required:
(a) Set direction = 0, enabling the drivers.
(b) Set strobe = 0, causing the nStrobe signal to default to the deasserted state.
(c) Set autoFd = 0, causing the nAutoFd signal to default to the deasserted state.
(d) Set mode = 011 (ECP Mode)
ECP address/RLE bytes or data bytes may be sent automatically by writing the ecpAFifo or ecpDFifo,
respectively.
6.3.13.1 Mode Switching
Software will execute P1284 negotiation and all operation prior to a data transfer phase under
programmed I/O control (mode 000 or 001). Hardware provides an automatic control line handshake,
moving data between the FIFO and the ECP port only in the data transfer phase (mode 011 or 010).
If the port is in mode 000 or 001 it may switch to any other mode. If the port is not in mode 000 or 001 it
can only be switched into mode 000 or 001. The direction can be changed only in mode 001.
When in extended forward mode, the software should wait for the FIFO to be empty before switching
back to mode 000 or 001. In ECP reverse mode the software waits for all the data to be read from the
FIFO before changing back to mode 000 or 001.
6.3.13.2 Command/Data
ECP mode allows the transfer of normal 8-bit data or 8-bit commands. In the forward direction, normal
data are transferred when HostAck is high and an 8-bit command is transferred when HostAck is low.
The most significant bits of the command indicate whether it is a run-length count (for compression) or a
channel address.
In the reverse direction, normal data are transferred when PeriphAck is high and an 8-bit command is
transferred when PeriphAck is low. The most significant bit of the command is always zero.
6.3.13.3 Data Compression
The W83627HF supports run length encoded (RLE) decompression in hardware and can transfer
compressed data to a peripheral. Note that the odd (RLE) compression in hardware is not supported. In
order to transfer data in ECP mode, the compression count is written to the ecpAFifo and the data byte
is written to the ecpDFifo.
6.3.14 FIFO Operation
The FIFO threshold is set in configuration register 5. All data transfers to or from the parallel port can
proceed in DMA or Programmed I/O (non-DMA) mode, as indicated by the selected mode. The FIFO is
used by selecting the Parallel Port FIFO mode or ECP Parallel Port Mode. After a reset, the FIFO is
disabled.
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6.3.15 DMA Transfers
DMA transfers are always to or from the ecpDFifo, tFifo, or CFifo. The DMA uses the standard PC DMA
services. The ECP requests DMA transfers from the host by activating the PDRQ pin. The DMA will
empty or fill the FIFO using the appropriate direction and mode. When the terminal count in the DMA
controller is reached, an interrupt is generated and serviceIntr is asserted, which will disable the DMA.
6.3.16 Programmed I/O (NON-DMA) Mode
The ECP or parallel port FIFOs can also be operated using interrupt driven programmed I/O.
Programmed I/O transfers are to the ecpDFifo at 400H and ecpAFifo at 000H or from the ecpDFifo
located at 400H, or to/from the tFifo at 400H. The host must set the direction, state, dmaEn = 0 and
serviceIntr = 0 in the programmed I/O transfers.
The ECP requests programmed I/O transfers from the host by activating the IRQ pin. The programmed
I/O will empty or fill the FIFO using the appropriate direction and mode.
6.4 Extension FDD Mode (EXTFDD)
In this mode, the W83627HF changes the printer interface pins to FDC input/output pins, allowing the
user to install a second floppy disk drive (FDD B) through the DB-25 printer connector. The pin
assignments for the FDC input/output pins are shown in Table 6-1.
After the printer interface is set to EXTFDD mode, the following occur:
(1) Pins MOB# and DSB# will be forced to inactive state.
(2) Pins DSKCHG#, RDATA#, WP#, TRAK0#, INDEX# will be logically ORed with pins PD4-PD0 to
serve as input signals to the FDC.
(3) Pins PD4-PD0 each will have an internal resistor of about 1K ohm to serve as pull-up resistor for
FDD open drain/collector output.
(4) If the parallel port is set to EXTFDD mode after the system has booted DOS or another operating
system, a warm reset is needed to enable the system to recognize the extension floppy drive.
6.5 Extension 2FDD Mode (EXT2FDD)
In this mode, the W83627HF changes the printer interface pins to FDC input/output pins, allowing the
user to install two external floppy disk drives through the DB-25 printer connector to replace internal
floppy disk drives A and B. The pin assignments for the FDC input/output pins are shown in Table6-1.
After the printer interface is set to EXTFDD mode, the following occur:
(1) Pins MOA#, DSA#, MOB#, and DSB# will be forced to inactive state.
(2) Pins DSKCHG#, RDATA#, WP#, TRAK0#, and INDEX# will be logically ORed with pins PD4-PD0 to
serve as input signals to the FDC.
(3) Pins PD4-PD0 each will have an internal resistor of about 1K ohm to serve as pull-up resistor for
FDD open drain/collector output.
(4) If the parallel port is set to EXT2FDD mode after the system has booted DOS or another operating
system, a warm reset is needed to enable the system to recognize the extension floppy drive.
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PRELIMINARY
7. KEYBOARD CONTROLLER
The KBC (8042 with licensed KB BIOS) circuit of W83627HF is designed to provide the functions
needed to interface a CPU with a keyboard and/or a PS/2 mouse, and can be used with IBMcompatible personal computers or PS/2-based systems. The controller receives serial data from the
keyboard or PS/2 mouse, checks the parity of the data, and presents the data to the system as a byte of
data in its output buffer. Then, The controller will asserts an interrupt to the system when data are
placed in its output buffer. The keyboard and PS/2 mouse are required to acknowledge all data
transmissions. No transmission should be sent to the keyboard or PS/2 mouse until an acknowledge is
received for the previous data byte.
KINH
P17
8042
P24
KIRQ
P25
MIRQ
P21
GATEA20
P20
KBRST
P27
KDAT
P10
P26
KCLK
T0
GP I/O PINS
Multiplex I/O PINS
P12~P16
P23
MCLK
T1
P22
MDAT
P11
Keyboard and Mouse Interface
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7.1 Output Buffer
The output buffer is an 8-bit read-only register at I/O address 60H (Default, PnP programmable I/O
address LD5-CR60 and LD5-CR61). The keyboard controller uses the output buffer to send the scan
code received from the keyboard and data bytes required by commands to the system. The output
buffer can only be read when the output buffer full bit in the register is "1".
7.2 Input Buffer
The input buffer is an 8-bit write-only register at I/O address 60H or 64H (Default, PnP programmable
I/O address LD5-CR60, LD5-CR61, LD5-CR62, and LD5-CR63). Writing to address 60H sets a flag to
indicate a data write; writing to address 64H sets a flag to indicate a command write. Data written to I/O
address 60H is sent to keyboard (unless the keyboard controller is expecting a data byte) through the
controller's input buffer only if the input buffer full bit in the status register is “0”.
7.3 Status Register
The status register is an 8-bit read-only register at I/O address 64H (Default, PnP programmable I/O
address LD5-CR62 and LD5-CR63), that holds information about the status of the keyboard controller
and interface. It may be read at any time.
BIT
BIT FUNCTION
DESCRIPTION
0
Output Buffer Full
0: Output buffer empty
1: Output buffer full
0: Input buffer empty
1: Input buffer full
This bit may be set to 0 or 1 by writing to the system flag bit
in the command byte of the keyboard controller. It defaults
to 0 after a power-on reset.
1
Input Buffer Full
2
System Flag
3
Command/Data
0: Data byte
1: Command byte
4
Inhibit Switch
0: Keyboard is inhibited
1: Keyboard is not inhibited
5
Auxiliary Device Output
Buffer
0: Auxiliary device output buffer empty
1: Auxiliary device output buffer full
6
General Purpose Timeout
0: No time-out error
1: Time-out error
7
Parity Error
0: Odd parity
1: Even parity (error)
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PRELIMINARY
7.4 Commands
COMMAND
FUNCTION
20h
Read Command Byte of Keyboard Controller
60h
Write Command Byte of Keyboard Controller
BIT DEFINITION
BIT
A4h
7
Reserved
6
IBM Keyboard Translate Mode
5
Disable Auxiliary Device
4
Disable Keyboard
3
Reserve
2
System Flag
1
Enable Auxiliary Interrupt
0
Enable Keyboard Interrupt
Test Password
Returns 0Fah if Password is loaded
Returns 0F1h if Password is not loaded
A5h
Load Password
Load Password until a "0" is received from the system
A6h
Enable Password
Enable the checking of keystrokes for a match with the password
A7h
Disable Auxiliary Device Interface
A8h
Enable Auxiliary Device Interface
A9h
Interface Test
BIT
BIT DEFINITION
00
No Error Detected
01
Auxiliary Device "Clock" line is stuck low
02
Auxiliary Device "Clock" line is stuck high
03
Auxiliary Device "Data" line is stuck low
04
Auxiliary Device "Data" line is stuck low
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PRELIMINARY
7.4 Commands, continued
COMMAND
AAh
FUNCTION
Self-test
Returns 055h if self test succeeds
ABh
Interface Test
BIT
BIT DEFINITION
00
No Error Detected
01
Keyboard "Clock" line is stuck low
02
Keyboard "Clock" line is stuck high
03
Keyboard "Data" line is stuck low
04
Keyboard "Data" line is stuck high
ADh
Disable Keyboard Interface
AEh
Enable Keyboard Interface
C0h
Read Input Port(P1) and send data to the system
C1h
Continuously puts the lower four bits of Port1 into STATUS register
C2h
Continuously puts the upper four bits of Port1 into STATUS register
D0h
Send Port2 value to the system
D1h
Only set/reset GateA20 line based on the system data bit 1
D2h
Send data back to the system as if it came from Keyboard
D3h
Send data back to the system as if it came from Auxiliary Device
D4h
Output next received byte of data from system to Auxiliary Device
E0h
Reports the status of the test inputs
FXh
Pulse only RC(the reset line) low for 6µS if Command byte is even
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PRELIMINARY
7.5 HARDWARE GATEA20/KEYBOARD RESET CONTROL LOGIC
The KBC implements a hardware control logic to speed-up GATEA20 and KBRESET. This control logic
is controlled by LD5-CRF0 as follows:
7.5.1 KB Control Register (Logic Device 5, CR-F0)
BIT
7
6
NAME
KCLKS1
KCLKS0
5
4
3
Reserved Reserved Reserved
2
1
0
P92EN
HGA20
HKBRST
KCLKS1, KCLKS0
This 2 bits are for the KBC clock rate selection.
=00
KBC clock input is 6 Mhz
=01
KBC clock input is 8 Mhz
=10
KBC clock input is 12 Mhz
=11
KBC clock input is 16 Mhz
P92EN (Port 92 Enable)
A "1" on this bit enables Port 92 to control GATEA20 and KBRESET.
A "0" on this bit disables Port 92 functions.
HGA20 (Hardware GATE A20)
A "1" on this bit selects hardware GATEA20 control logic to control GATE A20 signal.
A "0" on this bit disables hardware GATEA20 control logic function.
HKBRST (Hardware Keyboard Reset)
A "1" on this bit selects hardware KB RESET control logic to control KBRESET signal.
A "0" on this bit disable hardware KB RESET control logic function.
When the KBC receives a data follows a "D1" command, the hardware control logic sets or clears
GATE A20 according to the received data bit 1. Similarly, the hardware control logic sets or clears
KBRESET depending on the received data bit 0. When the KBC receives a "FE" command, the
KBRESET is pulse low for 6µS(Min.) with 14µS(Min.) delay.
GATEA20 and KBRESET are controlled by either the software control or the hardware control logic and
they are mutually exclusive. Then, GATEA20 and KBRESET are merged along with Port92 when
P92EN bit is set.
7.5.2 Port 92 Control Register (Default Value = 0x24)
BIT
7
6
5
4
3
2
1
0
NAME
Res. (0)
Res. (0)
Res. (1)
Res. (0)
Res. (0)
Res. (1)
SGA20
PLKBRST
SGA20 (Special GATE A20 Control)
A "1" on this bit drives GATE A20 signal to high.
A "0" on this bit drives GATE A20 signal to low.
PLKBRST (Pull-Low KBRESET)
A "1" on this bit causes KBRESET to drive low for 6µS(Min.) with 14µS(Min.) delay. Before issuing
another keyboard reset command, the bit must be cleared.
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PRELIMINARY
8. GENERAL PURPOSE I/O
W83627HF provides 24 input/output ports that can be individually configured to perform a simple basic
I/O function or a pre-defined alternate function. Those 24 GP I/O ports are divided into three groups,
each group contains 8 ports. The first group is configured through control registers in logical device 7,
the second group in logical device 8, and the third group in logical device 9. Users can configure each
individual port to be an input or output port by programming respective bit in selection register (CRF0: 0
= output, 1 = input). Invert port value by setting inversion register (CRF2: 0 = non-inverse, 1 = inverse).
Port value is read/written through data register (CRF1). Table 8.1 and 8.2 gives more details on GPIO's
assignment. In addition, GPIO1 is designed to be functional even in power loss condition (VCC or VSB
is off). Figure 8.1 shows the GP I/O port's structure. Right after Power-on reset, those ports default to
perform basic input function except ports in GPIO1 which maintains its previous settings until a battery
loss condition.
Table 8.1
SELECTION
BIT
INVERSION BIT
0 = NON INVERSE
0 = OUTPUT
1 = INVERSE
BASIC I/O OPERATIONS
1 = INPUT
0
0
Basic non-inverting output
0
1
Basic inverting output
1
0
Basic non-inverting input
1
1
Basic inverting input
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PRELIMINARY
Table 8.2
GP I/O PORT DATA
REGISTER
GP1
GP2
GP3
REGISTER BIT
ASSIGNMENT
GP I/O PORT
BIT 0
GP10
BIT 1
GP11
BIT 2
GP12
BIT 3
GP13
BIT 4
GP14
BIT 5
GP15
BIT 6
GP16
BIT 7
GP17
BIT 0
GP20
BIT 1
GP21
BIT 2
GP22
BIT 3
GP23
BIT 4
GP24
BIT 5
GP25
BIT 6
GP26
BIT 7
GP27
BIT 0
GP30
BIT 1
GP31
BIT 2
GP32
BIT 3
GP33
BIT 4
GP34
BIT 5
GP35
BIT 6
GP36
BIT 7
GP37
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PRELIMINARY
Figure 8.1
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PRELIMINARY
9. PLUG AND PLAY CONFIGURATION
The W83627HF uses Compatible PNP protocol to access configuration registers for setting up different
types of configurations. In W83627HF, there are eleven Logical Devices (from Logical Device 0 to
Logical Device B with the exception of logical device 4 for backward compatibility) which correspond to
eleven individual functions: FDC (logical device 0), PRT (logical device 1), UART1 (logical device 2),
UART2 (logical device 3), KBC (logical device 5), CIR (Consumer IR, logical device 6), GPIO1 (logical
device 7), GPIO2 (logical device 8), GPIO3 (logical device 9), ACPI ((logical device A), and hardware
monitor (logical device B). Each Logical Device has its own configuration registers (above CR30). Host
can access those registers by writing an appropriate logical device number into logical device select
register at CR7.
9.1 Compatible PnP
9.1.1 Extended Function Registers
In Compatible PnP, there are two ways to enter Extended Function and read or write the configuration
registers. HEFRAS (CR26 bit 6) can be used to select one out of these two methods of entering the
Extended Function mode as follows:
HEFRAS
0
1
address and value
write 87h to the location 2Eh twice
write 87h to the location 4Eh twice
After Power-on reset, the value on RTSA# (pin 43) is latched by HEFRAS of CR26. In Compatible PnP,
a specific value (87h) must be written twice to the Extended Functions Enable Register (I/O port address
2Eh or 4Eh). Secondly, an index value (02h, 07h-FFh) must be written to the Extended Functions Index
Register (I/O port address 2Eh or 4Eh same as Extended Functions Enable Register) to identify which
configuration register is to be accessed. The designer can then access the desired configuration
register through the Extended Functions Data Register (I/O port address 2Fh or 4Fh).
After programming of the configuration register is finished, an additional value (AAh) should be written to
EFERs to exit the Extended Function mode to prevent unintentional access to those configuration
registers. The designer can also set bit 5 of CR26 (LOCKREG) to high to protect the configuration
registers against accidental accesses.
The configuration registers can be reset to their default or hardware settings only by a cold reset (pin
MR = 1). A warm reset will not affect the configuration registers.
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PRELIMINARY
9.1.2 Extended Functions Enable Registers (EFERs)
After a power-on reset, the W83627HF enters the default operating mode. Before the W83627HF
enters the extended function mode, a specific value must be programmed into the Extended Function
Enable Register (EFER) so that the extended function register can be accessed. The Extended
Function Enable Registers are write-only registers. On a PC/AT system, their port addresses are 2Eh or
4Eh (as described in previous section).
9.1.3 Extended Function Index Registers (EFIRs), Extended Function Data Registers(EFDRs)
After the extended function mode is entered, the Extended Function Index Register (EFIR) must be
loaded with an index value (02h, 07h-FEh) to access Configuration Register 0 (CR0), Configuration
Register 7 (CR07) to Configuration Register FE (CRFE), and so forth through the Extended Function
Data Register (EFDR). The EFIRs are write-only registers with port address 2Eh or 4Eh (as described in
section 12.2.1) on PC/AT systems; the EFDRs are read/write registers with port address 2Fh or 4Fh (as
described in section 9.2.1) on PC/AT systems.
9.2 Configuration Sequence
To program W83627HF configuration registers, the following configuration sequence must be followed:
(1). Enter the extended function mode
(2). Configure the configuration registers
(3). Exit the extended function mode
9.2.1 Enter the extended function mode
To place the chip into the extended function mode, two successive wrtites of 0x87 must be applied to
Extended Function Enable Registers(EFERs, i.e. 2Eh or 4Eh).
9.2.2 Configurate the configuration registers
The chip selects the logical device and activates the desired logical devices through Extended Function
Index Register(EFIR) and Extended Function Data Register(EFDR). EFIR is located at the same
address as EFER, and EFDR is located at address (EFIR+1).
First, write the Logical Device Number (i.e.,0x07) to the EFIR and then write the number of the desired
logical device to the EFDR. If accessing the Chip(Global) Control Registers, this step is not required.
Secondly, write the address of the desired configuration register within the logical device to the EFIR and
then write (or read) the desired configuration register through EFDR.
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PRELIMINARY
9.2.3 Exit the extended function mode
To exit the extended function mode, one write of 0xAA to EFER is required. Once the chip exits the
extended function mode, it is in the normal running mode and is ready to enter the configuration mode.
9.2.4 Software programming example
The following example is written in Intel 8086 assembly language. It assumes that the EFER is located
at 2Eh, so EFIR is located at 2Eh and EFDR is located at 2Fh. If HEFRAS (CR26 bit 6) is set, 4Eh can
be directly replaced by 4Eh and 2Fh replaced by 4Fh.
;----------------------------------------------------------------------------------; Enter the extended function mode ,interruptible double-write |
;----------------------------------------------------------------------------------MOV DX,2EH
MOV AL,87H
OUT DX,AL
OUT DX,AL
;----------------------------------------------------------------------------; Configurate logical device 1, configuration register CRF0 |
;----------------------------------------------------------------------------MOV DX,2EH
MOV AL,07H
OUT DX,AL
; point to Logical Device Number Reg.
MOV DX,2FH
MOV AL,01H
OUT DX,AL
; select logical device 1
;
MOV DX,2EH
MOV AL,F0H
OUT DX,AL
; select CRF0
MOV DX,2FH
MOV AL,3CH
OUT DX,AL
; update CRF0 with value 3CH
;-----------------------------------------; Exit extended function mode |
;-----------------------------------------MOV DX,2EH
MOV AL,AAH
OUT DX,AL
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Revision 0.50
W83627HF/F
PRELIMINARY
8.
GENERAL PURPOSE I/O
W83627HF provides 24 input/output ports that can be individually configured to perform a simple
basic I/O function or a pre-defined alternate function. Those 24 GP I/O ports are divided into three
groups, each group contains 8 ports. The first group is configured through control registers in logical
device 7, the second group in logical device 8, and the third group in logical device 9. Users can
configure each individual port to be an input or output port by programming respective bit in selection
register (CRF0: 0 = output, 1 = input). Invert port value by setting inversion register (CRF2: 0 = noninverse, 1 = inverse). Port value is read/written through data register (CRF1). Table 8.1 and 8.2
gives more details on GPIO's assignment. In addition, GPIO1 is designed to be functional even in
power loss condition (VCC or VSB is off). Figure 8.1 shows the GP I/O port's structure. Right after
Power-on reset, those ports default to perform basic input function except ports in GPIO1 which
maintains its previous settings until a battery loss condition.
Table 8.1
SELECTION
BIT
INVERSION BIT
0 = NON INVERSE
0 = OUTPUT
1 = INVERSE
BASIC I/O OPERATIONS
1 = INPUT
0
0
Basic non-inverting output
0
1
Basic inverting output
1
0
Basic non-inverting input
1
1
Basic inverting input
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PRELIMINARY
Table 8.2
GP I/O PORT DATA
REGISTER
GP1
GP2
GP3
REGISTER BIT
ASSIGNMENT
GP I/O PORT
BIT 0
GP10
BIT 1
GP11
BIT 2
GP12
BIT 3
GP13
BIT 4
GP14
BIT 5
GP15
BIT 6
GP16
BIT 7
GP17
BIT 0
GP20
BIT 1
GP21
BIT 2
GP22
BIT 3
GP23
BIT 4
GP24
BIT 5
GP25
BIT 6
GP26
BIT 7
GP27
BIT 0
GP30
BIT 1
GP31
BIT 2
GP32
BIT 3
GP33
BIT 4
GP34
BIT 5
GP35
BIT 6
GP36
BIT 7
GP37
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PRELIMINARY
Figure 8.1
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Publication Release Date: Jul 1999
Revision 0.53
W83627HF/F
PRELIMINARY
9. PLUG AND PLAY CONFIGURATION
The W83627HF uses Compatible PNP protocol to access configuration registers for setting up
different types of configurations. In W83627HF, there are eleven Logical Devices (from Logical
Device 0 to Logical Device B with the exception of logical device 4 for backward compatibility) which
correspond to eleven individual functions: FDC (logical device 0), PRT (logical device 1), UART1
(logical device 2), UART2 (logical device 3), KBC (logical device 5), CIR (Consumer IR, logical
device 6), GPIO1 (logical device 7), GPIO2 (logical device 8), GPIO3 (logical device 9), ACPI
((logical device A), and hardware monitor (logical device B). Each Logical Device has its own
configuration registers (above CR30). Host can access those registers by writing an appropriate
logical device number into logical device select register at CR7.
9.1
Compatible PnP
9.1.1
Extended Function Registers
In Compatible PnP, there are two ways to enter Extended Function and read or write the configuration
registers. HEFRAS (CR26 bit 6) can be used to select one out of these two methods of entering the
Extended Function mode as follows:
HEFRAS
address and value
0
write 87h to the location 3F0h twice
1
write 87h to the location 370h twice
After Power-on reset, the value on RTSA (pin 51) is latched by HEFRAS of CR26. In Compatible
PnP, a specific value (87h) must be written twice to the Extended Functions Enable Register (I/O port
address 3F0h or 370h). Secondly, an index value (02h, 07h-FFh) must be written to the Extended
Functions Index Register (I/O port address 3F0h or 370h same as Extended Functions Enable
Register) to identify which configuration register is to be accessed. The designer can then access the
desired configuration register through the Extended Functions Data Register (I/O port address 3F1h
or 371h).
After programming of the configuration register is finished, an additional value (AAh) should be
written to EFERs to exit the Extended Function mode to prevent unintentional access to those
configuration registers. The designer can also set bit 5 of CR26 (LOCKREG) to high to protect the
configuration registers against accidental accesses.
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Revision 0.53
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PRELIMINARY
The configuration registers can be reset to their default or hardware settings only by a cold reset (pin
MR = 1). A warm reset will not affect the configuration registers.
9.1.2
Extended Functions Enable Registers (EFERs)
After a power-on reset, the W83627HF enters the default operating mode. Before the W83627HF
enters the extended function mode, a specific value must be programmed into the Extended Function
Enable Register (EFER) so that the extended function register can be accessed. The Extended
Function Enable Registers are write-only registers. On a PC/AT system, their port addresses are
3F0h or 370h (as described in previous section).
9.1.3
Extended Function Index Registers (EFIRs), Extended Function Data Registers(EFDRs)
After the extended function mode is entered, the Extended Function Index Register (EFIR) must be
loaded with an index value (02h, 07h-FEh) to access Configuration Register 0 (CR0), Configuration
Register 7 (CR07) to Configuration Register FE (CRFE), and so forth through the Extended Function
Data Register (EFDR). The EFIRs are write-only registers with port address 2Eh or 4Eh (as described
in section 12.2.1) on PC/AT systems; the EFDRs are read/write registers with port address 2Fh or 4Fh
(as described in section 9.2.1) on PC/AT systems.
9.2 Configuration Sequence
To program W83627HF configuration registers, the following configuration sequence must be
followed:
(1) Enter the extended function mode
(2) Configure the configuration registers
(3) Exit the extended function mode
9.2.1 Enter the extended function mode
To place the chip into the extended function mode, two successive wrtites of 0x87 must be applied to
Extended Function Enable Registers(EFERs, i.e. 2Eh or 4Eh).
9.2.2 Configurate the configuration registers
The chip selects the logical device and activates the desired logical devices through Extended
Function Index Register(EFIR) and Extended Function Data Register(EFDR). EFIR is located at the
same address as EFER, and EFDR is located at address (EFIR+1).
First, write the Logical Device Number (i.e.,0x07) to the EFIR and then write the number of the
desired logical device to the EFDR. If accessing the Chip(Global) Control Registers, this step is not
required.
Secondly, write the address of the desired configuration register within the logical device to the EFIR
and then write (or read) the desired configuration register through EFDR.
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Revision 0.53
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PRELIMINARY
9.2.3 Exit the extended function mode
To exit the extended function mode, one write of 0xAA to EFER is required. Once the chip exits the
extended function mode, it is in the normal running mode and is ready to enter the configuration
mode.
9.2.4 Software programming example
The following example is written in Intel 8086 assembly language. It assumes that the EFER is
located at 2Eh, so EFIR is located at 2Eh and EFDR is located at 2Fh. If HEFRAS (CR26 bit 6) is
set, 4Eh can be directly replaced by 4Eh and 2Fh replaced by 4Fh.
;----------------------------------------------------------------------------------; Enter the extended function mode ,interruptible double-write |
;----------------------------------------------------------------------------------MOV DX,2EH
MOV AL,87H
OUT DX,AL
OUT DX,AL
;----------------------------------------------------------------------------; Configurate logical device 1, configuration register CRF0 |
;----------------------------------------------------------------------------MOV DX,2EH
MOV AL,07H
OUT DX,AL
; point to Logical Device Number Reg.
MOV DX,2FH
MOV AL,01H
OUT DX,AL
; select logical device 1
;
MOV DX,2EH
MOV AL,F0H
OUT DX,AL
; select CRF0
MOV DX,2FH
MOV AL,3CH
OUT DX,AL
; update CRF0 with value 3CH
;-----------------------------------------; Exit extended function mode |
;-----------------------------------------MOV DX,2EH
MOV AL,AAH
OUT DX,AL
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Revision 0.53
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PRELIMINARY
10. ACPI REGISTERS FEATURES
W83627HF supports both ACPI and legacy power managements. The switch logic of the power
management block generates an SMI interrupt in the legacy mode and an PME interrupt in the ACPI
mode. The new ACPI feature routes SMI / PME logic output either to SMI or to PME .The
SMI / PME logic routes to SMI only when both PME_EN = 0 and SMIPME_OE = 1. Similarly, the
SMI / PME logic routes to PME only when both PME_EN = 1 and SMIPME_OE = 1.
PME_EN
IRQ events
SMI / PME Logic
SMIPME_OE
0
SMI
1
PME
SMIPME_OE
Device Idle
Timers
IRQs
Device Trap
Sleep/Wake
State machine
WAK_STS
Clock
Control
Global STBY
Timer
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Revision 0.53
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PRELIMINARY
11. HARDWARE MONITOR
11.1
General Description
The W83627HF can be used to monitor several critical hardware parameters of the system, including
power supply voltages, fan speeds, and temperatures, which are very important for a high-end
2 TM
computer system to work stable and properly. W83627HF provides both LPC and I C serial bus
interface to access hardware .
An 8-bit analog-to-digital converter (ADC) was built inside W83627HF. The W83627HF can
simultaneously monitor 9 analog voltage inputs, 3 fan tachometer inputs, 3 remote temperature, one
case-open detection signal. The remote temperature sensing can be performed by thermistors, or
TM
2N3904 NPN-type transistors, or directly from Intel Deschutes CPU thermal diode output. Also the
W83627HF provides: 2 PWM (pulse width modulation) outputs for the fan speed control; beep tone
output for warning; SMI#(through serial IRQ) , OVT#, GPO# signals for system protection events.
Through the application software or BIOS, the users can read all the monitored parameters of system
from time to time. And a pop-up warning can be also activated when the monitored item was out of
TM
TM
the proper/preset range. The application software could be Winbond's Hardware Doctor , or Intel
LDCM (LanDesk Client Management), or other management application software. Also the users can
set up the upper and lower limits (alarm thresholds) of these monitored parameters and to activate
one programmable and maskable interrupts. An optional beep tone could be used as warning signal
when the monitored parameters is out of the preset range.
TM
Additionally, 5 VID inputs are provided to read the VID of CPU (i.e. Pentium II) if applicable. This is
to provide the Vcore voltage correction automatically. Also W83627HF uniquely provides an optional
feature: early stage (before BIOS was loaded) beep warning. This is to detect if the fatal elements
present --- Vcore or +3.3V voltage fail, and the system can not be boomed up.
11.2
Access Interface
The W83627HF provides two interface for microprocessor to read/write hardware monitor internal
registers.
11.2.1 LPC interface
The first interface uses LPC Bus to access which the ports of low byte (bit2~bit0) are defined in the
port 5h and 6h. The other higher bits of these ports is set by W83627HF itself. The general decoded
address is set to port 295h and port 296h. These two ports are described as following:
Port 295h: Index port.
Port 296h: Data port.
The register structure is showed as the Figure 11.1
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Revision 0.53
W83627HF/F
PRELIMINARY
Configuration Register
40h
SMI# Status/Mask Registers
41h, 42h, 44h, 45h
VID<3:0>/Fan Divisor Register
47h
Serial Bus Address
48h
ISA
Data
Bus
Monitor Value Registers
20h~3Fh
and
60h~7Fh (auto-increment)
ISA
Address
Bus
VID<4>/Device ID
49h
Port 5h
Temperature 2, 3 Serial
Bus Address
4Ah
Index
Register
Control Register
4Bh~4Dh
Select Bank for 50h~5Fh Reg.
4Eh
Winbond Vendor ID
4Fh
BANK 0
R-T Table Value
BEEP Control Register
Winbond Test Register
50h~58h
Port 6h
Data
Register
BANK 1
Temperature 2 Control/Staus
Registers
50h~56h
BANK 2
Temperature 3 Control/Staus
Registers
50h~56h
BANK 4
Additional Control/Staus
Registers
50h~5Ch
BANK 5
Additional Limit Value &
Value RAM
50h~57h
Figure 11.1 : ISA interface access diagram
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PRELIMINARY
2
11.2.2 I C interface
2
The second interface uses I C Serial Bus. W83627HF hardware monitor has three serial bus address.
That is, the first address defined at CR[48h] can read/write all registers excluding Bank 1 and Bank 2
temperature sensor 2/3 registers. The second address defined at CR[4Ah] bit2-0 only read/write
temperature sensor 2 registers, and the third address defined at CR[4Ah] bit6-4 only can access
(read/write) temperature sensor 3 registers.
11.2.2.1
The first serial bus access timing is shown as follow:
(a) Serial bus write to internal address register followed by the data byte
0
7
8
0
7
8
SCL
SDA
0
1
Start By
Master
0
1
1
0
1
R/W
D7
D6
Ack
by
781D
Frame 1
Serial Bus Address Byte
D5
D4
D3
D2
D1
D0
Ack
by
781D
Frame 2
Internal Index Register Byte
0
7
8
SCL (Continued)
SDA (Continued)
D7
D6
D5
D4
D3
D2
D1
D0
Ack
by
781D
Stop
by
Master
Frame 3
Data Byte
(b) Serial bus write to internal address register only
0
7
8
0
7
8
SCL
SDA
0
1
Start By
Master
0
1
1
0
1
R/W
D7
D6
Ack
by
781D
Frame 1
Serial Bus Address Byte
D5
D4
D3
D2
D1
D0
Ack
by
781D
Frame 2
Internal Index Register Byte
Stop by
Master
0
(c) Serial bus read from a register with the internal address register prefer to desired location
0
7
8
0
7
8
SCL
0
SDA
Start By
Master
1
0
1
1
0
1
R/W
D7
Ack
by
781D
Frame 1
Serial Bus Address Byte
D6
D5
D4
D3
Frame 2
Data Byte
D2
D1
D0
Ack
Stop by
by
Master Master
0
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Revision 0.53
W83627HF/F
PRELIMINARY
11.2.2.2
The serial bus timing of the temperature 2 and 3 are shown as follow:
(a) Typical 2-byte read from preset pointer location (Temp, TOS, T HYST)
0
7
8
0
SCL
SDA
0
1
Start By
Master
0
1
1
0
1
R/W
D7
Ack
by
782D
Frame 1
Serial Bus Address Byte
7
...
...
D1
8
0
D0
D7
Ack
by
Master
Frame 2
MSB Data Byte
7
...
...
D1
D0
Frame 3
LSB Data Byte
Ack
by
Master
Stop by
Master
(b) Typical pointer set followed by immediate read for 2-byte register (Temp, TOS, T HYST)
0
7
8
4
0
SCL
SDA
1
0
Start By
Master
0
1
A2
A1
A0
R/W
0
0
7
8
0
SCL
SDA
1
0
Start By
Master
0
1
A2
A1
A0
0
0
0
Ack
by
782D
Frame 1
Serial Bus Address Byte
R/W
D7
7
...
...
Ack
by
782D
Frame 3
Serial Bus Address Byte
0
0
D1
D0
Ack
by
782D
Frame 2
Pointer Byte
D1
8
0
D0
D7
Ack
by
Master
Frame 4
MSB Data Byte
7
...
...
D1
D0
Frame 5
LSB Data Byte
No Ack
by
Master
Stop by
Master
0
(c) Typical read 1-byte from configuration register with preset pointer
0
7
8
0
7
8
SCL
SDA
1
Start By
Master
0
0
1
A2
A1
A0
R/W
D7
Ack
by
782D
Frame 1
Serial Bus Address Byte
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D6
D5
D4
Frame 2
Data Byte
D3
D2
D1
D0
No Ack
by
Master
Stop by
Master
Publication Release Date: Jul 1999
Revision 0.53
W83627HF/F
PRELIMINARY
(d) Typical pointer set followed by immediate read from configuration register
0
7
8
4
0
7
8
...
SCL
SDA
1
0
Start By
Master
0
1
A1
A2
A0
R/W
0
Frame 1
Serial Bus Address Byte
0
0
0
0
Ack
by
782D
7
8
0
0
D1
D0
...
Ack
by
782D
Frame 2
Pointer Byte
0
7
8
SCL (Cont..)
SDA (Cont..)
1
0
Repea
Start
By
Master
0
1
A2
A1
A0
R/W
D7
Frame 3
Serial Bus Address Byte
D5
D6
Ack
by
782D
D4
D2
D3
D1
D0
No Ack
by
Master
Frame 4
MSB Data Byte
Stop by
Master
(e) Temperature 2/3 configuration register Write
0
7
8
0
R/W
0
0
4
7
8
SCL
SDA
1
Start By
Master
0
0
1
A2
A1
A0
0
0
0
Ack
by
782D
Frame 1
Serial Bus Address Byte
0
0
D1
D0
Ack
by
782D
Frame 2
Pointer Byte
7
0
8
SCL (Cont...)
SDA (Cont...)
0
0
0
D4
D3
D2
Frame 3
Configuration Data Byte
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D1
D0
Ack
by
782D
Stop
by
Master
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Revision 0.53
W83627HF/F
PRELIMINARY
(f)
Temperature 2/3 TOS and THYST write
0
7
8
4
0
7
8
SCL
SDA
1
0
Start By
Master
0
1
A1
A2
A0
R/W
0
0
0
0
Ack
by
782D
Frame 1
Serial Bus Address Byte
0
7
8
0
0
D1
D0
Ack
by
782D
Frame 2
Pointer Byte
0
7
8
SCL (Cont...)
SDA (Cont...)
D7
D6
D5
D4
D3
D2
D1
D0
D7
Ack
by
781D
Frame 3
MSB Data Byte
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D6
D5
D4
D3
Frame 4
LSB Data Byte
D2
D1
D0
Ack
by
782D
Stop
by
Master
Publication Release Date: Jul 1999
Revision 0.53
W83627HF/F
PRELIMINARY
11.3 Analog Inputs
The maximum input voltage of the analog pin is 4.096V because the 8-bit ADC has a 16mv LSB.
Really, the application of the PC monitoring would most often be connected to power suppliers. The
CPU V-core voltage ,+3.3V ,battery and 5VSB voltage can directly connected to these analog inputs.
The +12V,-12V and -5V voltage inputs should be reduced a factor with external resistors so as to
obtain the input range. As Figure 11.2 shows.
Positive Inputs
VCOREA
Pin 100
VCOREB
+3.3VIN
Pin 99
Pin 98
Pin 97
Pin 74
AVCC(+5V)
VBAT
Pin 61
5VSB
R1
+12VIN
V1
Positive Input
Negative Input
Pin 96
8-bit ADC
with
16mV LSB
R2
R3
V2
V3
N12VIN
R5
Pin 95
Pin 94
N5VIN
R6
R
10K, 1%
Typical Thermister Connection
RTHM
10K, 25 C
R4
VREF
Pin 101
VTIN3
Pin 102
VTIN2
Pin 103
VTIN1
Pin 104
**The Connections of VTIN1 and VTIN2
are same as VTIN3
Figure. 11.2
11.3.1 Monitor over 4.096V voltage:
The input voltage +12VIN can be expressed as following equation.
12 VIN = V1 ×
R2
R1 + R 2
The value of R1 and R2 can be selected to 28K Ohms and 10K Ohms, respectively, when the input
voltage V1 is 12V. The node voltage of +12VIN can be subject to less than 4.096V for the maximun
input range of the 8-bit ADC. The Pin 97 is connected to the power supply VCC with +5V. There are
two functions in this pin with 5V. The first function is to supply internal analog power in the
W83627HF and the second function is that this voltage with 5V is connected to internal serial
resistors to monitor the +5V voltage. The value of two serial resistors are 34K ohms and 50K ohms so
that input voltage to ADC is 2.98V which is less than 4.096V of ADC maximum input voltage. The
express equation can represent as follows.
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Revision 0.53
W83627HF/F
PRELIMINARY
Vin = VCC ×
50 K Ω
50 K Ω + 34 K Ω
≅ 2 .98 V
where VCC is set to 5V.
The Pin 61 is connected to 5VSB voltage. W83627HF monitors this voltage and the internal two serial
resistors are 17K Ω and 33K Ω so that input voltage to ADC is 3.3V which less than 4.096V of ADC
maximum input voltage.
11.3.2 Monitor negative voltage:
The negative voltage should be connected two series resistors and a positive voltage VREF (is equal
to 3.6V). In the Figure 11.2, the voltage V2 and V3 are two negative voltage which they are -12V and
-5V respectively. The voltage V2 is connected to two serial resistors then is connected to another
terminal VREF which is positive voltage. So as that the voltage node N12VIN can be obtain a
posedge voltage if the scales of the two serial resirtors are carefully selected. It is recommanded from
Winbond that the scale of two serial resistors are R3=232K ohms and R4=56K ohm. The input
voltage of node N12VIN can be calculated by following equation.
N 12VIN = (VREF + V2 ) × (
232 KΩ
) + V2
232 KΩ + 56 KΩ
where VREF is equal 3.6V.
If the V2 is equal to -12V then the voltage is equal to 0.567V and the converted hexdecimal data is
set to 35h by the 8-bit ADC with 16mV-LSB.This monitored value should be converted to the real
negative votage and the express equation is shown as follows.
V2 =
N 12VIN − VREF × β
1− β
Where β is 232K/(232K+56K). If the N2VIN is 0.567 then the V2 is approximately equal to -12V.
The another negative voltage input V3 (approximate -5V) also can be evaluated by the similar
method and the serial resistors can be selected with R5=120K ohms and R6=56K ohms by the
Winbond recommended. The expression equation of V3 With -5V voltage is shown as follows.
V3 =
N 5VIN − VREF × γ
1− γ
Where the γ is set to 120K/(120K+56K). If the monitored ADC value in the N5VIN channel is 0.8635,
VREF=3.6V and the parameter γ is 0.6818 then the negative voltage of V3 can be evalated to be -5V.
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Revision 0.53
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PRELIMINARY
11.3.3 Temperature Measurement Machine
The temperature data format is 8-bit two's-complement for sensor 2 and 9-bit two's-complement for
sensor 1. The 8-bit temperature data can be obtained by reading the CR[27h]. The 9-bit temperature
data can be obtained by reading the 8 MSBs from the Bank1 CR[50h] and the LSB from the Bank1
CR[51h] bit 7. The format of the temperature data is show in Table 1.
Temperature
8-Bit Digital Output
9-Bit Digital Output
8-Bit Binary
8-Bit Hex
9-Bit Binary
9-Bit Hex
+125°C
0111,1101
7Dh
0,1111,1010
0FAh
+25°C
0001,1001
19h
0,0011,0010
032h
+1°C
0000,0001
01h
0,0000,0010
002h
+0.5°C
-
-
0,0000,0001
001h
+0°C
0000,0000
00h
0,0000,0000
000h
-0.5°C
-
-
1,1111,1111
1FFh
-1°C
1111,1111
FFh
1,1111,1110
1FFh
-25°C
1110,0111
E7h
1,1100,1110
1CEh
-55°C
1100,1001
C9h
1,1001,0010
192h
Table 2.
11.3.3.1
Monitor temperature from thermistor:
The W83627HF can connect three thermistors to measure three different envirment temperature. The
specification of thermistor should be considered to (1) β value is 3435K, (2) resistor value is 10K
ohms at 25°C. In the Figure 11.2, the themistor is connected by a serial resistor with 10K Ohms, then
connect to VREF (Pin 101).
11.3.3.2
2N3904
Monitor temperature from Pentium IITM thermal diode or bipolar transistor
TM
The W83627HF can alternate the thermistor to Pentium II (Deschutes) thermal diode interface or
TM
transistor 2N3904 and the circuit connection is shown as Figure 11.3. The pin of Pentium II D- is
connected to power supply ground (GND) and the pin D+ is connected to pin VTINx in the
W83627HF. The resistor R=30K ohms should be connected to VREF to supply the diode bias current
and the bypass capacitor C=3300pF should be added to filter the high frequency noise. The transistor
2N3904 should be connected to a form with a diode, that is, the Base (B) and Collector (C) in the
2N3904 should be tied togeter to act as a thermal diode.
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Revision 0.53
W83627HF/F
PRELIMINARY
VREF
R=30K, 1%
Bipolar Transistor
Temperature Sensor
VTINx
C=3300pF
C
B
2N3904
W83627HF
E
R=30K, 1%
OR
Pentium II
CPU
Therminal
Diode
D+
VTINx
C=3300pF
D-
Figure 11.3
11.4
FAN Speed Count and FAN Speed Control
11.4.1 Fan speed count
Inputs are provides for signals from fans equipped with tachometer outputs. The level of these signals
should be set to TTL level, and maximum input voltage can not be over +5.5V. If the input signals
from the tachometer outputs are over the VCC, the external trimming circuit should be added to
reduce the voltage to obtain the input specification. The normal circuit and trimming circuits are
shown as Figure 11.4.
Determine the fan counter according to:
Count =
135
. × 10 6
RPM × Divisor
In other words, the fan speed counter has been read from register CR28 or CR29 or CR2A, the fan
speed can be evaluated by the following equation.
RPM =
1.35 × 10 6
Count × Divisor
The default divisor is 2 and defined at CR47.bit7~4, CR4B.bit7~6, and Bank0 CR5D.bit5~7 which are
three bits for divisor. That provides very low speed fan counter such as power supply fan. The
followed table is an example for the relation of divisor, PRM, and count.
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Revision 0.53
W83627HF/F
PRELIMINARY
Divisor
Nominal
PRM
Time per
Revolution
Counts
70% RPM
Time for 70%
1
8800
6.82 ms
153
6160
9.74 ms
2 (default)
4400
13.64 ms
153
3080
19.48 ms
4
2200
27.27 ms
153
1540
38.96 ms
8
1100
54.54 ms
153
770
77.92 ms
16
550
109.08 ms
153
385
155.84 ms
32
275
218.16 ms
153
192
311.68 ms
64
137
436.32 ms
153
96
623.36 ms
128
68
872.64 ms
153
48
1246.72 ms
Table 1.
+12V
+12V
+5V
Pull-up resister
4.7K Ohms
diode
diode
+12V
+12V
Fan Input
FAN Out
W83627HF
10K
FAN
Connector
Fan with Tach Pull-Up to +5V
Pin 111-113
W83627HF
Fan with Tach Pull-Up to +12V, or Totem-Pole
Output and Register Attenuator
+12V
+12V
diode
Pull-up resister < 1K
or totem-pole output
diode
Pull-up resister
> 1K
+12V
FAN
Connector
Fan Input
GND
FAN
Connector
GND
14K~39K
FAN Out
Pin 111-113
GND
FAN Out
Pull-up resister
4.7K Ohms
+12V
Fan Input
Fan Input
FAN Out
Pin 111-113
> 1K
Pin 111-113
GND
3.9V Zener
3.9V Zener
W83627HF
FAN
Connector
W83627HF
Fan with Tach Pull-Up to +12V, or Totem-Pole
Output and Zener Clamp
Fan with Tach Pull-Up to +12V and Zener Clamp
Figure 11.4
- 98 -
Publication Release Date: Jul 1999
Revision 0.53
W83627HF/F
PRELIMINARY
11.4.2 Fan speed control
The W83627HF provides 2 sets for fan PWM speed control. The duty cycle of PWM can be
programmed by a 8-bit registers which are defined in the Bank0 CR5A and CR5B. The default duty
cycle is set to 100%, that is, the default 8-bit registers is set to FFh. The expression of duty can be
represented as follows.
Duty − cycle (%) =
Programmed 8 - bit Register Value
255
× 100%
The PWM clock frequency also can be program and defined in the Bank0.CR5C . The application
circuit is shown as follows.
+12V
R1
R2
PNP Transistor
D
PWM Clock Input
G
NMOS
S
+
C
-
FAN
Figure 11.5
11.5
SMI# interrupt mode
11.5.1 Voltage SMI# mode :
SMI# interrupt for voltage is Two-Times Interrupt Mode. Voltage exceeding high limit or going
below low limit will causes an interrupt if the previous interrupt has been reset by reading all the
interrupt Status Register. (Figure 11.6 )
11.5.2 Fan SMI# mode :
SMI# interrupt for fan is Two-Times Interrupt Mode. Fan count exceeding the limit, or exceeding
and then going below the limit, will causes an interrupt if the previous interrupt has been reset by
reading all the interrupt Status Register. (Figure 11.7 )
- 99 -
Publication Release Date: Jul 1999
Revision 0.53
W83627HF/F
PRELIMINARY
High limit
Fan Count limit
Low limit
SMI#
*
*
*
SMI#
*
*
*
*Interrupt Reset when Interrupt Status Registers are read
Figure 11.6
Figure 11.7
11.5.3 The W83627HF temperature sensor 1 SMI# interrupt has two modes:
(1) Comparator Interrupt Mode
Setting the THYST (Temperature Hysteresis) limit to 127°C will set temperature sensor 1 SMI# to
the Comparator Interrupt Mode. Temperature exceeds TO (Over Temperature) Limit causes an
interrupt and this interrupt will be reset by reading all the Interrupt Status Register. Once an
interrupt event has occurred by exceeding TO, then reset, if the temperature remains above the
TO , the interrupt will occur again when the next conversion has completed. If an interrupt event
has occurred by exceeding TO and not reset, the interrupts will not occur again. The interrupts
will continue to occur in this manner until the temperature goes below TO. (Figure 11.8 )
(2) Two-Times Interrupt Mode
Setting the THYST lower than TO will set temperature sensor 1 SMI# to the Two-Times Interrupt
Mode. Temperature exceeding TO causes an interrupt and then temperature going below THYST
will also cause an interrupt if the previous interrupt has been reset by reading all the interrupt
Status Register. Once an interrupt event has occurred by exceeding TO , then reset, if the
temperature remains above the THYST , the interrupt will not occur. (Figure 11.9 )
THYST
127'C
TOI
TOI
THYST
SMI#
*
*
*
*
SMI#
*
*
*
*Interrupt Reset when Interrupt Status Registers are read
- 100 -
Publication Release Date: Jul 1999
Revision 0.53
W83627HF/F
PRELIMINARY
Figure 11.8
Figure 11.9
11.5.4 The W83627HF temperature sensor 2 and sensor 3 SMI# interrupt has two modes and it
is programmed at CR[4Ch] bit 6.
(1) Comparator Interrupt Mode
Temperature exceeding TO causes an interrupt and this interrupt will be reset by reading all the
Interrupt Status Register. Once an interrupt event has occurred by exceeding TO, then reset, if
the temperature remains above the THYST, the interrupt will occur again when the next conversion
has completed. If an interrupt event has occurred by exceeding TO and not reset, the interrupts
will not occur again. The interrupts will continue to occur in this manner until the temperature
goes below THYST. ( Figure 11.10 )
(2) Two-Times Interrupt Mode
Temperature exceeding TO causes an interrupt and then temperature going below THYST will also
cause an interrupt if the previous interrupt has been reset by reading all the interrupt Status
Register. Once an interrupt event has occurred by exceeding TO , then reset, if the temperature
remains above the THYST , the interrupt will not occur. (Figure 11.11 )
TOI
TOI
THYST
SMI#
THYST
*
*
*
*
*
SMI#
*
*
*
*Interrupt Reset when Interrupt Status Registers are read
Figure 11.10
Figure 11.11
- 101 -
Publication Release Date: Jul 1999
Revision 0.53
W83627HF/F
PRELIMINARY
11.6
OVT# interrupt mode
The OVT# signal is only related with temperature sensor 2 and 3 (VTIN2 / VTIN3).
11.6.1 The W83627HF temperature sensor 2 and 3 Over-Temperature (OVT#) has the
following modes
(1) Comparator Mode :
Setting Bank1/2 CR[52h] bit 2 to 0 will set OVT# signal to comparator mode. Temperature
exceeding TO causes the OVT# output activated until the temperature is less than THYST. ( Figure
11.12)
(2) Interrupt Mode:
Setting Bank1/2 CR[52h] bit 2 to 1 will set OVT# signal to interrupt mode. Setting Temperature
exceeding TO causes the OVT# output activated indefinitely until reset by reading temperature
sensor 2 or sensor 3 registers. Temperature exceeding TO , then OVT# reset, and then
temperature going below THYST will also cause the OVT# activated indefinitely until reset by
reading temperature sensor2 or sensor 3 registers. Once the OVT# is activated by exceeding TO
, then reset, if the temperature remains above THYST , the OVT# will not be activated again.(
Figure 11.12)
To
THYST
OVT#
(Comparator Mode; default)
OVT#
*
(Interrupt Mode)
*
*
*
*Interrupt Reset when Temperature 2/3 is read
- 102 -
Publication Release Date: Jul 1999
Revision 0.53
W83627HF/F
PRELIMINARY
11.7 REGISTERS AND RAM
11.7.1 Address Register (Port x5h)
Data Port:
Port x5h
Power on Default Value
00h
Attribute:
Bit 6:0 Read/write , Bit 7: Read Only
Size:
8 bits
7
6
5
4
3
2
1
0
Data
Bit7: Read Only
The logical 1 indicates the device is busy because of a Serial Bus transaction or another LPC
bus transaction. With checking this bit, multiple LPC drivers can use W83627HF hardware
monitor without interfering with each other or a Serial Bus driver.
It is the user's responsibility not to have a Serial Bus and LPC bus operations at the same time.
This bit is:
Set: with a write to Port x5h or when a Serial Bus transaction is in progress.
Reset: with a write or read from Port x6h if it is set by a write to Port x5h, or when the Serial Bus
transaction is finished.
Bit 6-0: Read/Write
Bit 7
Bit 6
Bit 5
Busy
(Power On default 0)
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
A1
A0
Address Pointer (Power On default 00h)
A6
A5
A4
- 103 -
A3
A2
Publication Release Date: Jul 1999
Revision 0.53
W83627HF/F
PRELIMINARY
Address Pointer Index (A6-A0)
Registers and RAM
A6-A0 in
Hex
Power On Value of
Registers: <k7:0>in
Binary
Configuration Register
Interrupt
Status
Register 1
40h
41h
00001000
00000000
Interrupt
Register 2
Status
42h
00000000
SMI#Ý Mask Register
1
43h
00000000
SMIÝ Mask Register 2
44h
00000000
NMI Mask Register 1
45h
00000000
NMI Mask Register 2
VID/Fan
Divisor
Register
46h
47h
01000000
<7:4> = 0101;
<3:0> = VID3-VID0
Serial Bus
Register
48h
<7> = 0 ; <6:0> =
0101101
ID
49h
<7:1> = 0000001; <0> =
VID4
Temperature 2 and
Temperature 3 Serial
Bus Address Register
Pin Control Register
4Ah
<7:0> = 00000001
VID4 &
Register
Address
Device
4Bh
<7:0> = 01000100
IRQ/OVT#
Property
Select Register
4Ch
<7:0> = 00000000
FAN IN/OUT and
BEEP
Control
Register
4Dh
<7:0> = 00010101
Register
50h-5Fh
Bank Select Register
4Eh
<7> = 1 ; <6:3> =
Reserved ; <2:0> = 000
Winbond Vendor ID
Register
4Fh
<7:0> = 01011100 (High
Byte) <7:0> = 10100011
(Low Byte)
POST RAM
00-1Fh
Value RAM
20-3Fh
Notes
Auto-increment to the address of
Interrupt Status Register 2 after a
read or write to Port x6h.
Auto-increment to the address of
SMIÝ Mask Register 2 after a read
or write to Port x6h.
Auto-increment to the address of
NMI Mask Register 2 after a read
or write to Port x6h
Auto-increment to the next location
after a read or write to Port x6h
and stop at 1Fh.
- 104 -
Publication Release Date: Jul 1999
Revision 0.53
W83627HF/F
PRELIMINARY
Value RAM
60-7Fh
Temperature
Registers
2
Temperature
Registers
3
Additional
Configuration
Registers
Auto-increment to the next location
after a read or write to Port x6h
and stop at 7Fh.
Bank1
50h-56h
Bank2
50h-56h
Bank4
50h-5Dh
- 105 -
Publication Release Date: Jul 1999
Revision 0.53
W83627HF/F
PRELIMINARY
11.7.2 Data Register (Port x6h)
Data Port:
Port x6h
Power on Default Value
00h
Attribute:
Read/write
Size:
8 bits
7
6
5
4
3
2
1
0
Data
Bit 7-0: Data to be read from or to be written to RAM and Register.
11.7.3 Configuration Register  Index 40h
Register Location:
40h
Power on Default Value
01h
Attribute:
Read/write
Size:
8 bits
7
6
5
4
3
2
1
0
START
SMI#Enable
RESERVED
INT_Clear
RESERVED
RESERVED
RESERVED
INITIALIZATION
Bit 7: A one restores power on default value to all registers except the Serial Bus Address register.
This bit clears itself since the power on default is zero.
Bit 6: Reserced
Bit 5: Reserved
Bit 4: Reserved
Bit 3: A one disables the SMI# output without affecting the contents of Interrupt Status Registers.
The device will stop monitoring. It will resume upon clearing of this bit.
Bit 2: Reserved
Bit 1: A one enables the SMI# Interrupt output.
Bit 0: A one enables startup of monitoring operations, a zero puts the part in standby mode.
Note: The outputs of Interrupt pins will not be cleared if the user writes a zero to this location after an
interrupt has occurred unlike "INT_Clear'' bit.
- 106 -
Publication Release Date: Jul 1999
Revision 0.53
W83627HF/F
PRELIMINARY
11.7.4 Interrupt Status Register 1 Index 41h
Register Location:
41h
Power on Default Value
00h
Attribute:
Read Only
Size:
8 bits
7
6
5
4
3
2
1
0
VCOREA
VCOREB
+3.3VIN
+5VIN
TEMP1
TEMP2
FAN1
FAN2
Bit 7: A one indicates the fan count limit of FAN2 has been exceeded.
Bit 6: A one indicates the fan count limit of FAN1 has been exceeded.
Bit 5: A one indicates a High limit of VTIN2 has been exceeded from temperature sensor 2.
Bit 4: A one indicates a High limit of VTIN1 has been exceeded from temperature sensor 1.
Bit 3: A one indicates a High or Low limit of +5VIN has been exceeded.
Bit 2: A one indicates a High or Low limit of +3.3VIN has been exceeded.
Bit 1: A one indicates a High or Low limit of VCOREB has been exceeded.
Bit 0: A one indicates a High or Low limit of VCOREA has been exceeded.
- 107 -
Publication Release Date: Jul 1999
Revision 0.53
W83627HF/F
PRELIMINARY
11.7.5 Interrupt Status Register 2  Index 42h
Register Location:
42h
Power on Default Value
00h
Attribute:
Read Only
Size:
8 bits
7
6
5
4
3
2
1
0
+12VIN
-12VIN
-5VIN
FAN3
Chassis Intrusion
Temp3
Reserved
Reserved
Bit 7-6:Reserved.This bit should be set to 0.
Bit 5: A one indicates a High limit of VTIN3 has been exceeded from temperature sensor 3.
Bit 4: A one indicates Chassis Intrusion has gone high.
Bit 3: A one indicates the fan count limit of FAN3 has been exceeded.
Bit 2: A one indicates a High or Low limit of -5VIN has been exceeded.
Bit1: A one indicates a High or Low limit of -12VIN has been exceeded.
Bit0: A one indicates a High or Low limit of +12VIN has been exceeded.
11.7.6 SMI# Mask Register 1  Index 43h
Register Location:
43h
Power on Default Value
00h
Attribute:
Read/Write
Size:
8 bits
7
6
5
4
3
2
1
0
VCOREA
VCOREB
+3.3VIN
+5VIN
TEMP1
TEMP2
FAN1
FAN2
Bit 7-0: A one disables the corresponding interrupt status bit for SMI interrupt.
- 108 -
Publication Release Date: Jul 1999
Revision 0.53
W83627HF/F
PRELIMINARY
11.7.7 SMI# Mask Register 2  Index 44h
Register Location:
44h
Power on Default Value
00h
Attribute:
Read/Write
Size:
8 bits
7
6
5
4
3
2
1
0
+12VIN
-12VIN
-5VIN
FAN3
Chassis Intrusion
TEMP3
Reserved
Reserved
Bit 7-6: Reserved. This bit should be set to 0.
Bit 5-0: A one disables the corresponding interrupt status bit for SMI interrupt.
11.7.8 Reserved Register  Index 45h
11.7.9 Chassis Clear Register -- Index 46h
Register Location:
46h
Power on Default Value
00h
Attribute:
Read/Write
Size:
8 bits
7
6
5
4
3
2
1
0
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Chassis Clear
Bit 7: Set 1 , clear Chassis Intrusion event. This bit self clears after clearing Chassis Intrusion event.
Bit 6-0:Reserved. This bit should be set to 0.
- 109 -
Publication Release Date: Jul 1999
Revision 0.53
W83627HF/F
PRELIMINARY
11.7.10 VID/Fan Divisor Register  Index 47h
Register Location:
47h
Power on Default Value <7:4> is 0101, <3:0> is mapped to VID<3:0>
Attribute:
Read/Write
Size:
8 bits
7
6
5
4
3
2
1
0
VID0
VID1
VID2
VID3
FAN1DIV_B0
FAN1DIV_B1
FAN2DIV_B0
FAN2DIV_B1
Bit 7-6: FAN2 Speed Control.
Bit 5-4: FAN1 Speed Control.
Bit 3-0: The VID <3:0> inputs
Note : Please refer to Bank0 CR[5Dh] , Fan divisor table.
11.7.11 Serial Bus Address Register  Index 48h
Register Location:
48h
Power on Default Value Serial Bus address
2Dh
Size:
8 bits
7
6
5
4
3
2
1
0
Serial Bus Address
Reserved
Bit 7: Read Only - Reserved.
Bit 6-0: Read/Write - Serial Bus address <6:0>.
- 110 -
Publication Release Date: Jul 1999
Revision 0.53
W83627HF/F
PRELIMINARY
11.7.12 Value RAM  Index 20h- 3Fh or 60h - 7Fh (auto-increment)
Address A6-A0
Address A6-A0 with
Auto-Increment
20h
21h
60h
61h
VCOREA reading
VCOREB reading
22h
23h
24h
62h
63h
64h
+3.3VIN reading
+5VIN reading
+12VIN reading
25h
26h
27h
65h
66h
67h
-12VIN reading
-5VIN reading
Temperature reading
28h
68h
29h
69h
2Ah
6Ah
FAN1 reading
Note: This location stores the number of counts of the
internal clock per revolution.
FAN2 reading
Note: This location stores the number of counts of the
internal clock per revolution.
FAN3 reading
Note: This location stores the number of counts of the
internal clock per revolution.
2Bh
6Bh
VCOREA High Limit, default value is defined by
Vcore Voltage +0.2v.
2Ch
6Ch
2Dh
2Eh
2Fh
6Dh
6Eh
6Fh
VCOREA Low Limit, default value is defined by Vcore
Voltage -0.2v.
VCOREB High Limit.
VCOREB Low Limit.
+3.3VIN High Limit
30h
31h
32h
70h
71h
72h
+3.3VIN Low Limit
+5VIN High Limit
+5VIN Low Limit
33h
34h
35h
73h
74h
75h
+12VIN High Limit
+12VIN Low Limit
-12VIN High Limit
36h
37h
38h
76h
77h
78h
-12VIN Low Limit
-5VIN High Limit
-5VIN Low Limit
39h
3Ah
79h
7Ah
Temperature sensor 1 (VTIN1) High Limit
Temperature sensor 1 (VTIN1) Hysteresis Limit
- 111 -
Description
Publication Release Date: Jul 1999
Revision 0.53
W83627HF/F
PRELIMINARY
3Bh
7Bh
3Ch
7Ch
3Dh
7Dh
3E- 3Fh
7E- 7Fh
FAN1 Fan Count Limit
Note: It is the number of counts of the internal clock
for the Low Limit of the fan speed.
FAN2 Fan Count Limit
Note: It is the number of counts of the internal clock
for the Low Limit of the fan speed.
FAN3 Fan Count Limit
Note: It is the number of counts of the internal clock
for the Low Limit of the fan speed.
Reserved
Setting all ones to the high limits for voltages and fans (0111 1111 binary for temperature) means
interrupts will never be generated except the case when voltages go below the low limits.
11.7.13 Voltage ID (VID4) & Device ID Register - Index 49h
Register Location:
49h
Power on Default Value
<7:1> is 000,0001 binary
<0> is mapped to VID <4>
Size:
8 bits
7
6
5
4
3
2
1
0
VID4
DID<6:0>
Bit 7-1: Read Only - Device ID<6:0>
Bit 0 : Read/Write - The VID4 inputs.
- 112 -
Publication Release Date: Jul 1999
Revision 0.53
W83627HF/F
PRELIMINARY
11.7.14 Temperature 2 and Temperature 3 Serial Bus Address Register--Index 4Ah
Register Location:
4Ah
Power on Default Value
01h
Attribute:
Read/Write
Size:
8 bits
7
6
5
4
3
2
1
0
I2CADDR2
I2CADDR2
I2CADDR2
DIS_T2
I2CADDR3
I2CADDR3
I2CADDR3
DIS_T3
Bit 7: Set to 1, disable temperature sensor 3 and can not access any data from Temperature Sensor 3.
Bit 6-4: Temperature 3 Serial Bus Address. The serial bus address is 1001xxx. Where xxx are defined in
these bits.
Bit 3: Set to 1, disable temperature Sensor 2 and can not access any data from Temperature Sensor 2.
Bit 2-0: Temperature 2 Serial Bus Address. The serial bus address is 1001xxx. Where xxx are defined in
these bits.
11.7.15 Pin Control Register - Index 4Bh
Register Location:
Power on Default Value
Attribute:
Size:
4Bh
44h
Read/Write
8 bits
7
6
5
4
3
2
1
0
Reserved
Reserved
CLKINSEL
CLKINSEL
ADCOVSEL
ADCOVSEL
FAN3DIV_B0
FAN3DIV_B1
Bit 7-6:Fan3 speed divisor.
Please refer to Bank0 CR[5Dh] , Fan divisor table.
- 113 -
Publication Release Date: Jul 1999
Revision 0.53
W83627HF/F
PRELIMINARY
Bit 5-4: Select A/D Converter Clock Input.
<5:4> = 00 - default. ADC clock select 22.5 Khz.
<5:4> = 01- ADC clock select 5.6 Khz. (22.5K/4)
<5:4> = 10 - ADC clock select 1.4Khz. (22.5K/16)
<5:4> = 11 - ADC clock select 0.35 Khz. (22.5K/64)
Bit 3-2: Clock Input Select.
<3:2> = 00 - Pin 3 (CLKIN) select 14.318M Hz clock.
<3:2> = 01 - Default. Pin 3 (CLKIN) select 24M Hz clock.
<3:2> = 10 - Pin 3 (CLKIN) select 48M Hz clock .
<3:2> = 11 - Reserved. Pin3 no clock input.
Bit 1-0: Reserved. User defined.
11.7.16 IRQ/OVT# Property Select Register- Index 4Ch
Register Location:
4Ch
Power on Default Value
00h
Attribute:
Read/Write
Size:
8 bits
7
6
5
4
3
2
1
0
Reserved
Reserved
OVTPOL
DIS_OVT1
DIS_OVT2
Reserved
T23_INTMode
Reserved
Bit 7: Reserved. User Defined.
Bit6: Set to 1, the SMI# output type of Temperature 2 and 3 is set to Comparator Interrupt mode. Set
to 0, the SMI# output type is set to Two-Times Interrupt mode. (default 0)
Bit5: Reserved. User Defined.
Bit 4: Disable temperature sensor 3 over-temperature (OVT) output if set to 1. Default 0, enable
OVT2 output through pin OVT#.
Bit 3: Disable temperature sensor 2 over-temperature (OVT) output if set to 1. Default 0, enable
OVT1 output through pin OVT#.
Bit 2: Over-temperature polarity. Write 1, OVT# active high. Write 0, OVT# active low. Default 0.
Bit 1: Reserved.
Bit 0: Reserved.
- 114 -
Publication Release Date: Jul 1999
Revision 0.53
W83627HF/F
PRELIMINARY
11.7.17 FAN IN/OUT and BEEP Control Register- Index 4Dh
Register Location:
4Dh
Power on Default Value
15h
Attribute:
Read/Write
Size:
8 bits
7
6
5
4
3
2
1
0
FANINC1
FANOPV1
FANINC2
FANOPV2
FANINC3
FANOPV3
RESERVED
DIS_ABN
Bit 7: Disable power-on abnormal the monitor voltage including V-Core A and +3.3V. If these voltage
exceed the limit value, the pin (Open Drain) of BEEP will drives 300Hz and 600Hz frequency
signal. Write 1, the frequency will be disable. Default 0. After power on, the system should set
1 to this bit to 1 in order to disable BEEP.
Bit 6: Reserved.
Bit 5: FAN 3 output value if FANINC3 sets to 0. Write 1, then pin 18 always generate logic high
signal. Write 0, pin 18 always generates logic low signal. This bit default 0.
Bit 4: FAN 3 Input Control. Set to 1, pin 18 acts as FAN clock input, which is default value. Set to 0,
this pin 18 acts as FAN control signal and the output value of FAN control is set by this register
bit 5.
Bit 3: FAN 2 output value if FANINC2 sets to 0. Write 1, then pin 19 always generate logic high
signal. Write 0, pin 19 always generates logic low signal. This bit default 0.
Bit 2: FAN 2 Input Control. Set to 1, pin 19 acts as FAN clock input, which is default value. Set to 0,
this pin 19 acts as FAN control signal and the output value of FAN control is set by this register
bit 3.
Bit 1: FAN 1 output value if FANINC1 sets to 0. Write 1, then pin 20 always generate logic high
signal. Write 0, pin 20 always generates logic low signal. This bit default 0.
Bit 0: FAN 1 Input Control. Set to 1, pin 20 acts as FAN clock input, which is default value. Set to 0,
this pin 20 acts as FAN control signal and the output value of FAN control is set by this register
bit 1.
- 115 -
Publication Release Date: Jul 1999
Revision 0.53
W83627HF/F
PRELIMINARY
11.7.18 Register 50h ~ 5Fh Bank Select Register - Index 4Eh (No Auto Increase)
Register Location:
4Eh
Power on Default Value
80h
Attribute:
Read/Write
Size:
8 bits
7
6
5
4
3
2
1
0
BANKSEL0
BANKSEL1
BANKSEL2
Reserved
Reserved
Reserved
Reserved
HBACS
Bit 7: HBACS- High byte access. Set to 1, access Register 4Fh high byte register.
Set to 0, access Register 4Fh low byte register. Default 1.
Bit 6-3: Reserved. This bit should be set to 0.
Bit 2-0: Index ports 0x50~0x5F Bank select.
11.7.19 Winbond Vendor ID Register - Index 4Fh (No Auto Increase)
Register Location:
4Fh
Power on Default Value
<15:0> = 5CA3h
Attribute:
Read Only
Size:
16 bits
15
8
7
0
VIDH
VIDL
Bit 15-8: Vendor ID High Byte if CR4E.bit7=1.Default 5Ch.
Bit 7-0: Vendor ID Low Byte if CR4E.bit7=0. Default A3h.
11.7.20 Winbond Test Register -- Index 50h - 55h (Bank 0)
- 116 -
Publication Release Date: Jul 1999
Revision 0.53
W83627HF/F
PRELIMINARY
11.7.21 BEEP Control Register 1-- Index 56h (Bank 0)
Register Location:
56h
Power on Default Value
00h
Attribute:
Read/Write
Size:
8 bits
7
6
5
4
3
2
1
0
EN_VCA_BP
EN_VCB_BP
EN_V33_BP
EN_V5_BP
EN_T1_BP
EN_T2_BP
EN_FAN1_BP
EN_FAN2_BP
Bit 7: Enable BEEP Output from FAN 2 if the monitor value exceed the limit value. Write 1, enable
BEEP output, which is default value.
Bit 6: Enable BEEP Output from FAN 1 if the monitor value exceed the limit value. Write 1, enable
BEEP output, which is default value.
Bit 5: Enable BEEP Output from Temperature Sensor 2 if the monitor value exceed the limit value.
Write 1, enable BEEP output. Default 0
Bit 4: Enable BEEP output for Temperature Sensor 1 if the monitor value exceed the limit value.
Write 1, enable BEEP output. Default 0
Bit 3: Enable BEEP output from VDD (+5V), Write 1, enable BEEP output if the monitor value exceed
the limits value. Default 0, that is disable BEEP output.
Bit 2: Enable BEEP output from +3.3V. Write 1, enable BEEP output, which is default value.
Bit 1: Enable BEEP output from VCOREB. Write 1, enable BEEP output, which is default value.
Bit 0: Enable BEEP Output from VCOREA if the monitor value exceed the limits value. Write 1,
enable BEEP output, which is default value
11.7.22 BEEP Control Register 2-- Index 57h (Bank 0)
Register Location:
57h
Power on Default Value 80h
Attribute:
Size:
Read/Write
8 bits
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Revision 0.53
W83627HF/F
PRELIMINARY
7
6
5
4
3
2
1
0
EN_V12_BP
EN_NV12_BP
EN_NV5_BP
EN_FAN3_BP
EN_CASO_BP
EN_T3_BP
Reserved
EN_GBP
Bit 7: Enable Global BEEP. Write 1, enable global BEEP output. Default 1. Write 0, disable all BEEP
output.
Bit 6: Reserved. This bit should be set to 0.
Bit5: Enable BEEP Output from Temperature Sensor 3 if the monitor value exceed the limit value.
Write 1, enable BEEP output. Default 0
Bit 4: Enable BEEP output for case open if the monitor value exceed the limit value. Write 1, enable
BEEP output. Default 0.
Bit 3: Enable BEEP Output from FAN 3 if the monitor value exceed the limit value. Write 1, enable
BEEP output. Default 0.
Bit 2: Enable BEEP output from -5V, Write 1, enable BEEP output if the monitor value exceed the
limits value. Default 0, that is disable BEEP output.
Bit 1: Enable BEEP output from -12V, Write 1, enable BEEP output if the monitor value exceed the
limits value. Default 0, that is disable BEEP output.
Bit 0: Enable BEEP output from +12V, Write 1, enable BEEP output if the monitor value exceed the
limits value. Default 0, that is disable BEEP output.
11.7.23 Chip ID -- Index 58h (Bank 0)
Register Location:
58h
Power on Default Value
21h
Attribute:
Read Only
Size:
8 bits
7
6
5
4
3
2
1
0
CHIPID
Bit 7: Winbond Chip ID number. Read this register will return 21h.
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PRELIMINARY
11.7.24 Reserved Register -- Index 59h (Bank 0)
Register Location:
59h
Power on Default Value
<7>=0 and <6:4> = 111 and <3:0> = 0000
Attribute:
Read/Write
Size:
8 bits
7
6
5
4
3
2
1
0
Reserved
Reserved
Reserved
Reserved
SELPIIV1
SELPIIV2
SELPIIV3
Reserved
Bit 7: Reserved
Bit 6: Temperature sensor diode 3. Set to 1, select Pentium II compatible Diode. Set to 0 to select 2N3904
Bipolar mode.
Bit 5: Temperature sensor diode 2. Set to 1, select Pentium II compatible Diode. Set to 0 to select 2N3904
Bipolar mode.
Bit 4: Temperature sensor diode 1. Set to 1, select Pentium II compatible Diode. Set to 0 to select 2N3904
Bipolar mode.
Bit 3-0: Reserved
11.7.25 PWMOUT1 Control -- Index 5Ah (Bank 0)
Register Location:
5Ah
Power on default value:
FFh
Attribute:
Read/Write
Size:
8 bits
7
6
5
4
3
2
1
0
PWM1_DUTY
Bit 7: PWMOUT1 duty cycle control
Write FF, Duty cycle is 100%, Write 00, Duty cycle is 0%.
11.7.26 PWMOUT2 Control -- Index 5Bh (Bank 0)
Register Location:
5Bh
Power on default value:
FFh
Attribute:
Read/Write
Size:
8 bits
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Revision 0.53
W83627HF/F
PRELIMINARY
7
6
5
4
3
2
1
0
PWM2_DUTY
Bit 7: PWMOUT2 duty cycle control
Write FF, Duty cycle is 100%, Write 00, Duty cycle is 0%.
11.7.27 PWMOUT1/2 Clock Select -- Index 5Ch (Bank 0)
Register Location:
5Ch
Power on Default Value
11h
Attribute:
Read/Write
Size:
8 bits
7
6
5
4
3
2
1
0
PWM1CLKSEL
PWM1CLKSEL
PWM1CLKSEL
Reserved
PWM2CLKSEL
PWM2CLKSEL
PWM2CLKSEL
Reserved
Bit 7: Reserved
Bit 6-4: PWMOUT2 clock selection.
The clock defined frequency is same as PWMOUT1 clock selection.
Bit 3: Reserved
Bit 2-0: PWMOUT1 clock Selection.
<2:0> = 000: 46.87K Hz
<2:0> = 001: 23.43K Hz (Default)
<2:0> = 010: 11.72K Hz
<2:0> = 011: 5.85K Hz
<2:0> = 100: 2.93K Hz
11.7.28 VBAT Monitor Control Register -- Index 5Dh (Bank 0)
Register Location:
5Dh
Power on Default Value
00h
Attribute:
Read/Write
Size:
8 bits
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Revision 0.53
W83627HF/F
PRELIMINARY
7
6
5
4
3
2
1
0
EN_VBAT_MNT
DIODES1
DIODES2
DIODES3
RESERVE
FANDIV1_B2
FANDIV2_B2
FANDIV3_B2
Bit 7: Fan3 divisor Bit 2.
Bit 6: Fan2 divisor Bit 2.
Bit 5: Fan1 divisor Bit 2.
Bit 4: Reserved.
Bit 3: Temperature sensor 3 select into thermal diode such as Pentium II CPU supported. Set to 1,
select bipolar sensor. Set to 0, select thermistor sensor.
Bit 2: Sensor 2 type selection. Set to 1, select bipolar sensor. Set to 0, select thermistor sensor.
Bit 1: Sensor 1 type selection. Set to 1, select bipolar sensor. Set to 0, select thermistor sensor.
Bit 0: Set to 1, enable battery voltage monitor. Set to 0, disable battery voltage monitor. If enable this
bit, the monitor value is value after one monitor cycle. Note that the monitor cycle time is at
least
300ms for W83627HF hardware monitor.
Fan divisor table :
Bit 2 Bit 1
Bit 0
0
0
0
0
0
0
1
1
0
1
0
1
Fan
Divisor
1
2
4
8
Bit 2
Bit 1
Bit 0
Fan Divisor
1
1
1
1
0
0
1
1
0
1
0
1
16
32
64
128
11.7.29 Reserved Register -- 5Eh (Bank 0)
11.7.30 Reserved Register -- Index 5Fh (Bank 0)
11.7.31 Temperature Sensor 2 Temperature (High Byte) Register - Index 50h (Bank 1)
Register Location:
50h
Attribute:
Read Only
Size:
8 bits
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W83627HF/F
PRELIMINARY
7
6
5
4
3
2
1
0
TEMP2<8:1>
Bit 7: Temperature <8:1> of sensor 2, which is high byte.
11.7.32 Temperature Sensor 2 Temperature (Low Byte) Register - Index 51h (Bank 1)
Register Location:
51h
Attribute:
Read Only
Size:
8 bits
7
6
5
4
3
2
1
0
Reserved
TEMP2<0>
Bit 7: Temperature <0> of sensor2, which is low byte.
Bit 6-0: Reserved.
11.7.33 Temperature Sensor 2 Configuration Register - Index 52h (Bank 1)
Register Location:
52h
Power on Default Value
00h
Size:
8 bits
7
6
5
4
3
2
1
0
STOP2
INTMOD
Reserved
FAULT
FAULT
Reserved
Reserved
Reserved
Bit 7-5: Read - Reserved. This bit should be set to 0.
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PRELIMINARY
Bit 4-3: Read/Write - Number of faults to detect before setting OVT# output to avoid false tripping
due
to noise.
Bit 2: Read - Reserved. This bit should be set to 0.
Bit 1: Read/Write - OVT# Interrupt mode select. This bit default is set to 0, which is compared mode.
When set to 1, interrupt mode will be selected.
Bit 0: Read/Write - When set to 1 the sensor will stop monitor.
11.7.34 Temperature Sensor 2 Hysteresis (High Byte) Register - Index 53h (Bank 1)
Register Location:
53h
Power on Default Value
4Bh
Attribute:
Read/Write
Size:
8 bits
7
6
5
4
3
2
1
0
THYST2<8:1>
Bit 7-0: Temperature hysteresis bit 8-1, which is High Byte. The temperature default 75 degree C.
11.7.35 Temperature Sensor 2 Hysteresis (Low Byte) Register - Index 54h (Bank 1)
Register Location:
54h
Power on Default Value
00h
Attribute:
Read/Write
Size:
8 bits
7
6
5
4
3
2
1
0
Reserved
THYST2<0>
Bit 7: Hysteresis temperature bit 0, which is low Byte.
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PRELIMINARY
Bit 6-0: Reserved.
11.7.36 Temperature Sensor 2 Over-temperature (High Byte) Register - Index 55h (Bank 1)
Register Location:
55h
Power on Default Value
50h
Attribute:
Read/Write
Size:
8 bits
7
6
5
4
3
2
1
0
TOVF2<8:1>
Bit 7-0: Over-temperature bit 8-1, which is High Byte. The temperature default 80 degree C.
11.7.37 Temperature Sensor 2 Over-temperature (Low Byte) Register - Index 56h (Bank 1)
Register Location:
56h
Power on Default Value
00h
Attribute:
Read/Write
Size:
8 bits
7
6
5
4
3
2
1
0
Reserved
TOVF2<0>
Bit 7: Over-temperature bit 0, which is low Byte.
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PRELIMINARY
Bit 6-0: Reserved.
11.7.38 Temperature Sensor 3 Temperature (High Byte) Register - Index 50h (Bank 2)
Register Location:
50h
Attribute:
Read Only
Size:
8 bits
7
6
5
4
3
2
1
0
TEMP2<8:1>
Bit 7-0: Temperature <8:1> of sensor 2, which is high byte.
11.7.39 Temperature Sensor 3 Temperature (Low Byte) Register - Index 51h (Bank 2)
Register Location:
51h
Attribute:
Read Only
Size:
8 bits
7
6
5
4
3
2
1
0
Reserved
TEMP2<0>
Bit 7: Temperature <0> of sensor2, which is low byte.
Bit 6-0: Reserved.
11.7.40 Temperature Sensor 3 Configuration Register - Index 52h (Bank 2)
Register Location:
52h
Power on Default Value
00h
Attribute:
Read/Write
Size:
8 bits
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Revision 0.53
W83627HF/F
PRELIMINARY
7
6
5
4
3
2
1
0
STOP3
INTMOD
Reserved
FAULT
FAULT
Reserved
Reserved
Reserved
Bit 7-5: Read - Reserved. This bit should be set to 0.
Bit 4-3: Read/Write - Number of faults to detect before setting OVT# output to avoid false tripping
due to noise.
Bit 2: Read - Reserved. This bit should be set to 0.
Bit 1: Read/Write - OVT# Interrupt Mode select. This bit default is set to 0, which is Compared Mode.
When set to 1, Interrupt Mode will be selected.
Bit 0: Read/Write - When set to 1 the sensor will stop monitor.
11.7.41 Temperature Sensor 3 Hysteresis (High Byte) Register - Index 53h (Bank 2)
Register Location:
53h
Power on Default Value
4Bh
Attribute:
Read/Write
Size:
8 bits
7
6
5
4
3
2
1
0
THYST3<8:1>
Bit 7-0: Temperature hysteresis bit 8-1, which is High Byte. The temperature default 75 degree C.
11.7.42 Temperature Sensor 3 Hysteresis (Low Byte) Register - Index 54h (Bank 2)
Register Location:
54h
Power on Default Value
00h
Attribute:
Read/Write
Size:
8 bits
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Revision 0.53
W83627HF/F
PRELIMINARY
7
6
5
4
3
2
1
0
Reserved
THYST3<0>
Bit 7: Hysteresis temperature bit 0, which is low Byte.
Bit 6-0: Reserved.
11.7.43 Temperature Sensor 3 Over-temperature (High Byte) Register - Index 55h (Bank 2)
Register Location:
55h
Power on Default Value
50h
Attribute:
Read/Write
Size:
8 bits
7
6
5
4
3
2
1
0
TOVF3<8:1>
Bit 7-0: Over-temperature bit 8-1, which is High Byte. The temperature default 80 degree C.
11.7.44 Temperature Sensor 3 Over-temperature (Low Byte) Register - Index 56h(Bank 2)
Register Location:
56h
Power on Default Value
00h
Attribute:
Read/Write
Size:
8 bits
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Revision 0.53
W83627HF/F
PRELIMINARY
7
6
5
4
3
2
1
0
Reserved
TOVF3<0>
Bit 7: Over-temperature bit 0, which is low Byte.
Bit 6-0: Reserved.
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PRELIMINARY
11.7.45 Interrupt Status Register 3 -- Index 50h (BANK4)
Register Location:
50h
Power on Default Value
00h
Attribute:
Read Only
Size:
8 bits
7
6
5
4
3
2
1
0
5VSB
VBAT
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Bit 7-2: Reserved.
Bit 1: A one indicates a High or Low limit of VBAT has been exceeded.
Bit 0: A one indicates a High or Low limit of 5VSB has been exceeded.
11.7.46 SMI# Mask Register 3 -- Index 51h (BANK 4)
Register Location:
51h
Power on Default Value
00h
Attribute:
Read/Write
Size:
8 bits
7
6
5
4
3
2
1
0
5VSB
VBAT
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Bit 7-2: Reserved.
Bit 1: A one disables the corresponding interrupt status bit for SMI interrupt.
Bit 0: A one disables the corresponding interrupt status bit for SMI interrupt.
11.7.47 Reserved Register -- Index 52h (Bank 4)
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PRELIMINARY
11.7.48 BEEP Control Register 3-- Index 53h (Bank 4)
Register Location:
53h
Power on Default Value
00h
Attribute:
Read/Write
Size:
8 bits
7
6
5
4
3
2
1
0
EN_5VSB_BP
EN_VBAT_BP
Reserved
Reserved
Reserved
EN_USER_BP
Reserved
Reserved
Bit 7-6: Reserved.
Bit 5: User define BEEP output function. Write 1, the BEEP is always active. Write 0, this function is
inactive. (Default 0)
Bit 4-2: Reserved.
Bit 1: Enable BEEP output from VBAT. Write 1, enable BEEP output, which is default value.
Bit 0: Enable BEEP Output from 5VSB. Write 1, enable BEEP output, which is default value.
11.7.49 Temperature Sensor 1 Offset Register -- Index 54h (Bank 4)
Register Location:
54h
Power on Default Value
00h
Attribute:
Read/Write
Size:
8 bits
7
6
5
4
3
2
1
0
OFFSET1<7:0>
Bit 7-0: Temperature 1 base temperature. The temperature is added by both monitor value and offset
value.
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W83627HF/F
PRELIMINARY
11.7.50 Temperature Sensor 2 Offset Register -- Index 55h (Bank 4)
Register Location:
55h
Power on Default Value
00h
Attribute:
Read/Write
Size:
8 bits
OFFSET2<7:0>
Bit 7-0: Temperature 2 base temperature. The temperature is added by both monitor value and offset
value.
11.7.51 Temperature Sensor 3 Offset Register -- Index 56h (Bank 4)
Register Location:
56h
Power on Default Value
00h
Attribute:
Read/Write
Size:
8 bits
OFFSET3<7:0>
Bit 7-0: Temperature 3 base temperature. The temperature is added by both monitor value and offset
value.
11.7.52 Reserved Register -- Index 57h--58h
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PRELIMINARY
11.7.53 Real Time Hardware Status Register I -- Index 59h (Bank 4)
Register Location:
59h
Power on Default Value
00h
Attribute:
Read Only
Size:
8 bits
7
6
5
4
3
2
1
0
VCOREA_STS
VCOREB_STS
+3.3VIN_STS
+5VIN_STS
TEMP1_STS
TEMP2_STS
FAN1_STS
FAN2_STS
Bit 7: FAN 2 Status. Set 1, the fan speed counter is over the limit value. Set 0, the fan speed counter
is in the limit range.
Bit 6: FAN 1 Status. Set 1, the fan speed counter is over the limit value. Set 0, the fan speed counter
is in the limit range.
Bit 5: Temperature sensor 2 Status. Set 1, the voltage of temperature sensor is over the limit value.
Set 0, the voltage of temperature sensor is in the limit range.
Bit 4: Temperature sensor 1 Status. Set 1, the voltage of temperature sensor is over the limit value.
Set 0, the voltage of temperature sensor is in the limit range.
Bit 3: +5V Voltage Status. Set 1, the voltage of +5V is over the limit value. Set 0, the voltage of +5V
is in the limit range.
Bit 2: +3.3V Voltage Status. Set 1, the voltage of +3.3V is over the limit value. Set 0, the voltage of
+3.3V is in the limit range.
Bit 1: VCOREB Voltage Status. Set 1, the voltage of VCOREB is over the limit value. Set 0, the
voltage of
VCOREB is in the limit range.
Bit 0: VCOREA Voltage Status. Set 1, the voltage of VCORE A is over the limit value. Set 0, the
voltage of VCORE A is in the limit range.
11.7.54 Real Time Hardware Status Register II -- Index 5Ah (Bank 4)
Register Location:
5Ah
Power on Default Value
00h
Attribute:
Read Only
Size:
8 bits
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Revision 0.53
W83627HF/F
PRELIMINARY
7
6
5
4
3
2
1
0
+12VIN_STS
-5VIN_STS
FAN3_STS
TEMP3_STS
Reserved
Bit 7 6: Reserved
Bit 5: Temperature sensor 3 Status. Set 1, the voltage of temperature sensor is over the limit value.
Set 0, the voltage of temperature sensor is in the limit range.
Bit 4: Case Open Status. Set 1, the case open sensor is sensed the high value. Set 0
Bit 3: FAN3 Voltage Status. Set 1, the fan speed counter is over the limit value. Set 0, the fan speed
counter is during the limit range.
s. Set 1, the voltage of during the limit range.
12V is during the limit range.
-5V is
-12V is over the limit value. Set 0, the voltage of
Bit 0: +12V Voltage Status. Set 1, the voltage of +12V is over the limit value. Set 0, the voltage of
+12V is in the limit range.
Real Time Hardware Status Register III
Register Location:
Index 5Bh (Bank 4
5B
Power on
00h
Read Only
Size:
7
6
5
4
3
2
1
0
5VSB_STS
VBAT_STS
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Bit 7Bit 1:
VBAT is during the limit range.
Bit 0: 5VSB Voltage Status. Set 1, the voltage of 5VSB is over the limit value. Set 0, the voltage of
5VSB is in the limit range.
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W83627HF/F
PRELIMINARY
11.7.56 Reserved Register -- Index 5Ch (Bank 4)
11.7.57 VID Output Register -- Index 5Dh (Bank 4)
Register Location:
5Dh
Power on Default Value
<7:0> = 0000,0000h
Attribute:
Read/Write
Size:
8 bits
7
6
5
4
3
2
1
0
VIDOUT_0
VIDOUT_1
VIDOUT_2
VIDOUT_3
VIDOUT_4
Reserved
Reserved
VIDOUT_EN
Bit 7: VID Output Enable. Set 1, enable VID pins to output. Set 0, disable VID pins to output. Default
is
0.
Bit 6-5: Reserved.
Bit 4-0: Set 1, VID pins drive a 1 . Set 0, VID pins drive a 0. Default is 0.
11.7.58 Value RAM 2 Index 50h - 5Ah (auto-increment) (BANK 5)
Address A6-A0
Description
Auto-Increment
50h
5VSB reading
51h
VBAT reading
52h
Reserved
53h
Reserved
54h
5VSB High Limit
55h
5VSB Low Limit.
56h
VBAT High Limit
57h
VBAT Low Limit
11.7.59 Winbond Test Register -- Index 50h (Bank 6)
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W83627HF/F
PRELIMINARY
12. SERIAL IRQ
W83627HF supports a serial IRQ scheme. This allow a signal line to be used to report the legacy ISA
interrupt rerquests. Because more than one device may need to share the signal serial IRQ signal
line, an open drain signal scheme is used. The clock source is the PCI clock. The serial interrupt is
transfered on the IRQSER signal, one cycle consisting of three frames types: a start frame, several
IRQ/Data frame, and one Stop frame.
12.1
Start Frame
There are two modes of operation for the IRQSER Start frame: Quiet mode and Continuous mode.
In the Quiet mode, the peripheral drives the SERIRQ signal active low for one clock, and then tristates it. This brings all the states machines of the peripherals from idle to active states. The host
controller will then take over driving IRQSER signal low in the next clock and will continue driving the
IRQSER low for programmable 3 to 7 clock periods. This makes the total number of clocks low for 4
to 8 clock periods. After these clocks, the host controller will drive the IRQSER high for one clock
and then tri-states it.
In the Continuous mode, only the host controller initiates the START frame to update IRQ/Data line
information. The host controller drives the IRQSER signal low for 4 to 8 clock periods. Upon a reset,
the IRQSER signal is defaulted to the Continuous mode for the host controller to initiate the first Start
frame.
12.2
IRQ/Data Frame
Once the start frame has been initiated, all the peripherals must start counting frames based on the
rsing edge of the start pulse. Each IRQ/Data Frame is three clocks: Sample phase, Recovery phase,
and Turn-around phase.
During the Sample phase, the peripheral drives SERIRQ low if the corresponding IRQ is active. If the
corresponding IRQ is inactive, then IRQSER must be left tri-stated. During the Recovery phase, the
peripheral device drives the IRQSER high. During the Turn-around phase, the peripheral device left
the IRQSER tri-stated.
The IRQ/Data Frame has a number of specific order, as shown in Table 3-1.
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PRELIMINARY
Table 12-2 IRQSER Sampling periods
12.3
IRQ/Data Frame
Signal Sampled
# of clocks past Start
1
IRQ0
2
2
IRQ1
5
3
SMI
8
4
IRQ3
11
5
IRQ4
14
6
IRQ5
17
7
IRQ6
20
8
IRQ7
23
9
IRQ8
26
10
IRQ9
29
11
IRQ10
32
12
IRQ11
35
13
IRQ12
38
14
IRQ13
41
15
IRQ14
44
16
IRQ15
47
17
IOCHCK
50
18
INTA
53
19
INTB
56
20
INTC
59
21
INTD
62
32:22
Unassigned
95
Stop Frame
After all IRQ/Data Frames have completed, the host controller will terminate IRQSER by a Stop
frame. Only the host controller can initiate the Stop frame by driving IRQSER low for 2 or 3 clocks. If
the Stop Frame is low for 2 clocks, the next IRQSER cycle's Sample mode is the Quiet mode. If the
Stop Frame is low for 3 clocks, the next IRQSER cycle's Sample mode is the Continuous mode.
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Revision 0.53
W83627HF/F
PRELIMINARY
13. CONFIGURATION REGISTER
13.1 Chip (Global) Control Register
CR02 (Default 0x00)
Bit 7 - 1: Reserved.
Bit 0: SWRST --> Soft Reset.
CR07
Bit 7 - 0: LDNB7 - LDNB0 --> Logical Device Number Bit 7 - 0
CR20
Bit 7 - 0: DEVIDB7 - DEBIDB0 --> Device ID Bit 7 - Bit 0 = 0x52 (read only).
CR21
Bit 7 - 0: DEVREVB7 - DEBREVB0 --> Device Rev Bit 7 - Bit 0 = 0x1y (read only, y is version no).
CR22 (Default 0xff)
Bit 7: Reserved.
Bit 6: HMPWD
= 0 Power down
= 1 No Power down
Bit 5: URBPWD
= 0 Power down
= 1 No Power down
Bit 4: URAPWD
= 0 Power down
= 1 No Power down
Bit 3: PRTPWD
= 0 Power down
= 1 No Power down
Bit 2, 1: Reserved.
Bit 0: FDCPWD
= 0 Power down
= 1 No Power down
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Revision 0.53
W83627HF/F
PRELIMINARY
CR23 (Default 0x00)
Bit 7 - 1: Reserved.
Bit 0: IPD (Immediate Power Down). When set to 1, it will put the whole chip into power down
mode immediately.
CR24 (Default 0b1s000s0s)
Bit 7: EN16SA
= 0 12 bit Address Qualification
= 1 16 bit Address Qualification
Bit 6: CLKSEL
= 0 The clock input on Pin 1 should be 24 Mhz.
= 1 The clock input on Pin 1 should be 48 Mhz.
The corresponding power-on setting pin is SOUTB (pin 83).
Bit 5 - 3: Reserved.
Bit 2: ENKBC
= 0 KBC is disabled after hardware reset.
= 1 KBC is enabled after hardware reset.
This bit is read only, and set/reset by power-on setting pin. The corresponding power-on
setting pin is SOUTA (pin 54).
Bit 1: Reserved
Bit 0: PNPCSV
= 0 The Compatible PnP address select registers have default values.
= 1 The Compatible PnP address select registers have no default value.
When trying to make a change to this bit, new value of PNPCVS must be complementary to
the old one to make an effective change. For example, the user must set PNPCVS to 0 first
and then reset it to 1 to reset these PnP registers if the present value of PNPCVS is 1. The
corresponding power-on setting pin is NDTRA (pin 52).
CR25 (Default 0x00)
Bit 7 - 6: Reserved
Bit 5: URBTRI
Bit 4: URATRI
Bit 3: PRTTRI
Bit 2 - 1 : Reserved
Bit 0: FDCTRI.
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W83627HF/F
PRELIMINARY
CR26 (Default 0b0s000000)
Bit 7: SEL4FDD
=0
Select two FDD mode.
=1
Select four FDD mode.
Bit 6: HEFRAS
These two bits define how to enable Configuration mode. The corresponding power-on
setting pin is NRTSA (pin 51).
HEFRAS Address and Value
= 0 Write 87h to the location 2E twice.
= 1 Write 87h to the location 4Etwice.
Bit 5: LOCKREG
= 0 Enable R/W Configuration Registers.
= 1 Disable R/W Configuration Registers.
Bit 4:Reserve
Bit 3: DSFDLGRQ
= 0 Enable FDC legacy mode on IRQ and DRQ selection, then DO register bit 3 is effective
on selecting IRQ
= 1 Disable FDC legacy mode on IRQ and DRQ selection, then DO register bit 3 is not
effective on selecting IRQ
Bit 2: DSPRLGRQ
= 0 Enable PRT legacy mode on IRQ and DRQ selection, then DCR bit 4 is effective on
selecting IRQ
= 1 Disable PRT legacy mode on IRQ and DRQ selection, then DCR bit 4 is not effective
on selecting IRQ
Bit 1: DSUALGRQ
= 0 Enable UART A legacy mode IRQ selecting, then MCR bit 3 is effective on selecting
IRQ
= 1 Disable UART A legacy mode IRQ selecting, then MCR bit 3 is not effective on
selecting IRQ
Bit 0: DSUBLGRQ
= 0 Enable UART B legacy mode IRQ selecting, then MCR bit 3 is effective on selecting
IRQ
= 1 Disable UART B legacy mode IRQ selecting, then MCR bit 3 is not effective on
selecting IRQ
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Revision 0.53
W83627HF/F
PRELIMINARY
CR28 (Default 0x00)
Bit 7 - 3: Reserved.
Bit 2 - 0: PRTMODS2 - PRTMODS0
= 0xx Parallel Port Mode
= 100 Reserved
= 101 External FDC Mode
= 110 Reserved
= 111 External two FDC Mode
CR29 (GPIO3 multiplexed pin selection register. VBAT powered. Default 0x00)
Bit 7: PIN64S
=0
SUSLED (SUSLED control bits are in CRF3 of Logical Device 9)
=1
GP35
Bit 6: PIN69S
= 00
CIRRX#
= 01
GP34
Bit 5: PIN70S
=0
RSMRST#
=1
GP33
Bit 4: PIN71S
=0
PWROK
=1
GP32
Bit 3: PIN72S
=0
PWRCTL#
=1
GP31
Bit 2: PIN 73S
=0
SLP_SX#
=1
GP30
Bit 1: Reserved
Bit 0: Reserved
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Revision 0.53
W83627HF/F
PRELIMINARY
CR2A (GPIO multiplexed pin selection register 1. VCC powered. Default 0X7C)
Bit 7: Port Select (select Game Port or General Purpose I/O Port 1)
=0
Game Port
=1
General Purpose I/O Port 1 (pin121~128 select function GP10~GP17 or KBC Port 1)
Bit 6: PIN128S
=0
8042 P12
=1
GP10
Bit 5: PIN127S
=0
8042 P13
=1
GP11
Bit 4: PIN126S
=0
8042 P14
=1
GP12
Bit 3: PIN125S
=0
8042 P15
=1
GP13
Bit 2: PIN124S
=0
8042 P16
=1
GP14
Bit 1: PIN120S
=0
MSO (MIDI Serial Output)
=1
IRQIN0 (select IRQ resource through CRF4 Bit 7-4 of Logical Device 8)
Bit 1: PIN119S
=0
MS1 (MIDI Serial Input)
=1
GP20
CR2B(GPIO multiplexed pin selection register 2. VCC powered. Default 0XC0)
Bit 7:PIN92S
=0
SCL
=1
GP21
Bit 6:PIN91S
=0
SDA
=1
GP22
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Revision 0.53
W83627HF/F
PRELIMINARY
Bit 5: PIN90S
=0
PLED (PLED0 control bits are in CRF5 of Logical Device 8)
=1
GP23
Bit 4: PIN89S
=0
WDTO (Watch Dog Timer is controlled by CRF5, CRF6, CRF7 of Logical Device 8)
=1
GP24
Bit 3: PIN88S
=0
IRRX
=1
GP25
Bit 2: PIN87S
=0
IRTX
=1
GP26
Bit 1-0:PIN 2S
= 00
DRVDEN1
= 01
IRQIN1 (select IRQ resource through CRF4 Bit 7-4 of Logical Device8)
SMI# (For D version only)
= 10
Reserved
= 11
GP27
CR2C (Default 0x00)
Reserved
CR2E (Default 0x00)
Test Modes: Reserved for Winbond.
CR2F (Default 0x00)
Test Modes: Reserved for Winbond.
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PRELIMINARY
13.2 Logical Device 0 (FDC)
CR30 (Default 0x01 if PNPCSV = 0 during POR, default 0x00 otherwise)
Bit 7 - 1: Reserved.
Bit 0: = 1 Activates the logical device.
= 0 Logical device is inactive.
CR60, CR 61 (Default 0x03, 0xf0 if PNPCSV = 0 during POR, default 0x00, 0x00 otherwise)
These two registers select FDC I/O base address [0x100:0xFF8] on 8 byte boundary.
CR70 (Default 0x06 if PNPCSV = 0 during POR, default 0x00 otherwise)
Bit 7 - 4: Reserved.
Bit 3 - 0: These bits select IRQ resource for FDC.
CR74 (Default 0x02 if PNPCSV = 0 during POR, default 0x04 otherwise)
Bit 7 - 3: Reserved.
Bit 2 - 0: These bits select DRQ resource for FDC.
= 0x00 DMA0
= 0x01 DMA1
= 0x02 DMA2
= 0x03 DMA3
= 0x04 - 0x07 No DMA active
CRF0 (Default 0x0E)
FDD Mode Register
Bit 7: FIPURDWN
This bit controls the internal pull-up resistors of the FDC input pins RDATA, INDEX, TRAK0,
DSKCHG, and WP.
=0
The internal pull-up resistors of FDC are turned on.(Default)
=1
The internal pull-up resistors of FDC are turned off.
Bit 6: INTVERTZ
This bit determines the polarity of all FDD interface signals.
=0
FDD interface signals are active low.
=1
FDD interface signals are active high.
Bit 5: DRV2EN (PS2 mode only)
When this bit is a logic 0, indicates a second drive is installed and is reflected in status register A.
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W83627HF/F
PRELIMINARY
Bit 4: Swap Drive 0, 1 Mode
=0
No Swap (Default)
=1
Drive and Motor sel 0 and 1 are swapped.
Bit 3 - 2 Interface Mode
= 11
AT Mode (Default)
= 10 (Reserved)
= 01 PS/2
= 00 Model 30
Bit 1: FDC DMA Mode
= 0 Burst Mode is enabled
= 1 Non-Burst Mode (Default)
Bit 0: Floppy Mode
= 0 Normal Floppy Mode (Default)
= 1 Enhanced 3-mode FDD
CRF1 (Default 0x00)
Bit 7 - 6: Boot Floppy
= 00 FDD A
= 01 FDD B
= 10 FDD C
= 11 FDD D
Bit 5, 4: Media ID1, Media ID0. These bits will be reflected on FDC's Tape Drive Register bit 7, 6.
Bit 3 - 2: Density Select
= 00 Normal (Default)
= 01 Normal
= 10 1 ( Forced to logic 1)
= 11 0 ( Forced to logic 0)
Bit 1: DISFDDWR
= 0 Enable FDD write.
= 1 Disable FDD write(forces pins WE, WD stay high).
Bit 0: SWWP
= 0 Normal, use WP to determine whether the FDD is write protected or not.
= 1 FDD is always write-protected.
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W83627HF/F
PRELIMINARY
CRF2 (Default 0xFF)
Bit 7 - 6: FDD D Drive Type
Bit 5 - 4: FDD C Drive Type
Bit 3 - 2: FDD B Drive Type
Bit 1 - 0: FDD A Drive Type
CRF4 (Default 0x00)
FDD0 Selection:
Bit 7: Reserved.
Bit 6: Precomp. Disable.
= 1 Disable FDC Precompensation.
= 0 Enable FDC Precompensation.
Bit 5: Reserved.
Bit 4 - 3: DRTS1, DRTS0: Data Rate Table select (Refer to TABLE A).
= 00 Select Regular drives and 2.88 format
= 01 3-mode drive
= 10 2 Meg Tape
= 11 Reserved
Bit 2: Reserved.
Bit 1:0: DTYPE0, DTYPE1: Drive Type select (Refer to TABLE B).
CRF5 (Default 0x00)
FDD1 Selection: Same as FDD0 of CRF4.
TABLE A
Drive Rate Table
Select
DRTS1
DRTS0
0
0
0
1
1
0
Data Rate
DRATE1
1
0
0
1
1
0
0
1
1
0
0
1
Selected Data Rate
DRATE0
1
0
1
0
1
0
1
0
1
0
1
0
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MFM
1Meg
500K
300K
250K
1Meg
500K
500K
250K
1Meg
500K
2Meg
250K
FM
--250K
150K
125K
--250K
250K
125K
--250K
--125K
SELDEN
1
1
0
0
1
1
0
0
1
1
0
0
Publication Release Date: Jul 1999
Revision 0.53
W83627HF/F
PRELIMINARY
TABLE B
DTYPE0
0
DTYPE1
0
DRVDEN0(pin 2)
SELDEN
DRVDEN1(pin 3)
DRATE0
0
1
1
0
DRATE1
DRATE0
DRATE0
1
1
SELDEN
DRATE0
DRIVE TYPE
4/2/1 MB 3.5” “
2/1 MB 5.25”
2/1.6/1 MB 3.5” (3-MODE)
DRATE1
13.3 Logical Device 1 (Parallel Port)
CR30 (Default 0x01 if PNPCSV = 0 during POR, default 0x00 otherwise)
Bit 7 - 1: Reserved.
Bit 0:
= 1 Activates the logical device.
= 0 Logical device is inactive.
CR60, CR 61 (Default 0x03, 0x78 if PNPCSV = 0 during POR, default 0x00, 0x00 otherwise)
These two registers select Parallel Port I/O base address.
[0x100:0xFFC] on 4 byte boundary (EPP not supported) or
[0x100:0xFF8] on 8 byte boundary (all modes supported, EPP is only available when the base
address is on 8 byte boundary).
CR70 (Default 0x07 if PNPCSV = 0 during POR, default 0x00 otherwise)
Bit 7 - 4: Reserved.
Bit [3:0]: These bits select IRQ resource for Parallel Port.
CR74 (Default 0x04)
Bit 7 - 3: Reserved.
Bit 2 - 0: These bits select DRQ resource for Parallel Port.
0x00=DMA0
0x01=DMA1
0x02=DMA2
0x03=DMA3
0x04 - 0x07= No DMA active
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W83627HF/F
PRELIMINARY
CRF0 (Default 0x3F)
Bit 7: Reserved.
Bit 6 - 3: ECP FIFO Threshold.
Bit 2 - 0: Parallel Port Mode (CR28 PRTMODS2 = 0)
= 100 Printer Mode (Default)
= 000 Standard and Bi-direction (SPP) mode
= 001 EPP - 1.9 and SPP mode
= 101 EPP - 1.7 and SPP mode
= 010 ECP mode
= 011 ECP and EPP - 1.9 mode
= 111 ECP and EPP - 1.7 mode.
13.4 Logical Device 2 (UART A)¢ )
CR30 (Default 0x01 if PNPCSV = 0 during POR, default 0x00 otherwise)
Bit 7 - 1: Reserved.
Bit 0: = 1 Activates the logical device.
= 0 Logical device is inactive.
CR60, CR 61 (Default 0x03, 0xF8 if PNPCSV = 0 during POR, default 0x00, 0x00 otherwise)
These two registers select Serial Port 1 I/O base address [0x100:0xFF8] on 8 byte boundary.
CR70 (Default 0x04 if PNPCSV = 0 during POR, default 0x00 otherwise)
Bit 7 - 4: Reserved.
Bit 3 - 0: These bits select IRQ resource for Serial Port 1.
CRF0 (Default 0x00)
Bit 7 - 2: Reserved.
Bit 1 - 0: SUACLKB1, SUACLKB0
= 00
UART A clock source is 1.8462 Mhz (24MHz/13)
= 01
UART A clock source is 2 Mhz (24MHz/12)
= 10
UART A clock source is 24 Mhz (24MHz/1)
= 11
UART A clock source is 14.769 Mhz (24mhz/1.625)
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W83627HF/F
PRELIMINARY
13.5 Logical Device 3 (UART B)
CR30 (Default 0x01 if PNPCSV = 0 during POR, default 0x00 otherwise)
Bit 7 - 1: Reserved.
Bit 0: = 1 Activates the logical device.
= 0 Logical device is inactive.
CR60, CR 61 (Default 0x02, 0xF8 if PNPCSV = 0 during POR, default 0x00, 0x00 otherwise)
These two registers select Serial Port 2 I/O base address [0x100:0xFF8] on 8 byte boundary.
CR70 (Default 0x03 if PNPCSV = 0 during POR, default 0x00 otherwise)
Bit 7 - 4: Reserved.
Bit [3:0]: These bits select IRQ resource for Serial Port 2.
CRF0 (Default 0x00)
Bit 7 - 4: Reserved.
Bit 3: RXW4C
=0
No reception delay when SIR is changed from TX mode to RX mode.
=1
Reception delays 4 characters-time (40 bit-time) when SIR is changed from TX mode
to RX mode.
Bit 2: TXW4C
=0
No transmission delay when SIR is changed from RX mode to TX mode.
=1
Transmission delays 4 characters-time (40 bit-time) when SIR is changed from RX
mode to TX mode.
Bit 1 - 0: SUBCLKB1, SUBCLKB0
= 00
UART B clock source is 1.8462 Mhz (24MHz/13)
= 01
UART B clock source is 2 Mhz (24MHz/12)
= 10
UART B clock source is 24 Mhz (24MHz/1)
= 11
UART B clock source is 14.769 Mhz (24mhz/1.625)
CRF1 (Default 0x00)
Bit 7: Reserved.
Bit 6: IRLOCSEL. IR I/O pins' location select.
=0
Through SINB/SOUTB.
=1
Through IRRX/IRTX.
Bit 5: IRMODE2. IR function mode selection bit 2.
Bit 4: IRMODE1. IR function mode selection bit 1.
Bit 3: IRMODE0. IR function mode selection bit 0.
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Revision 0.53
W83627HF/F
PRELIMINARY
IR MODE
IR FUNCTION
IRTX
IRRX
00X
Disable
tri-state
high
010*
IrDA
Active pulse 1.6 µS
Demodulation into SINB/IRRX
011*
IrDA
Active pulse 3/16 bit time
Demodulation into SINB/IRRX
100
ASK-IR
Inverting IRTX/SOUTB pin
routed to SINB/IRRX
101
ASK-IR
Inverting IRTX/SOUTB & 500
KHZ clock
routed to SINB/IRRX
110
ASK-IR
Inverting IRTX/SOUTB
Demodulation into SINB/IRRX
111*
ASK-IR
Inverting IRTX/SOUTB & 500
KHZ clock
Demodulation into SINB/IRRX
Note: The notation is normal mode in the IR function.
Bit 2: HDUPLX. IR half/full duplex function select.
=0
The IR function is Full Duplex.
=1
The IR function is Half Duplex.
Bit 1: TX2INV.
=0
the SOUTB pin of UART B function or IRTX pin of IR function in normal condition.
=1
inverse the SOUTB pin of UART B function or IRTX pin of IR function.
Bit 0: RX2INV.
=0
the SINB pin of UART B function or IRRX pin of IR function in normal condition.
=1
inverse the SINB pin of UART B function or IRRX pin of IR function
13.6 Logical Device 5 (KBC)
CR30 (Default 0x01 if PNPCSV = 0 during POR, default 0x00 otherwise)
Bit 7 - 1: Reserved.
Bit 0: = 1 Activates the logical device.
= 0 Logical device is inactive.
CR60, CR 61 (Default 0x00, 0x60 if PNPCSV = 0 during POR, default 0x00 otherwise)
These two registers select the first KBC I/O base address [0x100:0xFFF] on 1 byte boundary.
CR62, CR 63 (Default 0x00, 0x64 if PNPCSV = 0 during POR, default 0x00 otherwise)
These two registers select the second KBC I/O base address [0x100:0xFFF] on 1 byte boundary.
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PRELIMINARY
CR70 (Default 0x01 if PNPCSV = 0 during POR, default 0x00 otherwise)
Bit 7 - 4: Reserved.
Bit [3:0]: These bits select IRQ resource for KINT (keyboard).
CR72 (Default 0x0C if PNPCSV = 0 during POR, default 0x00 otherwise)
Bit 7 - 4: Reserved.
Bit [3:0]: These bits select IRQ resource for MINT (PS2 Mouse)
CRF0 (Default 0x80)
Bit 7 - 6: KBC clock rate selection
= 00 Select 6MHz as KBC clock input.
= 01 Select 8MHz as KBC clock input.
= 10 Select 12Mhz as KBC clock input.
= 11 Select 16Mhz as KBC clock input.
(W83627HF/F-AW can support these 4 kinds of clock input, but W83627HF/F-PW only
support 12MHz clock input)
Bit 5 - 3: Reserved.
Bit 2: = 0 Port 92 disable.
= 1 Port 92 enable.
Bit 1: = 0 Gate20 software control.
= 1 Gate20 hardware speed up.
Bit 0: = 0 KBRST software control.
= 1 KBRST hardware speed up.
13.7 Logical Device 6 (CIR)
CR30 (Default 0x00)
Bit 7 - 1: Reserved.
Bit 0: = 1 Activates the logical device.
= 0 Logical device is inactive.
CR60, CR 61 (Default 0x00, 0x00)
These two registers select CIR I/O base address [0x100:0xFF8] on 8 byte boundary.
CR70 (Default 0x00)
Bit 7 - 4: Reserved.
Bit [3:0]: These bits select IRQ resource for CIR.
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W83627HF/F
PRELIMINARY
13.8 Logical Device 7 (Game Port and MIDI Port and GPIO Port 1)
CR30 (Default 0x00)
Bit 7 - 1: Reserved.
Bit 0: = 1 Activate Game Port and MIDI Port.
= 0 Game Port and MIDI Port is inactive.
CR60, CR 61 (Default 0x02, 0x01 if PNPCSV = 0 during POR, default 0x00 otherwise)
These two registers select the Game Port base address [0x100:0xFFF] on 1 byte boundary.
CR62, CR 63 (Default 0x03, 0x30 if PNPCSV = 0 during POR, default 0x00 otherwise)
These two registers select the MIDI Port base address [0x100:0xFFF] on 2 byte boundary.
CR70 (Default 0x09 if PNPCSV = 0 during POR, default 0x00 otherwise)
Bit 7 - 4: Reserved.
Bit [3:0]: These bits select IRQ resource for MIDI Port .
CRF0 (GP10-GP17 I/O selection register. Default 0xFF)
When set to a '1', respective GPIO port is programmed as an input port.
When set to a '0', respective GPIO port is programmed as an output port.
CRF1 (GP10-GP17 data register. Default 0x00)
If a port is programmed to be an output port, then its respective bit can be read/written.
If a port is programmed to be an input port, then its respective bit can only be read.
CRF2 (GP10-GP17 inversion register. Default 0x00)
When set to a '1', the incoming/outgoing port value is inverted.
When set to a '0', the incoming/outgoing port value is the same as in data register.
13.9 Logical Device 8 (GPIO Port 2)
CR30 (GP20-GP27 Default 0x00)
Bit 7 - 1: Reserved.
Bit 0: = 1 Activate GPIO2.
= 0 GPIO2 is inactive.
CRF0 (GP20-GP27 I/O selection register. Default 0xFF)
When set to a '1', respective GPIO port is programmed as an input port.
When set to a '0', respective GPIO port is programmed as an output port.
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PRELIMINARY
CRF1 (GP20-GP27 data register. Default 0x00)
If a port is programmed to be an output port, then its respective bit can be read/written.
If a port is programmed to be an input port, then its respective bit can only be read.
CRF2 (GP20-GP27 inversion register. Default 0x00)
When set to a '1', the incoming/outgoing port value is inverted.
When set to a '0', the incoming/outgoing port value is the same as in data register.
CRF3 (Default 0x00)
Bit 7 - 4: These bits select IRQ resource for IRQIN1.
Bit 3 - 0: These bits select IRQ resource for IRQIN0.
CRF4 (Reserved)
CRF5 (PLED mode register. Default 0x00)
Bit 7-6: select PLED mode
= 00
Power LED pin is tri-stated.
= 01
Power LED pin is drived low.
= 10
Power LED pin is a 1Hz toggle pulse with 50 duty cycle.
= 11
Power LED pin is a 1/4Hz toggle pulse with 50 duty cycle.
Bit 5-4: Reserved
Bit 3: select WDTO count mode.
=0
second
=1
minute
Bit 2: Enable the rising edge of keyboard Reset(P20) to force Time-out event.
=0
Disable
=1
Enable
Bit 1-0: Reserved
CRF6 (Default 0x00)
Watch Dog Timer Time-out value. Writing a non-zero value to this register causes the counter
to load the value to Watch Dog Counter and start counting down. If the Bit 7 and Bit 6 are set,
any Mouse Interrupt or Keyboard Interrupt event will also cause the reload of previously-loaded
non-zero value to Watch Dog Counter and start counting down. Reading this register returns
current value in Watch Dog Counter instead of Watch Dog Timer Time-out value.
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W83627HF/F
PRELIMINARY
Bit 7 - 0:
= 0x00 Time-out Disable
= 0x01 Time-out occurs after 1 second/minute
= 0x02 Time-out occurs after 2 second/minutes
= 0x03 Time-out occurs after 3 second/minutes
................................................
= 0xFF Time-out occurs after 255 second/minutes
CRF7 (Default 0x00)
Bit 7: Mouse interrupt reset Enable or Disable
= 1 Watch Dog Timer is reset upon a Mouse interrupt
= 0 Watch Dog Timer is not affected by Mouse interrupt
Bit 6: Keyboard interrupt reset Enable or Disable
= 1 Watch Dog Timer is reset upon a Keyboard interrupt
= 0 Watch Dog Timer is not affected by Keyboard interrupt
Bit 5: Force Watch Dog Timer Time-out, Write only*
= 1 Force Watch Dog Timer time-out event; this bit is self-clearing.
Bit 4: Watch Dog Timer Status, R/W
= 1 Watch Dog Timer time-out occurred.
= 0 Watch Dog Timer counting
Bit 3 -0: These bits select IRQ resource for Watch Dog. Setting of 2 selects SMI.
13.10 Logical Device 9 (GPIO Port 3 This power of the Port is standby source (VSB) )
CR30 (Default 0x00)
Bit 7 - 1: Reserved.
Bit 0: = 1 Activate GPIO3.
= 0 GPIO3 is inactive.
CRF0 (GP30-GP35 I/O selection register. Default 0xFF Bit 7-6: Reserve)
When set to a '1', respective GPIO port is programmed as an input port.
When set to a '0', respective GPIO port is programmed as an output port.
CRF1 (GP30-GP35 data register. Default 0x00 Bit 7-6: Reserve)
If a port is programmed to be an output port, then its respective bit can be read/written.
If a port is programmed to be an input port, then its respective bit can only be read.
CRF2 (GP30-GP35 inversion register. Default 0x00 Bit 7-6: Reserve)
When set to a '1', the incoming/outgoing port value is inverted.
When set to a '0', the incoming/outgoing port value is the same as in data register.
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W83627HF/F
PRELIMINARY
CRF3 (SUSLED mode register. Default 0x00)
Bit 7-6: select Suspend LED mode
= 00
Suspend LED pin is drived low.
= 01
Suspend LED pin is tri-stated.
= 10
Suspend LED pin is a 1Hz toggle pulse with 50 duty cycle.
= 11
Suspend LED pin is a 1/4Hz toggle pulse with 50 duty cycle.
This mode selection bit 7-6 keep its settings until battery power loss.
Bit 5 - 0: Reserved.
13.11 Logical Device A (ACPI)
CR30 (Default 0x00)
Bit 7 - 1: Reserved.
Bit 0: = 1 Activates the logical device.
= 0 Logical device is inactive.
CR70 (Default 0x00)
Bit 7 - 4: Reserved.
Bit 3 - 0: These bits select IRQ resources for PME .
CRE0 (Default 0x00)
Bit 7: DIS-PANSW_IN. Disable panel switch input to turn system power supply on.
=0
PANSW_IN is wire-ANDed and connected to PANSW_OUT.
=1
PANSW_IN is blocked and can not affect PANSW_OUT.
Bit 6: ENKBWAKEUP. Enable Keyboard to wake-up system via PANSW_OUT.
=0
Disable Keyboard wake-up function.
=1
Enable Keyboard wake-up function.
Bit 5: ENMSWAKEUP. Enable Mouse to wake-up system via PANSW_OUT.
=0
Disable Mouse wake-up function.
=1
Enable Mouse wake-up function.
Bit 4: MSRKEY. Select Mouse Left/Right Botton to wake-up system via PANSW_OUT.
=0
Select click on Mouse Left-botton twice to wake the system up.
=1
Select click on Mouse right-botton twice to wake the system up.
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Revision 0.53
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PRELIMINARY
Bit 3: ENCIRWAKEUP. Enable CIR to wake-up system via PANSW_OUT.
=0
Disable CIR wake-up function.
=1
Enable CIR wake-up function.
Bit 2: KB/MS Swap. Enable Keyboard/Mouse port-swap.
=0
Keyboard/Mouse ports are not swapped.
=1
Keyboard/Mouse ports are swapped.
Bit 1: MSXKEY. Enable any character received from Mouse to wake-up the system.
=0
Only click Mouse left/right-botton twice can wake the system up.
=1
Only click Mouse left/right-botton once can wake the system up.
Bit 0: KBXKEY. Enable any character received from Keyboard to wake-up the system.
=0
Only predetermined specific key combination can wake up the system.
=1
Any character received from Keyboard can wake up the system.
CRE1 (Default 0x00) Keyboard Wake-Up Index Register
This register is used to indicate which Keyboard Wake-Up Shift register or Predetermined key
Register is to be read/written via CRE2. The range of Keyboard wake-up index register is 0x00 0x19, and the range of CIR wake-up index register is 0x20 - 0x2F.
CRE2 Keyboard Wake-Up Data Register
This register holds the value of wake-up key register indicated by CRE1. This register can be
read/written.
CRE3 (Read only) Keyboard/Mouse Wake-Up Status Register
Bit 7-5: Reserved.
Bit 4: PWRLOSS_STS: This bit is set when power loss occurs.
Bit 3: CIR_STS. The Panel switch event is caused by CIR wake-up event. This bit is cleared by
reading this register.
Bit 2: PANSW_STS. The Panel switch event is caused by PANSW_IN. This bit is cleared by
reading this register.
Bit 1: Mouse_STS. The Panel switch event is caused by Mouse wake-up event. This bit is
cleared by reading this register.
Bit 0: Keyboard_STS. The Panel switch event is caused by Keyboard wake-up event. This bit is
cleared by reading this register.
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Revision 0.53
W83627HF/F
PRELIMINARY
CRE4 (Default 0x00)
Bit 7: Power loss control bit 2.
0 = Disable ACPI resume.
1 = Enable ACPI resume.
Bit 6-5: Power loss control bit <1:0>
00 = System always turn off when come back from power loss state.
01 = System always turn on when come back from power loss state.
10 = System turn on/off when come back from power loss state depend on the state
before power loss.
11 = Reserved.
Bit 4: Suspend clock source select
0 = Use internal clock source.
1 = Use external suspend clock source(32.768KHz).
Bit 3: Keyboard wake-up type select for wake-up the system from S1/S2.
0 = Password or Hot keys programmed in the registers.
1 =Any key.
Bit 2: Enable all wake-up event set in CRE0 can wake-up the system from S1/S2 state. This
bit is cleared when wake-up event occurs.
0 = Disable.
1 = Enable.
Bit 1 - 0: Reserved.
CRE5 (Default 0x00)
Bit 7: Reserved.
Bit 6 - 0: Compared Code Length. When the compared codes are storaged in the data register,
these data length should be written to this register.
CRE6 (Default 0x00)
Bit 7 - 6: Reserved.
Bit 5 - 0: CIR Baud Rate Divisor. The clock base of CIR is 32khz, so that the baud rate is 32khz
divided by ( CIR Baud Rate Divisor + 1).
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Revision 0.53
W83627HF/F
PRELIMINARY
CRE7 (Default 0x00)
Bit 7 - 3: Reserved.
Bit 2: Reset CIR Power-On function. After using CIR power-on, the software should write logical
1 to restart CIR power-on function.
Bit 1: Invert RX Data.
= 1 Inverting RX Data.
= 0 Not inverting RX Data.
Bit 0: Enable Demodulation.
= 1 Enable received signal to demodulate.
= 0 Disable received signal to demodulate.
CRF0 (Default 0x00)
Bit 7: CHIPPME. Chip level auto power management enable.
=0
disable the auto power management functions
=1
enable the auto power management functions.
Bit 6: CIRPME. Consumer IR port auto power management enable.
=0
disable the auto power management functions
=1
enable the auto power management functions.
Bit 5: MIDIPME. MIDI port auto power management enable.
=0
disable the auto power management functions
=1
enable the auto power management functions.
Bit 4: Reserved. Return zero when read.
Bit 3: PRTPME. Printer port auto power management enable.
=0
disable the auto power management functions.
=1
enable the auto power management functions.
Bit 2: FDCPME. FDC auto power management enable.
=0
disable the auto power management functions.
=1
enable the auto power management functions.
Bit 1: URAPME. UART A auto power management enable.
=0
disable the auto power management functions.
=1
enable the auto power management functions.
Bit 0: URBPME. UART B auto power management enable.
=0
disable the auto power management functions.
=1
enable the auto power management functions.
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Revision 0.53
W83627HF/F
PRELIMINARY
CRF1 (Default 0x00)
Bit 7: WAK_STS. This bit is set when the chip is in the sleeping state and an enabled resume
event occurs. Upon setting this bit, the sleeping/working state machine will transition the
system to the working state. This bit is only set by hardware and is cleared by writing a 1 to
this bit position or by the sleeping/working state machine automatically when the global
standby timer expires.
=0
the chip is in the sleeping state.
=1
the chip is in the working state.
Bit 6 - 5: Devices' trap status.
Bit 4: Reserved. Return zero when read.
Bit 3 - 0: Devices' trap status.
CRF3 (Default 0x00)
Bit 7 - 6: Reserved. Return zero when read.
Bit 5 - 0: Device's IRQ status.
These bits indicate the IRQ status of the individual device respectively. The device's IRQ status
bit is set by their source device and is cleared by writing a 1. Writing a 0 has no effect.
Bit 5: MOUIRQSTS. MOUSE IRQ status.
Bit 4: KBCIRQSTS. KBC IRQ status.
Bit 3: PRTIRQSTS. printer port IRQ status.
Bit 2: FDCIRQSTS. FDC IRQ status.
Bit 1: URAIRQSTS. UART A IRQ status.
Bit 0: URBIRQSTS. UART B IRQ status.
CRF4 (Default 0x00)
Bit 7 - 6: Reserved. Return zero when read.
Bit 5 - 0: These bits indicate the IRQ status of the individual GPIO function or logical device
respectively. The status bit is set by their source function or device and is cleared by
writing a1. Writing a 0 has no effect.
Bit 5: HMIRQSTS. Hardware monitor IRQ status.
Bit 4: WDTIRQSTS. Watch dog timer IRQ status.
Bit 3: CIRIRQSTS. Consumer IR IRQ status.
Bit 2: MIDIIRQSTS. MIDI IRQ status.
Bit 1: IRQIN1STS. IRQIN1 status.
Bit 0: IRQIN0STS. IRQIN0 status.
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Revision 0.53
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PRELIMINARY
CRF6 (Default 0x00)
Bit 7 - 6: Reserved. Return zero when read.
Bit 5 - 0: Enable bits of the SMI /PME generation due to the device's IRQ.
These bits enable the generation of an SMI / PME interrupt due to any IRQ of the devices.
SMI / PME logic output = (MOUIRQEN and MOUIRQSTS) or (KBCIRQEN and KBCIRQSTS) or
(PRTIRQEN and PRTIRQSTS) or (FDCIRQEN and FDCIRQSTS) or
(URAIRQEN and URAIRQSTS) or (URBIRQEN and URBIRQSTS) or
(HMIRQEN and HMIRQSTS) or (WDTIRQEN and WDTIRQSTS) or
(IRQIN3EN and IRQIN3STS) or (IRQIN2EN and IRQIN2STS) or
(IRQIN1EN and IRQIN1STS) or (IRQIN0EN and IRQIN0STS)
Bit 5: MOUIRQEN.
=0
disable the generation of an SMI / PME interrupt due to MOUSE's IRQ.
=1
enable the generation of an SMI / PME interrupt due to MOUSE's IRQ.
Bit 4: KBCIRQEN.
=0
disable the generation of an SMI /PME interrupt due to KBC's IRQ.
=1
enable the generation of an SMI / PME interrupt due to KBC's IRQ.
Bit 3: PRTIRQEN.
=0
disable the generation of an SMI /PME interrupt due to printer port's IRQ.
=1
enable the generation of an SMI / PME interrupt due to printer port's IRQ.
Bit 2: FDCIRQEN.
=0
disable the generation of an SMI / PME interrupt due to FDC's IRQ.
=1
enable the generation of an SMI / PME interrupt due to FDC's IRQ.
Bit 1: URAIRQEN.
=0
disable the generation of an SMI / PME interrupt due to UART A's IRQ.
=1
enable the generation of an SMI / PME interrupt due to UART A's IRQ.
Bit 0: URBIRQEN.
=0
disable the generation of an SMI /PME interrupt due to UART B's IRQ.
=1
enable the generation of an SMI / PME interrupt due to UART B's IRQ.
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Revision 0.53
W83627HF/F
PRELIMINARY
CRF7 (Default 0x00)
Bit 7 - 6: Reserved. Return zero when read.
Bit 5 - 0: Enable bits of the SMI /PME generation due to the GPIO IRQ function or device's IRQ.
Bit 5: HMIRQEN.
=0
disable the generation of an SMI /PME interrupt due to hardware monitor's IRQ.
=1
enable the generation of an SMI / PME interrupt due to hardware monitor's IRQ.
Bit 4: WDTIRQEN.
=0
disable the generation of an SMI / PME interrupt due to watch dog timer's IRQ.
=1
enable the generation of an SMI / PME interrupt due to watch dog timer's IRQ.
Bit 3: CIRIRQEN.
=0
disable the generation of an SMI / PME interrupt due to CIR's IRQ.
=1
enable the generation of an SMI /PME interrupt due to CIR's IRQ.
Bit 2: MIDIIRQEN.
=0
disable the generation of an SMI /PME interrupt due to MIDI's IRQ.
=1
enable the generation of an SMI / PME interrupt due to MIDI's IRQ.
Bit 1: IRQIN1EN.
=0
disable the generation of an SMI / PME interrupt due to IRQIN1's IRQ.
=1
enable the generation of an SMI / PME interrupt due to IRQIN1's IRQ.
Bit 0: IRQIN0EN.
=0
disable the generation of an SMI / PME interrupt due to IRQIN0's IRQ.
=1
enable the generation of an SMI / PME interrupt due to IRQIN0's IRQ.
CRF9 (Default 0x00)
Bit 7 - 3: Reserved. Return zero when read.
Bit 2: PME_EN: Select the power management events to be either an PME or SMI interrupt for
the IRQ events. Note that: this bit is valid only when SMIPME_OE = 1.
=0
the power management events will generate an SMI event.
=1
the power management events will generate an PME event.
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Revision 0.53
W83627HF/F
PRELIMINARY
Bit 1: FSLEEP: This bit selects the fast expiry time of individual devices.
=0
1 second.
=1
8 milli-seconds.
Bit 0: SMIPME_OE: This is the SMI and PME output enable bit.
=0
neither SMI nor PME will be generated. Only the IRQ status bit is set.
=1
an SMI or PME event will be generated.
CRFE, FF (Default 0x00)
Reserved for Winbond test.
13.12 Logical Device B (Hardware Monitor)
CR30 (Default 0x00)
Bit 7 - 1: Reserved.
Bit 0: = 1 Activates the logical device.
= 0 Logical device is inactive.
CR60, CR 61 (Default 0x00, 0x00)
These two registers select Hardware Monitor base address [0x100:0xFFF] on 8-byte boundary.
CR70 (Default 0x00)
Bit 7 - 4: Reserved.
Bit 3 - 0: These bits select IRQ resource for Hardware Monitor.
CRF0 (Default 0x00)
Bit 7 - 1: Reserved.
Bit 0: Disable initial abnormal beep (VcoreA and +3.3 V)
=0
Enable power-on abnormal beep
=1
Disable power-on abnormal beep
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Publication Release Date: Jul 1999
Revision 0.53
W83627HF/F
PRELIMINARY
14. SPECIFICATIONS
14.1 Absolute Maximum Ratings
PARAMETER
RATING
UNIT
-0.5 to 7.0
V
-0.5 to VDD+0.5
V
RTC Battery Voltage VBAT
2.2 to 4.0
V
Operating Temperature
0 to +70
°C
-55 to +150
°C
Power Supply Voltage (5V)
Input Voltage
Storage Temperature
Note: Exposure to conditions beyond those listed under Absolute Maximum Ratings may adversely affect the life and reliability of the
device.
14.2 DC CHARACTERISTICS
(Ta = 0° C to 70° C, VDD = 5V ± 10%, VSS = 0V)
PARAMETER
SYM.
MIN.
TYP.
MAX.
UNIT
CONDITIONS
RTC Battery Quiescent
Current
IBAT
2.4
uA
VBAT = 2.5 V
ACPI Stand-by Power
Supply Quiescent Current
IBAT
2.0
mA
VSB = 5.0 V, All ACPI pins are
not connected.
I/O8t - TTL level bi-directional pin with source-sink capability of 8 mA
Input Low Voltage
VIL
Input High Voltage
VIH
Output Low Voltage
VOL
Output High Voltage
VOH
Input High Leakage
ILIH
Input Low Leakage
ILIL
0.8
2.0
V
V
0.4
V
IOL = 8 mA
V
IOH = - 8 mA
+10
µA
VIN = VDD
-10
µA
VIN = 0V
2.4
I/O12t - TTL level bi-directional pin with source-sink capability of 12 mA
Input Low Voltage
VIL
Input High Voltage
VIH
Output Low Voltage
VOL
Output High Voltage
VOH
Input High Leakage
ILIH
Input Low Leakage
ILIL
0.8
2.0
V
V
0.4
V
IOL = 12 mA
V
IOH = -12 mA
+10
µA
VIN = VDD
-10
µA
VIN = 0V
2.4
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Publication Release Date: Oct 1998
Revision 0.51
W83627HF/F
PRELIMINARY
14.2 DC CHARACTERISTICS, continued
PARAMETER
SYM.
MIN.
TYP.
MAX.
UNIT
CONDITIONS
I/O12tp3 - 3.3 V TTL level bi-directional pin with source-sink capability of 12 mA
Input Low Voltage
VIL
Input High Voltage
VIH
Output Low Voltage
VOL
Output High Voltage
VOH
Input High Leakage
ILIH
Input Low Leakage
ILIL
0.8
V
2.0
V
0.4
V
IOL = 12 mA
V
IOH = -12 mA
+10
µA
VIN = 3.3V
-10
µA
VIN = 0V
2.4
I/OD12t - TTL level bi-directional pin with sink capability of 12 mA and open-drain
Input Low Voltage
VIL
0.8
V
Input High Voltage
VIH
Output Low Voltage
VOL
0.4
V
IOL = 12 mA
Input High Leakage
ILIH
+10
µA
VIN = 3.3V
Input Low Leakage
ILIL
-10
µA
VIN = 0V
2.0
V
I/O24t - TTL level bi-directional pin with source-sink capability of 24 mA
Input Low Voltage
VIL
Input High Voltage
VIH
Output Low Voltage
VOL
Output High Voltage
VOH
Input High Leakage
ILIH
Input Low Leakage
ILIL
0.8
V
2.0
V
0.4
V
IOL = 24 mA
V
IOH = -24 mA
+10
µA
VIN = VDD
-10
µA
VIN = 0V
2.4
OUT12t - TTL level output pin with source-sink capability of 12 mA
Output Low Voltage
VOL
Output High Voltage
VOH
0.4
2.4
V
IOL = 12 mA
V
IOH = -12 mA
OUT12tp3 - 3.3 V TTL level output pin with source-sink capability of 12 mA
Output Low Voltage
VOL
Output High Voltage
VOH
0.4
2.4
V
IOL = 12 mA
V
IOH = -12 mA
V
IOL = 12 mA
V
IOL = 24 mA
OD12 - Open-drain output pin with sink capability of 12 mA
Output Low Voltage
VOL
0.4
OD24 - Open-drain output pin with sink capability of 24 mA
Output Low Voltage
VOL
0.4
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Publication Release Date: Oct 1998
Revision 0.51
W83627HF/F
PRELIMINARY
14.2 DC CHARACTERISTICS, continued
PARAMETER
SYM.
MIN.
TYP.
MAX.
UNIT
CONDITIONS
INtd - TTL level input pin with internal pull down resistor
Input Low Voltage
VIL
Input High Voltage
VIH
Input High Leakage
ILIH
+10
µA
VIN = VDD
Input Low Leakage
ILIL
-10
µA
VIN = 0 V
R
47
KΩ
Input Low Voltage
VIL
0.8
V
Input High Voltage
VIH
Input High Leakage
ILIH
+10
µA
VIN = VDD
Input Low Leakage
ILIL
-10
µA
VIN = 0 V
pull down resistor
0.8
2.0
V
V
INt - TTL level input pin
2.0
V
INcs - CMOS level Schmitt-triggered input pin
Input Low Threshold Voltage
Vt-
1.3
1.5
1.7
V
VDD = 5 V
Input High Threshold Voltage
Vt+
3.2
3.5
3.8
V
VDD = 5 V
Hystersis
VTH
1.5
2
V
VDD = 5 V
Input High Leakage
ILIH
+10
µA
VIN = VDD
Input Low Leakage
ILIL
-10
µA
VIN = 0 V
INts - TTL level Schmitt-triggered input pin
Input Low Threshold Voltage
Vt-
0.5
0.8
1.1
V
VDD = 5 V
Input High Threshold Voltage
Vt+
1.6
2.0
2.4
V
VDD = 5 V
Hystersis
VTH
0.5
1.2
V
VDD = 5 V
Input High Leakage
ILIH
+10
µA
VIN = VDD
Input Low Leakage
ILIL
-10
µA
VIN = 0 V
INtsp3
- 3.3 V TTL level Schmitt-triggered input pin
Input Low Threshold Voltage
Vt-
0.5
0.8
1.1
V
VDD = 3.3 V
Input High Threshold Voltage
Vt+
1.6
2.0
2.4
V
VDD = 3.3 V
Hystersis
VTH
0.5
1.2
V
VDD = 3.3 V
Input High Leakage
ILIH
+10
µA
VIN = 3.3 V
Input Low Leakage
ILIL
-10
µA
VIN = 0 V
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Publication Release Date: Oct 1998
Revision 0.51
W83627HF/F
PRELIMINARY
15. APPLICATION CIRCUITS
15.1 Parallel Port Extension FDD
JP13
WE2/SLCT
WD2/PE
MOB2/BUSY
DSB2/ACK
PD7
PD6
PD5
DCH2/PD4
RDD2/PD3
STEP2/SLIN
WP2/PD2
DIR2/INIT
TRK02/PD1
HEAD2/ERR
IDX2/PD0
RWC2/AFD
STB
13
25
12
24
11
23
10
22
9
21
8
20
7
19
6
18
5
17
4
16
3
15
2
14
1
JP 13A
DCH2
HEAD2
RDD2
WP2
TRK02
WE2
WD2
STEP2
DIR2
MOB2
DSB2
IDX2
RWC2
34
32
30
28
26
24
22
20
18
16
14
12
10
8
6
4
2
33
31
29
27
25
23
21
19
17
15
13
11
9
7
5
3
1
EXT FDC
PRINTER PORT
Parallel Port Extension FDD Mode Connection Diagram
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Publication Release Date: Oct 1998
Revision 0.51
W83627HF/F
PRELIMINARY
15.2 Parallel Port Extension 2FDD
JP13
13
25
12
24
11
23
10
22
9
21
8
20
7
19
6
18
5
17
4
16
3
15
2
14
1
WE2/SLCT
WD2/PE
MOB2/BUSY
DSB2/ACK
DSA2/PD7
MOA2/PD6
PD5
DCH2/PD4
RDD2/PD3
STEP2/SLIN
WP2/PD2
DIR2/INIT
TRK02/PD1
HEAD2/ERR
IDX2/PD0
RWC2/AFD
STB
JP 13A
DCH2
HEAD2
RDD2
WP2
TRK02
WE2
WD2
STEP2
DIR2
MOB2
DSA2
DSB2
MOA2
IDX2
RWC2
34
32
30
28
26
24
22
20
18
16
14
12
10
8
6
4
2
33
31
29
27
25
23
21
19
17
15
13
11
9
7
5
3
1
EXT FDC
PRINTER PORT
Parallel Port Extension 2FDD Connection Diagram
15.3 Four FDD Mode
74LS139
7407(2)
W83977F
DSA
G1
A1
1Y0
1Y1
DSB
B1
1Y2
1Y3
2Y0
2Y1
2Y2
2Y3
MOA
MOB
G2
A2
DSA
DSB
DSC
DSD
MOA
MOB
MOC
MOD
B2
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Publication Release Date: Oct 1998
Revision 0.51
W83627HF/F
PRELIMINARY
16. ORDERING INSTRUCTION
PART NO.
KBC FIRMWARE
REMARKS
TM
W83627HF-AW
AMIKEY-2
W83627HF-PW
Phoenix MultiKey/42
TM
Only support 12MHz KBC
clock input
17. HOW TO READ THE TOP MARKING
Example: The top marking of W83627HF-AW
inbond
W83627HF-AW
 AM. MEGA. 87-96
821A2B282012345
1st line: Winbond logo
2nd line: the type number: W83627HF-AW
TM
3rd line: the source of KBC F/W -- American Megatrends Incorporated
4th line: the tracking code
821 A 2 C 282012345
821: packages made in '98, week 21
A: assembly house ID; A means ASE, S means SPIL.... etc.
2: Winbond internal use.
B: IC revision; A means version A, B means version B
282012345: wafer production series lot number
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Publication Release Date: Oct 1998
Revision 0.51
W83627HF/F
PRELIMINARY
18. PACKAGE DIMENSIONS
(128-pin QFP)
HE
A1
A2
b
c
D
E
e
HD
HE
L
L1
y
0
65
64
103
D
HD
39
128
e
38
b
c
Nom
Max
0.35
0.45
0.010
0.014
0.018
2.57
2.72
2.87
0.101
0.107
0.113
0.10
0.20
0.30
0.004
0.008
0.012
A2
A1
y
Nom
Max
Min
0.10
0.15
0.20
0.004
0.006
0.008
13.90
14.00
14.10
0.547
0.551
0.555
19.90
20.00
20.10
0.783
0.787
0.791
0.50
0.020
17.00
17.20
17.40
0.669
0.677
23.00
23.20
23.40
0.905
0.913
0.921
0.65
0.80
0.95
0.025
0.031
0.037
1.60
0.063
0.08
0
0.685
7
0.003
0
7
Note:
A
See Detail F
Seating Plane
Dimension in inch
0.25
Min
102
1
Dimension in mm
Symbol
E
L
L1
Detail F
1.Dimension D & E do not include interlead
flash.
2.Dimension b does not include dambar
protrusion/intrusion .
3.Controlling dimension : Millimeter
4.General appearance spec. should be based
on final visual inspection spec.
5. PCB layout please use the "mm".
Headquarters
Winbond Electronics (H.K.) Ltd.
No. 4, Creation Rd. III
Science-Based Industrial Park
Hsinchu, Taiwan
TEL: 886-35-770066
FAX: 886-35-789467
www: http://www.winbond.com.tw/
Rm. 803, World Trade Square, Tower II
123 Hoi Bun Rd., Kwun Tong
Kowloon, Hong Kong
TEL: 852-27516023-7
FAX: 852-27552064
Winbond Electronics
(North America) Corp.
2730 Orchard Parkway
San Jose, CA 95134 U.S.A.
TEL: 1-408-9436666
FAX: 1-408-9436668
Taipei Office
11F, No. 115, Sec. 3, Min-Sheng East Rd.
Taipei, Taiwan
TEL: 886-2-7190505
FAX: 886-2-7197502
TLX: 16485 WINTPE
Note: All data and specifications are subject to change without notice.
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Publication Release Date: Oct 1998
Revision 0.51