NM93C06LZ/C46LZ/C56LZ/C66LZ 256-/1024-/2048-/4096-Bit Serial EEPROM with Zero Power and Extended Voltage (2.7V to 5.5V) (MICROWIRE TM Bus Interface) General Description Features The NM93C06LZ/C46LZ/C56LZ/C66LZ devices are 256/ 1024/2048/4096 bits respectively, of CMOS non-volatile electrically erasable memory divided into 16/64/128/256 16-bit registers. They are fabricated using National Semiconductor’s floating-gate CMOS process for high reliability and low power consumption. These memory devices are available in both SO and TSSOP packages for small space considerations. The serial interface that operates these EEPROMs is MICROWIRE compatible for simple interface to standard microcontrollers and microprocessors. There are 7 instructions that control these devices: Read, Erase/Write Enable, Erase, Erase All, Write, Write All, and Erase/Write Disable. The ready/busy status is available on the DO pin to indicate the completion of a programming cycle. Y Y Y Y Y Y Y Y Y Y Y Less than 1.0 mA standby current 2.7V – 5.5V operation in all modes Typical active current of 100 mA Direct write: no erase before program Reliable CMOS floating gate technology MICROWIRE compatible serial I/O Self-timed programming cycle Device status indication during programming mode 40 years data retention Endurance: 106 data changes Packages available: 8-pin SO, 8-pin DIP, 8-pin TSSOP Block Diagram TL/D/11778 – 1 TRI-STATEÉ is a registered trademark of National Semiconductor Corporation. MICROWIRETM is a trademark of National Semiconductor Corporation. C1996 National Semiconductor Corporation TL/D/11778 RRD-B30M96/Printed in U. S. A. http://www.national.com NM93C06LZ/C46LZ/C56LZ/C66LZ 256-/1024-/2048-/4096-Bit Serial EEPROM with Zero Power and Extended Voltage (2.7V to 5.5V) (MICROWIRE Bus Interface) September 1996 Connection Diagram Pin Names Dual-in-Line Package (N) 8-Pin SO (M8) and 8-Pin TSSOP (MT8) Pin TL/D/11778–2 Top View See NS Package Number N08E and M08A Chip Select SK Serial Data Clock DI Serial Data Input DO Serial Data Output GND Ground VCC Power Supply Ordering Information Commercial Temperature Range (0§ C to a 70§ C) Order Number NM93C06LZN/NM93C46LZN NM93C56LZN/NM93C66LZN NM93C06LZM8/NM93C46LZM8 NM93C56LZM8/NM93C66LZM8 NM93C06LZMT8/NM93C46LZMT8 NM93C56LZMT8/NM93C66LZMT8 Extended Temperature Range (b40§ C to a 85§ C) Order Number NM93C06LZEN/NM93C46LZEN NM93C56LZEN/NM93C66LZEN NM93C06LZEM8/NM93C46LZEM8 NM93C56LZEM8/NM93C66LZEM8 NM93C06LZEMT8/NM93C46LZEMT8 NM93C56LZEMT8/NM93C66LZEMT8 Automotive Temperature Range (b40§ C to a 125§ C) Order Number NM93C06LZVN/NM93C46LZVN NM93C56LZVN/NM93C66LZVN NM93C06LZVM8/NM93C46LZVM8 NM93C56LZVM8/NM93C66LZVM8 NM93C06LZVMT8/NM93C46LZVMT8 NM93C56LZVMT8/NM93C66LZVMT8 http://www.national.com 2 Description CS LOW VOLTAGE (2.7V s 4.5V) SPECIFICATIONS Absolute Maximum Ratings (Note 1) Operating Conditions If Military/Aerospace specified devices are required, please contact the National Semiconductor Sales Office/Distributors for availability and specifications. b 65§ C to a 150§ C Ambient Storage Temperature Ambient Operating Temperature NM93C06LZ/46LZ/56LZ/66LZ 0§ C to a 70§ C NM93C06LZE/46LZE/56LZE/66LZE b40§ C to a 85§ C NM93C06LZV/46LZV/56LZV/66LZV b40§ C to a 125§ C All Input or Output Voltage with Respect to Ground Power Supply (VCC) Range Lead Temperature (Soldering, 10 sec.) ESD Rating 2.7V to 4.5V VCC a 1 to b0.3V a 300§ C 2000V DC and AC Electrical Characteristics Part Number Conditions Max Units ICC1 Symbol Operating Current CMOS Input Levels Parameter NM93C06/46/56/66LZ NM93C06/46/56/66LZE/V CS e VIH, SK e 250 kHz 1 1 mA ICC3 Standby Current NM93C06/46/56/66LZ NM93C06/46/56/66LZE/V CS e 0V 1 1 mA IIL Input Leakage NM93C06/46/56/66LZ NM93C06/46/56/66LZE/V VIN e 0V to VCC b 100 a 100 nA IOL Output Leakage NM93C06/46/56/66LZ NM93C06/46/56/66LZE/V VIN e 0V to VCC b 100 a 100 nA VIL2 Input Low Voltage 2V s VCC s 4.5V b 0.1 0.15 VCC V VIH2 Input High Voltage 2V s VCC s 4.5V 0.8 VCC VCC a 1 V VOL2 Output Low Voltage IOL e 10 mA VOH2 Output High Voltage IOH e b10 mA fSK SK Clock Frequency NM93C06/46/56/66LZ NM93C06/46/56/66LZE/V tSKH SK High Time NM93C06/46/56/66LZ NM93C06/46/56/66LZE/V (Note 2) 1 1 ms tSKL SK Low Time NM93C06/46/56/66LZ NM93C06/46/56/66LZE/V (Note 2) 1 1 ms tSKS SK Setup Time NM93C06/46/56/66LZ NM93C06/46/56/66LZE/V Relative to CS 50 50 ms tCS Minimum CS Low Time NM93C06/46/56/66LZ NM93C06/46/56/66LZE/V (Note 3) 1 1 ms tCSS CS Setup Time NM93C06/46/56/66LZ NM93C06/46/56/66LZE/V Relative to SK 0.2 0.2 ms tDH DO Hold Time Relative to SK 70 ns tDIS DI Setup Time Relative to SK 0.4 0.4 ms tCSH CS Hold Time Relative to SK 0 ms tDIH DI Hold Time Relative to SK 0.4 tPD1 Output Delay to ‘‘1’’ NM93C06/46/56/66LZ NM93C06/46/56/66LZE/V AC Test 2 2 ms tPD0 Output Delay to ‘‘0’’ NM93C06/46/56/66LZ NM93C06/46/56/66LZE/V AC Test 2 2 ms tSV CS to Status Valid NM93C06/46/56/66LZ NM93C06/46/56/66LZE/V AC Test 1 1 ms tDF CS to DO in TRI-STATEÉ NM93C06/46/56/66LZ NM93C06/46/56/66LZE/V AC Test CS e VIL 0.4 0.4 ms tWP Write Cycle Time NM93C06/46/56/66LZ VCC e 2.7V 15 ms NM93C06/46/56/66LZ NM93C06/46/56/66LZE/V 3 Min 0.2 0.9 VCC 0 0 V V 250 250 kHz ms http://www.national.com STANDARD VOLTAGE (4.5V s VCC s 5.5V) SPECIFICATIONS Absolute Maximum Ratings (Note 1) Operating Conditions If Military/Aerospace specified devices are required, please contact the National Semiconductor Sales Office/Distributors for availability and specifications. b 65§ C to a 150§ C Ambient Storage Temperature Ambient Operating Temperature NM93C06LZ/46LZ/56LZ/66LZ 0§ C to a 70§ C NM93C06LZE/46LZE/56LZE/66LZE b40§ C to a 85§ C NM93C06LZV/46LZV/56LZV/66LZV b40§ C to a 125§ C All Input or Output Voltage with Respect to Ground Power Supply (VCC) Range Lead Temperature (Soldering, 10 sec.) ESD Rating 4.5V to 5.5V VCC a 1 to b0.3V a 300§ C 2000V DC and AC Electrical Characteristics: 4.5V s VCC s 5.5V Part Number Conditions Max Units ICC1 Symbol Operating Current CMOS Input Levels Parameter NM93C06/46/56/66LZ NM93C06/46/56/66LZE/V CS e VIH, SK e 1 MHz SK e 1 MHz 2 2 mA ICC2 Operating Current TTL Input Levels NM93C06/46/56/66LZ NM93C06/46/56/66LZE/V CS e VIH, SK e 1 MHz 3 3 mA ICC3 Standby Current NM93C06/46/56/66LZ NM93C06/46/56/66LZE/V CS e 0V 50 50 mA IIL Input Leakage NM93C06/46/56/66LZ NM93C06/46/56/66LZE/V VIN e 0V to VCC b 2.5 b 10 2.5 10 nA IOL Output Leakage NM93C06/46/56/66LZ NM93C06/46/56/66LZE/V VIN e 0V to VCC b 2.5 b 10 2.5 10 nA VIL Input Low Voltage b 0.1 0.8 V VIH Input High Voltage 2 VCC a 1 V VOL1 Output Low Voltage 0.4 0.4 V VOH1 Output High Voltage VOL2 Output Low Voltage VOH2 Output High Voltage fSK SK Clock Frequency NM93C06/46/56/66LZ NM93C06/46/56/66LZE/V 0 0 tSKH SK High Time NM93C06/46/56/66LZ NM93C06/46/56/66LZE/V 250 300 ns tSKL SK Low Time NM93C06/46/56/66LZ NM93C06/46/56/66LZE/V 250 250 ns tCS Minimum CS Low Time NM93C06/46/56/66LZ NM93C06/46/56/66LZE/V (Note 3) 250 250 ns tCSS CS Setup Time NM93C06/46/56/66LZ NM93C06/46/56/66LZE/V Relative to SK 50 50 ns tDH DO Hold Time Relative to SK 70 ns http://www.national.com NM93C06/46/56/66LZ NM93C06/46/56/66LZE/V IOL e 2.1 mA IOH e 2.1 mA IOL e b400 mA NM93C06/46/56/66LZ NM93C06/46/56/66LZE/V 2.4 IOL e 10 mA IOH e b10 mA 4 Min V 0.2 0.9 VCC V V 1 1 MHz STANDARD VOLTAGE (4.5V s VCC s 5.5V) SPECIFICATIONS (Continued) DC and AC Electrical Characteristics VCC e 5.0V g 10% unless otherwise specified (Continued) Symbol Parameter Part Number Conditions Min NM93C06/46/56/66LZ NM93C06/46/56/66LZE/V Relative to SK 100 200 Max Units ns Relative to SK 0 ns Relative to SK 20 tDIS DI Setup Time tCSH CS Hold Time tDIH DI Hold Time tPD1 Output Delay to ‘‘1’’ NM93C06/46/56/66LZ NM93C06/46/56/66LZE/V AC Test 500 500 ns tPD0 Output Delay to ‘‘0’’ NM93C06/46/56/66LZ NM93C06/46/56/66LZE/V AC Test 500 500 ns tSV CS to Status Valid NM93C06/46/56/66LZ NM93C06/46/56/66LZE/V AC Test 500 500 ns tDF CS to DO in TRI-STATE NM93C06/46/56/66LZ NM93C06/46/56/66LZE/V AC Test CS e VIL 100 100 ns tWP Write Cycle Time 10 ms ns AC Test Conditions Output Load: 1 TTL Gate and CL e 100 pF VCC Range AC Test Conditions 4.5V k VCC k 5.5V Input Pulse Levels 0.8V and 2.0V Timing Measurement Level (VIL/VIH) 0.9V and 1.9V Timing Measurement Level (VOL/VOH) 0.8V and 2.0V (TTL Load Condition: IOL e 2.1 mA, IOH e b0.4 mA) 2.7V k VCC k 4.5V Input Pulse Levels 0.3V and 0.8 VCC Timing Measurement Level (VIL/VIH) 0.4V and 1.6V Timing Measurement Level (VOL/VOH) 0.8V and 1.6V (CMOS Load Condition: IOL e 10 mA, IOH e b10 mA) Capacitance TA e 25§ C, f e 1 MHz Test Max Units COUT Symbol Output Capacitance 5 pF CIN Input Capacitance 5 pF Note 1: Stress above those listed under ‘‘Absolute Maximum Ratings’’ may cause permanent damage to the device. This is a stress rating only, and functional operation of the device at these or any other conditions above those indicated in the operational sections of the specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Note 2: Minimum VCC requirements: All functional modes are guaranteed to full operation at VCC t 2V except the bulk programming op-codes ERAL and WRAL. These are regarded as test mode commands and are only guaranteed to VCC t 2.5V. Note 3: CS must be brought low for a minimum of 1 tCS between consecutive instruction cycles. 5 http://www.national.com Functional Description Write (WRITE): The WRITE instruction is followed by 16 bits of data to be written into the specified address. After the last bit of data is put on the data-in (DI) pin, CS must be brought low before the next rising edge of the SK clock. This falling edge of CS initiates the self-timed programming cycle. The DO pin indicates the READY/BUSY status of the chip if CS is brought high after a minimum of 250 ns (tCS). DO e logical 0 indicates that programming is still in progress. DO e 1 indicates that the register at the address specified in the instruction has been written with the data pattern specified in the instruction and the part is ready for another instruction. Erase All (ERAL): The ERAL instruction will simultaneously program all registers in the memory array and set each bit to the logical ‘‘1’’ state. The Erase All cycle is identical to the ERASE cycle except for the different op code. As in the ERASE mode, the DO pin indicates the READY/BUSY status of the chip. The ERASE ALL instruction is not required, see note below. Write All (WRAL): The WRAL instruction will simultaneously program all registers with the data pattern specified in the instruction. As in the WRITE mode, the DO pin indicates the READY/BUSY status of the chip. Erase/Write Disable (EWDS): To protect against accidental data disturb, the (EWDS) instruction disables all programming modes and should follow all programming operations. Execution of a READ instruction is independent of both the EWEN and EWDS instructions. The NM93C06/C46/C56/C66LZ devices have 7 instructions as described below. Note that the MSB of any instruction is a ‘‘1’’ and is viewed as a start bit in the interface sequence. For the C06LZ and C46LZ the next 8 bits carry the op code and the 6-bit address for register selection. For the C56LZ and C66LZ the next 10 bits carry the op code and the 8-bit address for register selection. Read (READ): The READ instruction outputs serial data on the DO pin. After the READ instruction is received, the instruction and address are decoded, followed by data transfer from the selected memory register into a serial-out shift register. A dummy bit (logical 0) precedes the 16-bit data output string. Output data changes are initiated by a low to high transition of the SK clock. Erase/Write Enable (EWEN): When VCC is applied to the part, it powers up in the Erase/Write Disable (EWDS) state. Therefore, all programming modes must be preceded by an Erase/Write Enable (EWEN) instruction. Once an Erase/ Write Enable instruction is executed, programming remains enabled until an Erase/Write Disable (EWDS) instruction is executed or until VCC is removed from the part. Erase (ERASE): The ERASE instruction will program all bits in the specified register to the logical ‘‘1’’ state. CS is brought low following the loading of the last address bit. This falling edge of the CS pin initiates the self-timed programming cycle. The DO pin indicates the READY/BUSY status of the chip. DO e logical ‘‘0’’ indicates that programming is still in progress. DO e logical ‘‘1’’ indicates that the register, at the address specified in the instruction, has been erased, and the part is ready for another instruction. Note: The NM93C06/C46/C56/C66LZ devices do not require an ‘‘ERASE’’ or ‘‘ERASE ALL’’ prior to the ‘‘WRITE’’ or ‘‘WRITE ALL’’ instructions. Instruction Set for the NM93C06LZ and NM93C46LZ Instruction SB Op Code Address Data Comments READ 1 10 A5–A0 Read data stored in memory, at specified address EWEN 1 00 11XXXX Write enable must precede all programming modes EWDS 1 11 A5–A0 WRITE 1 01 A5–A0 ERAL 1 00 10XXXX WRAL 1 00 01XXXX EWDS 1 00 00XXXX Erase register A5, A4, A3, A2, A1, A0 D15 – D0 Writes register Erases all registers D15 – D0 Writes all registers Disables all programming instructions Instruction Set for the NM93C56LZ and NM93C66LZ Instruction READ SB Op Code Address 1 10 A7–A0 Data Comments Read data stored in memory, at specified address EWEN 1 00 11XXXXXX EWDS 1 11 A7–A0 ERAL 1 00 10XXXXXX WRITE 1 01 A7–A0 D15 – D0 Write register if address is unprotected WRAL 1 00 01XXXXXX D15 – D0 Writes all registers EWDS 1 00 00XXXXXX http://www.national.com Write enable must precede all programming modes Erase selected register Erases all registers Disables all programming instructions 6 Timing Diagrams Synchronous Data Timing TL/D/11778 – 3 ² tSKS is not needed if DI e VIL when CS is going active (HIGH). READ TL/D/11778 – 4 *Address bits A5 and A4 become ‘‘don’t care’’ for NM93C06LZ. Address bit A7 becomes a ‘‘don’t care’’ for NM93C56LZ. EWEN TL/D/11778 – 5 *The NM93C56LZ and NM93C66LZ require a minimum of 11 clock cycles. The NM93C06LZ and NM93C46LZ require a minimum of 9 clock cycles. 7 http://www.national.com Timing Diagrams (Continued) EWDS TL/D/11778 – 6 *The NM93C56LZ and NM93C66LZ require a minimum of 11 clock cycles. The NM93C06LZ and NM93C46LZ require a minimum of 9 clock cycles. WRITE TL/D/11778 – 7 *Address bits A5 and A4 become ‘‘don’t care’’ for NM93C06LZ. Address bit A7 becomes a ‘‘don’t care’’ for NM93C56LZ. WRAL TL/D/11778 – 8 http://www.national.com 8 Timing Diagrams (Continued) ERASE TL/D/11778 – 9 *Address bits A5 and A4 become ‘‘don’t care’’ for NM93C06LZ. Address bit A7 becomes a ‘‘don’t care’’ for NM93C56LZ. ERAL TL/D/11778 – 10 9 http://www.national.com Physical Dimensions inches (millimeters) unless otherwise noted Molded Small Out-Line Package (M8) NS Package Number M08A http://www.national.com 10 Physical Dimensions inches (millimeters) unless otherwise noted (Continued) Note: Unless otherwise specified 1. Reference JEDEC Registration M0-153, Variation AA, Dated 7/93 8-Pin Molded TSSOP, JEDEC (MT8) NS Package Number MTC08 11 http://www.national.com NM93C06LZ/C46LZ/C56LZ/C66LZ 256-/1024-/2048-/4096-Bit Serial EEPROM with Zero Power and Extended Voltage (2.7V to 5.5V) (MICROWIRE Bus Interface) Physical Dimensions inches (millimeters) unless otherwise noted (Continued) 8-Lead Molded Dual-In-Line Package (N) NS Package Number N08E LIFE SUPPORT POLICY NATIONAL’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF NATIONAL SEMICONDUCTOR CORPORATION. As used herein: 1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and whose failure to perform, when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury to the user. National Semiconductor Corporation 1111 West Bardin Road Arlington, TX 76017 Tel: 1(800) 272-9959 Fax: 1(800) 737-7018 http://www.national.com 2. A critical component is any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness. 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