AK49256S / AK49256G 262,144 Word by 9 Bit MOS Dynamic Random Access Memory ACCUTEK MICROCIRCUIT CORPORATION DESCRIPTION Front View The Accutek AK49256 high density memory modules is a random access memory organized in 256K x 9 bit words. The assembly consists of nine standard 256K x 1 DRAMs in plastic leaded chip carriers (PLCC) mounted on the front side of a printed circuit board. The module can be configured as a leadless 30 pad SIM or a leaded 30 pin SIP. This packaging approach provides a 6 to 1 density increase over standard DIP packaging. 30-Pin SIM 30 1 30-Pin SIP The operation of the AK49256 is identical to nine 256K x 1 DRAMs. For the lower eight bits data input is tied to the data output and brought out separately for each device, with common RAS and CAS control. This common I/O feature dictates the use of early-write cycles to prevent contention of D and Q. Since the Write-Enable (WE) signal must always go low before CAS in a write cycle, Read-Write and Read-Modify-Write operation is not possible. For the ninth bit, the data input (D9) and the data output (Q9) pins are brought out separately and controlled by a separate PCAS for that bit. Bit nine is generally used for parity. 1 FEATURES · 262,144 by 9 bit organization · Optional 30 Pad leadless SIM (Single In-Line Module) or 30 Pin leaded SIP (Single In-Line Package) · Upward compatible with AK491024, AK591024, AK594096 and AK5916384 · Functionally and Pin compatible with AK59256A · JEDEC standard pinout · Common CAS and RAS control for the lower eight bits · Separate PCAS control for D9 and Q9 · 3.15 Watt active and 205 mW standby (max) · Operating free air temperature 00C to 700C PIN NOMENCLATURE PIN ASSIGNMENT FUNCTIONAL DIAGRAM PIN # SYMBOL PIN # SYMBOL 1 Vcc 16 DQ5 Data In / Data Out 2 CAS 17 A8 Data In 9 3 DQ! 18 NC 4 A0 19 NC 5 A1 20 DQ6 A0 - A8 Address Inputs DQ1 - DQ8 D9 Q9 Data Out 9 CAS, PCAS Column Address Strobe 6 DQ2 21 WE RAS Row Address Strobe 7 A2 22 Vss WE Write Enable 8 A3 23 DQ7 9 Vss 24 NC Vcc 5v Supply 10 DQ3 25 DQ8 Vss Ground 11 A4 26 Q9 12 A5 27 RAS 13 DQ4 28 PCAS 14 A6 29 D9 15 A7 30 Vcc NC No Connect MODULE OPTIONS Leadless SIM: AK49256S Leaded SIP: AK49256G MECHANICAL DIMENSIONS ORDERING INFORMATION PART NUMBER CODING INTERPRETATION Position 1 2 3 6 Inches 7 8 0.425 0..375 .100 .060 0.325 0.275 1 1 0.100 T.P. 3.525 3.475 3.100 3.090 30 0.100 TYP 0.200" MAX 0.053 0.047 Product AK = Accutek Memory Type 4 = Dynamic RAM 5 = CMOS Dynamic RAM 6 = Static RAM Organization/Word Width 1 = by 1 16 = by 16 4 = by 4 32 = by 32 8 = by 8 36 = by 36 9 = by 9 Size/Bits Depth 64 = 64K 4096 = 4 MEG 256 = 256K 8192 = 8 MEG 1024 = 1 MEG 16384 = 16 MEG Package Type G = Single In-Line Package (SIP) S = Single In-Line Module (SIM) D = Dual In-Line Package (DIP) W = .050 inch Pitch Edge Connect Z = Zig-Zag In-Line Package (ZIP) Special Designation P = Page Mode N = Nibble Mode K = Static Column Mode W = Write Per Bit Mode V = Video Ram Separator - = Commercial 00C to +700C M = Military Equivalent Screened (-550C to +1250C) I = Industrial Temperature Tested (-450C to +850C) X = Burned In Speed (first two significant digits) DRAMS SRAMS 50 = 50 nS 8 = 8 nS 60 = 60 nS 10 = 10 nS 70 = 70 nS 12 = 12 nS 80 = 80 nS 15 = 15 nS 0.024 0.016 8 5 0.685 0.635 7 4 0.100 TYP 6 3 0.100 TYP 5 2 0.685 0.635 4 1 The numbers and coding on this page do not include all variations available but are show as examples of the most widely used variations. Contact Accutek if other information is required. EXAMPLES: AK49256SP-10 256K x 9, 100 nSEC DRAM 30 pin SIM Configuration, Page Mode AK49256GK-80 256K x 9, 80 nSEC DRAM 30 pin SIP Configuration, Static Column Mode ACCUTEK MICROCIRCUIT CORPORATION 5 NEW PASTURE ROAD NEWBURYPORT, MA 01950-4040 PHONE: 978-465-6200 FAX: 978-462-3396 Email: [email protected] Internet: www.accutekmicro.com Accutek reserves the right to make changes in specifications at any time and without notice. Accutek does not assume any responsibility for the use of any circuitry described; no circuit patent licenses are implied. Preliminary data sheets contain minimum and maximum limits based upon design objectives, which are subject to change upon full characterization over the specific operating conditions.