DM74AS533 Octal D-Type Transparent Latch with TRI-STATEÉ Outputs General Description These 8-bit registers feature totem-pole TRI-STATE outputs designed specifically for driving highly-capacitive or relatively low-impedance loads. The high-impedance state and increased high-logic-level drive provide these registers with the capability of being connected directly to and driving the bus lines in a bus-organized system without need for interface or pull-up components. They are particularly attractive for implementing buffer registers, I/O ports, bidirectional bus drivers, and working registers. The eight inverting latches of the AS533 are transparent Dtype latches, meaning that while the enable (G) is high the Q outputs will follow the complement of the data (D) inputs. When the enable is taken low the output will be latched at the complement of the level of the data that was set up. A buffered output control input can be used to place the eight outputs in either a normal logic state (high or low logic levels) or a high-impedance state. In the high-impedance state the outputs neither load nor drive the bus lines significantly. The output control does not affect the internal operation of the latches. That is, the old data can be retained or new data can be entered even while the outputs are off. Features Y Y Y Y Switching specifications at 50 pF Switching specifications guaranteed over full temperature and VCC range Advanced oxide-isolated, ion-implanted Schottky TTL process TRI-STATE buffer-type outputs drive bus lines directly Connection Diagram Dual-In-Line Package TL/F/6311 – 1 Order Number DM74AS533WM or DM74AS533N See NS Package Number M20B or N20A TRI-STATEÉ is a registered trademark of National Semiconductor Corporation. C1995 National Semiconductor Corporation TL/F/6311 RRD-B30M105/Printed in U. S. A. DM74AS533 Octal D-Type Transparent Latch with TRI-STATE Outputs December 1989 Absolute Maximum Ratings Supply Voltage 7V Input Voltage 7V Voltage Applied to Disabled Output Operating Free Air Temperature Range Storage Temperature Range Typical iJA N Package M Package Note: The ‘‘Absolute Maximum Ratings’’ are those values beyond which the safety of the device cannot be guaranteed. The device should not be operated at these limits. The parametric values defined in the ‘‘Electrical Characteristics’’ table are not guaranteed at the absolute maximum ratings. The ‘‘Recommended Operating Conditions’’ table will define the conditions for actual device operation. 5.5V 0§ C to a 70§ C b 65§ C to a 150§ C 52.5§ C/W 70.5§ C/W Recommended Operating Conditions Symbol Parameter VCC Supply Voltage VIH High Level Input Voltage VIL Low Level Input Voltage IOH Min Nom Max Units 4.5 5 5.5 V 2 V 0.8 V High Level Output Current b 15 mA IOL Low Level Output Current 48 mA tW Width of Enable Pulse, High or Low 2 ns tSU Data Setup Time 2u ns tH Data Hold Time 3u TA Free Air Operating Temperature The ( ns 0 70 §C u) arrow indicates the positive edge of the Clock is used for reference. Electrical Characteristics over recommended operating free air temperature range. All typical values are measured at VCC e 5V, TA e 25§ C. Symbol VIK VOH Parameter Conditions Input Clamp Voltage VCC e 4.5V, II e b18 mA High Level Output Voltage VCC e 4.5V, IOH e Max Min 2.4 IOH e b2 mA, VCC e 4.5V to 5.5V Typ Max Units b 1.2 V 3.2 V VCC b 2 VOL Low Level Output Voltage VCC e 4.5V, IOL e Max II Input Current @ Max Input Voltage VCC e 5.5V, VIH e 7V IIH High Level Input Current VCC e 5.5V, VIH e 2.7V 20 mA IIL Low Level Input Current VCC e 5.5V, VIL e 0.4V b 0.5 mA IO Output Drive Current VCC e 5.5V, VO e 2.25V b 112 mA IOZH Off-State Output Current, High Level Voltage Applied VCC e 5.5V, VO e 2.7V 50 mA Off-State Output Current, Low Level Voltage Applied VCC e 5.5V, VO e 0.4V b 50 mA Supply Current VCC e 5.5V Outputs Open IOZL ICC 2 0.35 b 30 0.5 V 0.1 mA Outputs High 62 Outputs Low 64 100 100 Outputs Disabled 71 110 mA Switching Characteristics over recommended operating free air temperature range (Note 1) Symbol Parameter Conditions tPLH Propagation Delay Time Low to High Level Output tPHL Propagation Delay Time High to Low Level Output VCC e 4.5V to 5.5V RL e 500X CL e 50 pF From tPLH To Data Any Q Data Any Q Propagation Delay Time Low to High Level Output Enable Any Q tPHL Propagation Delay Time High to Low Level Output Enable Any Q tPZH Output Enable Time to High Level Output Output Control Any Q tPZL Output Enable Time to Low Level Output Output Control Any Q tPHZ Output Disable Time from High Level Output Output Control Any Q tPLZ Output Disable Time from Low Level Output Output Control Any Q Min Max Units 4 7.5 ns 4 7 ns 5 9 ns 4.5 8 ns 2 6.5 ns 4.5 9.5 ns 3 6.5 ns 3 7 ns Note 1: See Section 5 for test waveforms and output load. Logic Diagram Function Table Output Control Enable G D Output Q L L L H H H L X H L X X L H Q0 Z L e Low State, H e High State, X e Don’t Care Z e High Impedance State Q0 e Previous Condition of Q TL/F/6311 – 2 3 DM74AS533 Octal D-Type Transparent Latch with TRI-STATE Outputs Physical Dimensions inches (millimeters) Small Outline Package (M) Order Number DM74AS533WM NS Package Number M20B Molded Dual-In-Line Package (N) Order Number DM74AS533N NS Package Number N20A LIFE SUPPORT POLICY NATIONAL’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF NATIONAL SEMICONDUCTOR CORPORATION. As used herein: 1. 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