A4447 High Voltage Step Down Regulator Features and Benefits Description ▪ ▪ ▪ ▪ ▪ ▪ ▪ The A4447 is a 2 A, high efficiency general-purpose buck regulator designed for a wide variety of applications. The output voltage is adjustable from 0.8 to 24 V, based on a resistor divider and the 0.8 V ± 2 % reference. External components include an external clamping diode, inductor, and filter capacitor. The off-time is determined by an external resistor to ground. It operates in both continuous and discontinuous modes to maintain light load regulation. An internal blanking circuit is used to filter out transients due to the reverse recovery of the external clamp diode. Typical blanking time is 200 ns. Wide input voltage range: 8 to 50 V Integrated low RDS(on) DMOS switch 2 A continuous output current Adjustable fixed off-time Highly efficient Adjustable output: 0.8 to 24 V Small package with exposed thermal pad Package: 8 pin SOIC with exposed thermal pad (suffix LJ) This new device is ideal for various end products including applications with 8 to 50 V input voltage range and require up to 2 A output current, such as uninterruptible power supplies, point of sale (POS) applications, and industrial applications with 24 or 36 V bus. Applications include: ▪ Printer power supplies ▪ Office automation equipment ▪ POS thermal, laser, photo, and inkjet printers ▪ Tape drives ▪ Industrial applications Approximate Scale 1:1 Typical Application +42 V Efficiency vs. Output Current CBOOT 0.01 μF CIN1 0.22 μF CIN2 D1 ENB LX L1 A4447 TSET VOUT 3.3 V 2A VBIAS RTSET 54 k7 R1 2.87 k7 GND ESR FB R3 A 10 k7 A R3 required when CBYP connected 5 85 VIN R2 910 7 CBYP 0.22 μF COUT 220 μF 25 V Efficiency % BOOT 90 3.3 80 75 1.8 70 1.5 65 VOUT (V) 60 0 500 1000 IOUT (mA) Data is for reference only. Efficiency data from circuit shown in left panel. A4447-DS, Rev. 2 1500 2000 A4447 High Voltage Step Down Regulator Absolute Maximum Ratings Min. Typ. Max. Units VIN Supply Voltage Characteristic Symbol VIN – – 50 V VBIAS Input Voltage VBIAS –0.3 – 7 V VS –1 – – V VENB –0.3 – 7 V TA –20 – 85 °C SW Switching Voltage ENB Input Voltage Range Operating Ambient Temperature Range Conditions Junction Temperature TJ(max) – – 150 °C Storage Temperature Tstg –55 – 150 °C *Output current rating may be limited by duty cycle, ambient temperature, and heat sinking. Under any set of conditions, do not exceed the specified current ratings, or a junction temperature, TJ, of 150°C. Thermal Characteristics*may require derating at maximum conditions, see application section for optimization Characteristic Symbol Package Thermal Resistance (Junction to Ambient) RθJA Package Thermal Resistance (Junction to Pad) RθJP Test Conditions* Value Unit On 4-layer PCB based on JEDEC standard 35 ºC/W On 2-layer generic test PCB with 0.8 in.2 of copper area each side 62 ºC/W 2 ºC/W *Additional thermal information available on the Allegro™ website. Ordering Information Use the following complete part numbers when ordering: Part Number Packing Description A4447SLJTR-T 13-in. reel, 3000 pieces/reel LJ package, SOIC surface mount with exposed thermal pad; leadframe plating 100% matte tin. Allegro MicroSystems, LLC 115 Northeast Cutoff Worcester, Massachusetts 01615-0036 U.S.A. 1.508.853.5000; www.allegromicro.com 2 A4447 High Voltage Step Down Regulator Functional Block Diagram BOOT VIN Boot Charge + VIN – VOUT LX L1 ESR D1 COUT ENB Switch PWM Control Switch Disable μC CBYP Clamp + TSET FB – I_Demand – R3 Error + I_Peak COMP GND VBB UVLO TSD Soft Start Ramp Generation Bias Supply VBIAS VBIAS is connected to VOUT when VOUT target is between 3.3 and 5 V; otherwise, keep VBIAS open 0.8 V Allegro MicroSystems, LLC 115 Northeast Cutoff Worcester, Massachusetts 01615-0036 U.S.A. 1.508.853.5000; www.allegromicro.com 3 A4447 High Voltage Step Down Regulator ELECTRICAL CHARACTERISTICS1,2 at TA = 25°C, VIN = 8 to 50 V (unless noted otherwise) Characteristics VIN Quiescent Current3 VBIAS Input Current Buck Switch On Resistance Fixed Off-Time Proportion Feedback Voltage Output Voltage Regulation Symbol IVIN(Q) IBIAS RDS(on) toff Test Conditions Min. Typ. Max. Units VENB = LOW, IOUT = 0 mA, VIN = 42 V, VBIAS = VOUT – 0.90 1.35 mA VENB = LOW, IOUT = 0 mA, VIN = 42 V, VBIAS < 3 V – 4.4 6.35 mA VENB = HIGH – – 100 μA VBIAS = VOUT – 3.5 5 mA TA = 25°C, IOUT = 2 A – 450 – mΩ TA = 125°C, IOUT = 2 A – 650 – mΩ –15 – 15 % 0.784 0.8 0.816 V Based on calculated value VFB –3 – 3 % Feedback Input Bias Current VOUT IFB IOUT = 0 mA to 2 A –400 –100 100 nA Soft Start Time tss 5 10 15 ms Buck Switch Current Limit ICL VFB > 0.4 V 2.2 – 3 A VFB < 0.4 V 0.5 – 1.2 A ENB Open Circuit Voltage VOC Output disabled 2.0 – 7 V – – 1.0 V ENB Input Voltage Threshold VENB(0) LOW level input (Logic 0), output enabled ENB Input Current IENB(0) VENB = 0 V –10 – –1 μA VIN Undervoltage Threshold VUVLO VIN rising 6.6 6.9 7.2 V VIN Undervoltage Hysteresis VUVLO(hys) VIN falling Thermal Shutdown Temperature Thermal Shutdown Hysteresis TJTSD TJTSD(hys) 0.7 – 1.1 V Temperature increasing – 165 – °C Recovery = TJTSD – TJTSD(hys) – 15 – °C 1Negative current is defined as coming out of (sourcing) the specified device pin. over the junction temperature range of 0ºC to 125ºC are assured by design and characterization. 3VBIAS is connected to VOUT when the V OUT target is between 3.3 and 5 V. 2Specifications Allegro MicroSystems, LLC 115 Northeast Cutoff Worcester, Massachusetts 01615-0036 U.S.A. 1.508.853.5000; www.allegromicro.com 4 A4447 High Voltage Step Down Regulator Functional Description The A4447 is a fixed off-time, current mode controlled, buck regulator. The regulator requires an external clamping diode, inductor, and filter capacitor. It operates in both continuous and discontinuous modes. An internal blanking circuit is used to filter out transients resulting from the reverse recovery of the external clamp diode. Typical blanking time is 200 ns. of the following fault conditions: • VIN < 6 V • ENB pin = open circuit • TSD fault When the device comes out of a TSD fault, it will go into a soft start to limit inrush current. The value of a resistor between the TSET and GND determines the fixed off-time (see graph in the tOFF section). tOFF. The value of a resistor between the TSET pin and ground determines the fixed off-time. The formula to calculate tOFF (μs) is: ⎛ 1– 0.03 × VBIAS⎞ (2) ⎟ , tOFF = RTSET ⎜ 10.2 × 109 VOUT = VFB × (1 + R1/R2) (1) Light Load Regulation. To maintain voltage regulation during light load conditions, the switching regulator enters a cycle-skipping mode. As the output current decreases, there remains some energy that is stored during the power switch minimum on-time. In order to prevent the output voltage from rising, the regulator skips cycles once it reaches the minimum on-time, effectively making the off-time larger. Soft Start. An internal ramp generator and counter allow the output to slowly ramp up. This limits the maximum demand on the external power supply by controlling the inrush current required to charge the external capacitor and any DC load at startup. Internally, the ramp is set to 10 ms nominal rise time. During soft start, current limit is 2.2 A minimum. The following conditions are required to trigger a soft start: • VIN > 6 V • ENB pin input falling edge • Reset of a TSD (thermal shut down) event VBIAS. To improve overall system efficiency, the regulator output, VOUT, is connected to the VBIAS input to supply the operating bias current during normal operating conditions. During startup the circuitry is run off of the VIN supply. VBIAS should be connected to VOUT when the VOUT target level is between 3.3 and 5 V. If the output voltage is less than 3.3 V, then the A4447 can operate with an internal supply and pay a penalty in efficiency, as the bias current will come from the high voltage supply, VIN. VBIAS can also be supplied with an external voltage source. No power-up sequencing is required for normal operation. ON/OFF Control. The ENB pin is externally pulled to ground to enable the device and begin the soft start sequence. When the ENB is open circuited, the switcher is disabled and the output decays to 0 V. Protection. The buck switch will be disabled under one or more ⎝ ⎠ where RTSET (kΩ) is the value of the resistor. If the VBIAS pin is left open, use VBIAS = 0 in equation 2. Results are shown in the following graph: Off-Time Setting versus Resistor Value 200 180 160 140 RTSET (kΩ) VOUT. The output voltage is adjustable from 0.8 to 24 V, set by an external resistor divider. The voltage can be calculated with the following formula: VBIAS = 5 V 120 VBIAS = 3.3 V 100 80 60 40 20 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 tOFF (µs) The RTSET resistor should be not smaller than 7.65 kΩ ±2% to prevent very short off-times from violating the minimum on-time of the switcher. Shorted Load. If the voltage on the FB pin falls below 0.4 V, the regulator will invoke a 0.85 A typical overcurrent limit to handle the shorted load condition at the regulator output. For low output voltages at power up and in the case of a shorted output, the offtime is extended to prevent loss of control of the current limit due to the minimum on-time of the switcher. The extension of the off-time is based on the value of the TSET multiplier and the FB voltage, as shown in the following table: VFB (V) TSET Multiplier < 0.16 8 × tOFF < 0.32 4 × tOFF < 0.5 2 × tOFF > 0.5 tOFF Allegro MicroSystems, LLC 115 Northeast Cutoff Worcester, Massachusetts 01615-0036 U.S.A. 1.508.853.5000; www.allegromicro.com 5 A4447 High Voltage Step Down Regulator Component Selection L1. The inductor must be rated to handle the total load current. The value should be chosen to keep the ripple current to a reasonable value. The ripple current, IRIPPLE, can be calculated by: IRIPPLE = VL(OFF) × tOFF / L (3) VL(OFF) = VOUT + Vf + IL(AV) × RL (4) Substituting into equation 7: fSW = 1 / (7 μs +1.12 μs) = 123 kHz Higher inductor values can be chosen to lower the ripple current. This may be an option if it is required to increase the total maximum current available above that drawn from the switching regulator. The maximum total current available, ILOAD(MAX) , is: Example: ILOAD(MAX) = ICL(min) – IRIPPLE / 2 (8) Given VOUT = 5 V, Vf = 0.55 V, VIN = 42 V, ILOAD = 0.5 A, power inductor with L = 180 μH and RL = 0.5 Ω Rdc at 55°C, tOFF = 7 μs, and RDS(on) = 1 Ω. where ICL(min) is 2.2 A, from the Electrical Characteristics table. Substituting into equation 4: D1. The Schottky catch diode should be rated to handle 1.2 times the maximum load current. The voltage rating should be higher VL(OFF) = 5 V + 0.55 V+ 0.5 A × 0.5 Ω = 5.8 V than the maximum input voltage expected during all operating Substituting into equation 3: conditions. The duty cycle for high input voltages can be very close to 100%. IRIPPLE = 5.8 V × 7 μs / 180 μH = 225 mA The switching frequency, fSW, can then be estimated by: COUT. The main consideration in selecting an output capacitor fSW = 1 / ( tON + tOFF ) (5) tON = IRIPPLE × L / VL(ON) (6) VL(ON) = VIN – IL(AV) × RDS(on) – IL(AV) × RL– VOUT (7) Substituting into equation 7: VL(ON) = 42 V – 0.5 A × 1 Ω – 0.5 A × 0.5 Ω – 5 V = 36 V Substituting into equation 6: tON = 225 mA × 180 μH / 36 V = 1.12 μs is voltage ripple on the output. For electrolytic output capacitors, a low-ESR type is recommended. The peak-to-peak output voltage ripple is simply IRIPPLE × ESR. Note that increasing the inductor value can decrease the ripple current. The minimum voltage rating of the capacitor is 10 V. However, because ESR decreases with voltage, the most cost-effective choice may be rated higher in voltage. It is recommended that the ESR be less than 100 mΩ. Allegro MicroSystems, LLC 115 Northeast Cutoff Worcester, Massachusetts 01615-0036 U.S.A. 1.508.853.5000; www.allegromicro.com 6 A4447 High Voltage Step Down Regulator RTSET Selection. Correct selection of RTSET values will ensure that minimum on time of the switcher is not violated and prevent the switcher from cycle skipping. For a given VIN to VOUT ratio, RTSET must be greater than or equal to the value defined by the curve in the RTEST Value Selection graph below. Note. The curve represents the minimum RTSET value. When calculating RTSET , be sure to use VIN(max) / VOUT(min). Resistor tolerance should also be considered, so that under all operating conditions the resistance on the TSET pin remains as close to the curve as possible. The RTEST Selection table shows recommended RTSET values based on common operating conditions. For other operating con- ditions, refer to the RTSET Value Selection graph. CBYP Selection. In certain applications, CBYP can be used to improve closed loop response of the converter. Typically, a 0.22 uF capacitor ensures better loop response for wide range of applications. Resistor R3 prevents negative voltage on the FB pin due to CBYP capacitor during sudden changes in VOUT . FB Resistor Selection. The impedance of the FB network should be kept low to improve noise immunity. Large value resistors can pick up noise generated by the inductor, which can affect voltage regulation of the switcher. RTSET Value Selection* Selection Graph Recommended Common Values 70 65 60 55 Violation of Minimum On-Time VIN / VOUT 50 45 40 35 30 25 20 Safe Operating Area 15 10 5 0 0 15 30 45 60 75 90 105 120 RTSET (kΩ) 135 150 165 180 195 210 VIN (V) 42 42 42 42 24 24 24 24 12 12 12 12 VOUT (V) 5 3.3 1.8 1.5 5 3.3 1.8 1.5 5 3.3 1.8 1.5 VIN / VOUT 8.4 12.7 23.3 28 4.8 7.3 13.3 16 2.4 3.6 6.6 8 RTSET Value (kΩ) 37.4 54.9 90.9 105 20.0 32.4 54.9 66.5 7.68 13.7 30.1 37.4 *The RTSET resistor should be not smaller than 7.65 kΩ ±2% to prevent very short off-times from violating the minimum on-time of the switcher. Allegro MicroSystems, LLC 115 Northeast Cutoff Worcester, Massachusetts 01615-0036 U.S.A. 1.508.853.5000; www.allegromicro.com 7 A4447 High Voltage Step Down Regulator Recommended Components Component Description Part Number L1 Sumida 68 μH RCH1216BNP-680K D1 NIEC Schottky Barrier Diode 60 V TO-252AA NSQ03A06 CBYP Ceramic X7A 0.22 μF 100 V Generic CBOOT CIN COUT Ceramic X7A 0.01 μF 100 V Generic Electrolytic 100 μF 50 V; must be able to handle worst case ripple curent Generic Ceramic X7A 0.22 μF 50 V Generic United Chemi-Con PXA 220 μF 16 V Low ESR PXA16VC221MJ12TP Rubycon ZL 220 μF 25 V Low ESR 25ZL220M8x11.5 (Option 1) Panasonic FM 220 μF 25 V Low ESR (Option 2) EEUFM1E221 VOUT 1.5 V 1.8 V 3.3 V 5V R1 1.30 kΩ 2.55 kΩ 2.87 kΩ 6.34 kΩ R2 1.47 kΩ 2.00 kΩ 0.910 kΩ 1.20 kΩ R3 10 kΩ Allegro MicroSystems, LLC 115 Northeast Cutoff Worcester, Massachusetts 01615-0036 U.S.A. 1.508.853.5000; www.allegromicro.com 8 A4447 High Voltage Step Down Regulator Recommended PCB Layout In order to minimize the effects of ground bounce and offset issues, it is important to have a low impedance ground located very close to the device. This grounding scheme is known as star grounding. It is likely that a ground plane will be necessary to meet thermal requirements. The recommended land pattern illustrates how to create a low impedance ground that will also assist with removing thermal energy from the device. The input capacitor must be placed as close as possible to the VIN terminal because during the on cycle it is responsible for supplying the current to the switcher. During the off cycle, the current path is from the negative terminal of the COUT cap, through the diode and inductor, and then to the load. As a result, COUT and the rectifier diode must share the connection at the negative terminal of the CIN capacitor in order to reduce ground bounce when the diode is conducting. The inductor should be connected as close as possible to the switching node to minimize noise. Some applications may require a shielded inductor due to EMI restrictions. This will depend on the application and parameters defined by the system that will host the regulator. The high voltage-switching node could affect RTSET. If longer off-times are used, the resistance on the RTSET pin can be quite large. When designing the layout, try to keep RTSET away from the inductor and switching node. It is also beneficial to keep the trace as short as possible to reduce the effect of noise injection. Because of this layout guideline, the TSET pin is located on the other side of the device, away from the switching node. The FB resistor network should have a lower impedance to avoid interference from the switching node. Because the impedance on the FB node can be controlled, it is not as critical to keep the network isolated. It is important to keep the ground trace short so that ground bounce cannot effect the output voltage regulation. Star Ground CIN1 VIN VIN GND U1 CBOOT CIN2 CBOOT CIN2 1 GND BOOT ENB D1 RTSET GND RTSET R3 A4447 PAD D1 LX TSET VBIAS GND FB R3 R2 R2 GND VIN R1 CBYP CBYP L1 R1 COUT L1 CIN1 COUT VOUT VOUT Exposed copper thermal ground area on the unpopulated side of the PCB The large star ground area on the populated side of the PCB, shown in the diagram as the GND nodes, supports high current throughput, and allows the VOUT node to be located as close as practical to the A4447 (U1). Thermal conduction from the A4447 is enhanced by direct contact of its exposed thermal pad to the smaller ground area under the A4447. This area is connected by thermal vias to the large copper ground plane on the unpopulated side of the PCB. Allegro MicroSystems, LLC 115 Northeast Cutoff Worcester, Massachusetts 01615-0036 U.S.A. 1.508.853.5000; www.allegromicro.com 9 A4447 High Voltage Step Down Regulator Optimizing Thermal Layout The features of the printed circuit board, including heat conduction and adjacent thermal sources such as other components, have a very significant effect on the thermal performance of the device. To optimize thermal performance, the following should be taken into account: • The device exposed thermal pad should be connected to as much copper area as is available. • Copper thickness should be as high as possible (for example, 2 oz. or greater for higher power applications). • The greater the quantity of thermal vias, the better the dissipation. If the expense of vias is a concern, studies have shown that concentrating the vias directly under the device in a tight pattern, as shown in figure 6, has the greatest effect. • Additional exposed copper area on the opposite side of the board should be connected by means of the thermal vias. The copper should cover as much area as possible. • Other thermal sources should be placed as remote from the device as possible Signal traces LJ package footprint 0.7 mm 0.7 mm LJ package exposed thermal pad Top-layer exposed copper Ø0.3 mm via Suggested PCB layout for thermal optimization (maximum available bottom-layer copper recommended) Allegro MicroSystems, LLC 115 Northeast Cutoff Worcester, Massachusetts 01615-0036 U.S.A. 1.508.853.5000; www.allegromicro.com 10 A4447 High Voltage Step Down Regulator Package LJ, 8 Pin SOIC 4.90 ±0.10 0.65 8° 0° 8 B 3.90 ±0.10 A 1 6.00 ±0.20 2.41 1.04 REF 2 1 1.27 0.40 3.30 NOM SEATING PLANE GAUGE PLANE Branded Face SEATING PLANE 0.10 C C 0.15 0.00 1.27 BSC 2 C PCB Layout Reference View For Reference Only; not for tooling use (reference MS-012BA) Dimensions in millimeters Dimensions exclusive of mold flash, gate burrs, and dambar protrusions Exact case and lead configuration at supplier discretion within limits shown 1.70 MAX 0.51 0.31 5.60 3.30 0.25 BSC 8X 1.27 1.75 0.25 0.17 2.41 NOM 8 A Terminal #1 mark area B Exposed thermal pad (bottom surface); dimensions may vary with device C Reference land pattern layout (reference IPC7351 SOIC127P600X175-9AM); all pads a minimum of 0.20 mm from all adjacent pads; adjust as necessary to meet application process requirements and PCB layout tolerances; when mounting on a multilayer PCB, thermal vias at the exposed thermal pad land can improve thermal dissipation (reference EIA/JEDEC Standard JESD51-5) Terminal List Table Pin Out Diagram BOOT 1 8 VIN ENB 2 7 LX TSET 3 6 VBIAS GND 4 5 FB Pad Number 1 2 3 4 5 6 7 8 Name BOOT ENB TSET GND FB VBIAS LX VIN Description Gate drive boost node On/off control; logic input Off-time setting Ground Feedback for adjustable regulator Bias supply input Buck switching node Supply input Allegro MicroSystems, LLC 115 Northeast Cutoff Worcester, Massachusetts 01615-0036 U.S.A. 1.508.853.5000; www.allegromicro.com 11 A4447 High Voltage Step Down Regulator Revision History Revision Revision Date Rev. 2 March 19, 2013 Description of Revision Add component recommendations Copyright ©2008-2013, Allegro MicroSystems, LLC Allegro MicroSystems, LLC reserves the right to make, from time to time, such departures from the detail specifications as may be required to permit improvements in the performance, reliability, or manufacturability of its products. Before placing an order, the user is cautioned to verify that the information being relied upon is current. Allegro’s products are not to be used in life support devices or systems, if a failure of an Allegro product can reasonably be expected to cause the failure of that life support device or system, or to affect the safety or effectiveness of that device or system. The information included herein is believed to be accurate and reliable. However, Allegro MicroSystems, LLC assumes no responsibility for its use; nor for any infringement of patents or other rights of third parties which may result from its use. For the latest version of this document, visit our website: www.allegromicro.com Allegro MicroSystems, LLC 115 Northeast Cutoff Worcester, Massachusetts 01615-0036 U.S.A. 1.508.853.5000; www.allegromicro.com 12