A8293 Single LNB Supply and Control Voltage Regulator Features and Benefits Description ▪ 2-wire serial I2C™ -compatible interface: control (write) and status (read) ▪ LNB voltages (8 programmable levels) compatible with all common standards including domestic Japan models ▪ Tracking switch-mode power converter for lowest dissipation ▪ Integrated converter switches and current sensing ▪ Provides up to 700 mA load current ▪ Static current limit circuit allows full current at startup and 13→18 V output transition; reliably starts wide load range ▪ Push-pull output stage minimizes 13→18 V and 18→13 V output transition times for highly capacitive loads ▪ Adjustable rise/fall time via external timing capacitor ▪ Built-in tone oscillator, factory-trimmed to 22 kHz facilitates DiSEqC™ tone encoding, even at no-load ▪ Four methods of 22 kHz tone generation, via I2C™ data bits and/or external pin ▪ Auxiliary modulation input ▪ LNB overcurrent with timer ▪ Diagnostics for output voltage level, input supply UVLO Intended for analog and digital satellite receivers, this single low noise block converter regulator (LNBR) is a monolithic linear and switching voltage regulator, specifically designed to provide the power and the interface signals to an LNB down converter via coaxial cable. The A8293 requires few external components, with the boost switch and compensation circuitry integrated inside of the device. A high switching frequency is chosen to minimize the size of the passive filtering components, further assisting in cost reduction. The high levels of component integration ensure extremely low noise and ripple figures. The A8293 has been designed for high efficiency, utilizing the Allegro® advanced BCD process. The integrated boost switch has been optimized to minimize both switching and static losses. To further enhance efficiency, the voltage drop across the tracking regulator has been minimized. For DiSEqC™ communications, several schemes are available for generating tone signals, all the way down to no-load, and using either the internal clock or an external time source. Packages: 20-contact, 4 × 4 mm MLP/QFN (suffix ES) 28 contact, 5 × 5 mm MLP/QFN (suffix ET) Continued on the next page… Functional Block Diagram L1 33 μH VS D1 C2 100 μF C1 100 nF C5 100 μF VIN LX GNDLX C4 100 nF C6 1 μF BOOST VCP VREG D3 A Charge Pump C3 220 nF Boost Converter Regulator TMode EXTM fsw VDD R1 R2 R3 R4 LNB Voltage Control DAC Wave Shape Linear Stage VOUT LNB TCAP EXTM SDA SCL fsw TGate D2 C8 100 nF C10 220 nF C9 10 nF D4 A Fault Monitor I 2 C™Compatible Interface OCP PNG TSD VUV Clock Divider 22 kHz TCAP C7 10 nF (or 22 nF) Oscillator ADD IRQ A PAD For recommended external components, refer to table 7 8293-DS, Rev. 4 GND D3 and D4 are used for surge protection. A8293 Single LNB Supply and Control Voltage Regulator Description (continued) A comprehensive set of fault registers are provided, which comply with all the common standards, including: overcurrent, thermal shutdown, undervoltage, and power not good. The A8293 is supplied in two lead (Pb) free MLP/QFN packages: ES, 20-contact, 4 mm × 4 mm, 0.75 nominal overall height, and ET, 28-contact, 5 mm × 5 mm, 0.90 nominal overall height. The device uses a 2-wire bidirectional serial interface, compatible with the I2C™ standard, that operates up to 400 kHz. Selection Guide Part Number Packing1 Description A8293SESTR-T2 7 in. reel, 1500 pieces/reel 12 mm carrier tape ES package, MLP/QFN surface mount 4 mm × 4 mm × 0.75 mm nominal height A8293SETTR-T2,3 7 in. reel, 1500 pieces/reel 12 mm carrier tape ET package, MLP/QFN surface mount 5 mm × 5 mm × 0.90 mm nominal height 1Contact Allegro for additional packing options. plating 100% matte tin. 3This variant is in production but has been determined to be NOT FOR NEW DESIGN. This classification indicates that sale of this device is currently restricted to existing customer applications. The variant should not be purchased for new design applications because obsolescence in the near future is probable. Status date change September 21, 2010. 2Leadframe Absolute Maximum Ratings Rating Units Load Supply Voltage, VIN pin Characteristic Symbol VIN Conditions 30 V Output Current1 IOUT Internally Limited A –0.3 to 33 V –1 to 33 V –0.3 to 30 V –0.3 to 41 V Logic Input Voltage, EXTM pin –0.3 to 5 V Logic Input Voltage, other pins –0.3 to 7 V Logic Output Voltage –0.3 to 7 V Output Voltage, BOOST pin Surge2 Output Voltage, LNB pin Output Voltage, LX pin Output Voltage, VCP pin VCP Operating Ambient Temperature TA –20 to 85 °C Junction Temperature TJ(max) 150 °C Storage Temperature Tstg –55 to 150 °C 1Output current rating may be limited by duty cycle, ambient temperature, and heat sinking. Under any set of conditions, do not exceed the specified current ratings, or a junction temperature, TJ, of 150°C. 2Use Allegro recommended Application circuit. Package Thermal Characteristics* Package RθJA (°C/W) PCB ES 37 (estimated) 4-layer ET 32 4-layer * Additional information is available on the Allegro website. Allegro MicroSystems, Inc. 115 Northeast Cutoff Worcester, Massachusetts 01615-0036 U.S.A. 1.508.853.5000; www.allegromicro.com 2 A8293 Single LNB Supply and Control Voltage Regulator 13 NC FLOAT 4 12 EXTM 5 11 22 FLOAT 23 NC 24 NC 25 VIN 26 LX 20 NC TCAP 3 SCL NC 4 IRQ FLOAT 5 17 NC EXTM 6 16 NC NC 7 15 NC 19 GND PAD GND 8 ADD 10 SDA 9 8 VREG 7 6 NC 21 NC 2 (Top View) ES Package 18 NC IRQ 14 3 GND 1 VCP NC 13 TCAP PAD BOOST SCL 12 GND ADD 11 FLOAT 14 SDA 10 15 2 9 1 VCP VREG BOOST 27 GNDLX 28 LNB 16 NC 17 VIN 18 LX 19 GND 20 LNB Device Pin-out Diagram ET Package Terminal List Table Name Number ES ET ADD 10 11 Function Address select FLOAT 4, 15 5, 22 BOOST 1 1 These pins must not be connected to anything; do not ground these pins Tracking supply voltage to linear regulator EXTM 5 6 External modulation input GND 7, 14 8, 19 GNDLX 19 27 Signal ground Boost switch ground IRQ 11 14 Interrupt request LNB 20 28 Output voltage to LNB LX 18 NC 6, 13, 16 PAD Pad 26 4, 7, 13, 1518, 20, 21, 23, 24 Pad SCL 12 12 I2C™-compatible clock input SDA 9 10 I2C™-compatible data input/output Inductor drive point No connection Exposed pad; connect to the ground plane, for thermal dissipation TCAP 3 3 Capacitor for setting the rise and fall time of the LNB output VCP 2 2 Gate supply voltage VIN 17 25 Supply input voltage VREG 8 9 Analog supply Allegro MicroSystems, Inc. 115 Northeast Cutoff Worcester, Massachusetts 01615-0036 U.S.A. 1.508.853.5000; www.allegromicro.com 3 A8293 Single LNB Supply and Control Voltage Regulator ELECTRICAL CHARACTERISTICS at TA = 25°C, VIN = 9 to 16 V, unless noted otherwise1 Characteristics Symbol Test Conditions Min. Typ. Max. Units –3.0 – +3.0 % General Set-Point Accuracy, Load and Line Regulation Supply Current Boost Switch On Resistance Err IIN(Off) ENB bit = 0, LNB output disabled, VIN = 12 V – – 10.0 mA IIN(On) ENB bit = 1, LNB output enabled, ILOAD = 0 mA, VIN = 12 V – – 19.0 mA RDS(on)BOOST ILOAD = 450 mA – 300 – mΩ 320 352 384 kHz VIN = 9 V, VOUT = 19.0 V – 2.7 – A ∆VREG VBOOST – VLNB, no tone signal, ILOAD = 450 mA – 800 – mV ICHG TCAP capacitor (C7) charging –12.5 –10 –7.5 μA 7.5 10 12.5 μA Switching Frequency fSW Switch Current Limit ILIMSW Linear Regulator Voltage Drop TCAP Pin Current Relative to selected VLNB target level, ILOAD = 0 to 450 mA IDISCHG TCAP capacitor (C7) discharging Output Voltage Rise Time2 tr(VLNB) For VLNB 13 → 18 V; CTCAP = 5.6 nF, ILOAD = 450 mA – 500 – μs Output Voltage Pull-Down Time2 tf(VLNB) For VLNB 18 → 13 V; CLOAD = 100 μF, ILOAD = 0 mA – 12.5 – ms IRLNB ENB bit = 0, VLNB = 33 V , BOOST capacitor (C5) fully charged – 1 5 mA Vrip,n(pp) 20 MHz BWL; reference circuit shown in Functional Block diagram; contact Allegro for additional information on application circuit board design – 30 – mVPP ILIMLNB VBOOST – VLNB = 800 mV – 700 800 mA Output Reverse Current Ripple and Noise on LNB Output3 Protection Circuitry Output Overcurrent Limit4 Overcurrent Disable Time VIN Undervoltage Lockout Threshold VIN Turn On Threshold – 48 – ms VUVLO tDIS VIN falling 7.05 7.35 7.65 V VIN(th) VIN rising 7.40 7.70 8.00 V VUVLOHYS – 350 – mV Thermal Shutdown Threshold2 TJ – 165 – °C Thermal Shutdown Hysteresis2 ∆TJ – 20 – °C Undervoltage Hysteresis Power Not Good Flag Set Power Not Good Flag Reset Power Not Good Hysteresis PNGSET With respect to VLNB 77 85 93 % PNGRESET With respect to VLNB 82 90 98 % With respect to VLNB – 5 – % 20 22 24 kHz 400 620 800 mV PNGHYS Tone Tone Frequency Tone Amplitude, Peak-to-Peak fTONE VTONE(pp) ILOAD = 0 to 450 mA, CLOAD = 750 nF Continued on the next page… Allegro MicroSystems, Inc. 115 Northeast Cutoff Worcester, Massachusetts 01615-0036 U.S.A. 1.508.853.5000; www.allegromicro.com 4 A8293 Single LNB Supply and Control Voltage Regulator ELECTRICAL CHARACTERISTICS (continued) at TA = 25°C, VIN = 9 to 16 V, unless noted otherwise1 Min. Typ. Max. Units Tone Duty Cycle Characteristics DCTONE Symbol ILOAD = 0 to 450 mA, CLOAD = 750 nF 40 50 60 % Tone Rise Time trTONE ILOAD = 0 to 450 mA, CLOAD = 750 nF 5 10 15 μs Tone Fall Time tfTONE ILOAD = 0 to 450 mA, CLOAD = 750 nF 5 10 15 μs VEXTM(H) 2.0 – – V VEXTM(L) – – 0.8 V IEXTMLKG –1 – 1 μA EXTM Logic Input EXTM Input Leakage Test Conditions I2C™-Compatible Interface Logic Input (SDA,SCL) Low Level VSCL(L) – – 0.8 V Logic Input (SDA,SCL) High Level VSCL(H) 2.0 – – V Logic Input Hysteresis VI2CIHYS – 150 – mV –10 <±1.0 10 μA ILOAD = 3 mA – – 0.4 V Vt2COut = 0 to 7 V – – 10 μA – – 400 kHz – – 250 ns Logic Input Current II2CI VI2CI = 0 to 7 V Logic Output Voltage SDA and IRQ Vt2COut(L) Logic Output Leakage SDA and IRQ Vt2CLKG SCL Clock Frequency fCLK Output Fall Time tfI2COut Bus Free Time Between Stop/Start Vt2COut(H) to Vt2COut(L) tBUF 1.3 – – μs Hold Time Start Condition tHD:STA 0.6 – – μs Setup Time for Start Condition tSU:STA 0.6 – – μs tLOW 1.3 – – μs SCL Low Time SCL High Time Data Setup Time tHIGH 0.6 – – μs tSU:DAT 100 – – ns 0 – 900 ns 0.6 – – μs Data Hold Time tHD:DAT Setup Time for Stop Condition tSU:STO For tHD:DAT(min) , the master device must provide a hold time of at least 300 ns for the SDA signal in order to bridge the undefined region of the SCL signal falling edge I2C™ Address Setting ADD Voltage for Address 0001,000 Address1 0 – 0.7 V ADD Voltage for Address 0001,001 Address2 1.3 – 1.7 V ADD Voltage for Address 0001,010 Address3 2.3 – 2.7 V ADD Voltage for Address 0001,011 Address4 3.3 – 5.0 V 1Operation at 16 V may be limited by power loss in the linear regulator. 2Guaranteed by worst case process simulations and system characterization. Not production tested. 3LNB output ripple and noise are dependent on component selection and PCB layout. Refer to the Application Schematic and PCB layout recommendations. Not production tested. 4Current from the LNB output may be limited by the choice of Boost components. I2C™ Interface Timing Diagram tSU:STA tHD:STA tSU:DAT tHD:DAT tSU:STO tBUF SDA SCL tLOW tHIGH Allegro MicroSystems, Inc. 115 Northeast Cutoff Worcester, Massachusetts 01615-0036 U.S.A. 1.508.853.5000; www.allegromicro.com 5 A8293 Single LNB Supply and Control Voltage Regulator Functional Description Protection The A8293 has a wide range of protection features and fault diagnostics which are detailed in the Status Register section. Boost Converter/Linear Regulator The A8293 solution contains a tracking current-mode boost converter and linear regulator. The boost converter tracks the requested LNB voltage to within 800 mV, to minimize power dissipation. Under conditions where the input voltage, VBOOST , is greater than the output voltage, VLNB, the linear regulator must drop the differential voltage. When operating in these conditions, care must be taken to ensure that the safe operating temperature range of the A8293 is not exceeded. The boost converter operates at 352 kHz typical: 16 times the internal 22 kHz tone frequency. All the loop compensation, current sensing, and slope compensation functions are provided internally. The A8293 has internal pulse-by-pulse current limiting on the boost converter and DC current limiting on the LNB output to protect the IC against short circuits. When the LNB output is shorted, the LNB output current is limited to 700 mA typical, and the IC will be shut down if the overcurrent condition lasts for more than 48 ms. If this occurs, the A8293 must be reenabled for normal operation. The system should provide sufficient time between successive restarts to limit internal power dissipation; a minimum of 2 s is recommended. At extremely light loads, the boost converter operates in a pulse-skipping mode. Pulse skipping occurs when the BOOST voltage rises to approximately 450 mV above the BOOST target output voltage. Pulse skipping stops when the BOOST voltage drops 200 mV below the pulse skipping level. In the case that two or more set top box LNB outputs are connected together by the customer (e.g., with a splitter), it is possible that one output could be programmed at a higher voltage than the other. This would cause a voltage on one output that is higher than its programmed voltage (e.g., 19 V on the output of a 13 V programmed voltage). The output with the highest voltage will effectively turn off the other outputs. As soon as this voltage is reduced below the value of the other outputs, the A8293 output will auto-recover to their programmed levels. Charge Pump. Generates a supply voltage above the internal and fall times can be set by the value of the capacitor connected from the TCAP pin to GND (CTCAP or C7 in the Applications Schematic). Note that during start-up, the BOOST pin is precharged to the input voltage minus a voltage drop. As a result, the slew rate control for the BOOST pin occurs from this voltage. The value of CTCAP can be calculated using the following formula: CTCAP = (ITCAP × 6) / SR , where SR is the required slew rate of the LNB output voltage, in V/s, and ITCAP is the TCAP pin current specified in the data sheet. The recommended value for CTCAP, 10 nF, should provide satisfactory operation for most applications. However, in some cases, it may be necessary to increase the value of CTCAP to avoid activating the current limit of the LNB output. One such situation is when two set-top boxes are connected in parallel. If this is the case, the following formula can be used to calculate CTCAP: CTCAP ≥ (ITCAP × 6)(2 × CBOOST) / ILIMLNB , CTCAP ≥ (10 μA × 6)(2 × 100 μF) / 500 mA = 24 nF . The minimum value of CTCAP is 2.2 nF. There is no theoretical maximum value of CTCAP however too large a value will probably cause the voltage transition specification to be exceeded. Tone generation is unaffected by the value of CTCAP . Pull-Down Rate Control. In applications that have to operate at very light loads and that require large load capacitances (in the order of tens to hundreds of microfarads), the output linear stage provides approximately 40 mA of pull-down capability. This ensures that the output volts are ramped from 18 V to 13 V in a reasonable amount of time. ODT (Overcurrent Disable Time) If the LNB output current exceeds 700 mA, typical, for more than 48 ms, then the LNB output will be disabled and the OCP bit will be set. Short Circuit Handling If the LNB output is shorted to ground, the LNB output current will be clamped to 700 mA, typical. If the short circuit condition lasts for more than 48 ms, the A8293 will be disabled and the OCP bit will be set. tracking regulator output to drive the linear regulator control. Auto-Restart Slew Rate Control. During either start-up, or when the output After a short circuit condition occurs, the host controller should periodically reenable the A8293 to check if the short circuit has voltage at the LNB pin is transitioning, the output voltage rise Allegro MicroSystems, Inc. 115 Northeast Cutoff Worcester, Massachusetts 01615-0036 U.S.A. 1.508.853.5000; www.allegromicro.com 6 A8293 Single LNB Supply and Control Voltage Regulator been removed. Consecutive startup attempts should allow at least 2 s of delay between restarts. In-Rush Current At start-up or during an LNB reconfiguration event, a transient surge current above the normal DC operating level can be provided by the A8293. This current increase can be as high as 700 mA, typical, for as long as required, up to a maximum of 48 ms. Tone Generation The A8293 solution offers four options for tone generation, providing maximum flexibility to cover every application. The EXTM pin (external modulation), in conjunction with the I2C™ control bits: TMODE (tone modulation) and TGATE (tone gate), provide the necessary control. The TMODE bit controls whether the tone source is either internal or external (via the EXTM pin). Both the EXTM pin and TGATE bit determine the 22 kHz control, whether gated or clocked. Four options for tone generation are shown in figure 1. Note that when using option 4, when EXTM stops clocking, the LNB volts park at the LNB voltage, either plus or minus half the tone signal amplitude, depending on the state of EXTM. For example, if the EXTM is held low, the LNB DC voltage is the LNB programmed voltage minus 325 mV (typical). EXTM TMODE TGATE Tone (LNB Ref) LNB (V) Option 1 – Use internal tone, gated by the TGATE bit. EXTM TMODE TGATE Tone (LNB Ref) LNB (V) Option 2 – Use internal tone, gated by the EXTM pin. EXTM TMODE TGATE Tone (LNB Ref) LNB (V) Option 3 – Use external tone, gated by the TGATE bit. EXTM TMODE TGATE Tone (LNB Ref) LNB (V) Option 4 – Use external tone. Figure 1. Options for tone generation Allegro MicroSystems, Inc. 115 Northeast Cutoff Worcester, Massachusetts 01615-0036 U.S.A. 1.508.853.5000; www.allegromicro.com 7 A8293 Single LNB Supply and Control Voltage Regulator I2C™-Compatible Interface fined by the remaining two bits, are selected by the ADD input. The address is transmitted MSB first. 3. Data Cycles. Write – 6 bits of data and 2 bits for addressing four internal control registers, followed by an acknowledge bit. See Control Register section for more information. Read – Two status registers, where register 1 is read first, followed by register 2, then register 1, and so on. At the start of any read sequence, register 1 is always read first. Data is transmitted MSB first. 4. Stop Condition. Defined by a positive edge on the SDA line, while SCL is high. Except to indicate a Start or Stop condition, SDA must be stable while the clock is high. SDA can only be changed while SCL is low. It is possible for the Start or Stop condition to occur at any time during a data transfer. The A8293 always responds by resetting the data transfer sequence. This is a serial interface that uses two bus lines, SCL and SDA, to access the internal Control and Status registers of the A8293. Data is exchanged between a microcontroller (master) and the A8293 (slave). The clock input to SCL is generated by the master, while SDA functions as either an input or an open drain output, depending on the direction of the data. Timing Considerations The control sequence of the communication through the I2C™compatible interface is composed of several steps in sequence: 1. Start Condition. Defined by a negative edge on the SDA line, while SCL is high. 2. Address Cycle. 7 bits of address, plus 1 bit to indicate read (1) or write (0), and an acknowledge bit. The first five bits of the address are fixed as: 00010. The four optional addresses, de- The Read/Write bit is used to determine the data transfer direction. If the Read/Write bit is high, the master reads the contents of acknowledge from LNBR Start Address acknowledge from LNBR W Control Data SDA 0 0 0 1 0 A1 A0 0 AK SCL 1 2 3 4 5 6 7 8 9 I1 I0 D5 D4 D3 Stop D2 D1 D0 AK Write to Register acknowledge from LNBR Start Address no acknowledge from master R Status Register 1 SDA 0 0 0 1 0 A1 A0 1 AK SCL 1 2 3 4 5 6 7 8 9 D7 D6 D5 D4 D3 D2 Stop D1 D0 NAK Read One Byte from Register acknowledge from LNBR Start Address R acknowledge from LNBR Status Data in Register 1 SDA 0 0 0 1 0 A1 A0 1 AK SCL 1 2 3 4 5 6 7 8 9 D7 D6 D5 D4 D3 D2 D1 no acknowledge from master Status Data in Register 2 D0 AK - - - - D3 D2 D1 Stop D0 NAK Read Multiple Bytes from Register Figure 2. I2C™ Interface. Read and write sequences. Allegro MicroSystems, Inc. 115 Northeast Cutoff Worcester, Massachusetts 01615-0036 U.S.A. 1.508.853.5000; www.allegromicro.com 8 A8293 Single LNB Supply and Control Voltage Regulator register 1, followed by register 2 if a further read is performed. If the Read/Write bit is low, the master writes data to one of the two Control registers. Note that multiple writes are not permitted. All write operations must be preceded with the address. The Acknowledge bit has two functions. It is used by the master to determine if the slave device is responding to its address and data, and it is used by the slave when the master is reading data back from the slave. When the A8293 decodes the 7-bit address field as a valid address, it responds by pulling SDA low during the ninth clock cycle. During a data write from the master, the A8293 also pulls SDA low during the clock cycle that follows the data byte, in order to indicate that the data has been successfully received. In both cases, the master device must release the SDA line before the ninth clock cycle, in order to allow this handshaking to occur. During a data read, the A8293 acknowledges the address in the same way as in the data write sequence, and then retains control of the SDA line and send the data from register 1 to the master. On completion of the eight data bits, the A8293 releases the SDA line before the ninth clock cycle, in order to allow the master to acknowledge the data. If the master holds the SDA line low during this Acknowledge bit, the A8293 responds by sending the data from register 2 to the master. Data bytes continue to be sent to the master until the master releases the SDA line during the Acknowledge bit. When this is detected, the A8293 stops sending data and waits for a stop signal. Interrupt Request The A8293 also provides an interrupt request pin, IRQ, which is an open-drain, active-low output. This output may be connected to a common IRQ line with a suitable external pull-up and can Start Address be used with other I2C™-compatible devices to request attention from the master controller. The IRQ output becomes active when either the A8293 first recognizes a fault condition, or at power-on, when the main supply, VIN , and the internal logic supply, VREG , reach the correct operating conditions. It is only reset to inactive when the I2C™ master addresses the A8293 with the Read/Write bit set (causing a read). Fault conditions are indicated by the TSD, VUV, and OCP bits, and are latched in the Status register. See the Status register section for full description. The DIS and PNG status bits do not cause an interrupt. The PNG bit is continually updated, apart from the DIS bit, which changes when the LNB is either disabled, faulted, or is enabled. When the master recognizes an interrupt, it addresses all slaves connected to the interrupt line in sequence, and then reads the status register to determine which device is requesting attention. The A8293 latches all conditions in the Status register until the completion of the data read. The action at the resampling point is further defined in the Status Register section. The bits in the Status register are defined such that the all-zero condition indicates that the A8293 is fully active with no fault conditions. When VIN is initially applied, the I2C™-compatible interface does not respond to any requests until the internal logic supply VREG has reached its operating level. Once VREG has reached this point, the IRQ output goes active, and the VUV bit is set. After the A8293 acknowledges the address, the IRQ flag is reset. After the master reads the status registers, the registers are updated with the VUV reset. R Status Register 1 SDA 0 0 0 1 0 A1 A0 1 AK SCL 1 2 3 4 5 6 7 8 9 D7 D6 D5 D4 D3 D2 Stop D1 D0 NAK IRQ Fault Event Read after Interrupt Reload Status Register Figure 3. I2C™ Interface. Read sequences after interrupt request. Allegro MicroSystems, Inc. 115 Northeast Cutoff Worcester, Massachusetts 01615-0036 U.S.A. 1.508.853.5000; www.allegromicro.com 9 A8293 Single LNB Supply and Control Voltage Regulator Control Registers (I2C™-Compatible Write Register) All main functions of the A8293 are controlled through the I2C™compatible interface via the 8-bit Control registers. As the A8293 contains numerous control options, it is necessary to have two control registers. Each register contains up to 6 bits of data (bit 0 to bit 5), followed by 2 bits for the register address (bit 6 and bit 7). The power-up states for the control functions are all 0s. The following tables define the control bits for each address and the settings for output voltage: Table 1. Control Register Address (I1, I0) = 00 Bit 0 Bit 1 Bit 2 VSEL0 VSEL1 VSEL2 Bit 3 VSEL3 Bit 4 Bit 5 ODT ENB Bit 6 Bit 7 I0 I1 Bit Name Function 0 VSEL0 1 VSEL1 2 VSEL2 3 VSEL3 4 ODT 5 ENB 6 I0 Address Bit: 0 7 I1 Address Bit: 0 See table 3, Output Voltage Amplitude Selection 0: LNB = Low range 1: LNB = High range 1 (recommended): The ODT functions are always enabled, but setting 1 recommended at all times. 0: Disable LNB Output 1: Enable LNB Output These three bits provide incremental control over the voltage on the LNB output. The available voltages provide the necessary levels for all the common standards plus the ability to add line compensation in increments of 333 mV. The voltage levels are defined in table 3, Output Voltage Amplitude Selection. Switches between the low level and high level output voltages on the LNB output. 0 selects the low level voltage and 1 selects the high level. The low-level center voltage is 12.709 V nominal and the high level is 18.042 V nominal. These may be increased in steps of 333 mV using the VSEL2, VSEL1 and VSEL0 control register bits. The overcurrent disable timer is always enabled. Enables the LNB output. When set to 1 the LNB output is switched on. When set to 0, the LNB output is disabled. Address Address Allegro MicroSystems, Inc. 115 Northeast Cutoff Worcester, Massachusetts 01615-0036 U.S.A. 1.508.853.5000; www.allegromicro.com 10 A8293 Single LNB Supply and Control Voltage Regulator Table 2. Control Register Address (I1, I0) = 10 Bit 0 Bit 0 Bit 1 Bit 2 Bit 3 Bit 4 Bit 5 Bit 6 Bit 7 Name TMODE Function 0: External Tone 1: Internal Tone 0: Tone Gated Off 1 TGATE 2 - Not Used (0 recommended) 3 - Not Used 4 - Not Used 5 - Not Used 6 I0 Address Bit: 0 7 I1 Address Bit: 1 1: Tone Gated On TMODE Tone Mode. Selects between the use of an external 22 kHz logic signal or the use of the internal 22 kHz oscillator to control the tone generation on the LNB output. A 0 selects the external tone and a 1 selects the internal tone. See the Tone Generation section for more information TGATE Tone Gate. Allows either the internal or external 22 kHz tone signals to be gated, unless the EXTM is selected for gating. When set to 0, the selected tone (via TMODE) is off. When set to 1, the selected tone is on. See Tone Generation Section for more information. – Not Used. – Not Used. – Not Used. – Not Used. I0 Address. I1 Address. Allegro MicroSystems, Inc. 115 Northeast Cutoff Worcester, Massachusetts 01615-0036 U.S.A. 1.508.853.5000; www.allegromicro.com 11 A8293 Single LNB Supply and Control Voltage Regulator Table 3. Output Voltage Amplitude Selection VSEL3 VSEL2 VSEL1 VSEL0 LNB (V) 0 0 0 0 12.709 0 0 0 1 13.042 0 0 1 0 13.375 0 1 0 0 14.042 0 1 1 1 15.042 1 0 0 0 18.042 1 0 1 0 18.709 1 0 1 1 19.042 Allegro MicroSystems, Inc. 115 Northeast Cutoff Worcester, Massachusetts 01615-0036 U.S.A. 1.508.853.5000; www.allegromicro.com 12 A8293 Single LNB Supply and Control Voltage Regulator Status Registers (I2C™-Compatible Read Register) As the A8293 has a comprehensive set of status reporting bits, it is necessary to have two Status registers. When performing a The main fault conditions: overcurrent (OCP), undervoltage (VUV) and overtemperature (TSD), are all indicated by setting the relevant bits in the Status registers. In all fault cases, once the bit is set, it remains latched until the A8293 is read by the I2C™ master, assuming the fault has been resolved. The current status of the LNB output is indicated by the disable bit, DIS. The DIS bit is set when either a fault occurs or if the LNB is disabled intentionally. This bit is latched, and is reset when the LNB is commanded on again. The power not good (PNG) is the only bit which may be reset without an I2C™ read sequence. Table 4 summarizes the condition of each bit when set and how it is reset. multiple read function, register 1 is read followed by register 2, then register 1 again and so on. Whenever a new read function is performed, register 1 is always read first. The normal sequence of the master in a fault condition will be to detect the fault by reading the Status registers, then rereading the Status registers until the status bit is reset indicating the fault condition is reset. The fault may be detected either by continuously polling, by responding to an interrupt request (IRQ), or by detecting a fault condition externally and performing a diagnostic poll of all slave devices. Note that the fully-operational condition of the Status registers is all 0s, to simplify checking of the Status bit. Table 4. Status Register Bit Setting Status Bit – Function Not used Reset Condition Set – Not used DIS LNB disabled, either intentionally or due to fault Latched LNB enabled and no fault OCP Overcurrent Latched I2C™ read and fault removed PNG Power not good – Not used Non-latched – LNB volts in range Not used TSD Thermal shutdown Latched I2C™ read and fault removed VUV Undervoltage Latched I2C™ read and fault removed Allegro MicroSystems, Inc. 115 Northeast Cutoff Worcester, Massachusetts 01615-0036 U.S.A. 1.508.853.5000; www.allegromicro.com 13 A8293 Single LNB Supply and Control Voltage Regulator Table 5. Status Register 1 Bit 0 DIS Bit 1 Bit 2 – OCP Bit 3 Bit 4 – PNG Bit 5 Bit 6 – TSD Bit 7 VUV Bit Name Function 0 DIS LNB output disabled 1 – Not Used 2 OCP Overcurrent 3 – Not Used 4 PNG Power Not Good 5 – Not Used 6 TSD Thermal Shutdown 7 VUV VIN Undervoltage LNB Output Disabled. DIS is used to indicate the current condition of the LNB output. At power-on, or if a fault condition occurs, DIS will be set. This bit changing to 1 does not cause the IRQ to activate because the LNB output may be disabled intentionally by the I2C™ master. This bit will be reset at the end of a write sequence if the LNB output is enabled. Not used. Overcurrent. If the LNB output detects an overcurrent condition, for greater than 48 ms, the LNB output will be disabled. The OCP bit will be set to indicate that an overcurrent has occurred and the disable bit, DIS, will be set. The Status register is updated on the rising edge of the 9th clock pulse in the data read sequence, where the OCP bit is reset in all cases, allowing the master to reenable the LNB output. If the overcurrent timer is not enabled, the device operate in current limit indefinitely and the OCP bit will be set. If the overcurrent condition is removed, the OCP bit will automatically be reset. Note that if the overcurrent operates long enough, and a thermal shutdown occurs, the LNB output will be disabled and the TSD bit will be set. Not used. Power Not Good. Set to 1 when the LNB output is enabled and the LNB voltage is below 85% of the programmed voltage. The PNG is reset when the LNB volts are within 90% of the programmed LNB voltage. Not used. Thermal Shutdown. 1 indicates that the A8293 has detected an overtemperature condition and has disabled the LNB output. The disable bit, DIS, will also be set. The status of the overtemperature condition is sampled on the rising edge of the 9th clock pulse in the data read sequence. If the condition is no longer present, then the TSD bit will be reset, allowing the master to reenable the LNB output if required. If the condition is still present, then the TSD bit will remain at 1. Undervoltage Lockout. 1 indicates that the A8293 has detected that the input supply, VIN is, or has been, below the minimum level and an undervoltage lockout has occurred disabling the LNB outputs. The disable bit, DIS, will also be set and the A8293 will not reenable the output until so instructed by writing the relevant bit into the control registers. The status of the undervoltage condition is sampled on the rising edge of the 9th clock pulse in the data read sequence. If the condition is no longer present, then the VUV bit will be reset allowing the master to reenable the LNB output if required. If the condition is still present, then the VUV bit will remain at 1. Allegro MicroSystems, Inc. 115 Northeast Cutoff Worcester, Massachusetts 01615-0036 U.S.A. 1.508.853.5000; www.allegromicro.com 14 A8293 Single LNB Supply and Control Voltage Regulator Table 6. Status Register 2 Bit 0 – Bit 1 – Bit 2 – Bits 3 to 7 Bit Name Function 0 – Not Used 1 – Not Used 2 – Not Used 3 – Not Used 4 – Not Used 5 – Not Used 6 – Not Used 7 – Not Used Not used. Not used. Not used. Not used. Allegro MicroSystems, Inc. 115 Northeast Cutoff Worcester, Massachusetts 01615-0036 U.S.A. 1.508.853.5000; www.allegromicro.com 15 A8293 Single LNB Supply and Control Voltage Regulator Table 7. Component Selection Table Component C1, C4, C8 C2, C5 C3 Characteristics Manufacturer Device 100 nF, 50 V, X5R or X7R, 0603 100 μF, 35 VMIN , ESR < 75 mΩ, IRIPPLE > 700 mA Panasonic: EEU-FM1H101B ChemiCon: EKZE500ELL101MHB5D Nichicon: UHC1V101MPT 220 nF, 10 VMIN, X5R or X7R, 0402 or 0603 C6 1.0 μF, 25 VMIN, X5R or X7R, 1206 C7 10 nF, 10 VMIN, X5R or X7R, 0402 or 0603 C9 10 nF, 50 V, X5R or X7R, 0402 or 0603 C10 220 nF, 50 V, X5R or X7R, 0805 TDK: C3216X7R1E105K Murata: GRM31MR71E105KA01 Taiyo Yuden: TMK316BJ105KL-T Kemet: C1206C105K3RACTU Schottky diode, 40 V, 1 A, SOD-123 Diodes, Inc: B140HW-7 Central Semi: CMMSH1-40 D3 Schottky diode, 40 V, 3 A, SMA Sanken: SFPB-74 Vishay: B340A-E3/5AT Diodes, Inc.: B340A-13-F Central Senmi: CMSH3-40MA D4 TVS, 20 VRM, 32 VCL at 500 A (8/20 μs), 3000 W ST:LNBTVS6-221S Littelfuse: SMDJ20A L1 33 H, ISAT > 2.6 A, DCR < 90 mΩ TDK: TSL1112RA-330K2R3-PF Taiyo Yuden: LHLC10TB330K Coilcraft: DR0810-333L D1, D2 R1 to R4 Determined by VDD, bus capacitance, etc. Allegro MicroSystems, Inc. 115 Northeast Cutoff Worcester, Massachusetts 01615-0036 U.S.A. 1.508.853.5000; www.allegromicro.com 16 A8293 Single LNB Supply and Control Voltage Regulator Package ES 20-Pin MLP/QFN 0.30 4.00 ±0.10 1 2 0.50 20 20 0.95 A 1 2 4.00 ±0.10 2.45 4.10 2.45 4.10 21X D SEATING PLANE 0.08 C +0.05 0.25 –0.07 0.75 ±0.05 0.50 C C PCB Layout Reference View For Reference Only, not for tooling use (reference DWG-2864, JEDEC MO-220 WGGD) Dimensions in millimeters Exact case and lead configuration at supplier discretion within limits shown A Terminal #1 mark area B Exposed thermal pad (reference only, terminal #1 identifier appearance at supplier discretion) 0.40 ±0.10 B 2.45 2 1 C Reference land pattern layout (reference IPC7351 QFN50P400X400X80-21BM) All pads a minimum of 0.20 mm from all adjacent pads; adjust as necessary to meet application process requirements and PCB layout tolerances; when mounting on a multilayer PCB, thermal vias at the exposed thermal pad land can improve thermal dissipation (reference EIA/JEDEC Standard JESD51-5) D Coplanarity includes exposed thermal pad and terminals 20 2.45 Allegro MicroSystems, Inc. 115 Northeast Cutoff Worcester, Massachusetts 01615-0036 U.S.A. 1.508.853.5000; www.allegromicro.com 17 A8293 Single LNB Supply and Control Voltage Regulator Package ET 28-Pin MLP/QFN 0.30 5.00 ±0.15 1.15 28 1 2 0.50 28 1 A 5.00 ±0.15 3.15 4.80 3.15 29X D SEATING PLANE 0.08 C C 4.80 C +0.05 0.25 –0.07 PCB Layout Reference View 0.90 ±0.10 0.50 For Reference Only (reference JEDEC MO-220VHHD-1) Dimensions in millimeters Exact case and lead configuration at supplier discretion within limits shown +0.20 0.55 –0.10 A Terminal #1 mark area B 3.15 2 1 28 3.15 B Exposed thermal pad (reference only, terminal #1 identifier appearance at supplier discretion) C Reference land pattern layout (reference IPC7351 QFN50P500X500X100-29V1M); All pads a minimum of 0.20 mm from all adjacent pads; adjust as necessary to meet application process requirements and PCB layout tolerances; when mounting on a multilayer PCB, thermal vias at the exposed thermal pad land can improve thermal dissipation (reference EIA/JEDEC Standard JESD51-5) D Coplanarity includes exposed thermal pad and terminals Allegro MicroSystems, Inc. 115 Northeast Cutoff Worcester, Massachusetts 01615-0036 U.S.A. 1.508.853.5000; www.allegromicro.com 18 A8293 Single LNB Supply and Control Voltage Regulator Revision History Revision Revision Date Rev. 4 March 12, 2012 Description of Revision Update Output Voltage Amplitude I2C™ is a trademark of Philips Semiconductors. DiSEqC™ is a trademark of Eutelsat S.A. Copyright ©2007-2012, Allegro MicroSystems, Inc. Allegro MicroSystems, Inc. reserves the right to make, from time to time, such departures from the detail specifications as may be required to permit improvements in the performance, reliability, or manufacturability of its products. Before placing an order, the user is cautioned to verify that the information being relied upon is current. Allegro’s products are not to be used in life support devices or systems, if a failure of an Allegro product can reasonably be expected to cause the failure of that life support device or system, or to affect the safety or effectiveness of that device or system. The information included herein is believed to be accurate and reliable. However, Allegro MicroSystems, Inc. assumes no responsibility for its use; nor for any infringement of patents or other rights of third parties which may result from its use. For the latest version of this document, visit our website: www.allegromicro.com Allegro MicroSystems, Inc. 115 Northeast Cutoff Worcester, Massachusetts 01615-0036 U.S.A. 1.508.853.5000; www.allegromicro.com 19