ALTERA 5CEBA2U19C8N

Cyclone V Device Datasheet
June 2013
CV-51002-3.4
CV-51002-3.4
Datasheet
This datasheet describes the electrical characteristics, switching characteristics,
configuration specifications, and I/O timing for Cyclone® V devices.
Cyclone V devices are offered in commercial and industrial grades. Commercial
devices are offered in –C6 (fastest), –C7, and –C8 speed grades. Industrial devices are
offered in the –I7 speed grade. Automotive devices are offered in the –A7 speed
grade.
f For more information about the densities and packages of devices in the Cyclone V
family, refer to the Cyclone V Device Overview.
Electrical Characteristics
The following sections describe the electrical characteristics of Cyclone V devices.
Operating Conditions
Cyclone V devices are rated according to a set of defined parameters. To maintain the
highest possible performance and reliability of the Cyclone V devices, you must
consider the operating requirements described in this datasheet.
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for products or services.
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9001:2008
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Page 2
Electrical Characteristics
Absolute Maximum Ratings
Absolute maximum ratings define the maximum operating conditions for Cyclone V
devices. The values are based on experiments conducted with the devices and
theoretical modeling of breakdown and damage mechanisms.
The functional operation of the device is not implied for these conditions.
c Conditions other than those listed in Table 1 may cause permanent damage to the
device. Additionally, device operation at the absolute maximum ratings for extended
periods of time may have adverse effects on the device.
Table 1 lists the Cyclone V absolute maximum ratings.
Table 1. Absolute Maximum Ratings for Cyclone V Devices—Preliminary
Symbol
Description
Minimum
Maximum
Unit
VCC
Core voltage and periphery circuitry power supply
–0.5
1.35
V
VCCPGM
Configuration pins power supply
–0.5
3.75
V
VCC_AUX
Auxiliary supply
–0.5
3.75
V
VCCBAT
Battery back-up power supply for design security volatile key register
–0.5
3.75
V
VCCPD
I/O pre-driver power supply
–0.5
3.75
V
VCCIO
I/O power supply
–0.5
3.9
V
VCCA_FPLL
PLL analog power supply
–0.5
3.75
V
VCCH_GXB
Transceiver high voltage power
–0.5
3.75
V
VCCE_GXB
Transceiver power
–0.5
1.35
V
VCCL_GXB
Transceiver clock network power
–0.5
1.35
V
VI
DC input voltage
–0.5
3.80
V
VCC_HPS
HPS core voltage and periphery circuitry power supply
–0.5
1.35
V
VCCPD_HPS
HPS I/O pre-driver power supply
–0.5
3.75
V
VCCIO_HPS
HPS I/O power supply
–0.5
3.9
V
VCCRSTCLK_HPS HPS reset and clock input pins power supply
–0.5
3.75
V
VCCPLL_HPS
HPS PLL analog power supply
–0.5
3.75
V
IOUT
DC output current per pin
–25
40
mA
TJ
Operating junction temperature
–55
125
°C
TSTG
Storage temperature (No bias)
–65
150
°C
Cyclone V Device Datasheet
June 2013
Altera Corporation
Electrical Characteristics
Page 3
Maximum Allowed Overshoot and Undershoot Voltage
During transitions, input signals may overshoot to the voltage listed in Table 2 and
undershoot to -2.0 V for input currents less than 100 mA and periods shorter than
20 ns.
The maximum allowed overshoot duration is specified as a percentage of high time
over the lifetime of the device. A DC signal is equivalent to 100% duty cycle.
For example, a signal that overshoots to 4.00 V can only be at 4.00 V for ~15% over the
lifetime of the device; for a device lifetime of 10 years, this amounts to 1.5 years.
Table 2 lists the maximum allowed input overshoot voltage and the duration of the
overshoot voltage as a percentage of device lifetime.
Table 2. Maximum Allowed Overshoot During Transitions for Cyclone V Devices—Preliminary
Symbol
Vi (AC)
Description
AC input voltage
June 2013 Altera Corporation
Condition (V)
Overshoot Duration as % of High Time
Unit
3.8
100
%
3.85
68
%
3.9
45
%
3.95
28
%
4
15
%
4.05
13
%
4.1
11
%
4.15
9
%
4.2
8
%
4.25
7
%
4.3
5.4
%
4.35
3.2
%
4.4
1.9
%
4.45
1.1
%
4.5
0.6
%
4.55
0.4
%
4.6
0.2
%
Cyclone V Device Datasheet
Page 4
Electrical Characteristics
Recommended Operating Conditions
Recommended operating conditions are the functional operation limits for the AC
and DC parameters for Cyclone V devices.
Table 3 lists the steady-state voltage values expected from Cyclone V devices. Power
supply ramps must all be strictly monotonic, without plateaus.
Table 3. Recommended Operating Conditions for Cyclone V Devices—Preliminary (Part 1 of 2)
Symbol
Description
Condition
Minimum
Typical
Maximum
Unit
VCC
Core voltage, periphery circuitry power supply,
transceiver physical coding sublayer (PCS)
power supply, and transceiver PCI Express®
(PCIe®) hard IP digital power supply
—
1.07
1.1
1.13
V
VCC_AUX
Auxiliary supply
—
2.375
2.5
2.625
V
I/O pre-driver (3.3 V) power supply
—
3.135
3.3
3.465
V
I/O pre-driver (3.0 V) power supply
—
2.85
3.0
3.15
V
I/O pre-driver (2.5 V) power supply
—
2.375
2.5
2.625
V
I/O buffers (3.3 V) power supply
—
3.135
3.3
3.465
V
I/O buffers (3.0 V) power supply
—
2.85
3.0
3.15
V
I/O buffers (2.5 V) power supply
—
2.375
2.5
2.625
V
I/O buffers (1.8 V) power supply
—
1.71
1.8
1.89
V
I/O buffers (1.5 V) power supply
—
1.425
1.5
1.575
V
I/O buffers (1.35 V) power supply
—
1.283
1.35
1.418
V
I/O buffers (1.25 V) power supply
—
1.19
1.25
1.31
V
I/O buffers (1.2 V) power supply
—
1.14
1.2
1.26
V
Configuration pins (3.3 V) power supply
—
3.135
3.3
3.465
V
Configuration pins (3.0 V) power supply
—
2.85
3.0
3.15
V
Configuration pins (2.5 V) power supply
—
2.375
2.5
2.625
V
Configuration pins (1.8 V) power supply
—
1.71
1.8
1.89
V
PLL analog voltage regulator power supply
—
2.375
2.5
2.625
V
Battery back-up power supply
(For design security volatile key register)
—
1.2
—
3.0
V
VI
DC input voltage
—
–0.5
—
3.6
V
VO
Output voltage
—
0
—
VCCIO
V
Commercial
0
—
85
°C
Industrial
–40
—
100
°C
Automotive
–40
—
125
°C
June 2013
Altera Corporation
VCCPD
(1)
VCCIO
VCCPGM
VCCA_FPLL
VCCBAT
TJ
(2)
(3)
Operating junction temperature
Cyclone V Device Datasheet
Electrical Characteristics
Page 5
Table 3. Recommended Operating Conditions for Cyclone V Devices—Preliminary (Part 2 of 2)
Symbol
tRAMP (4)
Description
Power supply ramp time
Condition
Minimum
Typical
Maximum
Unit
Standard POR
200 µs
—
100 ms
—
Fast POR
200 µs
—
4 ms
—
Notes to Table 3:
(1) VCCPD must be 2.5 V when VCCIO is 2.5, 1.8, 1.5, 1.35, 1.25 or 1.2 V. VCCPD must be 3.0 V when VCCIO is 3.0 V. VCCPD must be 3.3 V when VCCIO
is 3.3 V.
(2) PLL digital voltage is regulated from VCCA_FPLL.
(3) If you do not use the design security feature in Cyclone V devices, connect VCCBAT to a 1.5-V, 2.5-V, or 3.0-V power supply. The power-on reset
(POR) circuitry monitors VCCBAT. Cyclone V devices do not exit POR if VCCBAT stays low.
(4) This is also applicable to HPS power supply. For HPS power supply, refer to tRAMP specifications for standard POR when HPS_PORSEL = 0 and
tRAMP specifications for fast POR when HPS_PORSEL = 1.
Table 4 lists the transceiver power supply recommended operating conditions for
Cyclone V GX and GT devices.
Table 4. Transceiver Power Supply Operating Conditions for Cyclone V GX and GT Devices—Preliminary
Symbol
VCCH_GXBL
VCCE_GXBL (1), (2)
VCCL_GXBL
(1), (2)
Description
Minimum
Typical
Maximum
Unit
Transceiver high voltage power (left side)
2.375
2.5
2.625
V
Transmitter and receiver power (left side)
1.07/1.17
1.1/1.2
1.13/1.23
V
Clock network power (left side)
1.07/1.17
1.1/1.2
1.13/1.23
V
Notes to Table 4:
(1) Altera recommends increasing the VCCE_GXBL and VCCL_GXBL typical value from 1.1 V to 1.2 V for Cyclone V GT FPGA systems which require full
compliance to the PCIe Gen2 transmit jitter specification. For more information about the maximum full duplex channels recommended in
Cyclone V GT and ST devices under this condition, refer to the Transceiver Protocol Configurations in Cyclone V Devices chapter.
(2) Altera recommends increasing the VCCE_GXBL and VCCL_GXBL typical value from 1.1 V to 1.2 V for full compliance to CPRI transmit jitter
specification at 4.9152 Gbps (Cyclone V GT and ST devices) and 6.144Gbps (Cyclone V GT devices only). For more information about the
maximum full duplex channels recommended in Cyclone V GT devices for CPRI 6.144 Gbps, refer to the Transceiver Protocol Configurations
in Cyclone V Devices chapter.
Table 5 lists the steady-state voltage values expected from Cyclone V
system-on-a-chip (SoC) FPGA with ARM®-based hard processor system (HPS). Power
supply ramps must all be strictly monotonic, without plateaus.
Table 5. HPS Power Supply Operating Conditions for Cyclone V SE, SX, and ST Devices (1)—Preliminary (Part 1 of 2)
Symbol
VCC_HPS
VCCPD_HPS
VCCIO_HPS
(2)
Description
Minimum
Typical
Maximum
Unit
HPS core voltage and periphery circuitry power
supply
1.07
1.1
1.13
V
HPS I/O pre-driver (3.3 V) power supply
3.135
3.3
3.465
V
HPS I/O pre-driver (3.0 V) power supply
2.85
3.0
3.15
V
HPS I/O pre-driver (2.5 V) power supply
2.375
2.5
2.625
V
HPS I/O buffers (3.3 V) power supply
3.135
3.3
3.465
V
HPS I/O buffers (3.0 V) power supply
2.85
3.0
3.15
V
HPS I/O buffers (2.5 V) power supply
2.375
2.5
2.625
V
HPS I/O buffers (1.8 V) power supply
1.71
1.8
1.89
V
HPS I/O buffers (1.5 V) power supply
1.425
1.5
1.575
V
HPS I/O buffers (1.2 V) power supply
1.14
1.2
1.26
V
June 2013 Altera Corporation
Cyclone V Device Datasheet
Page 6
Electrical Characteristics
Table 5. HPS Power Supply Operating Conditions for Cyclone V SE, SX, and ST Devices (1)—Preliminary (Part 2 of 2)
Symbol
Description
Minimum
Typical
Maximum
Unit
HPS reset and clock input pins (3.3 V) power supply
3.135
3.3
3.465
V
HPS reset and clock input pins (3.0 V) power supply
2.85
3.0
3.15
V
HPS reset and clock input pins (2.5 V) power supply
2.375
2.5
2.625
V
HPS reset and clock input pins (1.8 V) power supply
1.71
1.8
1.89
V
VCCPLL_HPS
HPS PLL analog voltage regulator power supply
2.375
2.5
2.625
V
VCC_AUX_SHARED
HPS and FPGA shared auxiliary power supply
2.375
2.5
2.625
V
VCCRSTCLK_HPS
Notes to Table 5:
(1) Refer to Table 3 for the steady-state voltage values expected from the FPGA portion of the Cyclone V system-on-a-chip (SoC) FPGAs.
(2) VCCPD_HPS must be 2.5 V when VCCIO_HPS is 2.5, 1.8, 1.5, or 1.2 V. VCCPD_HPS must be 3.0 V when VCCIO_HPS is 3.0 V. VCCPD_HPS must be 3.3 V when
VCCIO_HPS is 3.3 V.
DC Characteristics
This section lists the following specifications:
■
Supply Current and Power Consumption
■
I/O Pin Leakage Current
■
Bus Hold Specifications
■
OCT Specifications
■
Pin Capacitance
■
Hot Socketing
Supply Current and Power Consumption
Standby current is the current drawn from the respective power rails used for power
budgeting.
Altera offers two ways to estimate power for your design—the Excel-based Early
Power Estimator (EPE) and the Quartus® II PowerPlay Power Analyzer feature.
Use the Excel-based Early Power Estimator (EPE) before you start your design to
estimate the supply current for your design. The EPE provides a magnitude estimate
of the device power because these currents vary greatly with the resources you use.
The Quartus II PowerPlay Power Analyzer provides better quality estimates based on
the specifics of the design after you complete place-and-route. The PowerPlay Power
Analyzer can apply a combination of user-entered, simulation-derived, and estimated
signal activities that, when combined with detailed circuit models, yields very
accurate power estimates.
f For more information about power estimation tools, refer to the PowerPlay Early Power
Estimator User Guide and the PowerPlay Power Analysis chapter in the Quartus II
Handbook.
Cyclone V Device Datasheet
June 2013
Altera Corporation
Electrical Characteristics
Page 7
I/O Pin Leakage Current
Table 6 lists the Cyclone V I/O pin leakage current specifications.
Table 6. I/O Pin Leakage Current for Cyclone V Devices—Preliminary
Symbol
Description
Conditions
Min
Typ
Max
Unit
II
Input pin
VI = 0 V to VCCIOMAX
–30
—
30
µA
IOZ
Tri-stated I/O pin
VO = 0 V to VCCIOMAX
–30
—
30
µA
Bus Hold Specifications
Table 7 lists the Cyclone V device bus hold specifications. The bus-hold trip points are
based on calculated input voltages from the JEDEC standard.
Table 7. Bus Hold Parameters for Cyclone V Devices—Preliminary
VCCIO (V)
1.2
Parameter Symbol Conditions
1.5
1.8
2.5
3.0
3.3
Unit
Min
Max
Min
Max
Min
Max
Min
Max
Min
Max
Min
Max
8
—
12
—
30
—
50
—
70
—
70
—
µA
–8
—
–12
—
–30
—
–50
—
–70
—
–70
—
µA
Bus-hold,
low,
sustaining
current
ISUSL
Bus-hold,
high,
sustaining
current
ISUSH
Bus-hold,
low,
overdrive
current
IODL
0V < VIN <
VCCIO
—
125
—
175
—
200
—
300
—
500
—
500
µA
Bus-hold,
high,
overdrive
current
IODH
0V < VIN <
VCCIO
—
–125
—
–175
—
–200
—
–300
—
–500
—
–500
µA
Bus-hold
trip point
VTRIP
—
0.3
0.9
1.07
0.7
1.7
0.8
2
0.8
2
V
VIN > VIL
(max.)
VIN < VIH
(min.)
June 2013 Altera Corporation
0.375 1.125 0.68
Cyclone V Device Datasheet
Page 8
Electrical Characteristics
OCT Specifications
If you enable on-chip termination (OCT) calibration, calibration is automatically
performed at power up for I/Os connected to the calibration block.
Table 8 lists the Cyclone V OCT termination calibration accuracy specifications. The
OCT calibration accuracy is valid at the time of calibration only.
Table 8. OCT Calibration Accuracy Specifications for Cyclone V Devices
Calibration Accuracy
Symbol
Description
Conditions (V)
Unit
–C6
–C7, –I7
–C8, –A7
25-Ω RS
Internal series termination
with calibration
(25-Ω setting)
VCCIO = 3.0, 2.5,
1.8, 1.5, 1.2
±15
±15
±15
%
50-Ω RS
Internal series termination
with calibration
(50-Ω setting)
VCCIO = 3.0, 2.5,
1.8, 1.5, 1.2
±15
±15
±15
%
34-Ω and 40-Ω RS
Internal series termination
with calibration
(34-Ω and 40-Ω setting)
VCCIO = 1.5, 1.35,
1.25, 1.2
±15
±15
±15
%
48-Ω, 60-Ω, and
80-Ω RS
Internal series termination
with calibration
(48-Ω, 60-Ω, and 80-Ω
setting)
VCCIO = 1.2
±15
±15
±15
%
50-Ω RT
Internal parallel
termination with calibration
(50-Ω setting)
VCCIO = 2.5, 1.8,
1.5, 1.2
-10 to +40
-10 to +40
-10 to +40
%
20-Ω, 30-Ω,
40-Ω, 60-Ω, and
120-Ω RT
Internal parallel
termination with calibration
(20-Ω, 30-Ω, 40-Ω,
60-Ω, and 120-Ω setting)
VCCIO = 1.5, 1.35,
1.25
-10 to +40
-10 to +40
-10 to +40
%
VCCIO = 1.2
-10 to +40
-10 to +40
-10 to +40
%
VCCIO = 3.0, 2.5,
1.8, 1.5, 1.2
±15
±15
±15
%
Internal parallel
60-Ω and 120-Ω RT termination with calibration
(60-Ω and 120-Ω setting)
25-Ω RS_left_shift
Internal left shift series
termination with calibration
(25-Ω RS_left_shift setting)
1
Cyclone V Device Datasheet
Calibration accuracy for the calibrated on-chip series termination (RS OCT) and
on-chip parallel termination (RT OCT) are applicable at the moment of calibration.
When process, voltage, and temperature (PVT) conditions change after calibration,
the tolerance may change.
June 2013
Altera Corporation
Electrical Characteristics
Page 9
Table 9 lists the Cyclone V OCT without calibration resistance tolerance to PVT
changes.
Table 9. OCT Without Calibration Resistance Tolerance Specifications for Cyclone V Devices—Preliminary
Resistance Tolerance
Symbol
Description
Conditions (V)
Unit
–C6
–C7, –I7
–C8, –A7
25-Ω RS
Internal series termination
without calibration
(25-Ω setting)
VCCIO = 3.0 and 2.5
±30
±40
±40
%
25-Ω RS
Internal series termination
without calibration
(25-Ω setting)
VCCIO = 1.8 and 1.5
±30
±40
±40
%
25-Ω RS
Internal series termination
without calibration
(25-Ω setting)
VCCIO = 1.2
±35
±50
±50
%
50-Ω RS
Internal series termination
without calibration (50-Ω
setting)
VCCIO = 3.0 and 2.5
±30
±40
±40
%
50-Ω RS
Internal series termination
without calibration
(50-Ω setting)
VCCIO = 1.8 and 1.5
±30
±40
±40
%
50-Ω RS
Internal series termination
without calibration
(50-Ω setting)
VCCIO = 1.2
±35
±50
±50
%
100-Ω RD
Internal differential
termination (100-Ω
setting)
VCCIO = 2.5
±25
±40
±40
%
Use Table 10 to determine the OCT variation after power-up calibration and
Equation 1 to determine the OCT variation without recalibration.
Equation 1. OCT Variation Without Recalibration (1),
(2), (3), (4), (5), (6)—Preliminary
dR
dR
R OCT = R SCAL ⎛ 1 + 〈 ------- × ΔT〉 ± 〈 ------- × ΔV 〉⎞
⎝
⎠
dT
dV
Notes to Equation 1:
(1) The ROCT value calculated from Equation 1 shows the range of OCT resistance with the variation of temperature and
VCCIO.
(2) RSCAL is the OCT resistance value at power-up.
(3) ΔT is the variation of temperature with respect to the temperature at power up.
(4) ΔV is the variation of voltage with respect to VCCIO at power up.
(5) dR/dT is the percentage change of RSCAL with temperature.
(6) dR/dV is the percentage change of RSCAL with voltage.
June 2013 Altera Corporation
Cyclone V Device Datasheet
Page 10
Electrical Characteristics
Table 10 lists the OCT variation with temperature and voltage after the power-up
calibration. The OCT variation is valid for a VCCIO range of ±5% and a temperature
range of 0° to 85°C.
Table 10. OCT Variation after Power-Up Calibration for Cyclone V Devices
Symbol
Description
VCCIO (V)
Typical
3.0
0.100
2.5
0.100
1.8
0.100
1.5
0.100
1.35
0.150
1.25
0.150
1.2
0.150
3.0
0.189
2.5
0.208
1.8
0.266
1.5
0.273
1.35
0.200
1.25
0.200
1.2
0.317
OCT variation with voltage without
recalibration
dR/dV
OCT variation with temperature
without recalibration
dR/dT
Unit
%/mV
%/°C
Pin Capacitance
Table 11 lists the Cyclone V device family pin capacitance.
Table 11. Pin Capacitance for Cyclone V Devices
Symbol
Description
Value
Unit
CIOTB
Input capacitance on top and bottom I/O pins
5.5
pF
CIOLR
Input capacitance on left and right I/O pins
5.5
pF
COUTFB
Input capacitance on dual-purpose clock output and feedback pins
5.5
pF
Hot Socketing
Table 12 lists the hot socketing specifications for Cyclone V devices.
Table 12. Hot Socketing Specifications for Cyclone V Devices—Preliminary
Symbol
Description
Maximum
IIOPIN (DC)
DC current per I/O pin
300 μA
IIOPIN (AC)
AC current per I/O pin
8 mA
IXCVR-TX (DC)
DC current per transceiver transmitter (TX) pin
100 mA
IXCVR-RX (DC)
DC current per transceiver receiver (RX) pin
50 mA
(1)
Note to Table 12:
(1) The I/O ramp rate is 10 ns or more. For ramp rates faster than 10 ns, |IIOPIN| = C dv/dt, in which C is the I/O pin
capacitance and dv/dt is the slew rate.
Cyclone V Device Datasheet
June 2013
Altera Corporation
Electrical Characteristics
Page 11
Internal Weak Pull-Up Resistor
Table 13 lists the weak pull-up resistor values for Cyclone V devices.
All I/O pins have an option to enable weak pull-up except the configuration, test, and
JTAG pins. For more information about the pins that support internal weak pull-up
and internal weak pull-down features, refer to the Cyclone V Device Family Pin
Connection Guidelines.
Table 13. Internal Weak Pull-Up Resistor Values for Cyclone V Devices—Preliminary
Symbol
RPU
Description
Value of the I/O pin pull-up resistor before and during
configuration, as well as user mode if you have enabled the
programmable pull-up resistor option.
Conditions (V) (1)
Typ (2)
Unit
VCCIO = 3.3 ±5%
25
kΩ
VCCIO = 3.0 ±5%
25
kΩ
VCCIO = 2.5 ±5%
25
kΩ
VCCIO = 1.8 ±5%
25
kΩ
VCCIO = 1.5 ±5%
25
kΩ
VCCIO = 1.35 ±5%
25
kΩ
VCCIO = 1.25 ±5%
25
kΩ
VCCIO = 1.2 ±5%
25
kΩ
Notes to Table 13:
(1) Pin pull-up resistance values may be lower if an external source drives the pin higher than VCCIO.
(2) These specifications are valid with ±10% tolerances to cover changes over PVT.
I/O Standard Specifications
Table 14 through Table 19 list the input voltage (VIH and VIL), output voltage (VOH and
VOL), and current drive characteristics (IOH and IOL) for various I/O standards
supported by Cyclone V devices.
For an explanation of terms used in Table 14 through Table 19, refer to “Glossary” on
page 1–54.
Table 14. Single-Ended I/O Standards for Cyclone V Devices—Preliminary (Part 1 of 2)
I/O
Standard
VCCIO (V)
VIL (V)
VIH (V)
VOL (V)
VOH (V)
IOL (1) IOH (1)
(mA) (mA)
Min
Typ
Max
Min
Max
Min
Max
Max
Min
3.3-V
LVTTL
3.135
3.3
3.465 –0.3
0.8
1.7
3.6
0.45
2.4
4
–4
3.3-V
LVCMOS
3.135
3.3
3.465 –0.3
0.8
1.7
3.6
0.2
VCCIO – 0.2
2
–2
3.0-V
LVTTL
2.85
3
3.15
–0.3
0.8
1.7
3.6
0.4
2.4
2
–2
3.0-V
LVCMOS
2.85
3
3.15
–0.3
0.8
1.7
3.6
0.2
VCCIO – 0.2
0.1
–0.1
3.0-V PCI
2.85
3
3.15
—
0.3 x VCCIO
0.5 x VCCIO
VCCIO + 0.3
0.1 x VCCIO
0.9 x VCCIO
1.5
–0.5
3.0-V PCI-X
2.85
3
3.15
—
0.35 x VCCIO
0.5 x VCCIO
VCCIO + 0.3
0.1 x VCCIO
0.9 x VCCIO
1.5
–0.5
2.5 V
2.375
2.5
2.625 –0.3
0.7
1.7
3.6
0.4
2
1
–1
1.8 V
1.71
1.8
1.89
–0.3 0.35 x VCCIO 0.65 x VCCIO
VCCIO + 0.3
0.45
VCCIO – 0.45
2
–2
1.5 V
1.425
1.5
1.575 –0.3 0.35 x VCCIO 0.65 x VCCIO
VCCIO + 0.3
0.25 x VCCIO 0.75 x VCCIO
2
–2
June 2013 Altera Corporation
Cyclone V Device Datasheet
Page 12
Electrical Characteristics
Table 14. Single-Ended I/O Standards for Cyclone V Devices—Preliminary (Part 2 of 2)
I/O
Standard
1.2 V
VCCIO (V)
VIL (V)
VIH (V)
Min
Typ
Max
Min
Max
1.14
1.2
1.26
–0.3 0.35 x VCCIO
Min
Max
0.65 x VCCIO
VCCIO + 0.3
VOL (V)
VOH (V)
Max
Min
IOL (1) IOH (1)
(mA) (mA)
0.25 x VCCIO 0.75 x VCCIO
2
–2
Note to Table 14:
(1) To meet the IOL and IOH specifications, you must set the current strength settings accordingly. For example, to meet the 3.3-V LVTTL specification
(4 mA), you should set the current strength settings to 4 mA. Setting at lower current strength may not meet the IOL and IOH specifications in the
handbook.
Table 15. Single-Ended SSTL, HSTL, and HSUL I/O Reference Voltage Specifications for Cyclone V Devices—Preliminary
I/O
Standard
VCCIO(V)
VREF(V)
VTT(V)
Min
Typ
Max
Min
Typ
Max
Min
Typ
Max
SSTL-2
Class I, II
2.375
2.5
2.625
0.49 x VCCIO
0.5 x VCCIO
0.51 x VCCIO
VREF – 0.04
VREF
VREF + 0.04
SSTL-18
Class I, II
1.71
1.8
1.89
0.833
0.9
0.969
VREF – 0.04
VREF
VREF + 0.04
SSTL-15
Class I, II
1.425
1.5
1.575
0.49 x VCCIO
0.5 x VCCIO
0.51 x VCCIO
0.49 x VCCIO
0.5 x VCCIO
0.51 x VCCIO
SSTL-135
Class I, II
1.283
1.35
1.418
0.49 x VCCIO
0.5 x VCCIO
0.51 x VCCIO
0.49 x VCCIO
0.5 x VCCIO
0.51 x VCCIO
SSTL-125
Class I, II
1.19
1.25
1.26
0.49 x VCCIO
0.5 x VCCIO
0.51 x VCCIO
0.49 x VCCIO
0.5 x VCCIO
0.51 x VCCIO
HSTL-18
Class I, II
1.71
1.8
1.89
0.85
0.9
0.95
—
VCCIO/2
—
HSTL-15
Class I, II
1.425
1.5
1.575
0.68
0.75
0.9
—
VCCIO/2
—
HSTL-12
Class I, II
1.14
1.2
1.26
0.47 x VCCIO
0.5 x VCCIO
0.53 x VCCIO
—
VCCIO/2
—
HSUL-12
1.14
1.2
1.3
0.49 x VCCIO
0.5 x VCCIO
0.51 x VCCIO
—
—
—
Table 16. Single-Ended SSTL, HSTL, and HSUL I/O Standards Signal Specifications for Cyclone V Devices—
Preliminary (Part 1 of 2)
VIL(DC) (V)
VIH(DC) (V)
VIL(AC) (V)
VIH(AC) (V)
VOL (V)
VOH (V)
Min
Max
Min
Max
Max
Min
Max
Min
Iol (1)
(mA)
SSTL-2
Class I
–0.3
VREF – 0.15
VREF + 0.15
VCCIO + 0.3
VREF – 0.31
VREF + 0.31
VTT – 0.608
VTT + 0.608
8.1
–8.1
SSTL-2
Class II
–0.3
VREF – 0.15
VREF + 0.15
VCCIO + 0.3
VREF – 0.31
VREF + 0.31
VTT – 0.81
VTT + 0.81
16.2
–16.2
SSTL-18
Class I
–0.3
VREF –
0.125
VREF + 0.125
VCCIO + 0.3
VREF – 0.25
VREF + 0.25
VTT – 0.603
VTT + 0.603
6.7
–6.7
SSTL-18
Class II
–0.3
VREF –
0.125
VREF + 0.125
VCCIO + 0.3
VREF – 0.25
VREF + 0.25
0.28
VCCIO – 0.28
13.4
–13.4
SSTL-15
Class I
—
VREF – 0.1
VREF + 0.1
—
VREF –
0.175
VREF + 0.175
0.2 x VCCIO
0.8 x VCCIO
8
–8
I/O
Standard
Cyclone V Device Datasheet
June 2013
Altera Corporation
Ioh (1)
(mA)
Electrical Characteristics
Page 13
Table 16. Single-Ended SSTL, HSTL, and HSUL I/O Standards Signal Specifications for Cyclone V Devices—
Preliminary (Part 2 of 2)
VIL(DC) (V)
VIH(DC) (V)
VIL(AC) (V)
VIH(AC) (V)
VOL (V)
VOH (V)
Min
Max
Min
Max
Max
Min
Max
Min
Iol (1)
(mA)
SSTL-15
Class II
—
VREF – 0.1
VREF + 0.1
—
VREF –
0.175
VREF + 0.175
0.2 x VCCIO
0.8 x VCCIO
16
–16
SSTL-135
—
VREF – 0.09
VREF + 0.09
—
VREF – 0.16
VREF + 0.16
0.2 x VCCIO
0.8 x VCCIO
—
—
SSTL-125
—
VREF – 0.85
VREF + 0.85
—
VREF – 0.15
VREF + 0.15
0.2 x VCCIO
0.8 x VCCIO
—
—
HSTL-18
Class I
—
VREF – 0.1
VREF + 0.1
—
VREF – 0.2
VREF + 0.2
0.4
VCCIO – 0.4
8
–8
HSTL-18
Class II
—
VREF – 0.1
VREF + 0.1
—
VREF – 0.2
VREF + 0.2
0.4
VCCIO – 0.4
16
–16
HSTL-15
Class I
—
VREF – 0.1
VREF + 0.1
—
VREF – 0.2
VREF + 0.2
0.4
VCCIO – 0.4
8
–8
HSTL-15
Class II
—
VREF – 0.1
VREF + 0.1
—
VREF – 0.2
VREF + 0.2
0.4
VCCIO – 0.4
16
–16
HSTL-12
Class I
–0.1
5
VREF – 0.08
VREF + 0.08 VCCIO + 0.15
VREF – 0.15
VREF + 0.15
0.25 x VCCIO 0.75 x VCCIO
8
–8
HSTL-12
Class II
–0.1
5
VREF – 0.08
VREF + 0.08 VCCIO + 0.15
VREF – 0.15
VREF + 0.15
0.25 x VCCIO 0.75 x VCCIO
16
–16
HSUL-12
—
VREF – 0.13
VREF + 0.13
VREF – 0.22
VREF + 0.22
0.1 x VCCIO
—
—
I/O
Standard
—
0.9 x VCCIO
Ioh (1)
(mA)
Note to Table 16:
(1) To meet the IOL and IOH specifications, you must set the current strength settings accordingly. For example, to meet the SSTL15CI specification (8 mA), you
should set the current strength settings to 8 mA. Setting at lower current strength may not meet the IOL and IOH specifications in the handbook.
Table 17. Differential SSTL I/O Standards for Cyclone V Devices—Preliminary
VCCIO (V)
I/O Standard
VSWING(DC) (V)
VX(AC) (V)
VSWING(AC) (V)
Min
Typ
Max
Min
Max
Min
Typ
Max
Min
Max
SSTL-2 Class I, II
2.375
2.5
2.625
0.3
VCCIO +
0.6
VCCIO/2 –
0.2
—
VCCIO/2 +
0.2
0.62
VCCIO + 0.6
SSTL-18 Class I, II
1.71
1.8
1.89
0.25
VCCIO +
0.6
VCCIO/2 –
0.175
—
VCCIO/2 +
0.175
0.5
VCCIO + 0.6
SSTL-15 Class I, II
1.425
1.5
1.575
0.2
(1)
VCCIO/2 –
0.15
—
VCCIO/2 +
0.15
2(VIH(AC) –
VREF)
2(VIL(AC) –
VREF)
SSTL-135
1.283
1.35
1.45
0.18
(1)
VCCIO/2 –
0.15
VCCIO/2
VCCIO/2 +
0.15
2(VIH(AC) –
VREF)
2(VIL(AC) –
VREF)
SSTL-125
1.19
1.25
1.31
0.18
(1)
VCCIO/2 –
0.15
VCCIO/2
VCCIO/2 +
0.15
2(VIH(AC) –
VREF)
2(VIL(AC) –
VREF)
Note to Table 17:
(1) The maximum value for VSWING(DC) is not defined. However, each single-ended signal needs to be within the respective single-ended limits
(VIH(DC) and VIL(DC)).
June 2013 Altera Corporation
Cyclone V Device Datasheet
Page 14
Electrical Characteristics
Table 18. Differential HSTL and HSUL I/O Standards for Cyclone V Devices—Preliminary
I/O
Standard
VCCIO (V)
VDIF(DC) (V)
VX(AC) (V)
VCM(DC) (V)
VDIF(AC) (V)
Min
Typ
Max
Min
Max
Min
Typ
Max
Min
Typ
Max
Min
Max
HSTL-18
Class I, II
1.71
1.8
1.89
0.2
—
0.78
—
1.12
0.78
—
1.12
0.4
—
HSTL-15
Class I, II
1.425
1.5
1.575
0.2
—
0.68
—
0.9
0.68
—
0.9
0.4
—
HSTL-12
Class I, II
1.14
1.2
1.26
0.16
VCCIO
+ 0.3
—
0.5 x
VCCIO
—
0.4 x V
0.5 x
VCCIO
0.6 x
VCCIO
0.3
VCCIO
+ 0.48
HSUL-12
1.14
0.26
0.5 x VCCIO
– 0.12
0.5 x
VCCIO
0.5 x
VCCIO
+0.12
0.5 x
VCCIO
0.6 x
VCCIO
0.44
0.44
1.2
1.3
0.26
CCIO
0.4 x V
CCIO
Table 19. Differential I/O Standard Specifications for Cyclone V Devices—Preliminary
I/O Standard
Min
PCML
2.5 V
LVDS (3)
VID (mV) (1)
VCCIO (V)
Typ
Max
Min Condition Max
LVPECL (6)
Min
Condition
VOD (V)
Max
Min
(2)
VOCM (V)
Typ Max
Min
Typ
(2)
Max
Transmitter, receiver, and input reference clock pins of high-speed transceivers use the PCML I/O standard. For
transmitter, receiver, and reference clock I/O pin specifications, refer to Table 20.
2.375 2.5 2.625 100
RSDS (HIO) (4) 2.375 2.5 2.625 100
Mini-LVDS
(HIO) (5)
VICM(DC) (V)
2.375 2.5 2.625 200
2.375 2.5 2.625 300
0.05
DMAX
≤700 Mbps
1.80
1.05
DMAX
>700 Mbps
1.55
—
0.25
—
600
0.300
VCM =
1.25 V
—
VCM =
1.25 V
—
—
0.247
—
0.6
1.45
0.1
0.2
0.6
0.5
1.2
1.4
—
1.425
0.25
—
0.6
1
1.2
1.4
0.60
DMAX
≤700 Mbps
1.80
DMAX
>700 Mbps
—
—
—
—
—
—
1.00
1.60
—
1.125 1.25 1.375
SLVS
2.375 2.5 2.625 100
VCM =
1.25 V
—
0.05
—
1.8
—
—
—
—
—
—
Sub-LVDS
2.375 2.5 2.625 100
VCM =
1.25 V
—
0.05
—
1.8
—
—
—
—
—
—
HiSpi
2.375 2.5 2.625 100
VCM =
1.25 V
—
0.05
—
1.8
—
—
—
—
—
—
Notes to Table 19:
(1) The minimum VID value is applicable over the entire common mode range, VCM.
(2) RL range: 90 ≤ RL ≤ 110 Ω
(3) For optimized LVDS receiver performance, the receiver voltage input range must be within 1.0 V to 1.6 V for data rate above 700 Mbps and 0.00 V to 1.85 V
for data rate below 700 Mbps.
(4) For optimized RSDS receiver performance, the receiver voltage input range must be within 0.25 V to 1.45 V.
(5) For optimized mini-LVDS receiver performance, the receiver voltage input range must be within 0.300 V to 1.425 V.
(6) For optimized LVPECL receiver performance, the receiver voltage input range must be within 0.85 V to 1.75 V for data rate above 700 Mbps and 0.45 V to
1.95 V for data rate below 700 Mbps.
Cyclone V Device Datasheet
June 2013
Altera Corporation
Switching Characteristics
Page 15
Switching Characteristics
This section provides performance characteristics of Cyclone V core and periphery
blocks for commercial grade devices.
Transceiver Performance Specifications
This section describes transceiver performance specifications.
Table 20 lists the Cyclone V GX, GT, SX, and ST transceiver specifications.
Table 20. Transceiver Specifications for Cyclone V GX, GT, SX, and ST Devices—Preliminary (Part 1 of 4)
Symbol/
Description
Conditions
Transceiver
Speed Grade 6
Transceiver
Speed Grade 5 (1)
Min
Typ
Max
Min
Typ
Max
Transceiver
Speed Grade 7
Min
Typ
Unit
Max
Reference Clock
Supported I/O
Standards
Input frequency from
REFCLK input pins (3)
1.2 V PCML, 1.5 V PCML, 2.5 V PCML, Differential LVPECL (2), HCSL, and LVDS
—
27
—
550
27
—
550
27
—
550
MHz
Rise time
20% to 80% of
rising clock
edge
—
—
250
—
—
250
—
—
250
ps
Fall time
80% to 20% of
falling clock
edge
—
—
250
—
—
250
—
—
250
ps
Duty cycle
—
45
—
55
45
—
55
45
—
55
%
Peak-to-peak
differential input voltage
—
200
—
2000
200
—
2000
200
—
2000
mV
Spread-spectrum
modulating clock
frequency
PCIe
30
—
33
30
—
33
30
—
33
kHz
Spread-spectrum
downspread
PCIe
—
—
—
—
—
—
—
On-chip termination
resistors
—
—
—
—
—
—
—
Ω
VICM (AC coupled)
—
VCCE_GXBL supply (5), (6)
VICM (DC coupled)
HCSL I/O
standard for the
PCIe reference
clock
250
—
550
250
—
550
250
—
550
mV
10 Hz
—
—
–50
—
—
–50
—
—
–50
dBc/Hz
100 Hz
—
—
–80
—
—
–80
—
—
–80
dBc/Hz
1 KHz
—
—
–110
—
—
–110
—
—
–110
dBc/Hz
10 KHz
—
—
–120
—
—
–120
—
—
–120
dBc/Hz
100 KHz
—
—
–120
—
—
–120
—
—
–120
dBc/Hz
≥1 MHz
—
—
–130
—
—
–130
—
—
–130
dBc/Hz
Transmitter REFCLK
Phase Noise (4)
June 2013 Altera Corporation
0 to
–0.5%
100
0 to
–0.5%
100
VCCE_GXBL supply
0 to
–0.5%
100
VCCE_GXBL supply
Cyclone V Device Datasheet
V
Page 16
Switching Characteristics
Table 20. Transceiver Specifications for Cyclone V GX, GT, SX, and ST Devices—Preliminary (Part 2 of 4)
Symbol/
Description
RREF
Conditions
Transceiver
Speed Grade 6
Transceiver
Speed Grade 5 (1)
Transceiver
Speed Grade 7
Unit
Min
Typ
Max
Min
Typ
Max
Min
Typ
Max
—
—
2000
±1%
—
—
2000
±1%
—
—
2000
±1%
—
Ω
PCIe
Receiver Detect
—
125
—
—
125
—
—
125
—
MHz
—
75
—
100/
125 (7)
75
—
100/
125 (7)
75
—
100/
125 (7)
MHz
Transceiver Clocks
fixedclk clock
frequency
Transceiver
Reconfiguration
Controller IP
(mgmt_clk_clk) clock
frequency
Receiver
Supported I/O
Standards
1.5 V PCML, 2.5 V PCML, LVPECL, and LVDS
Data rate
—
614
—
5000/
6144 (8)
614
—
3125
614
—
2500
Mbps
Absolute VMAX for a
receiver pin (9)
—
—
—
1.2
—
—
1.2
—
—
1.2
V
Absolute VMIN for a
receiver pin
—
–0.4
—
—
–0.4
—
—
–0.4
—
—
V
Maximum peak-to-peak
differential input voltage
VID (diff p-p) before
device configuration
—
—
—
1.6
—
—
1.6
—
—
1.6
V
Maximum peak-to-peak
differential input voltage
VID (diff p-p) after
device configuration
—
—
—
2.2
—
—
2.2
—
—
2.2
V
Minimum differential
eye opening at the
receiver serial input
pins (10)
—
85
—
—
85
—
—
85
—
—
mV
85−Ω setting
—
85
—
—
85
—
—
85
—
Ω
100−Ω setting
—
100
—
—
100
—
—
100
—
Ω
120−Ω setting
—
120
—
—
120
—
—
120
—
Ω
150-Ω setting
—
150
—
—
150
—
—
150
—
Ω
2.5 V PCML,
LVPECL, and
LVDS
VCCE_GXBL supply (5), (6)
Differential on-chip
termination resistors
VICM (AC coupled)
VCCE_GXBL supply
1.5 V PCML
tLTR
(11)
tLTD
(12)
tLTD_manual
(13)
Cyclone V Device Datasheet
VCCE_GXBL supply
0.7
V
V
—
—
—
10
—
—
10
—
—
10
µs
—
—
—
4
—
—
4
—
—
4
µs
—
—
—
4
—
—
4
—
—
4
µs
June 2013
Altera Corporation
Switching Characteristics
Page 17
Table 20. Transceiver Specifications for Cyclone V GX, GT, SX, and ST Devices—Preliminary (Part 3 of 4)
Symbol/
Description
tLTR_LTD_manual
(14)
Conditions
—
Programmable PPM
detector (15)
—
Run Length
—
Programmable
equalization (AC)
and DC gain
—
Transceiver
Speed Grade 5 (1)
Transceiver
Speed Grade 6
Transceiver
Speed Grade 7
Min
Typ
Max
Min
Typ
Max
Min
Typ
Max
15
—
—
15
—
—
15
—
—
±62.5, 100, 125, 200, 250, 300, 500, and 1000
—
—
200
—
—
200
—
Unit
µs
ppm
—
200
Refer to Figure 1 and Figure 2
UI
dB
Transmitter
Supported I/O
Standards
1.5 V PCML
Data rate
—
614
—
5000/
6144 (8)
614
—
3125
614
—
2500
Mbps
VOCM (AC coupled)
—
—
650
—
—
650
—
—
650
—
mV
85−Ω setting
—
85
—
—
85
—
—
85
—
Ω
Differential on-chip
termination resistors
(16)
100−Ω setting
—
100
—
—
100
—
—
100
—
Ω
120−Ω setting
—
120
—
—
120
—
—
120
—
Ω
150-Ω setting
—
150
—
—
150
—
—
150
—
Ω
—
30
—
160
30
—
160
30
—
160
ps
(16)
—
30
—
160
30
—
160
30
—
160
ps
Supported data range
—
614
—
5000/
6144 (8)
614
—
3125
614
—
2500
Mbps
fPLL supported data
range
—
614
—
3125
614
—
3125
614
—
3125
Mbps
25
—
187.5
25
—
163.84
25
—
156.25
MHz
Rise time
Fall time
CMU PLL
Transceiver-FPGA Fabric Interface
Interface speed
(single-width mode)
June 2013 Altera Corporation
—
Cyclone V Device Datasheet
Page 18
Switching Characteristics
Table 20. Transceiver Specifications for Cyclone V GX, GT, SX, and ST Devices—Preliminary (Part 4 of 4)
Symbol/
Description
Interface speed
(double-width mode)
Conditions
—
Transceiver
Speed Grade 6
Transceiver
Speed Grade 5 (1)
Transceiver
Speed Grade 7
Min
Typ
Max
Min
Typ
Max
Min
Typ
Max
25
—
163.84
25
—
163.84
25
—
156.25
Unit
MHz
Notes to Table 20:
(1) Transceiver Speed Grade 5 covers specifications for Cyclone V GT and ST devices.
(2) Differential LVPECL signal levels must comply to the minimum and maximum peak-to-peak differential input voltage specified in this table.
(3) The reference clock frequency must be ≥ 307.2 MHz to be fully compliance to CPRI transmit jitter specification at 6.144 Gbps. For more information about
CPRI 6.144 Gbps, refer to the Transceiver Protocol Configurations in Cyclone V Devices chapter.
(4) The transmitter REFCLK phase jitter is 30 ps p-p at bit error rate (BER) 10-12.
(5) Altera recommends increasing the VCCE_GXBL and VCCL_GXBL typical value from 1.1 V to 1.2 V for Cyclone V GT FPGA systems which require full compliance
to the PCIe Gen2 transmit jitter specification. For more information about the maximum full duplex channels recommended in Cyclone V GT and ST
devices under this condition, refer to the Transceiver Protocol Configurations in Cyclone V Devices chapter.
(6) Altera recommends increasing the VCCE_GXBL and VCCL_GXBL typical value from 1.1 V to 1.2 V for full compliance to CPRI transmit jitter specification at
4.9152 Gbps (Cyclone V GT and ST devices) and 6.144 Gbps (Cyclone V GT devices only). For more information about the maximum full duplex channels
recommended in Cyclone V GT devices for CPRI 6.144 Gbps, refer to the Transceiver Protocol Configurations in Cyclone V Devices chapter.
(7) The maximum supported clock frequency is 100 MHz if the PCIe hard IP block is enabled or 125 MHz if the PCIe hard IP block is not enabled.
(8) Cyclone V GT devices support up to three full duplex channels that is compliant to 6144-Mbps CPRI protocol in every two transceiver banks. For CPRI
6144-Mbps transmit jitter compliance, Altera recommends that you use only up to three full-duplex transceiver channels for two transceiver banks in
CPRI Mode. The transceivers are a grouped in transceiver banks of three channels. For more information about the transceiver bank, refer to the
Transceiver Architecture in Cyclone V Devices chapter.
(9) The device cannot tolerate prolonged operation at this absolute maximum.
(10) The differential eye opening specification at the receiver input pins assumes that you have disabled the Receiver Equalization feature. If you enable the
Receiver Equalization feature, the receiver circuitry can tolerate a lower minimum eye opening, depending on the equalization level.
(11) tLTR is the time required for the receive CDR to lock to the input reference clock frequency after coming out of reset.
(12) tLTD is time required for the receiver CDR to start recovering valid data after the rx_is_lockedtodata signal goes high.
(13) tLTD_manual is the time required for the receiver CDR to start recovering valid data after the rx_is_lockedtodata signal goes high when the CDR is
functioning in the manual mode.
(14) tLTR_LTD_manual is the time the receiver CDR must be kept in lock to reference (LTR) mode after the rx_is_lockedtoref signal goes high when the CDR
is functioning in the manual mode.
(15) The rate matcher supports only up to ±300 parts per million (ppm).
(16) The Quartus II software automatically selects the appropriate slew rate depending on the configured data rate or functional mode.
Cyclone V Device Datasheet
June 2013
Altera Corporation
Switching Characteristics
Page 19
Figure 1 shows the continuous time-linear equalizer (CTLE) response for Cyclone V
devices with data rates > 3.25 Gbps.
Figure 1. CTLE Response for Cyclone V Devices with Data Rates > 3.25 Gbps
June 2013 Altera Corporation
Cyclone V Device Datasheet
Page 20
Switching Characteristics
Figure 2 shows the CTLE response for Cyclone V devices with data rates ≤ 3.25 Gbps.
Figure 2. CTLE Response for Cyclone V Devices with Data Rates ≤ 3.25 Gbps
Cyclone V Device Datasheet
June 2013
Altera Corporation
Switching Characteristics
Page 21
Table 21 lists the TX VOD settings for Cyclone V transceiver channels.
Table 21. Typical TX VOD Setting for Cyclone V Transceiver Channels = 100 Ω—Preliminary
Symbol
VOD differential peak to peak
typical
VOD Setting (1)
VOD Value (mV)
VOD Setting (1)
VOD Value (mV)
0
0
32
640
1
20
33
660
2
40
34
680
3
60
35
700
4
80
36
720
5
100
37
740
6
120
38
760
7
140
39
780
8
160
40
800
9
180
41
820
10
200
42
840
11
220
43
860
12
240
44
880
13
260
45
900
14
280
46
920
15
300
47
940
16
320
48
960
17
340
49
980
18
360
50
1000
19
380
51
1020
20
400
52
1040
21
420
53
1060
22
440
54
1080
23
460
55
1100
24
480
56
1120
25
500
57
1140
26
520
58
1160
27
540
59
1180
28
560
60
1200
29
580
61
1220
30
600
62
1240
31
620
63
1260
Note to Table 21:
(1) Convert these values to their binary equivalent form if you are using the dynamic reconfiguration mode for PMA
analog controls.
June 2013 Altera Corporation
Cyclone V Device Datasheet
Page 22
Switching Characteristics
Table 22 lists the simulation data on the transmitter pre-emphasis levels in dB for the
first post tap under the following conditions:
■
Low-frequency data pattern—five 1s and five 0s
■
Data rate—2.5 Gbps
The levels listed are a representation of possible pre-emphasis levels under the
specified conditions only and the pre-emphasis levels may change with data pattern
and data rate.
1
To predict the pre-emphasis level for your specific data rate and pattern, run
simulations using the Cyclone V HSSI HSPICE models.
Table 22. Transmitter Pre-Emphasis Levels for Cyclone V Devices (1), (2), (3), (4)—Preliminary (Part 1 of 2)
Quartus II 1st Post Tap
Pre-Emphasis Setting
Quartus II VOD Setting
10
(200 mV)
20
(400 mV)
30
(600 mV)
35
(700 mV)
40
(800 mV)
45
(900 mV)
50
(1000 mV)
Unit
0
0
0
0
0
0
0
0
dB
1
1.97
0.88
0.43
0.32
0.24
0.19
0.13
dB
2
3.58
1.67
0.95
0.76
0.61
0.5
0.41
dB
3
5.35
2.48
1.49
1.2
1
0.83
0.69
dB
4
7.27
3.31
2
1.63
1.36
1.14
0.96
dB
5
—
4.19
2.55
2.1
1.76
1.49
1.26
dB
6
—
5.08
3.11
2.56
2.17
1.83
1.56
dB
7
—
5.99
3.71
3.06
2.58
2.18
1.87
dB
8
—
6.92
4.22
3.47
2.93
2.48
2.11
dB
9
—
7.92
4.86
4
3.38
2.87
2.46
dB
10
—
9.04
5.46
4.51
3.79
3.23
2.77
dB
11
—
10.2
6.09
5.01
4.23
3.61
—
dB
12
—
11.56
6.74
5.51
4.68
3.97
—
dB
13
—
12.9
7.44
6.1
5.12
4.36
—
dB
14
—
14.44
8.12
6.64
5.57
4.76
—
dB
15
—
—
8.87
7.21
6.06
5.14
—
dB
16
—
—
9.56
7.73
6.49
—
—
dB
17
—
—
10.43
8.39
7.02
—
—
dB
18
—
—
11.23
9.03
7.52
—
—
dB
19
—
—
12.18
9.7
8.02
—
—
dB
20
—
—
13.17
10.34
8.59
—
—
dB
21
—
—
14.2
11.1
—
—
—
dB
22
—
—
15.38
11.87
—
—
—
dB
23
—
—
—
12.67
—
—
—
dB
24
—
—
—
13.48
—
—
—
dB
Cyclone V Device Datasheet
June 2013
Altera Corporation
Switching Characteristics
Page 23
Table 22. Transmitter Pre-Emphasis Levels for Cyclone V Devices (1), (2), (3), (4)—Preliminary (Part 2 of 2)
Quartus II 1st Post Tap
Pre-Emphasis Setting
Quartus II VOD Setting
10
(200 mV)
20
(400 mV)
30
(600 mV)
35
(700 mV)
40
(800 mV)
45
(900 mV)
50
(1000 mV)
Unit
25
—
—
—
14.37
—
—
—
dB
26
—
—
—
—
—
—
—
dB
27
—
—
—
—
—
—
—
dB
28
—
—
—
—
—
—
—
dB
29
—
—
—
—
—
—
—
dB
30
—
—
—
—
—
—
—
dB
31
—
—
—
—
—
—
—
dB
Notes to Table 22:
(1) The 1st post tap pre-emphasis settings must satisfy |B| + |C| ≤ 60
|B| = VOD setting with termination value, RTERM = 100 Ω
|C| = 1st post tap pre-emphasis setting
(2) |B| – |C| > 5 for data rates < 5 Gbps and |B| – |C| > 8.25 for data rates > 5 Gbps.
(3) (VMAX/VMIN – 1)% < 600%, where VMAX = |B| + |C| and VMIN = |B| – |C|.
(4) For example, when VOD = 800 mV, the corresponding VOD value setting is 40.
To check the validity of the 1st post tap pre-emphasis setting = 2
|B| + |C| ≤ 60 → 40 + 2 = 42
|B| –|C| > 5 → 40 – 2 = 38
(VMAX/VMIN – 1)% < 600% → (42/38 – 1)% = 10.52%
Therefore, the 1st post tap pre-emphasis setting = 2 is a valid condition.
June 2013 Altera Corporation
Cyclone V Device Datasheet
Page 24
Switching Characteristics
Core Performance Specifications
This section describes the clock tree, phase-locked loop (PLL), digital signal
processing (DSP), and memory block specifications.
Clock Tree Specifications
Table 23 lists the clock tree specifications for Cyclone V devices.
Table 23. Clock Tree Performance for Cyclone V Devices—Preliminary
Performance
Parameter
Unit
–C6
–C7, –I7
–C8, –A7
Global clock and Regional clock
550
550
460
MHz
Peripheral clock
155
155
155
MHz
PLL Specifications
Table 24 lists the Cyclone V PLL specifications when operating in the commercial (0°
to 85°C), industrial (–40° to 100°C), and automotive (–40° to 125°C) junction
temperature ranges.
Table 24. PLL Specifications for Cyclone V Devices (1)—Preliminary (Part 1 of 3)
Symbol
Parameter
Min
–C6 speed grade
fIN
Input clock frequency
–C7, –I7 speed grades
–C8, –A7 speed grades
fINPFD
Integer input clock frequency to the PFD
fFINPFD
Fractional input clock frequency to the PFD
fVCO (3)
PLL VCO operating range
tEINDUTY
MHz
—
622 (2)
MHz
5
—
500 (2)
MHz
5
—
325
MHz
—
TBD (1)
MHz
5
50
600
—
1600
MHz
—
1400
MHz
–C8, –A7 speed grades
600
—
1300
MHz
40
—
60
%
—
550 (4)
MHz
—
550 (4)
MHz
—
460 (4)
MHz
—
667 (4)
MHz
MHz
–C7, –I7 speed grades
–C6 speed grade
fOUT_EXT
—
5
600
–C8, –A7 speed grades
Output frequency for external clock
output
Unit
670 (2)
–C7, –I7 speed grades
–C6 speed grade
fOUT
Max
–C6 speed grade
Input clock or external feedback clock input duty cycle
Output frequency for internal global
or regional clock
Typ
—
—
—
—
–C7, –I7 speed grades
—
—
667 (4)
–C8, –A7 speed grades
—
—
533 (4)
MHz
tOUTDUTY
Duty cycle for external clock output (when set to 50%)
45
50
55
%
tFCOMP
External feedback clock compensation time
—
—
10
ns
tDYCONFIGCLK
Dynamic configuration clock
—
—
100
MHz
tLOCK
Time required to lock from end-of-device configuration or
deassertion of areset
—
—
1
ms
tDLOCK
Time required to lock dynamically (after switchover or
reconfiguring any non-post-scale counters/delays)
—
—
1
ms
Cyclone V Device Datasheet
June 2013
Altera Corporation
Switching Characteristics
Page 25
Table 24. PLL Specifications for Cyclone V Devices (1)—Preliminary (Part 2 of 3)
Symbol
Parameter
PLL closed-loop low bandwidth
fCLBW
PLL closed-loop medium bandwidth
(9)
Min
Typ
Max
Unit
—
0.3
—
MHz
—
1.5
—
MHz
—
4
—
MHz
tPLL_PSERR
Accuracy of PLL phase shift
—
—
±50
ps
tARESET
Minimum pulse width on the areset signal
10
—
—
ns
Input clock cycle-to-cycle jitter (FREF ≥ 100 MHz)
—
—
0.15
UI (p-p)
Input clock cycle-to-cycle jitter (FREF < 100 MHz)
—
—
±750
ps (p-p)
PLL closed-loop high bandwidth
tINCCJ
(5), (6)
(7)
tOUTPJ_DC
Period jitter for dedicated clock output (FOUT ≥ 100 MHz)
—
—
TBD
(1)
ps (p-p)
mUI (p-p)
Period jitter for dedicated clock output (FOUT < 100 MHz)
—
—
TBD
(1)
Cycle-to-cycle jitter for dedicated clock output
(FOUT ≥ 100 MHz)
—
—
TBD
(1)
ps (p-p)
Cycle-to-cycle jitter for dedicated clock output
(FOUT < 100 MHz)
—
—
TBD
(1)
mUI (p-p)
Period jitter for clock output on regular I/O
(FOUT ≥ 100 MHz)
—
—
TBD
(1)
ps (p-p)
Period jitter for clock output on regular I/O
(FOUT < 100 MHz)
—
—
TBD
(1)
mUI (p-p)
Cycle-to-cycle jitter for clock output on regular I/O
(FOUT ≥ 100 MHz)
—
—
TBD
(1)
ps (p-p)
Cycle-to-cycle jitter for clock output on regular I/O
(FOUT < 100 MHz)
—
—
TBD
(1)
mUI (p-p)
tOUTPJ_DC_F
Period jitter for dedicated clock output in fractional mode
—
—
TBD (1)
—
tOUTCCJ_DC_F
Cycle-to-cycle jitter for dedicated clock output in fractional
mode
—
—
TBD (1)
—
tOUTPJ_IO_F
Period jitter for clock output on regular I/O in fractional mode
—
—
TBD (1)
—
tOUTCCJ_IO_F
Cycle-to-cycle jitter for clock output on regular I/O in
fractional mode
—
—
TBD (1)
—
—
—
TBD
(1)
tCASC_OUTPJ_DC
Period jitter for dedicated clock output in cascaded PLLs (FOUT
≥ 100 MHz)
ps (p-p)
Period jitter for dedicated clock output in cascaded PLLs (FOUT
< 100 MHz)
—
—
TBD
(1)
mUI (p-p)
(7)
tOUTCCJ_DC
tOUTPJ_IO
(7), (10)
tOUTCCJ_IO
(7), (8)
(7), (10)
June 2013 Altera Corporation
Cyclone V Device Datasheet
Page 26
Switching Characteristics
Table 24. PLL Specifications for Cyclone V Devices (1)—Preliminary (Part 3 of 3)
Symbol
Parameter
tDRIFT
Frequency drift after PFDENA is disabled for a duration of
100 µs
dKBIT
Bit number of Delta Sigma Modulator (DSM)
kVALUE
Numerator of fraction
fRES
Resolution of VCO frequency (fINPFD =100 MHz)
Min
Typ
Max
Unit
—
—
±10
%
—
24
TBD (1) 8388608
—
—
Bits
TBD (1)
—
—
Hz
5.96
Notes to Table 24:
(1) Pending silicon characterization.
(2) This specification is limited in the Quartus II software by the I/O maximum frequency. The maximum I/O frequency is different for each I/O standard.
(3) The VCO frequency reported by the Quartus II software takes into consideration the VCO post-scale counter K value. Therefore, if the counter K has
a value of 2, the frequency reported can be lower than the fVCO specification.
(4) This specification is limited by the lower of the two: I/O fMAX or FOUT of the PLL.
(5) A high input jitter directly affects the PLL output jitter. To have low PLL output clock jitter, you must provide a clean clock source with jitter < 120 ps.
(6) FREF is fIN/N, specification applies when N = 1.
(7) Peak-to-peak jitter with a probability level of 10–12 (14 sigma, 99.99999999974404% confidence level). The output jitter specification applies to
the intrinsic jitter of the PLL, when an input jitter of 30 ps is applied. The external memory interface clock output jitter specifications use a different
measurement method and are available in Table 30 on page 1–30.
(8) The cascaded PLL specification is only applicable with the following condition:
a. Upstream PLL: 0.59 MHz ≤ Upstream PLL BW < 1 MHz
b. Downstream PLL: Downstream PLL BW > 2 MHz
(9) High bandwidth PLL settings are not supported in external feedback mode.
(10) External memory interface clock output jitter specifications use a different measurement method, which is available in Table 30 on page 1–30.
DSP Block Specifications
Table 25 lists the Cyclone V DSP block performance specifications.
Table 25. DSP Block Performance Specifications for Cyclone V Devices—Preliminary
Performance
Mode
Unit
–C6
–C7, –I7
–C8, –A7
Independent 9 x 9 Multiplication
340
300
260
MHz
Independent 18 x 19 Multiplication
287
250
200
MHz
Independent 18 x 18 Multiplication
287
250
200
MHz
Independent 27 x 27 Multiplication
250
200
160
MHz
Independent 18 x 25 Multiplication
310
250
200
MHz
Modes using One DSP Block
Independent 20 x 24 Multiplication
310
250
200
MHz
Two 18 x 19 Multiplier Adder Mode
310
250
200
MHz
18 x 18 Multiplier Added Summed with 36-bit Input
310
250
200
MHz
310
250
200
MHz
Modes using Two DSP Blocks
Complex 18 x 19 multiplication
Cyclone V Device Datasheet
June 2013
Altera Corporation
Switching Characteristics
Page 27
Memory Block Specifications
Table 26 lists the Cyclone V memory block specifications.
To achieve the maximum memory block performance, use a memory block clock that
comes through global clock routing from an on-chip PLL and set to 50% output duty
cycle. Use the Quartus II software to report timing for the memory block clocking
schemes.
When you use the error detection cyclical redundancy check (CRC) feature, there is no
degradation in fMAX.
Table 26. Memory Block Performance Specifications for Cyclone V Devices—Preliminary
Resources Used
Memory
MLAB
M10K
Block
Performance
Mode
Unit
ALUTs
Memory
–C6
–C7, –I7
–C8, –A7
Single port, all supported widths
0
1
420
350
300
MHz
Simple dual-port, all supported
widths
0
1
420
350
300
MHz
Simple dual-port with read and
write at the same address
0
1
340
290
240
MHz
ROM, all supported width
0
1
420
350
300
MHz
Single-port, all supported widths
0
1
315
275
240
MHz
Simple dual-port, all supported
widths
0
1
315
275
240
MHz
Simple dual-port with the
read-during-write option set to
Old Data, all supported widths
0
1
275
240
180
MHz
True dual port, all supported
widths
0
1
315
275
240
MHz
ROM, all supported widths
0
1
315
275
240
MHz
Min Pulse Width (clock high time)
—
—
1,450
1,550
1,650
ps
Min Pulse Width (clock low time)
—
—
1,000
1,200
1,350
ps
Periphery Performance
This section describes periphery performance and the high-speed I/O and external
memory interface.
1
Actual achievable frequency depends on design- and system-specific factors. You
must perform HSPICE/IBIS simulations based on your specific design and system
setup to determine the maximum achievable frequency in your system.
June 2013 Altera Corporation
Cyclone V Device Datasheet
Page 28
Switching Characteristics
High-Speed I/O Specifications
Table 27 lists high-speed I/O timing for Cyclone V devices.
Table 27. High-Speed I/O Specifications for Cyclone V Devices (1),
(2), (3)—Preliminary
–C6
Symbol
(Part 1 of 2)
–C7, –I7
–C8, –A7
Conditions
Unit
Min
Typ
Max
Min
Typ
Max
Min
Typ
Max
fHSCLK_in (input
clock frequency)
True Differential I/O
Standards
Clock boost factor W = 1
to 40 (4)
5
—
437.5
5
—
420
5
—
320
MHz
fHSCLK_in (input
clock frequency)
Single Ended I/O
Standards
Clock boost factor W = 1
to 40 (4)
5
—
320
5
—
320
5
—
275
MHz
fHSCLK_OUT (output
clock frequency)
—
5
—
420
5
—
370
5
—
320
MHz
SERDES factor
J = 4 to 10 (5)
(6)
—
840
(6)
—
740
(6)
—
640
Mbps
SERDES factor J = 1 to 2,
Uses DDR Registers
(6)
—
(9)
(6)
—
(9)
(6)
—
(9)
Mbps
Emulated
Differential I/O
Standards with
Three External
Output Resistor
Networks - fHSDR
(data rate) (7)
SERDES factor J = 4 to 10
(6)
—
640
(6)
—
640
(6)
—
550
Mbps
Emulated
Differential I/O
Standards with One
External Output
Resistor Network fHSDR (data rate) (7)
SERDES factor J = 4 to 10
(6)
—
170
(6)
—
170
(6)
—
170
Mbps
Total Jitter for Data Rate,
600 Mbps - 840 Mbps
—
—
350 (8)
—
—
380 (8)
—
—
500 (8)
ps
Total Jitter for Data Rate,
< 600 Mbps
—
—
0.1
—
—
TBD
—
—
TBD
UI
tx Jitter - Emulated
Differential I/O
Standards with
Three External
Output Resistor
Networks
Total Jitter for Data Rate
< 640 Mbps
—
—
500
—
—
500
—
—
500
ps
tx Jitter - Emulated
Differential I/O
Standards with One
External Output
Resistor Network
Total Jitter for Data Rate
< 640 Mbps
—
—
0.15
—
—
0.15
—
—
0.15
UI
Transmitter
True Differential I/O
Standards - fHSDR
(data rate)
tx Jitter - True
Differential I/O
Standards
Cyclone V Device Datasheet
June 2013
Altera Corporation
Switching Characteristics
Page 29
Table 27. High-Speed I/O Specifications for Cyclone V Devices (1),
(2), (3)—Preliminary
–C6
Symbol
tDUTY
tRISE & tFALL
TCCS
(Part 2 of 2)
–C7, –I7
–C8, –A7
Conditions
Unit
Min
Typ
Max
Min
Typ
Max
Min
Typ
Max
TX output clock duty
cycle for both True and
Emulated Differential I/O
Standards
45
50
55
45
50
55
45
50
55
%
True Differential I/O
Standards
—
—
200
—
—
200
—
—
200
ps
Emulated Differential I/O
Standards with Three
External Output Resistor
Networks
—
—
250
—
—
250
—
—
300
ps
Emulated Differential I/O
Standards with One
External Output Resistor
Network
—
—
300
—
—
300
—
—
300
ps
True Differential I/O
Standards
—
—
200
—
—
250
—
—
250
ps
Emulated Differential I/O
Standards with Three
External Output Resistor
Networks
—
—
300
—
—
300
—
—
300
ps
Emulated Differential I/O
Standards with One
External Output Resistor
Network
—
—
300
—
—
300
—
—
300
ps
SERDES factor
J = 4 to 10 (5)
(6)
—
875 (7)
(6)
—
840 (7)
(6)
—
SERDES factor J = 1 to 2,
Uses DDR Registers
(6)
—
(9)
(6)
—
(9)
(6)
—
(9)
Mbps
—
—
—
350
—
—
350
—
—
350
ps
Receiver
fHSDR (data rate)
Sampling Window
640 (7) Mbps
Notes to Table 27:
(1)
(2)
(3)
(4)
(5)
(6)
(7)
(8)
(9)
When J = 1 or 2, bypass the serializer/deserializer (SERDES) block.
For LVDS applications, you must use the PLLs in integer PLL mode.
This is achieved by using the LVDS clock network.
Clock Boost Factor (W) is the ratio between the input data rate and the input clock rate.
The Fmax specification is based on the fast clock used for serial data. The interface Fmax is also dependent on the parallel clock domain which is
design dependent and requires timing analysis.
The minimum specification depends on the clock source (for example, the PLL and clock pin) and the clock routing resource (global, regional,
or local) that you use. The I/O differential buffer and input register do not have a minimum toggle rate.
You must calculate the leftover timing margin in the receiver by performing link timing closure analysis. You must consider the board skew
margin, transmitter channel-to-channel skew, and receiver sampling margin to determine the leftover timing margin.
The specifications are retrieved without partial reconfiguration support.
The maximum ideal data rate is the SERDES factor (J) x PLL max output frequency (fout), provided you can close the design timing and the signal
integrity simulation is clean.You can estimate the achievable maximum data rate by performing link timing closure analysis. You must consider
the board skew margin, transmitter delay margin, and receiver sampling margin to determine the maximum data rate supported.
June 2013 Altera Corporation
Cyclone V Device Datasheet
Page 30
Switching Characteristics
DLL Range, DQS Logic Block and Memory Output Clock Jitter Specifications
Table 28 lists the DLL operating frequency range specifications for Cyclone V devices.
Table 28. DLL Operating Frequency Range Specifications for Cyclone V Devices
Parameter
–C6
–C7, –I7
–C8
DLL operating frequency range
167 – 400
167 – 400
167 – 333
Unit
MHz
Table 29 lists the DQS phase shift error for Cyclone V devices. This error specification
is the absolute maximum and minimum error.
Table 29. DQS Phase Shift Error Specification for DLL-Delayed Clock (tDQS_PSERR) for Cyclone V
Devices (1) —Preliminary
Number of DQS Delay Buffer
–C6
–C7, –I7
–C8
Unit
2
40
80
80
ps
Note to Table 29:
(1) The numbers are preliminary pending silicon characterization.
Table 30 lists the memory output clock jitter specifications for Cyclone V devices.
The memory output clock jitter measurements are for 200 consecutive clock cycles, as
specified in the JEDEC DDR2/DDR3 SDRAM standard.
The memory output clock jitter is applicable when an input jitter of 30 ps (p-p) is
applied with bit error rate (BER) 10–12, equivalent to 14 sigma.
Altera recommends using the UniPHY intellectual property (IP) with PHYCLK
connections for better jitter performance.
Table 30. Memory Output Clock Jitter Specification for Cyclone V Devices—Preliminary
–C6
Clock
Network
Symbol
Clock period jitter
PHYCLK
tJIT(per)
Cycle-to-cycle period
jitter
PHYCLK
tJIT(cc)
Parameter
Cyclone V Device Datasheet
–C7, –I7
–C8
Unit
Min
Max
Min
Max
Min
Max
–90
90
–90
90
–90
90
180
180
180
June 2013
ps
ps
Altera Corporation
Switching Characteristics
Page 31
OCT Calibration Block Specifications
Table 31 lists the OCT calibration block specifications for Cyclone V devices.
Table 31. OCT Calibration Block Specifications for Cyclone V Devices—Preliminary
Symbol
Description
Min
Typ
Max
Unit
OCTUSRCLK
Clock required by OCT calibration blocks
—
—
20
MHz
TOCTCAL
Number of OCTUSRCLK clock cycles required for
RS OCT /RT OCT calibration
—
1000
—
Cycles
TOCTSHIFT
Number of OCTUSRCLK clock cycles required for OCT code
to shift out
—
32
—
Cycles
TRS_RT
Time required between the dyn_term_ctrl and oe signal
transitions in a bidirectional I/O buffer to dynamically switch
between RS OCT and RT OCT
—
2.5
—
ns
Figure 3 shows the timing diagram for the oe and dyn_term_ctrl signals.
Figure 3. Timing Diagram for the oe and dyn_term_ctrl Signals
Tristate
RX
TX
Tristate
RX
oe
dyn_term_ctrl
TRS_RT
TRS_RT
Duty Cycle Distortion (DCD) Specifications
Table 32 lists the worst-case DCD for Cyclone V devices. The output DCD cycle only
applies to the I/O buffer. It does not cover the system DCD.
Table 32. Worst-Case DCD on I/O Pins for Cyclone V Devices—Preliminary
–C6
–C7, –I7
–C8, –A7
Symbol
Output Duty Cycle
June 2013 Altera Corporation
Unit
Min
Max
Min
Max
Min
Max
45
55
45
55
45
55
%
Cyclone V Device Datasheet
Page 32
Switching Characteristics
HPS Specifications
This section provides HPS specifications and timing for Cyclone V devices.
For HPS reset, the minimum reset pulse widths for the HPS cold and warm reset
signals (HPS_nRST and HPS_nPOR) are six clock cycles of HPS_CLK1.
The data in Table 33 through Table 45 is preliminary and pending silicon
characterization.
HPS Clock Performance
Table 33 lists the HPS clock performance for Cyclone V devices.
Table 33. HPS Clock Performance for Cyclone V Devices—Preliminary
Symbol/Description
–C6
–C7, –I7
–C8, –A7
Unit
mpu_base_clk
800
800
600
MHz
main_base_clk
400
400
300
MHz
QSPI Timing Characteristics
Table 34 lists the queued serial peripheral interface (QSPI) timing characteristics for
Cyclone V devices.
Table 34. QSPI Timing Requirements for Cyclone V Devices—Preliminary
Symbol
Description
Min
Typ
Max
Unit
Fclk
CLK clock frequency
—
—
108
MHz
Tdutycycle
QSPI_CLK duty cycle
TBD
—
TBD
%
Tdssfrst
Output delay QSPI_SS valid before first clock edge
8
—
TBD
ns
Tdsslst
Output delay QSPI_SS valid after last clock edge
8
—
TBD
ns
Tdio
IO Data output delay
–1
—
1
ns
Tdinmax
Maximum data input delay from falling edge of
QSPI_CLK to data arrival at SoC
—
—
20
ns
Figure 4 shows the timing diagram for QSPI timing characteristics.
Figure 4. QSPI Timing Diagram
Tdsslst
QSPI_SS
Tdssfrst
QSPI_CLK
Tdio
QSPI_DATA
Cyclone V Device Datasheet
Tdinmax
Data Out
Data In
June 2013
Altera Corporation
Switching Characteristics
Page 33
SPI Timing Characteristics
Table 35 lists the serial peripheral interface (SPI) master timing characteristics for
Cyclone V devices. The setup and hold times can be used for Texas Instruments SSP
mode and National Semiconductor Microwire mode.
Table 35. SPI Master Timing Requirements for Cyclone V Devices—Preliminary
Symbol
Description
Min
Typ
Max
Unit
ns
Tclk
CLK clock period
TBD
20
TBD
Tdutycycle
SPI_CLK duty cycle
TBD
—
TBD
%
Tdssfrst
Output delay SPI_SS valid before first clock edge
8
—
TBD
ns
Tdsslst
Output delay SPI_SS valid after last clock edge
8
—
TBD
ns
Tdio
Master-out slave-in (MOSI) output delay
–1
—
1
ns
Tdinmax
Maximum data input delay from falling edge of
SPI_CLK to data arrival at SoC
—
—
500
ns
Figure 5 shows the timing diagram for SPI master timing characteristics.
Figure 5. SPI Master Timing Diagram
Tdsslst
SPI_SS
Tdssfrst
SPI_CLK (scpol = 0)
SPI_CLK (scpol = 1)
Tdio
SPI_MOSI (scph = 1)
Tdinmax
SPI_MISO (scph = 1)
Tdio
SPI_MOSI (scph = 0)
Tdinmax
SPI_MISO (scph = 0)
Table 36 lists the SPI slave timing characteristics for Cyclone V devices. The setup and
hold times can be used for Texas Instruments SSP mode and National Semiconductor
Microwire mode.
Table 36. SPI Slave Timing Requirements for Cyclone V Devices—Preliminary (Part 1 of 2)
Symbol
Description
Min
Typ
Max
Unit
Tclk
CLK clock period
TBD
20
TBD
ns
Ts
MOSI Setup time
5
—
TBD
ns
Th
MOSI Hold time
5
—
TBD
ns
Tsuss
Setup time SPI_SS valid before first clock edge
8
—
TBD
ns
June 2013 Altera Corporation
Cyclone V Device Datasheet
Page 34
Switching Characteristics
Table 36. SPI Slave Timing Requirements for Cyclone V Devices—Preliminary (Part 2 of 2)
Symbol
Description
Thss
Hold time SPI_SS valid after last clock edge
Td
Master-in slave-out (MISO) output delay
Min
Typ
Max
Unit
8
—
TBD
ns
TBD
—
6
ns
Figure 6 shows the timing diagram for SPI slave timing characteristics.
Figure 6. SPI Slave Timing Diagram
Thss
SPI_SS
Tsuss
SPI_CLK (scpol = 0)
SPI_CLK (scpol = 1)
Td
SPI_MISO (scph = 1)
Ts
Th
SPI_MOSI (scph = 1)
Td
SPI_MISO (scph = 0)
Ts
Th
SPI_MOSI (scph = 0)
SD/MMC Timing Characteristics
Table 37 lists the secure digital (SD)/MultiMediaCard (MMC) timing characteristics
for Cyclone V devices.
Table 37. SD/MMC Timing Requirements for Cyclone V Devices—Preliminary
Symbol
Description
Min
Max
Unit
Tclk
SDMMC_CLK_OUT clock period
20
TBD
ns
Tdutycycle
SDMMC_CLK_OUT duty cycle
TBD
TBD
%
Td
SDMMC_CMD/SDMMC_D output delay
TBD
6
ns
Tdinmax
Maximum input delay from rising edge of SDMMC_CLK to
data arrival at SoC
—
25
ns
Cyclone V Device Datasheet
June 2013
Altera Corporation
Switching Characteristics
Page 35
Figure 7 shows the timing diagram for SD/MMC timing characteristics.
Figure 7. SD/MMC Timing Diagram
SDMMC_CLK_OUT
Td
SDMMC_CMD & SDMMC_D (Out)
Command/Data Out
Tdinmax
SDMMC_CMD & SDMMC_D (In)
Command/Data In
USB Timing Characteristics
Table 38 lists the USB timing characteristics for Cyclone V devices.
Table 38. USB Timing Requirements for Cyclone V Devices—Preliminary
Symbol
Description
Min
Typ
Max
Unit
Tclk
USB CLK clock period
TBD
16.67
TBD
ns
Td
CLK to USB_STP/USB_DATA[7:0] output delay
TBD
—
8
ns
Tsu
Setup time for USB_DIR/USB_NXT/USB_DATA[7:0]
2
—
TBD
ns
Th
Hold time for USB_DIR/USB_NXT/USB_DATA[7:0]
1.5
—
TBD
ns
Figure 8 shows the timing diagram for USB timing characteristics.
Figure 8. USB Timing Diagram
USB_CLK
USB_STP
Td
USB_DATA[7:0]
To PHY
From PHY
Tsu
Th
USB_DIR & USB_NXT
Ethernet Media Access Controller (EMAC) Timing Characteristics
Table 39 lists the reduced gigabit media independent interface (RGMII) TX timing
characteristics for Cyclone V devices.
Table 39. RGMII TX Timing Requirements for Cyclone V Devices—Preliminary
Symbol
Description
Min
Typ
Max
Unit
Tclk (1000Base-T) TX_CLK clock period
TBD
8
TBD
ns
Tclk (100Base-T)
TX_CLK clock period
TBD
40
TBD
ns
Tclk (10Base-T)
TX_CLK clock period
TBD
400
TBD
ns
Tdutycycle
TX_CLK duty cycle
TBD
—
TBD
%
Td
TX_CLK to TXD/TX_CTL output data delay
–0.5
—
0.5
ns
June 2013 Altera Corporation
Cyclone V Device Datasheet
Page 36
Switching Characteristics
Figure 9 shows the timing diagram for RGMII TX timing characteristics.
Figure 9. RGMII TX Timing Diagram
TX_CLK
TX_D[3:0]
Td
TX_CTL
Table 40 lists the RGMII RX timing characteristics for Cyclone V devices.
Table 40. RGMII RX Timing Requirements for Cyclone V Devices—Preliminary
Symbol
Description
Min
Typ
Max
Unit
Tclk (1000Base-T) RX_CLK clock period
TBD
8
TBD
ns
Tclk (100Base-T)
RX_CLK clock period
TBD
40
TBD
ns
Tclk (10Base-T)
RX_CLK clock period
TBD
400
TBD
ns
Tsu
RX_D/RX_CTL setup time
1
—
TBD
ns
Th
RX_D/RX_CTL hold time
1
—
TBD
ns
Figure 10 shows the timing diagram for RGMII RX timing characteristics.
Figure 10. RGMII RX Timing Diagram
RX_CLK
Tsu
Th
RX_D[3:0]
RX_CTL
Table 41 lists the management data input/output (MDIO) timing characteristics for
Cyclone V devices.
Table 41. MDIO Timing Requirements for Cyclone V Devices—Preliminary
Symbol
Description
Min
Typ
Max
Unit
TBD
400
TBD
ns
Tclk
MDC clock period
Td
MDC to MDIO output data delay
10
—
TBD
ns
Ts
Setup time for MDIO data
10
—
TBD
ns
Th
Hold time for MDIO data
10
—
TBD
ns
Cyclone V Device Datasheet
June 2013
Altera Corporation
Switching Characteristics
Page 37
Figure 11 shows the timing diagram for MDIO timing characteristics.
Figure 11. MDIO Timing Diagram
MDC
Td
MDIO_OUT
Th
Tsu
MDIO_IN
I2C Timing Characteristics
Table 42 lists the I2C timing characteristics for Cyclone V devices.
Table 42. I2C Timing Requirements for Cyclone V Devices—Preliminary
Standard Mode
Symbol
Fast Mode
Description
Unit
Min
Max
Min
Max
TBD
10
TBD
2.5
µs
Tclk
Serial clock (SCL) clock period
Tclkhigh
SCL high time
4
TBD
0.6
TBD
µs
Tclklow
SCL low time
4.7
TBD
1.3
TBD
µs
Ts
Setup time for serial data line (SDA) data to
SCL
250
TBD
100
TBD
ns
Th
Hold time for SCL to SDA data
TBD
3.45
TBD
0.9
µs
Td
SCL to SDA output data delay
8
TBD
8
TBD
ns
Figure 12 shows the timing diagram for I2C timing characteristics.
Figure 12. I2C Timing Diagram
I2C_SCL
Ts
Td
Th
I2C_SDA
Data Out
Data In
NAND Timing Characteristics
Table 43 lists the NAND timing characteristics for Cyclone V devices.
Table 43. NAND ONFI 1.0 Timing Requirements for Cyclone V Devices—Preliminary (Part 1 of 2)
Symbol
Description
Min
Max
Unit
Twp
Write enable pulse width
10
TBD
ns
Twh
Write enable hold time
7
TBD
ns
Trp
Read Enable pulse width
10
TBD
ns
Treh
Read enable holdtime
7
TBD
ns
Tclesu
Command latch enable to write enable setup time
10
TBD
ns
Tcleh
Command latch enable to write enable hold time
5
TBD
ns
June 2013 Altera Corporation
Cyclone V Device Datasheet
Page 38
Switching Characteristics
Table 43. NAND ONFI 1.0 Timing Requirements for Cyclone V Devices—Preliminary (Part 2 of 2)
Symbol
Description
Min
Max
Unit
Tcesu
Chip enable to write enable setup time
15
TBD
ns
Tceh
Chip enable to write enable hold time
5
TBD
ns
Talesu
Address latch enable to write enable setup time
10
TBD
ns
Taleh
Address latch enable to write enable hold time
5
TBD
ns
Tdsu
Data to write enable setup time
10
TBD
ns
Tdh
Data to write enable hold time
5
TBD
ns
Tdrb
Write enable high to ready/busy low
TBD
100
ns
Tcea
Chip enable to data access time
TBD
25
ns
Trea
Read enable to data access time
TBD
16
ns
Trhz
Read enable to data high impedance
TBD
100
ns
Trb
Ready to read enable low
20
TBD
ns
Figure 13 shows the timing diagram for NAND command latch timing characteristics.
Figure 13. NAND Command Latch Timing Diagram
NAND_CLE
NAND_CE
Tclesu
Tcesu
Tceh
Twp
Tcleh
NAND_WE
Talesu
Taleh
NAND_ALE
Tdsu
NAND_DQ[7:0]
Tdh
Command
Tdrb
NAND_RB
Cyclone V Device Datasheet
June 2013
Altera Corporation
Switching Characteristics
Page 39
Figure 14 shows the timing diagram for NAND address latch timing characteristics.
Figure 14. NAND Address Latch Timing Diagram
NAND_CLE
NAND_CE
Tcesu
Tclesu
Twp
Twh
NAND_WE
Talesu
Taleh
NAND_ALE
Tdsu
Tdh
Address
NAND_DQ[7:0]
Figure 15 shows the timing diagram for NAND data write timing characteristics.
Figure 15. NAND Data Write Timing Diagram
NAND_CLE
NAND_CE
Tcleh
Twp
Tceh
NAND_WE
Talesu
NAND_ALE
Tdsu
Tdh
NAND_DQ[7:0]
June 2013 Altera Corporation
Din
Cyclone V Device Datasheet
Page 40
Switching Characteristics
Figure 16 shows the timing diagram for NAND data read timing characteristics.
Figure 16. NAND Data Read Timing Diagram
Tcea
NAND_CE
Trp
Treh
NAND_RE
Trhz
Trea
NAND_DQ[7:0]
Dout
Trb
NAND_RB
ARM Trace Timing Characteristics
Table 44 lists the ARM trace timing characteristics for Cyclone V devices.
Table 44. ARM Trace Timing Requirements for Cyclone V Devices—Preliminary
Description
Min
Typ
Max
Unit
CLK clock period
TBD
8
TBD
ns
CLK maximum duty cycle
TBD
—
TBD
%
–1
—
1
ns
CLK to D0 –D7 output data delay
UART Interface
The maximum UART baud rate is 6.25 megasymbols per second.
GPIO Interface
Table 45 lists the general-purpose I/O (GPIO) pulse width for Cyclone V devices.
Table 45. GPIO Pulse Width for Cyclone V Devices—Preliminary
Description
Minimum detectable pulse width
Min
Max
Unit
40
TBD
ns
CAN Interface
The maximum controller area network (CAN) data rate is 1 Mbps.
Cyclone V Device Datasheet
June 2013
Altera Corporation
Configuration Specification
Page 41
Configuration Specification
This section provides configuration specifications and timing for Cyclone V devices.
POR Specifications
Table 46 lists the specifications for fast and standard POR delay for Cyclone V devices.
Table 46. Fast and Standard POR Delay Specification for Cyclone V Devices (1)
POR Delay
Fast (2)
Standard
Minimum
Maximum
Unit
4
12
ms
100
300
ms
Notes to Table 46:
(1) Select the POR delay based on the MSEL setting as described in the “Configuration Schemes for Cyclone V
Devices” table in the Configuration, Design Security, and Remote System Upgrades in Cyclone V Devices chapter.
(2) The maximum pulse width of the fast POR delay is 12 ms, providing enough time for the PCIe hard IP to initialize
after the POR trip.
JTAG Configuration Timing
Table 47 lists the JTAG timing parameters and values for Cyclone V devices.
Table 47. JTAG Timing Parameters and Values for Cyclone V Devices—Preliminary
Symbol
Min
Max
Unit
TCK clock period
30
—
ns
tJCP
TCK clock period
167 (1)
—
ns
tJCH
TCK clock high time
14
—
ns
tJCL
TCK clock low time
14
—
ns
tJPSU (TDI)
TDI JTAG port setup time
1
—
ns
tJPSU (TMS)
TMS JTAG port setup time
3
—
ns
tJPH
JTAG port hold time
5
tJPCO
JTAG port clock to output
—
11
(2)
ns
tJPZX
JTAG port high impedance to valid output
—
14
(2)
ns
14
(2)
ns
tJCP
tJPXZ
Description
JTAG port valid output to high impedance
—
—
ns
Notes to Table 47:
(1) The minimum TCK clock period is 167 ns if VCCBAT is within the range 1.2 V – 1.5 V when you perform the volatile
key programming.
(2) A 1 ns adder is required for each VCCIO voltage step down from 3.0 V. For example, tJPCO = 12 ns if VCCIO of the TDO
I/O bank = 2.5 V, or 13 ns if it equals 1.8 V.
June 2013 Altera Corporation
Cyclone V Device Datasheet
Page 42
Configuration Specification
FPP Configuration Timing
This section describes the fast passive parallel (FPP) configuration timing parameters
for Cyclone V devices.
DCLK-to-DATA[] Ratio (r) for FPP Configuration
FPP configuration requires a different DCLK-to-DATA[] ratio when you turn on
encryption or the compression feature.
Depending on the DCLK-to-DATA[] ratio, the host must send a DCLK frequency that is r
times the DATA[] rate in byte per second (Bps) or word per second (Wps). For
example, in FPP x16 where the r is 2, the DCLK frequency must be 2 times the DATA[]
rate in Wps.
Cyclone V devices use additional clock cycles to decrypt and decompress the
configuration data.
Table 48 lists the DCLK-to-DATA[] ratio for each combination.
Table 48. DCLK-to-DATA[] Ratio for Cyclone V Devices—Preliminary
Configuration Scheme
FPP (8-bit wide)
FPP (16-bit wide)
1
Cyclone V Device Datasheet
Encryption
Compression
DCLK-to-DATA[] ratio (r)
Off
Off
1
On
Off
1
Off
On
2
On
On
2
Off
Off
1
On
Off
2
Off
On
4
On
On
4
If the DCLK-to-DATA[] ratio is greater than 1, at the end of configuration, you can only
stop the DCLK (DCLK-to-DATA[] ratio – 1) clock cycles after the last data is latched into
the Cyclone V device.
June 2013
Altera Corporation
Configuration Specification
Page 43
FPP Configuration Timing when DCLK to DATA[] = 1
Figure 17 shows the timing waveform for an FPP configuration when using a
MAX® II device as an external host. This waveform shows timing when the
DCLK-to-DATA[] ratio is 1.
1
When you enable decompression or the design security feature, the DCLK-to-DATA[]
ratio varies for FPP x8 and FPP x16. For the respective DCLK-to-DATA[] ratio, refer to
Table 48 on page 1–42.
Figure 17. DCLK-to-DATA[] FPP Configuration Timing Waveform for Cyclone V Devices When the Ratio is 1 (1)
tCF2ST1
tCFG
tCF2CK
nCONFIG
nSTATUS (2)
tSTATUS
tCF2ST0
t
(6)
CLK
CONF_DONE (3)
tCF2CD
tST2CK
tCH tCL
(4)
DCLK
tDH
DATA[15..0](5)
Word 0 Word 1 Word 2 Word 3
User Mode
Word n-2 Word n-1
tDSU
User I/O
High-Z
User Mode
INIT_DONE (7)
tCD2UM
Notes to Figure 17:
(1) The beginning of this waveform shows the device in user mode. In user mode, nCONFIG, nSTATUS, and CONF_DONE are at logic-high levels. When
nCONFIG is pulled low, a reconfiguration cycle begins.
(2) After power up, the Cyclone V device holds nSTATUS low for the time of the POR delay.
(3) After power up, before and during configuration, CONF_DONE is low.
(4) Do not leave DCLK floating after configuration. You can drive it high or low, whichever is more convenient.
(5) For FPP x16, use DATA[15..0]. For FPP x8, use DATA[7..0]. DATA[15..0] are available as a user I/O pin after configuration. The state of this
pin depends on the dual-purpose pin settings.
(6) To ensure a successful configuration, send the entire configuration data to the Cyclone V device. CONF_DONE is released high when the Cyclone V
device receives all the configuration data successfully. After CONF_DONE goes high, send two additional falling edges on DCLK to begin initialization
and enter user mode.
(7) After the option bit to enable the INIT_DONE pin is configured into the device, INIT_DONE goes low.
June 2013 Altera Corporation
Cyclone V Device Datasheet
Page 44
Configuration Specification
Table 49 lists the timing parameters for Cyclone V devices for an FPP configuration
when the DCLK-to-DATA[] ratio is 1.
Table 49. DCLK-to-DATA[] FPP Timing Parameters for Cyclone V Devices When the Ratio is 1—Preliminary
Symbol
Parameter
Minimum
Maximum
Unit
tCF2CD
nCONFIG low to CONF_DONE low
—
600
ns
tCF2ST0
nCONFIG low to nSTATUS low
—
600
ns
tCFG
nCONFIG low pulse width
2
—
µs
tSTATUS
nSTATUS low pulse width
268
1506
(1)
µs
tCF2ST1
nCONFIG high to nSTATUS high
—
1506
(2)
µs
tCF2CK
nCONFIG high to first rising edge on DCLK
1506
—
µs
tST2CK
nSTATUS high to first rising edge of DCLK
2
—
µs
tDSU
DATA[] setup time before rising edge on
DCLK
5.5
—
ns
tDH
DATA[] hold time after rising edge on DCLK
0
—
ns
tCH
DCLK high time
0.45 x 1/fMAX
—
s
tCL
DCLK low time
0.45 x 1/fMAX
—
s
tCLK
DCLK period
1/fMAX
—
s
fMAX
DCLK frequency (FPP x8 and x16)
—
125
MHz
tCD2UM
CONF_DONE high to user mode
175
437
µs
tCD2CU
CONF_DONE high to CLKUSR enabled
4 × maximum DCLK period
—
—
tCD2UMC
CONF_DONE high to user mode with CLKUSR
option on
—
—
—
Cycles
Tinit
(3)
Number of clock cycles required for device
initialization
tCD2CU + (Tinit x CLKUSR
period)
17,408
Notes to Table 49:
(1) You can obtain this value if you do not delay configuration by extending the nCONFIG or nSTATUS low pulse width.
(2) You can obtain this value if you do not delay configuration by externally holding nSTATUS low.
(3) The minimum and maximum numbers apply only if you chose the internal oscillator as the clock source for initializing the device.
Cyclone V Device Datasheet
June 2013
Altera Corporation
Configuration Specification
Page 45
FPP Configuration Timing when DCLK to DATA[] > 1
Figure 18 shows the timing waveform for an FPP configuration when using a MAX II
device or microprocessor as an external host. This waveform shows timing when the
DCLK-to-DATA[]ratio is more than 1.
Figure 18. FPP Configuration Timing Waveform for Cyclone V Devices When the DCLK-to-DATA[] Ratio is > 1
(1)
tCF2ST1
tCFG
tCF2CK
nCONFIG
nSTATUS (2)
CONF_DONE (3)
tSTATUS
tCF2ST0
tCF2CD
tCL
tST2CK
DCLK (5)
(7)
tCH
1
2
r
1
2
r
(6)
1
r
1
(4)
2
tCLK
Word 0
DATA[15..0] (7)
tDSU
User I/O
tDH
Word 1
Word 3
User Mod
Word (n-1)
tDH
User Mod
High-Z
INIT_DONE (8)
tCD2UM
Notes to Figure 18:
(1) The beginning of this waveform shows the device in user mode. In user mode, nCONFIG, nSTATUS, and CONF_DONE are at logic high levels.
When nCONFIG is pulled low, a reconfiguration cycle begins.
(2) After power up, the Cyclone V device holds nSTATUS low for the time as specified by the POR delay.
(3) After power up, before and during configuration, CONF_DONE is low.
(4) Do not leave DCLK floating after configuration. You can drive it high or low, whichever is more convenient.
(5) “r” denotes the DCLK-to-DATA[] ratio. For the DCLK-to-DATA[] ratio based on the decompression and the design security feature enable
settings, refer to Table 48 on page 1–42.
(6) If needed, pause DCLK by holding it low. When DCLK restarts, the external host must provide data on the DATA[15..0] pins prior to sending
the first DCLK rising edge.
(7) To ensure a successful configuration, send the entire configuration data to the Cyclone V device. CONF_DONE is released high after the Cyclone V
device receives all the configuration data successfully. After CONF_DONE goes high, send two additional falling edges on DCLK to begin
initialization and enter user mode.
(8) After the option bit to enable the INIT_DONE pin is configured into the device, INIT_DONE goes low.
June 2013 Altera Corporation
Cyclone V Device Datasheet
Page 46
Configuration Specification
Table 50 lists the timing parameters for Cyclone V devices when the
DCLK-to-DATA[]ratio is more than 1.
Table 50. DCLK-to-DATA[] FPP Timing Parameters for Cyclone V Devices when the Ratio is > 1 (1)—Preliminary
Symbol
Parameter
Minimum
Maximum
Unit
tCF2CD
nCONFIG low to CONF_DONE low
—
600
ns
tCF2ST0
nCONFIG low to nSTATUS low
—
600
ns
tCFG
nCONFIG low pulse width
2
—
µs
tSTATUS
nSTATUS low pulse width
268
1506
(2)
µs
tCF2ST1
nCONFIG high to nSTATUS high
—
1506
(3)
µs
tCF2CK
nCONFIG high to first rising edge on DCLK
1506
—
µs
tST2CK
nSTATUS high to first rising edge of DCLK
2
—
µs
tDSU
DATA[] setup time before rising edge on
DCLK
5.5
—
ns
tDH
DATA[] hold time after rising edge on DCLK
N – 1/fDCLK (4)
—
s
tCH
DCLK high time
0.45 x 1/fMAX
—
s
tCL
DCLK low time
0.45 x 1/fMAX
—
s
tCLK
DCLK period
1/fMAX
—
s
fMAX
DCLK frequency (FPP x8 and x16)
—
125
MHz
tR
Input rise time
—
40
ns
tF
Input fall time
—
40
ns
tCD2UM
CONF_DONE high to user mode (5)
175
437
µs
tCD2CU
CONF_DONE high to CLKUSR enabled
4 × maximum DCLK period
—
—
tCD2UMC
CONF_DONE high to user mode with CLKUSR
option on
—
—
—
Cycles
Number of clock cycles required for device
initialization
Tinit
tCD2CU + (Tinit x CLKUSR
period)
17,408
Notes to Table 50:
(1)
(2)
(3)
(4)
(5)
Use these timing parameters when you use decompression and the design security features.
This value can be obtained if you do not delay configuration by extending the nCONFIG or nSTATUS low pulse width.
This value can be obtained if you do not delay configuration by externally holding nSTATUS low.
N is the DCLK-to-DATA[] ratio and fDCLK is the DCLK frequency of the system.
The minimum and maximum numbers apply only if you chose the internal oscillator as the clock source for initializing the device.
Cyclone V Device Datasheet
June 2013
Altera Corporation
Configuration Specification
Page 47
AS Configuration Timing
Figure 19 shows the timing waveform for the active serial (AS) x1 mode and AS x4
mode configuration timing.
Figure 19. AS Configuration Timing Waveform for Cyclone V Devices
tCF2ST1
nCONFIG
nSTATUS
CONF_DONE
nCSO
DCLK
tCO
tDH
Read Address
AS_DATA0/ASDO
tSU
AS_DATA1 (1)
bit 0
bit 1
bit (n − 2) bit (n − 1)
tCD2UM (2)
INIT_DONE (3)
User I/O
User Mode
Notes to Figure 19:
(1) If you are using AS x4 mode, this signal represents the AS_DATA[3..0] and EPCQ sends in 4-bits of data for each DCLK cycle.
(2) The initialization clock can be from the internal oscillator or the CLKUSR pin.
(3) After the option bit to enable the INIT_DONE pin is configured into the device, INIT_DONE goes low.
Table 51 lists the timing parameters for AS x1 and AS x4 configurations in Cyclone V
devices.
The minimum and maximum numbers apply to both the internal oscillator and
CLKUSR when either one is used as the clock source for device configuration.
The tCF2CD, tCF2ST0, tCFG, tSTATUS, and tCF2ST1 timing parameters are identical to the
timing parameters for passive serial (PS) mode listed in Table 53 on page 1–49. You
can obtain the tCF2ST1 value if you do not delay configuration by externally holding
nSTATUS low.
Table 51. AS Timing Parameters for AS x1 and x4 Configurations in Cyclone V Devices—Preliminary
Symbol
Parameter
Minimum
Maximum
Unit
tCO
DCLK falling edge to the AS_DATA0/ASDO output
—
4
µs
tSU
Data setup time before the falling edge on DCLK
1.5
—
ns
tDH
Data hold time after the falling edge on DCLK
0
—
ns
tCD2UM
CONF_DONE high to user mode
175
437
µs
tCD2CU
CONF_DONE high to CLKUSR enabled
4 x maximum DCLK period
—
—
tCD2UMC
CONF_DONE high to user mode with CLKUSR option on
—
—
—
Cycles
Tinit
Number of clock cycles required for device initialization
June 2013 Altera Corporation
tCD2CU + (Tinit x CLKUSR
period)
17,408
Cyclone V Device Datasheet
Page 48
Configuration Specification
Table 52 lists the internal clock frequency specification for the AS configuration
scheme.
The DCLK frequency specification applies when you use the internal oscillator as the
configuration clock source.
The AS multi-device configuration scheme does not support DCLK frequency of
100 MHz.
Table 52. DCLK Frequency Specification in the AS Configuration Scheme for Cyclone V Devices—Preliminary
Parameter
Minimum
DCLK frequency in AS
configuration scheme
Remote update only in AS
mode
Typical
Maximum
Unit
5.3
7.9
12.5
MHz
10.6
15.7
25.0
MHz
21.3
31.4
50.0
MHz
42.6
62.9
100.0
MHz
—
—
12.5
MHz
PS Configuration Timing
Figure 20 shows the timing waveform for a PS configuration when using a MAX II
device or microprocessor as an external host.
Figure 20. PS Configuration Timing Waveform for Cyclone V Devices (1)
tCF2ST1
tCFG
tCF2CK
nCONFIG
nSTATUS (2)
tSTATUS
tCF2ST0
t
(5)
CLK
CONF_DONE (3)
tCF2CD
tST2CK
tCH tCL
(4)
DCLK
tDH
DATA0
Bit 0
Bit 1
Bit 2
Bit 3
Bit (n-1)
tDSU
User I/O
High-Z
User Mod
INIT_DONE (6)
tCD2UM
Notes to Figure 20:
(1) The beginning of this waveform shows the device in user mode. In user mode, nCONFIG, nSTATUS, and CONF_DONE are at logic high levels. When
nCONFIG is pulled low, a reconfiguration cycle begins.
(2) After power up, the Cyclone V device holds nSTATUS low for the time of the POR delay.
(3) After power up, before and during configuration, CONF_DONE is low.
(4) Do not leave DCLK floating after configuration. You can drive it high or low, whichever is more convenient.
(5) To ensure a successful configuration, send the entire configuration data to the Cyclone V device. CONF_DONE is released high after the Cyclone V
device receives all the configuration data successfully. After CONF_DONE goes high, send two additional falling edges on DCLK to begin
initialization and enter user mode.
(6) After the option bit to enable the INIT_DONE pin is configured into the device, INIT_DONE goes low.
Cyclone V Device Datasheet
June 2013
Altera Corporation
Configuration Specification
Page 49
Table 53 lists the PS timing parameter for Cyclone V devices.
Table 53. PS Timing Parameters for Cyclone V Devices—Preliminary
Symbol
Parameter
Minimum
Maximum
Unit
tCF2CD
nCONFIG low to CONF_DONE low
—
600
ns
tCF2ST0
nCONFIG low to nSTATUS low
—
600
ns
tCFG
nCONFIG low pulse width
2
—
µs
tSTATUS
nSTATUS low pulse width
268
1506
(1)
µs
tCF2ST1
nCONFIG high to nSTATUS high
—
1506
(2)
µs
tCF2CK
nCONFIG high to first rising edge on DCLK
1506
—
µs
tST2CK
nSTATUS high to first rising edge of DCLK
2
—
µs
tDSU
DATA[] setup time before rising edge on DCLK
5.5
—
ns
tDH
DATA[] hold time after rising edge on DCLK
0
—
ns
tCH
DCLK high time
0.45 x 1/fMAX
—
s
tCL
DCLK low time
0.45 x 1/fMAX
—
s
tCLK
DCLK period
1/fMAX
—
s
fMAX
DCLK frequency
—
125
MHz
tCD2UM
CONF_DONE high to user mode (3)
175
437
µs
tCD2CU
CONF_DONE high to CLKUSR enabled
4 x maximum DCLK period
—
—
tCD2UMC
CONF_DONE high to user mode with CLKUSR option on
tCD2CU + (Tinit x CLKUSR period)
—
—
Tinit
Number of clock cycles required for device initialization
17,408
—
Cycles
Notes to Table 53:
(1) You can obtain this value if you do not delay configuration by extending the nCONFIG or nSTATUS low pulse width.
(2) You can obtain this value if you do not delay configuration by externally holding nSTATUS low.
(3) The minimum and maximum numbers apply only if you chose the internal oscillator as the clock source for initializing the device.
June 2013 Altera Corporation
Cyclone V Device Datasheet
Page 50
Configuration Specification
Initialization
Table 54 lists the initialization clock source option, the applicable configuration
schemes, and the maximum frequency for Cyclone V devices.
Table 54. Initialization Clock Source Option and the Maximum Frequency for Cyclone V Devices
Initialization Clock Source
Internal Oscillator
CLKUSR (1)
Configuration Schemes
Maximum
Frequency
(MHz)
AS, PS, and FPP
12.5
PS and FPP
125
AS
100
Minimum Number of
Clock Cycles
Tinit
Note to Table 54:
(1) To enable CLKUSR as the initialization clock source, turn on the Enable user-supplied start-up clock (CLKUSR)
option in the Quartus II software from the General panel of the Device and Pin Options dialog box.
Configuration Files
Use Table 55 to estimate the file size before design compilation. Different
configuration file formats, such as a hexadecimal file (.hex) or tabular text file (.ttf)
format, have different file sizes.
For the different types of configuration file and file sizes, refer to the Quartus II
software. However, for a specific version of the Quartus II software, any design
targeted for the same device has the same uncompressed configuration file size.
Table 55 lists the uncompressed raw binary file (.rbf) sizes for Cyclone V devices.
Table 55. Uncompressed .rbf Sizes for Cyclone V Devices—Preliminary (Part 1 of 2)
Variant
Cyclone V
E (1)
Cyclone V GX
Cyclone V GT
Cyclone V SE (1)
Cyclone V Device Datasheet
Member Code
Configuration .rbf Size (bits)
IOCSR .rbf Size (bits)
A2
21,061,120
275,608
A4
21,061,120
275,608
A5
33,958,336
322,072
A7
56,167,328
435,288
A9
102,871,552
400,408
C3
14,512,096
320,280
C4
33,958,336
322,072
C5
33,958,336
322,072
C7
56,167,328
435,288
C9
102,871,552
400,408
D5
33,958,336
322,072
D7
56,167,328
435,288
D9
102,871,552
400,408
A2 (2)
33,958,336
322,072
A4 (2)
33,958,336
322,072
A5
56,057,408
324,888
A6
56,057,408
324,888
June 2013
Altera Corporation
Configuration Specification
Page 51
Table 55. Uncompressed .rbf Sizes for Cyclone V Devices—Preliminary (Part 2 of 2)
Variant
Cyclone V SX
Member Code
Configuration .rbf Size (bits)
IOCSR .rbf Size (bits)
C2 (2)
33,958,336
322,072
C4 (2)
33,958,336
322,072
C5
56,057,408
324,888
C6
56,057,408
324,888
D5
56,057,408
324,888
D6
56,057,408
324,888
Cyclone V ST
Notes to Table 55:
(1) No PCIe hard IP, configuration via protocol (CvP) is not supported in this family.
(2) This device will be supported in a future release of the Quartus II software.
Table 56 lists the minimum configuration time estimation for Cyclone V devices. The
estimated values are based on the configuration .rbf sizes in Table 55.
Table 56. Minimum Configuration Time Estimation for Cyclone V Devices—Preliminary (Part 1 of 2)
Active Serial (1)
Variant
Cyclone V E
Cyclone V GX
Cyclone V GT
Cyclone V SE
Cyclone V SX
Fast Passive Parallel (2)
Width
DCLK
(MHz)
Minimum
Configuration
Time (ms)
Width
DCLK
(MHz)
Minimum
Configuration Time
(ms)
A2
4
100
53
16
125
11
A4
4
100
53
16
125
11
A5
4
100
85
16
125
17
A7
4
100
140
16
125
28
A9
4
100
257
16
125
51
C3
4
100
36
16
125
7
C4
4
100
85
16
125
17
C5
4
100
85
16
125
17
C7
4
100
140
16
125
28
C9
4
100
257
16
125
51
D5
4
100
85
16
125
17
D7
4
100
140
16
125
28
D9
4
100
257
16
125
51
A2
4
100
85
16
125
17
A4
4
100
85
16
125
17
A5
4
100
140
16
125
28
A6
4
100
140
16
125
28
C2
4
100
85
16
125
17
C4
4
100
85
16
125
17
C5
4
100
140
16
125
28
C6
4
100
140
16
125
28
Member Code
June 2013 Altera Corporation
Cyclone V Device Datasheet
Page 52
Configuration Specification
Table 56. Minimum Configuration Time Estimation for Cyclone V Devices—Preliminary (Part 2 of 2)
Active Serial (1)
Variant
Width
DCLK
(MHz)
Minimum
Configuration
Time (ms)
Width
DCLK
(MHz)
Minimum
Configuration Time
(ms)
D5
4
100
140
16
125
28
D6
4
100
140
16
125
28
Member Code
Cyclone V ST
Fast Passive Parallel (2)
Notes to Table 55:
(1) DCLK frequency of 100 MHz using external CLKUSR.
(2) Maximum FPGA FPP bandwidth may exceed bandwidth available from some external storage or control logic.
Remote System Upgrades Circuitry Timing Specification
Table 57 lists the timing parameter specifications for the remote system upgrade
circuitry.
Table 57. Remote System Upgrade Circuitry Timing Specification for Cyclone V Devices—
Preliminary
Parameter
Minimum
Maximum
Unit
tMAX_RU_CLK (1)
—
40
MHz
tRU_nCONFIG (2)
250
—
ns
250
—
ns
tRU_nRSTIMER
(3)
Notes to Table 57:
(1) This clock is user-supplied to the remote system upgrade circuitry. If you are using the ALTREMOTE_UPDATE
megafunction, the clock user-supplied to the ALTREMOTE_UPDATE megafunction must meet this specification.
(2) This is equivalent to strobing the reconfiguration input of the ALTREMOTE_UPDATE megafunction high for the
minimum timing specification. For more information, refer to the “Remote System Upgrade State Machine”
section in the Configuration, Design Security, and Remote System Upgrades in Cyclone V Devices chapter.
(3) This is equivalent to strobing the reset timer input of the ALTREMOTE_UPDATE megafunction high for the
minimum timing specification. For more information, refer to the “User Watchdog Timer” section in the
Configuration, Design Security, and Remote System Upgrades in Cyclone V Devices chapter.
User Watchdog Internal Oscillator Frequency Specification
Table 58 lists the frequency specifications for the user watchdog internal oscillator.
Table 58. User Watchdog Internal Oscillator Frequency Specifications for Cyclone V Devices—
Preliminary
Parameter
User watchdog internal
oscillator frequency
Cyclone V Device Datasheet
Minimum
Typical
Maximum
Unit
5.3
7.9
12.5
MHz
June 2013
Altera Corporation
I/O Timing
Page 53
I/O Timing
Altera offers two ways to determine I/O timing—the Excel-based I/O Timing and the
Quartus II Timing Analyzer.
Excel-based I/O timing provides pin timing performance for each device density and
speed grade. The data is typically used prior to designing the FPGA to get an estimate
of the timing budget as part of the link timing analysis.
The Quartus II Timing Analyzer provides a more accurate and precise I/O timing
data based on the specifics of the design after you complete place-and-route.
f You can download the Excel-based I/O Timing spreadsheet from the Cyclone V
Devices Documentation webpage.
Programmable IOE Delay
Table 59 lists the Cyclone V IOE programmable delay settings.
Table 59. IOE Programmable Delay for Cyclone V Devices
Fast Model
Available
Settings
Minimum
Offset
D1
31
0
0.508
D3
7
0
D4
31
D5
31
Parameter
Slow Model
Unit
Industrial Commercial
–C6
–C7
–C8
–I7
–A7
0.517
0.971
1.187
1.194
1.179
1.160
ns
1.761
1.793
3.291
4.022
3.961
3.999
3.929
ns
0
0.510
0.519
1.180
1.187
1.195
1.180
1.160
ns
0
0.508
0.517
0.970
1.186
1.194
1.179
1.179
ns
Programmable Output Buffer Delay
Table 60 lists the delay chain settings that control the rising and falling edge delays of
the output buffer. The default delay is 0 ps.
You can set the programmable output buffer delay in the Quartus II software by
setting the Output Buffer Delay Control assignment to either positive, negative, or
both edges, with the specific values stated here (in ps) for the Output Buffer Delay
assignment.
Table 60. Programmable Output Buffer Delay for Cyclone V Devices
Symbol
DOUTBUF
Parameter
Rising and/or falling edge
delay
(1)—Preliminary
Typical
Unit
0 (default)
ps
50
ps
100
ps
150
ps
Note to Table 60:
(1) Pending data extraction from the Quartus II software.
June 2013 Altera Corporation
Cyclone V Device Datasheet
Page 54
Glossary
Glossary
Table 61 lists the glossary for this datasheet.
Table 61. Glossary Table (Part 1 of 4)
Letter
Subject
Definitions
A
B
—
—
C
Receiver Input Waveforms
Single-Ended Waveform
Positive Channel (p) = VIH
VID
Negative Channel (n) = VIL
VCM
Ground
Differential Waveform
VID
p−n=0V
VID
D
Differential I/O
Standards
Transmitter Output Waveforms
Single-Ended Waveform
Positive Channel (p) = VOH
VOD
Negative Channel (n) = VOL
VCM
Ground
Differential Waveform
VOD
p−n=0V
VOD
E
F
—
—
fHSCLK
Left/right PLL input clock frequency.
fHSDR
High-speed I/O block—Maximum/minimum LVDS data transfer rate
(fHSDR = 1/TUI).
G
H
—
—
I
Cyclone V Device Datasheet
June 2013
Altera Corporation
Glossary
Page 55
Table 61. Glossary Table (Part 2 of 4)
Letter
Subject
J
Definitions
High-speed I/O block—Deserialization factor (width of parallel data bus).
JTAG Timing Specifications:
TMS
TDI
J
t JCP
JTAG Timing
Specifications
t JCH
t JCL
t JPH
t JPSU
TCK
tJPZX
t JPXZ
t JPCO
TDO
K
L
M
—
—
N
O
Diagram of PLL Specifications
(1)
CLKOUT Pins
Switchover
fOUT_EXT
4
CLK
fIN
N
fINPFD
PFD
CP
LF
VCO fVCO
Core Clock
Counters
C0..C17
fOUT
PLL
Specifications
GCLK
RCLK
Delta Sigma
Modulator
P
Key
Reconfigurable in User Mode
External Feedback
Note:
(1) Core Clock can only be fed by dedicated clock input pins or PLL outputs.
Some tables show the designation as “Preliminary”. Preliminary characteristics are created
using simulation results, process data, and other known parameters.
Preliminary
Q
R
—
RL
June 2013 Altera Corporation
Final numbers are based on actual silicon characterization and testing. The numbers reflect
the actual performance of the device under worst-case silicon process, voltage, and junction
temperature conditions. There are no preliminary designations on finalized tables.
—
Receiver differential input discrete resistor (external to the Cyclone V device).
Cyclone V Device Datasheet
Page 56
Glossary
Table 61. Glossary Table (Part 3 of 4)
Letter
Subject
Sampling window
(SW)
Definitions
Timing Diagram—the period of time during which the data must be valid in order to capture
it correctly. The setup and hold times determine the ideal strobe position within the sampling
window, as shown:
Bit Time
0.5 x TCCS
RSKM
Sampling Window
(SW)
RSKM
0.5 x TCCS
The JEDEC standard for the SSTL and HSTL I/O defines both the AC and DC input signal
values. The AC values indicate the voltage levels at which the receiver must meet its timing
specifications. The DC values indicate the voltage levels at which the final logic state of the
receiver is unambiguously defined. After the receiver input has crossed the AC value, the
receiver changes to the new logic state.
The new logic state is then maintained as long as the input stays beyond the DC threshold.
This approach is intended to provide predictable receiver timing in the presence of input
waveform ringing.
S
Single-Ended Voltage Referenced I/O Standard
Single-ended
voltage
referenced I/O
standard
VCCIO
VOH
VIH (AC )
VIH(DC)
VREF
VIL(DC)
VIL(AC )
VOL
VSS
tC
High-speed receiver/transmitter input and output clock period.
TCCS (channelto-channel-skew)
The timing difference between the fastest and slowest output edges, including the tCO
variation and clock skew, across channels driven by the same PLL. The clock is included in
the TCCS measurement (refer to the Timing Diagram figure under SW in this table).
High-speed I/O block—Duty cycle on high-speed transmitter output clock.
Timing Unit Interval (TUI)
tDUTY
The timing budget allowed for skew, propagation delays, and the data sampling window.
(TUI = 1/(Receiver Input Clock Frequency Multiplication Factor) = tC/w)
T
U
tFALL
Signal high-to-low transition time (80-20%)
tINCCJ
Cycle-to-cycle jitter tolerance on the PLL clock input
tOUTPJ_IO
Period jitter on the general purpose I/O driven by a PLL
tOUTPJ_DC
Period jitter on the dedicated clock output driven by a PLL
tRISE
Signal low-to-high transition time (20–80%)
—
Cyclone V Device Datasheet
—
June 2013
Altera Corporation
Document Revision History
Page 57
Table 61. Glossary Table (Part 4 of 4)
Letter
V
W
Subject
Definitions
VCM(DC)
DC common mode input voltage.
VICM
Input common mode voltage—The common mode of the differential signal at the receiver.
VID
Input differential voltage swing—The difference in voltage between the positive and
complementary conductors of a differential transmission at the receiver.
VDIF(AC)
AC differential input voltage—Minimum AC input differential voltage required for switching.
VDIF(DC)
DC differential input voltage— Minimum DC input differential voltage required for switching.
VIH
Voltage input high—The minimum positive voltage applied to the input which is accepted by
the device as a logic high.
VIH(AC)
High-level AC input voltage
VIH(DC)
High-level DC input voltage
VIL
Voltage input low—The maximum positive voltage applied to the input which is accepted by
the device as a logic low.
VIL(AC)
Low-level AC input voltage
VIL(DC)
Low-level DC input voltage
VOCM
Output common mode voltage—The common mode of the differential signal at the
transmitter.
VOD
Output differential voltage swing—The difference in voltage between the positive and
complementary conductors of a differential transmission at the transmitter.
VSWING
Differential input voltage
VX
Input differential cross point voltage
VOX
Output differential cross point voltage
W
High-speed I/O block—Clock Boost Factor
X
Y
—
—
Z
Document Revision History
Table 62 lists the revision history for this document.
Table 62. Document Revision History (Part 1 of 2)
Date
June 2013
May 2013
Version
3.4
3.3
June 2013 Altera Corporation
Changes
■
Updated Table 20, Table 27, and Table 34.
■
Updated “UART Interface” and “CAN Interface” sections.
■
Removed the following tables:
■
Table 45. UART Baud Rate for Cyclone V Devices
■
Table 47. CAN Pulse Width for Cyclone V Devices
■
Added Table 33.
■
Updated Figure 5, Figure 6, Figure 17, Figure 19, and Figure 20.
■
Updated Table 1, Table 4, Table 5, Table 10, Table 13, Table 19, Table 20, Table 26,
Table 32, Table 35, Table 36, Table 43, Table 53, Table 54, Table 57, and Table 61.
Cyclone V Device Datasheet
Page 58
Document Revision History
Table 62. Document Revision History (Part 2 of 2)
Date
Version
March 2013
January 2013
November 2012
3.2
3.1
Changes
■
Added HPS reset information in the “HPS Specifications” section.
■
Added Table 57.
■
Updated Table 1, Table 2, Table 17, Table 20, Table 52, and Table 56.
■
Updated Figure 18.
Updated Table 4, Table 20, and Table 56.
■
Updated Table 1, Table 4, Table 5, Table 9, Table 14, Table 16, Table 17, Table 19,
Table 20, Table 25, Table 28, Table 52, Table 55, Table 56, and Table 59.
■
Removed table: Transceiver Block Jitter Specifications for Cyclone V GX Devices.
■
Added HPS information:
3.0
■
Added “HPS Specifications” section.
■
Added Table 33, Table 34, Table 35, Table 36, Table 37, Table 38, Table 39, Table 40,
Table 41, Table 42, Table 43, Table 44, Table 45, and Table 46.
■
Added Figure 4, Figure 5, Figure 6, Figure 7, Figure 8, Figure 9, Figure 10, Figure 11,
Figure 12, Figure 13, Figure 14, Figure 15, and Figure 16.
■
Updated Table 3.
Updated for the Quartus II software v12.0 release:
June 2012
February 2012
Restructured document.
■
Removed “Power Consumption” section.
■
Updated Table 1,Table 3, Table 19, Table 20, Table 25, Table 27, Table 28, Table 30,
Table 31, Table 34, Table 36, Table 37, Table 38, Table 39, Table 41, Table 43, and
Table 46.
■
Added Table 22, Table 23, and Table 29.
■
Added Figure 1 and Figure 2.
■
Added “Initialization” and “Configuration Files” sections.
■
Added automotive speed grade information.
■
Added Figure 2–1.
■
Updated Table 2–3, Table 2–8, Table 2–9, Table 2–19, Table 2–20, Table 2–21,
Table 2–22, Table 2–23, Table 2–24, Table 2–25, Table 2–26, Table 2–27, Table 2–28,
Table 2–30, Table 2–35, and Table 2–43.
■
Minor text edits.
■
Added Table 2–5.
■
Updated Table 2–3, Table 2–4, Table 2–11, Table 2–13, Table 2–20, and Table 2–21.
2.0
1.2
November 2011
1.1
October 2011
1.0
Cyclone V Device Datasheet
■
Initial release.
June 2013
Altera Corporation