NSC DS15BA101SD

DS15BA101
1.5 Gbps Differential Buffer with Adjustable Output Voltage
General Description
Features
The DS15BA101 is a high-speed differential buffer for cable
driving, level translation, signal buffering, and signal repeating applications. Its fully differential signal path ensures exceptional signal integrity and noise immunity and it drives both
differential and single-ended transmission lines at data rates
in excess of 1.5 Gbps.
Output voltage amplitude is adjustable via a single external
resistor for level translation and cable driving applications into
50-ohm single-ended and 100-ohm differential mode
impedances.
The DS15BA101 is powered from a single 3.3V supply and
consumes 150 mW (typ) at 1.5 Gbps. It operates over the full
−40°C to +85°C industrial temperature range and is available
in a space saving 3x3 mm LLP-8 package.
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■
■
■
■
■
■
Data rates from DC to 1.5+ Gbps
Differential or single-ended input
Adjustable output amplitude
Single 3.3V supply
Industrial -40°C to +85°C temperature
Low power: 150 mW (typ) at 1.5 Gbps
Space-saving 3 x 3 mm LLP-8 package
Applications
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■
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Cable extension applications
Level translation
Signal buffering and repeating
Security cameras
Typical Application
20199902
© 2007 National Semiconductor Corporation
201999
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DS15BA101 1.5 Gbps Differential Buffer with Adjustable Output Voltage
April 2007
DS15BA101
ESD Rating (HBM)
ESD Rating (MM)
Absolute Maximum Ratings (Note 1)
Supply Voltage:
Input Voltage (all inputs)
Output Current
Storage Temperature Range
Junction Temperature
Lead Temperature
(Soldering 4 Sec)
Package Thermal Resistance
θJA LLP-8
θJC LLP-8
−0.5V to 3.6V
−0.3V to VCC+0.3V
28 mA
−65°C to +150°C
+150°C
5 kV
250V
Recommended Operating
Conditions
Supply Voltage (VCC – GND):
Operating Free Air Temperature (TA)
DS15BA101SD
+260°C
3.3V ±5%
−40°C to +85°C
+90.7°C/W
+41.2°C/W
DC Electrical Characteristics
Over Supply Voltage and Operating Temperature ranges, unless otherwise specified (Notes 2, 3).
Symbol Parameter
Conditions
Reference
VICM
Input Common Mode Voltage
(Note 4)
IN+, IN-
VID
Differential Input Voltage Swing
VOS
Output Common Mode Voltage
VOUT
Output Voltage
ICC
Supply Current
Min
Typ
0.8
100
OUT+, OUT-
Max
Units
VCC –
VID/2
V
2000
mVP−P
VCC –
VOUT/2
V
Single-ended, 50Ω load
RVO = 953Ω 1%,
400
mVP-P
Single-ended, 50Ω load
RVO = 487Ω 1%,
800
mVP-P
(Note 5)
45
49
mA
Max
Units
AC Electrical Characteristics
Over Supply Voltage and Operating Temperature ranges, unless otherwise specified (Note 3).
Symbol Parameter
Conditions
Reference
Min
Typ
DRMAX
Maximum Data Rate
(Note 4)
IN+, IN-
1.5
2.0
tLHT
Output Low to High Transition
Time
20% – 80%
(Note 6)
OUT+, OUT-
tHLT
Output High to Low Transition
Time
tPLHD
Propagation Low to High Delay
(Note 4)
tPHLD
Propagation High to Low Delay
(Note 4)
tTJ
Total Jitter
1.5 Gbps
Gbps
120
220
ps
120
220
ps
0.95
1.10
1.35
ns
0.95
1.10
1.35
26
ns
psP-P
Note 1: "Absolute Maximum Ratings" are those parameter values beyond which the life and operation of the device cannot be guaranteed. The stating herein of
these maximums shall not be construed to imply that the device can or should be operated at or beyond these values. The table of "Electrical Characteristics"
specifies acceptable device operating conditions.
Note 2: Current flow into device pins is defined as positive. Current flow out of device pins is defined as negative. All voltages are stated referenced to GND.
Note 3: Typical values are stated for VCC = +3.3V and TA = +25°C.
Note 4: Specification is guaranteed by characterization.
Note 5: Maximum ICC is measured at VCC = +3.465V and TA = +70°C.
Note 6: Specification is guaranteed by characterization and verified by test.
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2
DS15BA101
Connection Diagram
20199901
8-Pad LLP
Order Number DS15BA101SD or DS15BA101SDX
See NS Package Number SDA08A
Pin Descriptions
Pin #
Name
Description
1
IN+
Non-inverting input pin.
2
IN-
Inverting input pin.
3
GND
Circuit common (ground reference).
4
RVO
Output voltage amplitude control. Connect a resistor to VCC to set output voltage.
5
VCC
Positive power supply (+3.3V).
6
GND
Circuit common (ground reference).
7
OUT-
Non-inverting output pin.
8
OUT+
Inverting output pin.
3
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DS15BA101
Device Operation
ified common-mode range. The IN+ and IN- pins are selfbiased at approximately 2.1V with VCC = 3.3V. The following
three figures illustrate typical DC-coupled interface to common differential drivers.
INPUT INTERFACING
The DS15BA101 accepts either differential or single-ended
input. The inputs are self-biased, allowing for simple AC or
DC coupling. DC-coupled inputs must be kept within the spec-
20199920
Typical LVDS Driver DC-Coupled Interface to DS15BA101 Input
20199921
Typical CML Driver DC-Coupled Interface to DS15BA101 Input
20199922
Typical LVPECL Driver DC-Coupled Interface to DS15BA101 Input
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4
20199923
Typical DS15BA101 Output DC-Coupled Interface to an LVDS, CML or LVPECL Receiver
5
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DS15BA101
RVO network should be removed to minimize parasitic capacitance. The following figure illustrates typical DC-coupled interface to common differential receivers and assumes that the
receivers have high impedance inputs. While most receivers
have a common mode input range that can accomodate CML
signals, it is recommended to check respective receiver's
datasheet prior to implementing the suggested interface implementation.
OUTPUT INTERFACING
The DS15BA101 uses current mode outputs. Single-ended
output levels are 400 mVP-P into AC-coupled 100Ω differential
cable (with RVO = 953Ω) or into AC-coupled 50Ω coaxial cable
(with RVO = 487Ω). Output level is controlled by the value of
the RVO resistor connected between the RVO and VCC.
The RVO resistor should be placed as close as possible to the
RVO pin. In addition, the copper in the plane layers below the
DS15BA101
CAT5e/6/7 and twinax) and 50Ω coaxial cables. Setting correct DS15BA101 output amplitude and proper cable termination are keys for optimal operation. The following two figures
show recommended chipset configuration for 100Ω differential and 50Ω coaxial cables.
CABLE EXTENDER APPLICATION
The DS15BA101 together with the DS15EA101 form a cable
extender chipset optimized for extending serial data streams
from serializer/deserializer (SerDes) pairs and field programmable gate arrays (FPGAs) over 100Ω differential (i.e.
20199905
Cable Extender Chipset Connection Diagram for 100Ω Differential Cables
20199906
Cable Extender Chipset Connection Diagram for 50Ω Coaxial Cables
REFERENCE DESIGN
There is a complete reference design (P/N: DriveCable02EVK) available for evaluation of the cable extender chipset (DS15BA101
and DS15EA101). Fore more information visit http://www.national.com/appinfo/lvds/drivecable02evk.html.
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DS15BA101
Typical Performance
20199911
20199910
2.0 Gbps Differential DS15BA101 Output
RVO = 953Ω, H:100 ps / DIV, V:100 mV / DIV
1.5 Gbps Differential DS15BA101 Output
RVO = 953Ω, H:100 ps / DIV, V:100 mV / DIV
20199913
20199912
2.0 Gbps Single-ended DS15BA101 Output
RVO = 487Ω, H:100 ps / DIV, V:100 mV / DIV
1.5 Gbps Single-ended DS15BA101 Output
RVO = 487Ω, H:100 ps / DIV, V:100 mV / DIV
7
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DS15BA101
Physical Dimensions inches (millimeters) unless otherwise noted
8-Pad LLP
Order Number DS15BA101SD or DS15BA101SDX
NS Package Number SDA08A
(See AN-1187 for PCB Design and Assembly Recommendations)
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8
DS15BA101
Notes
9
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DS15BA101 1.5 Gbps Differential Buffer with Adjustable Output Voltage
Notes
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Copyright© 2007 National Semiconductor Corporation
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