AOZ1025D EZBuck™ 8A Synchronous Buck Regulator General Description Features The AOZ1025D is a high efficiency, simple to use, buck regulator, capable of up to 8A with an external low side MOSFET. The AOZ1025D works from a 4.75V to 16V input voltage range, 4.75 to 16V operating input voltage range Synchronous rectification: Integrated high side MOSFET High efficiency: up to 95% The AOZ1025D comes in a 5 x 4 DFN-16 package and is rated over a -40°C to +85°C ambient temperature range. Internal soft start Output voltage adjustable to 0.8V Up to 8A continuous output current Fixed 500kHz PWM operation Cycle-by-cycle current limit Short-circuit protection Thermal shutdown Small size 5 x 4 DFN-16 package Applications Point of load DC/DC conversion Desktops/graphics cards PCIe graphics cards Set top boxes Blu-Ray and HD-DVD–recorders LCD TVs Typical Application 5V DC VIN = 12V C1, C2 22µF Ceramic VIN EN L1 2.2µH AOZ1025D COMP RC CC GOOD VOUT LX NGATE R1 FB AGND PGND C3, C4, C5 22µF Ceramic R2 Figure 1. 1.2V/8A Synchronous Buck Regulator Rev. 1.4 June 2012 www.aosmd.com Page 1 of 15 AOZ1025D Ordering Information Part Number Ambient Temperature Range Package Environmental AOZ1025DIL -40°C to +85°C 5 x 4 DFN-16 Green Product AOS Green Products use reduced levels of Halogens, and are also RoHS compliant. Please visit www.aosmd.com/media/AOSGreenPolicy.pdf for additional information. Pin Configuration LX 1 16 LX VIN 2 15 LX VIN 3 14 LX VIN 4 13 NGATE VIN 5 12 PGOOD AGND 6 11 PGND FB 7 10 EN NC 8 9 COMP LX AGND 5 x 4 DFN-16 (Top Thru View) Pin Description Pin Number Pin Name Pin Function 1 LX PWM output connection to inductor. Thermal connection for output stage. 2, 3, 4, 5 VIN Supply voltage input. When VIN rises above the UVLO threshold the device starts up. 6 AGND 7 FB The FB pin is used to determine the output voltage via a resistor divider between the output and GND. 8 NC Not connected 9 COMP Reference connection for controller section. Also used as thermal connection for controller section. Electrically needs to be connected to PGND External loop compensation pin. 10 EN 11 PGND 12 PGOOD Power Good. Open drain. Use resistor to pull up to 5V supply. 13 NGATE Low side MOSFET driver; Connect it to the gate of external low side MOSFET. 14, 15, 16 LX Rev. 1.4 June 2012 The enable pin is active high. Do not leave it open. Power ground. Electrically needs to be connected to AGND. PWM output connection to inductor. Thermal connection for output stage. www.aosmd.com Page 2 of 15 AOZ1025D Block Diagram VIN UVLO & POR EN Internal +5V 5V LDO Regulator OTP + ISen – Reference & Bias Softstart Q1 ILimit + + 0.8V EAmp FB – – PWM Control Logic PWM Comp + Level Shifter + FET Driver LX LDRV 500kHz/68kHz Oscillator COMP + 0.2V – 0.72V + Frequency Foldback Comparator PGOOD – Over Voltage Comparator 0.96V 0.86V – + AGND PGND Absolute Maximum Ratings Recommend Operating Ratings Exceeding the Absolute Maximum ratings may damage the device. The device is not guaranteed to operate beyond the Maximum Operating Ratings. Parameter Supply Voltage (VIN) Rating Parameter 18V LX to AGND -0.7V to VIN+0.3V EN to AGND -0.3V to VIN+0.3V FB to AGND -0.3V to 6V COMP to AGND -0.3V to 6V PGND to AGND -0.3V to +0.3V Junction Temperature (TJ) +150°C Storage Temperature (TS) -65°C to +150°C ESD Rating(1) 2kV Note: 1. Devices are inherently ESD sensitive, handling precautions are required. Human body model rating: 1.5kΩ in series with 100pF. Rev. 1.4 June 2012 Supply Voltage (VIN) Output Voltage Range Ambient Temperature (TA) Rating 4.75V to 16V 0.8V to VIN -40°C to +85°C Package Thermal Resistance 5 x 4 DFN-16 (JA)(2) 50°C/W Package Thermal Resistance 5 x 4 DFN-16 (JC)(2) 5°C/W Note: 2. The value of JA is measured with the device mounted on 1-in2 FR-4 board with 2oz. Copper, in a still air environment with TA = 25°C. The value in any given application depends on the user's specific board design. www.aosmd.com Page 3 of 15 AOZ1025D Electrical Characteristics TA = 25°C, VIN = VEN = 12V, VOUT = 1.2V unless otherwise specified(3) Symbol VIN VUVLO Parameter Conditions Supply Voltage Typ. 4.75 Input Under-Voltage Lockout Threshold VIN Rising VIN Falling 4.1 3.7 1.2 Supply Current (Quiescent) IOUT = 0, VFB = 1.2V, VEN > 1.2V IOFF Shutdown Supply Current VEN = 0V VFB Feedback Voltage IIN Min. 0.788 0.8 Max. Units 16 V V 3 mA 30 µA 0.812 V Load Regulation 0.5 % Line Regulation 0.2 % IFB Feedback Voltage Input Current VEN EN Input Threshold VHYS EN Input Hysteresis 200 Off Threshold On Threshold 0.6 2 100 nA V mV MODULATOR fO Frequency 350 DMAX Maximum Duty Cycle 100 DMIN Minimum Duty Cycle 500 600 kHz % 6 % Error Amplifier Voltage Gain 500 V/ V Error Amplifier Transconductance 200 µA / V PROTECTION ILIM Current Limit 10 A Over-Temperature Shutdown Limit TJ Rising TJ Falling 150 100 °C VPR Output Over-voltage Protection Threshold Off Threshold On Threshold 960 860 mV tSS Soft Start Interval 3 4 6.5 ms 0.5 V 1 µA POWER GOOD VOLPG PG LOW Voltage IOL = 1mA PG Leakage VPGL PG Threshold Voltage -12 PG Threshold Voltage Hysteresis PG Delay Time -10 -8 % 3 % 128 µs OUTPUT STAGE High-Side Switch On-Resistance VIN = 12V 43 57 mΩ LOW SIDE DRIVER Pull-up Resistance 20 Pull-up Resistance 7 Ω Ω Note: 3. Specification in BOLD indicate an ambient temperature range of -40°C to +85°C. These specifications are guaranteed by design. Rev. 1.4 June 2012 www.aosmd.com Page 4 of 15 AOZ1025D Maximum Output Current Maximum output current of buck converters such as AOZ1025D is related with driving capability and thermal condition. AOZ1025D’s driving voltage varies with the input voltage. When input voltage is higher than 6.5V, the driver inside the AOZ1025D can drive both high side and low side MOSFETs to deliver 8A output current; but when the input voltage is 5V, the recommended maximum output current is de-rated to 6A. The output voltage within a fixed input voltage directed determines the turn-on ratio of integrated PMOS, and thus the thermal condition of AOZ1025D during the operation. The following diagrams show the safe operation region of AOZ1025 operating at VIN = 5V, and VIN = 12V respectively. VIN = 12V Safe Operation Region VIN = 5V Safe Operation Region 9 7 6 7 Output Current (A) Output Current (A) 8 6 5 4 3 5 4 3 2 2 1 1 0 0.8 1.3 1.8 2.3 2.8 3.3 3.8 4.3 4.8 0 0.8 5.3 1.3 1.8 Output Voltage (V) 2.3 2.8 3.3 3.8 Output Voltage (V) Input Voltage Vs. Maximum Output Current AOZ1025D’s driving voltage varies with the input voltage.þWhen input voltage is higher than 6.5V, the driver inside the AOZ1025D can drive both high side and low side MOSFETs to deliver 8A output current; but when the input voltage is 5V, the recommended maximum output current is de-rated to 6A.þThe following diagram shows relations of the input voltage and the maximum output current of AOZ1025D. Input Voltage vs. Maximum Output Current 9 8 Current (A) 7 6 5 4 3 2 5 Rev. 1.4 June 2012 6 7 8 9 10 11 12 Voltage (V) www.aosmd.com 13 14 15 16 Page 5 of 15 AOZ1025D Efficiency The efficiency was measured based on Figure 1 with the low-side external MOSFET (AO4722). Efficiency Efficiency (V = 5V) (VIN IN = 5V) 100 100 (V = 12V) (VIN IN = 12V) 100 100 95 95 95 95 = 5.0V V VO O = 5.0V 90 90 Efficiency (%) (%) Efficiency Efficiency (%) (%) Efficiency V = 3.3V VO O = 3.3V 85 85 = 1.8V V VO O = 1.8V 80 80 V = 1.1V VO O = 1.1V 75 75 90 90 V = 3.3V VO O = 3.3V 85 85 V = 1.8V VO O = 1.8V 80 80 75 75 = 1.1V V VO O = 1.1V 70 70 70 70 00 11 22 33 44 55 66 11 22 33 44 55 66 77 88 Current Current (A) (A) Current Current (A) (A) Rev. 1.4 June 2012 00 www.aosmd.com Page 6 of 15 AOZ1025D Detailed Description The AOZ1025D is a current-mode step down regulator with integrated high-side PMOS switch. It operates from a 4.75V to 16V input voltage range and supplies up to 8A of load current. The duty cycle can be adjusted from 6% to 100% allowing a wide range of output voltage. Features include enable control, Power-On Reset, input under voltage lockout, output over voltage protection, fixed internal soft-start and thermal shut down. The AOZ1025D uses a P-Channel MOSFET as the high-side switch. It saves the bootstrap capacitor normally seen in a circuit which is using an NMOS switch. Switching Frequency Enable and Soft Start The AOZ1025D has internal soft start feature to limit in-rush current and ensure the output voltage ramps up smoothly to regulation voltage. A soft start process begins when the input voltage rises to 4.0V and voltage on EN pin is HIGH. In soft start process, the output voltage is ramped to regulation voltage in typically 4ms. The 4ms soft start time is set internally. The voltage on EN pin must rise above 1.8V to enable the AOZ1025D. When voltage on EN pin falls below 0.6V, the AOZ1025D is disabled. Steady-State Operation Under steady-state conditions, the converter operates in fixed frequency and Continuous-Conduction Mode (CCM). The AOZ1025D integrates an internal P-MOSFET as the high-side switch. Inductor current is sensed by amplifying the voltage drop across the drain to source of the high side power MOSFET. Output voltage is divided down by the external voltage divider at the FB pin. The difference of the FB pin voltage and reference is amplified by the internal transconductance error amplifier. The error voltage, which shows on the COMP pin, is compared against the current signal, which is sum of inductor current signal and ramp compensation signal, at PWM comparator input. If the current signal is less than the error voltage, the internal high-side switch is on. The inductor current flows from the input through the inductor to the output. When the current signal exceeds the error voltage, the high-side switch is off. The inductor current is freewheeling through the external low-side N-MOSFET switch to output. The internal adaptive FET driver guarantees no turn on overlap of both high-side and low-side switch. Rev. 1.4 June 2012 The AOZ1025D uses an external freewheeling NMOSFET to realize synchronous rectification. It greatly improves the converter efficiency and reduces power loss in the low-side switch. The AOZ1025D switching frequency is fixed and set by an internal oscillator. The practical switching frequency could range from 350 kHz to 600 kHz due to device variation. Output Voltage Programming Output voltage can be set by feeding back the output to the FB pin by using a resistor divider network. In the application circuit shown in Figure 1. The resistor divider network includes R1 and R2. Usually, a design is started by picking a fixed R2 value and calculating the required R1 with equation: R 1 V O = 0.8 1 + ------- R 2 Some standard value of R1, R2 and most used output voltage values are listed in Table 1. Table 1. VO (V) R1 (kΩ) R2 (kΩ) 0.8 1.0 Open 1.2 4.99 10 1.5 10 11.5 1.8 12.7 10.2 2.5 21.5 10 3.3 31.6 10 5.0 52.3 10 The combination of R1 and R2 should be large enough to avoid drawing excessive current from the output, which will cause power loss. www.aosmd.com Page 7 of 15 AOZ1025D Protection Features Application Information The AOZ1025D has multiple protection features to prevent system circuit damage under abnormal conditions. The basic AOZ1025D application circuit is show in Figure 1. Component selection is explained below. Over Current Protection (OCP) The sensed inductor current signal is also used for over current protection. Since the AOZ1025D employs peak current mode control, the COMP pin voltage is proportional to the peak inductor current. The COMP pin voltage is limited to be between 0.4V and 2.5V internally. The peak inductor current is automatically limited cycle by cycle. When the output is shorted to ground under fault conditions, the inductor current decays very slow during a switching cycle because of VO = 0V. To prevent catastrophic failure, a secondary current limit is designed inside the AOZ1025D. The measured inductor current is compared against a preset voltage which represents the current limit. When the output current is more than current limit, the high side switch will be turned off and EN pin will be pulled down. The converter will initiate a soft start once the over-current condition disappears. Output Over Voltage Protection (OVP) The AOZ1025D monitors the feedback voltage: when the feedback voltage is higher than 960mV, it immediate turns-off the PMOS to protect the output voltage overshoot at fault condition. When feedback voltage is lower than 840mV, the PMOS is allowed to turn on in the next cycle. Under-voltage Lock-out (UVLO) A power-on reset circuit monitors the input voltage. When the input voltage exceeds 4V, the converter starts operation. When input voltage falls below 3.7V, the converter will be shut down. Thermal Protection An internal temperature sensor monitors the junction temperature. It shuts down the internal control circuit and high side PMOS if the junction temperature exceeds 150°C. The regulator will restart automatically under the control of soft-start circuit when the junction temperature decreases to 100°C. Input Capacitor The input capacitor must be connected to the VIN pin and PGND pin of AOZ1025D to maintain steady input voltage and filter out the pulsing input current. The voltage rating of input capacitor must be greater than maximum input voltage plus ripple voltage. The input ripple voltage can be approximated by equation below: VO VO IO V IN = ----------------- 1 – --------- --------f C IN V IN V IN Since the input current is discontinuous in a buck converter, the current stress on the input capacitor is another concern when selecting the capacitor. For a buck circuit, the RMS value of input capacitor current can be calculated by: VO VO - 1 – -------- I CIN_RMS = I O -------V IN V IN if we let m equal the conversion ratio: VO -------- = m V IN The relationship between the input capacitor RMS current and voltage conversion ratio is calculated and shown in Figure 2. It can be seen that when VO is half of VIN, CIN is under the worst current stress. The worst current stress on CIN is 0.5 x IO. 0.5 0.4 ICIN_RMS(m) 0.3 IO 0.2 0.1 Power Good The output of Power-Good is an open drain N-channel MOSFET, which supplies an active high power good stage. A pull-up resistor should connect this pin to a DC power trail with maximum voltage no higher than 6V. The AOZ1025D monitors the FB voltage: when FB pin voltage is lower than 90% of the normal voltage, N-channel MOSFET turns on and the Power-Good pin is pulled low, which indicates the power is abnormal. Rev. 1.4 June 2012 www.aosmd.com 0 0 0.5 m 1 Figure 2. ICIN vs. Voltage Conversion Ratio Page 8 of 15 AOZ1025D For reliable operation and best performance, the input capacitors must have current rating higher than ICIN_RMS at worst operating conditions. Ceramic capacitors are preferred for input capacitors because of their low ESR and high current rating. Depending on the application circuits, other low ESR tantalum capacitor may also be used. When selecting ceramic capacitors, X5R or X7R type dielectric ceramic capacitors should be used for their better temperature and voltage characteristics. Note that the ripple current rating from capacitor manufactures are based on certain amount of life time. Further de-rating may be necessary in practical design. Inductor The inductor is used to supply constant current to output when it is driven by a switching voltage. For given input and output voltage, inductance and switching frequency together decide the inductor ripple current, which is: VO VO - I L = ----------- 1 – -------fL V IN The selected output capacitor must have a higher rated voltage specification than the maximum desired output voltage including ripple. De-rating needs to be considered for long term reliability. Output ripple voltage specification is another important factor for selecting the output capacitor. In a buck converter circuit, output ripple voltage is determined by inductor value, switching frequency, output capacitor value and ESR. It can be calculated by the equation below: 1 V O = I L ESR CO + ------------------------- 8fC O where, CO is output capacitor value, and ESRCO is the equivalent series resistance of the output capacitor. When low ESR ceramic capacitor is used as output capacitor, the impedance of the capacitor at the switching frequency dominates. Output ripple is mainly caused by capacitor value and inductor ripple current. The output ripple voltage calculation can be simplified to: The peak inductor current is: I L I Lpeak = I O + -------2 1 V O = I L ------------------------8fC O High inductance gives low inductor ripple current but requires larger size inductor to avoid saturation. Low ripple current reduces inductor core losses. It also reduces RMS current through inductor and switches, which results in less conduction loss. Usually, peak to peak ripple current on inductor is designed to be 20% to 40% of output current. When selecting the inductor, make sure it is able to handle the peak current without saturation even at the highest operating temperature. The inductor takes the highest current in a buck circuit. The conduction loss on inductor need to be checked for thermal and efficiency requirements. Surface mount inductors in different shape and styles are available from Coilcraft, Elytone and Murata. Shielded inductors are small and radiate less EMI noise. But they cost more than unshielded inductors. The choice depends on EMI requirement, price and size. Output Capacitor The output capacitor is selected based on the DC output voltage rating, output ripple voltage specification and ripple current rating. Rev. 1.4 June 2012 If the impedance of ESR at switching frequency dominates, the output ripple voltage is mainly decided by capacitor ESR and inductor ripple current. The output ripple voltage calculation can be further simplified to: V O = I L ESR CO For lower output ripple voltage across the entire operating temperature range, X5R or X7R dielectric type of ceramic, or other low ESR tantalum are recommended to be used as output capacitors. In a buck converter, output capacitor current is continuous. The RMS current of output capacitor is decided by the peak to peak inductor ripple current. It can be calculated by: I L I CO_RMS = ---------12 Usually, the ripple current rating of the output capacitor is a smaller issue because of the low current stress. When the buck inductor is selected to be very small and inductor ripple current is high, output capacitor could be overstressed. www.aosmd.com Page 9 of 15 AOZ1025D Loop Compensation The AOZ1025D employs peak current mode control for easy use and fast transient response. Peak current mode control eliminates the double pole effect of the output L&C filter. It greatly simplifies the compensation loop design. With peak current mode control, the buck power stage can be simplified to be a one-pole and one-zero system in frequency domain. The pole is dominant pole can be calculated by: 1 f P1 = ----------------------------------2 C O R L The zero is a ESR zero due to output capacitor and its ESR. It is can be calculated by: 1 f Z1 = -----------------------------------------------2 C O ESR CO To design the compensation circuit, a target crossover frequency fC for close loop must be selected. The system crossover frequency is where control loop has unity gain. The crossover is the also called the converter bandwidth. Generally a higher bandwidth means faster response to load transient. However, the bandwidth should not be too high because of system stability concern. When designing the compensation loop, converter stability under all line and load condition must be considered. Usually, it is recommended to set the bandwidth to be equal or less than 1/10 of switching frequency. The AOZ1025D operates at a fixed 500kHz switching frequency. It is recommended to choose a crossover frequency equal or less than 40kHz. f C = 40kHz The strategy for choosing RC and CC is to set the cross over frequency with RC and set the compensator zero with CC. Using selected crossover frequency, fC, to calculate RC: where; CO is the output filter capacitor, RL is load resistor value, and ESRCO is the equivalent series resistance of output capacitor. The compensation design is actually to shape the converter control loop transfer function to get desired gain and phase. Several different types of compensation network can be used for the AOZ1025D. For most cases, a series capacitor and resistor network connected to the COMP pin sets the pole-zero and is adequate for a stable high-bandwidth control loop. In the AOZ1025D, FB pin and COMP pin are the inverting input and the output of internal error amplifier. A series R and C compensation network connected to COMP provides one pole and one zero. The pole is: G EA f P2 = ------------------------------------------2 C C G VEA VO 2 C O R C = f C ---------- ----------------------------V G G FB EA CS where; fC is the desired crossover frequency. For best performance, fC is set to be about 1/10 of the switching frequency; VFB is 0.8V, GEA is the error amplifier transconductance, which is 200 x 10-6 A/V, and GCS is the current sense circuit transconductance, which is 10.8 A/V The compensation capacitor CC and resistor RC together make a zero. This zero is put somewhere close to the dominate pole fp1 but lower than 1/5 of selected crossover frequency. CC can is selected by: 1.5 C C = ----------------------------------2 R C f P1 where; GEA is the error amplifier transconductance, which is 200 x 10-6 A/V, GVEA is the error amplifier voltage gain, which is 500 V/V, and CC is the compensation capacitor. The previous equation can also be simplified to: CO RL C C = --------------------RC The zero given by the external compensation network, capacitor CC and resistor RC, is located at: 1 f Z2 = ----------------------------------2 C C R C Rev. 1.4 June 2012 www.aosmd.com Page 10 of 15 AOZ1025D Thermal Management and Layout Consideration Several layout tips are listed below for the best electric and thermal performance: In the AOZ1025 buck regulator circuit, the major power dissipating components are the AOZ1025 output inductor, and low-side NMOSFET. The total power dissipation of converter circuit can be measured by input power minus output power: 1. Do not use thermal relief connection to the VIN and the PGND pin. Pour a maximized copper area to the PGND pin and the VIN pin to help thermal dissipation. P total_loss = V IN I IN – V O I O The power dissipation of inductor can be approximately calculated by output current and DCR of inductor: P inductor_loss = IO2 R inductor 1.1 The power dissipation of low-side NMOSFET can be approximately calculated by output current, Rdson, and duty cycle (VO / VIN). VO P inductor_loss = IO2 R inductor 1 – --------- V IN The actual junction temperature can be calculated with power dissipation in the AOZ1025 and thermal impedance from junction to ambient. 2. Input capacitor should be connected to the VIN pin and the PGND pin as close as possible. 3. A ground plane is preferred. If a ground plane is not used, separate PGND from AGND and connect them only at one point to avoid the PGND pin noise coupling to the AGND pin. 4. Make the current trace from LX pins to L to Co to the PGND as short as possible. 5. Pour copper plane on all unused board area and connect it to stable DC nodes, like VIN, PGND or SGND. 6. Keep sensitive signal trace away from switching node, LX. The copper pour area connected to the LX pin should be as wide as possible to avoid the switching noise on the LX pin coupling to other part of circuit. T junction = P total_loss – P inductor_loss – P nmos_loss JA + T amb The thermal performance of the AOZ1025D is strongly affected by the PCB layout. Extra care should be taken by users during design to ensure that the IC will operate under the recommended environmental conditions. Figure 3. AOZ1025D (DFN 5x4) PCB Layout Rev. 1.4 June 2012 www.aosmd.com Page 11 of 15 AOZ1025D Package Dimensions, DFN-16 5x4 D A PIN#1 IDA D/2 B e 1 L E/2 aaa C E E2 2 INDEX AREA (D/2xE/2) D2 aaa C 5 TOP VIEW D3 BOTTOM VIEW ccc C A3 Seating C Plane A 4 ddd C 3 A1 b bbb CAB SIDE VIEW Dimensions in millimeters RECOMMENDED LAND PATTERN 0.25 0.3 0.5 0.6 1.75 3.5 0.15 2.3 0.25 1.9 2.0 UNIT: mm Symbols A A1 A3 b D D2 D3 E E2 e L R aaa bbb ccc ddd Min. 0.80 0.00 0.17 1.75 1.85 2.15 0.40 – – – – Nom. 0.90 0.02 0.20 REF 0.25 5.00 BSC 1.90 2.00 4.00 BSC 2.30 0.50 BSC 0.50 0.30 REF 0.15 0.10 0.10 0.08 Max. 1.00 0.05 0.35 2.00 2.10 2.40 0.60 – – – – Dimensions in inches Symbols A A1 A3 b D D2 D3 E E2 e L R aaa bbb ccc ddd Min. 0.031 0.000 Nom. Max. 0.035 0.039 0.001 0.002 0.008 REF 0.007 0.010 0.014 0.197 BSC 0.069 0.075 0.079 0.073 0.079 0.083 0.157 BSC 0.085 0.091 0.094 0.020 BSC 0.016 0.020 0.024 0.012 REF – 0.006 – – 0.004 – – 0.004 – – 0.003 – Notes: 1. All dimensions are in millimeters. 2. The location of the terminal #1 identifier and terminal numbering convention conforms to JEDEC publication 95 SP-002. 3. Dimension b applies to metallized terminal and is measured between 0.15mm and 0.30mm from the terminal tip. If the terminal has the optional radius on the other end of the terminal, the dimension b should not be measured in that radius area. 4. Coplanarity applies to the terminals and all other bottom surface metallization. 5. Drawing shown are for illustration only. Rev. 1.4 June 2012 www.aosmd.com Page 12 of 15 AOZ1025D Tape Dimensions, DFN-16 5x4 Tape R0 20 0. .40 T D1 E1 E2 D0 E B0 Feeding Direction K0 P0 A0 Unit: mm Package A0 B0 K0 D0 D1 E E1 E2 P0 P1 P2 T DFN 5x4 (12 mm) 5.30 ±0.10 4.30 ±0.10 1.20 ±0.10 1.50 Min. Typ. 1.50 +0.10 / –0 12.00 ±0.30 1.75 ±0.10 5.50 ±0.10 8.00 ±0.10 4.00 ±0.20 2.00 ±0.10 0.30 ±0.05 Leader/Trailer and Orientation Trailer Tape (300mm Min.) Rev. 1.4 June 2012 Components Tape Orientation in Pocket www.aosmd.com Leader Tape (500mm Min.) Page 13 of 15 AOZ1025D II R1 59 Reel Dimensions, DFN-16 5x4 I R1 6.0±1 21 M R1 I 27 Zoom In R6 R1 P R5 5 B W1 III Zoom In 3-1.8 0.05 II /4 ø1 .0 A A N=ø100±2 3- .9 ±0 " A ø2 3-ø1 3- /8" Zoom In ø9 6± 0.2 5 1.8 6.0 1.8 6.45±0.05 8.00 6.2 ø2 2.20 1. 8.9±0.1 14 REF 0.00 0 5.0 ø13.0 R1.10 R3.10 C 1.8 12 REF 11.90 ø86 .0±0 10° 41.5 REF 43.00 44.5±0.1 44.5±0.1 .95 R3 4.0 6.10 VIEW: C 3- " 16 ø3 / 3- 38° 40° 10.0 EF 46.0±0.1 R0.5 .1 3.3 6.50 R4 8R R1 2.00 ø9 20 ø17.0 A 0.00 -0.05 2.00 6.50 ø3 /1 8.0±0.1 0.80 3.00 2.5 1.80 +0.05 6" 8.000.00 10.71 6° Rev. 1.4 June 2012 www.aosmd.com Page 14 of 15 AOZ1025D Package Marking Z1025DI Part Number Code Underline Denotes Green Product FAYWLT Assembly Lot Code Fab & Assembly Location Year & Week Code This data sheet contains preliminary data; supplementary data may be published at a later date. Alpha & Omega Semiconductor reserves the right to make changes at any time without notice. LIFE SUPPORT POLICY ALPHA & OMEGA SEMICONDUCTOR PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS. As used herein: 1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body or (b) support or sustain life, and (c) whose failure to perform when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury of the user. Rev. 1.4 June 2012 2. A critical component in any component of a life support, device, or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness. www.aosmd.com Page 15 of 15