AOZ1231-01 28V/4A Synchronous EZBuckTM Regulator General Description Features The AOZ1231-01 is high-efficiency, easy-to-use DC/DC synchronous buck regulator that operates up to 28V. The device is capable of supplying 4A of continuous output current with an output voltage adjustable down to 0.8V (±1.0%). Wide input voltage range: The AOZ1231-01 integrates an internal linear regulator to generate 5.3V VCC from the input source. If the input voltage is lower than 5.3V, the linear regulator operates in low drop-output mode and the VCC voltage is equal to input voltage minus the drop-output voltage of the internal linear regulator. A proprietary constant on-time PWM control with input feed-forward results in ultra-fast transient response while maintaining relatively constant switching frequency over the entire input voltage range. The switching frequency can be externally set up to 1MHz. The devices feature multiple protection functions such as VCC under-voltage lockout, cycle-by-current limit, output over-voltage protection, short-circuit protection, and thermal shutdown. The AOZ1231-01 is available in a 5mm × 5mm QFN-30L package and is rated over a -40°C to +85°C ambient temperature range. – 4.5V to 28V (internal VCC) – 2.7V to 28V (external VCC) 4A continuous output current Output voltage adjustable to 0.8V (±1.0%) Low RDS(ON) internal NFETs – 40m high-side – 25m low-side Constant On-time with input feed-forward Programmable frequency up to 1MHz Internal 5.3V, 20mA linear regulator Ceramic capacitor stable Adjustable soft start Power Good output Over voltage protection Integrated bootstrap diode Cycle-by-cycle current limit Short-circuit protection Thermal shutdown Thermally enhanced 5mm × 5mm QFN-30L package Applications Portable computers Compact desktop PCs Servers Graphics cards Set top boxes LCD TVs Cable modems Point of load DC/DC converters Telecom/Networking/Datacom equipment Rev. 1.1 June 2012 www.aosmd.com Page 1 of 17 AOZ1231-01 Typical Application for VIN = 12V or above Input = 12V or above IN C2 22μF RTON TON AIN BST VCC C4 1μF R3 100kΩ AOZ1231-01 LX Power Good PGOOD C5 0.1μF Output 1.05V, 4A L1 2.2μH R1 FB Off On EN R2 C3 100μF AGND SS CSS PGND Analog Ground Power Ground Typical Application for VIN = 5V Input = 5V IN C2 22μF RTON TON AIN BST VCC R3 100kΩ C4 1μF AOZ1231-01 LX Power Good PGOOD C5 0.1μF Output 1.05V, 4A L1 2.2μH R1 FB Off On EN R2 SS C3 100μF AGND CSS PGND Analog Ground Power Ground Rev. 1.1 June 2012 www.aosmd.com Page 2 of 17 AOZ1231-01 Typical Application for High Light Load Efficiency Requirement or VIN = 3.3V Input IN C2 22μF RTON TON AIN BST 5V VCC R3 100kΩ C4 1μF AOZ1231-01 LX Power Good PGOOD C5 0.1μF Output 1.05V, 4A L1 2.2μH R1 FB Off On EN R2 PFM C3 100μF AGND SS CSS PGND Analog Ground Power Ground Ordering Information Part Number Ambient Temperature Range Package Environmental AOZ1231QI-01 -40°C to +85°C 30-Pin 5mm x 5mm QFN Green Product AOS Green Products use reduced levels of Halogens, and are also RoHS compliant. Please visit www.aosmd.com/media/AOSGreenPolicy.pdf for additional information. Rev. 1.1 June 2012 www.aosmd.com Page 3 of 17 AOZ1231-01 SS AGND VCC BST PGND LX LX LX Pin Configuration 30 29 28 27 26 25 24 23 PGOOD 1 22 LX EN 2 21 LX PFM 3 20 LX AGND 4 19 PGND FB 5 18 PGND 17 PGND 16 PGND 15 PGND 10 11 12 13 14 PGND 9 PGND IN 8 PGND 7 IN AIN IN IN 6 LX IN TON AGND 30-pin 5mm x 5mm QFN (Top View) Pin Description Pin Number Pin Name Pin Function 1 PGOOD Power Good Signal Output. PGOOD is an open-drain output used to indicate the status of the output voltage. It is internally pulled low when the output voltage is 10% lower than the nominal regulation voltage for 50µs (typical time) or 15% higher than the nominal regulation voltage. PGOOD is pulled low during soft-start and shut down. 2 EN 3 PFM 4, 29 AGND 5 FB 6 TON On-Time Setting Input. Connect a resistor between VIN and TON to set the on time. 7 AIN Supply Input for analog functions. 8, 9, 10, 11 IN 12, 13, 14, 15, 16, 17, 18, 19, 26 PGND Power Ground. 20, 21, 22, 23, 24, 25 LX Switching Node. 27 BST Bootstrap Capacitor Connection. The AOZ1231-01 includes an internal bootstrap diode. Connect an external capacitor between BST and LX as shown in the Typical Application diagrams. 28 VCC Output for internal linear regulator. Bypass VCC to AGND with a 1µF ceramic capacitor. Place the capacitor close to VCC pin. 30 SS Rev. 1.1 June 2012 Enable Input. The AOZ1231-01 is enabled when EN is pulled high. The device shuts down when EN is pulled low. PFM Selection Input. Connect PFM pin to VCC/VIN for forced PWM operation. Connect PFM pin to ground for PFM operation to improve light load efficiency. Analog Ground. Feedback Input. Adjust the output voltage with a resistive voltage-divider between the regulator’s output and AGND. Supply Input. IN is the regulator input. All IN pins must be connected together. Soft-Start Time Setting Pin. Connect a capacitor between SS and AGND to set the soft-start time. www.aosmd.com Page 4 of 17 AOZ1231-01 Absolute Maximum Ratings Maximum Operating Ratings Exceeding the Absolute Maximum Ratings may damage the device. Parameter The device is not guaranteed to operate beyond the Maximum Operating ratings. Rating IN, AIN, TON, PFM to AGND Parameter -0.3V to 30V LX to AGND -2V to 30V BST to AGND -0.3V to 36V SS, PGOOD, FB, EN to AGND -0.3V to 6V PGND to AGND -0.3V to +0.3V Junction Temperature (TJ) +150°C Storage Temperature (TS) -65°C to +150°C ESD Rating(1) 2kV Rating Supply Voltage (VIN) 4.5V to 28V Output Voltage Range 0.8V to 0.85*VIN Ambient Temperature (TA) -40°C to +85°C Package Thermal Resistance HS MOSFET 25°C/W LS MOSFET 20°C/W PWM Controller 50°C/W Note: 1. Devices are inherently ESD sensitive, handling precautions are required. Human body model rating: 1.5k in series with 100pF. 2. LX to PGND Transient (t<20ns) ------ -7V to VIN + 7V. Electrical Characteristics TA = 25°C, VIN = 12V, EN = 5V, unless otherwise specified. Specifications in BOLD indicate a temperature range of -40°C to +85°C. Symbol VIN VUVLO Iq Parameter Conditions IN Supply Voltage Min. Typ. 4.5 Under-Voltage Lockout Threshold of Vcc Vcc rising Vcc falling 3.2 4.0 3.7 Max Units 28 V 4.4 V Quiescent Supply Current of Vcc IOUT = 0, VFB = 1.0V, VEN > 2V 2 3 mA IOFF Shutdown Supply Current VEN = 0V 1 20 A VFB Feedback Voltage TA = 25°C TA = 0°C to 85°C 0.800 0.800 0.808 0.812 V IFB 0.792 0.788 Load Regulation 0.5 % Line Regulation 1 % FB Input Bias Current 200 nA Enable VEN EN Input Threshold VEN_HYS EN Input Hysteresis Off threshold On threshold 0.5 2.5 100 V mV PFM Control Input Threshold PFM Mode threshold Force PWM threshold 0.5 2.5 Input Hysteresis 100 V mV Modulator TON On Time RTON = 100k, VIN = 12V RTON = 100k, VIN = 24V 200 250 150 300 ns TON_MIN Minimum On Time 100 ns TOFF_MIN Minimum Off Time 250 ns Rev. 1.1 June 2012 www.aosmd.com Page 5 of 17 AOZ1231-01 Electrical Characteristics (Continued) TA = 25°C, VIN = 12V, EN = 5V, unless otherwise specified. Specifications in BOLD indicate a temperature range of -40°C to +85°C. Symbol Parameter Conditions Min. Typ. Max Units VSS = 0, CSS = 0.001F to 0.1F 7 10 15 A 0.5 V ±1 A 18 -8 % Soft-Start ISS_OUT SS Source Current Power Good Signal VPG_LOW PGOOD Low Voltage IOL = 1mA PGOOD Leakage Current VPGH VPGL TPG_L PGOOD Threshold FB rising FB falling 12 -12 15 -10 PGOOD Threshold Hysteresis 3 % PGOOD Fault Delay Time (FB falling) 50 s Under Voltage and Over Voltage Protection VPL Under Voltage threshold TPL Under Voltage Delay Time VPH Over Voltage Threshold FB rising Under Voltage Shutdown Blanking Time VIN = 12V, VEN = 0V, VCC = 5V 20 High-Side NFET On-Resistance VIN = 12V 40 High-Side NFET Leakage VEN = 0V, VLX = 0V TUV_LX FB falling -30 -25 -20 s 128 12 15 % 18 % mS Power Stage Output RDS(ON) RDS(ON) Low-Side NFET On-Resistance VLX = 12V Low-Side NFET Leakage VEN = 0V 25 60 m 10 A 30 m 10 A Over-current and Thermal Protection ILIM Valley Current Limit Thermal Shutdown Threshold Rev. 1.1 June 2012 VIN = 4.5V VIN = 28V TJ rising TJ falling www.aosmd.com 3 4 A 145 100 °C Page 6 of 17 AOZ1231-01 Functional Block Diagram BST AIN PGood IN LDO VCC EN UVLO TOFF_MIN Q Reference & Bias 0.8V Error Comp SS ISENCE (AC) FB PG Logic Timer S Q R LX FB Decode ILIM Comp ILIM_VALLEY Current Information Processing ISENSE OTP ISENSE ISENSE (AC) Vcc TON Q Timer PFM TON TON Generator Light Load Comp Light Load Threshold ISENSE PGND Rev. 1.1 June 2012 www.aosmd.com AGND Page 7 of 17 AOZ1231-01 Typical Performance Characteristics Circuit of Typical Application. TA = 25°C, VIN = 12V, VOUT = 1.05V, fs = 600kHz unless otherwise specified. Load Transient 0.8A (20%) to 3.2A (80%) Forced CCM Mode (Io = 0A) Vo ripple 100mV/div Vo ripple 50mV/div Io 1A/div VLX 5V/div 2μs/div 100μs/div Full Load (4A) Start-up Full Load Short Ven 5V/div VLX 5V/div Pgood 5V/div Vo 2V/div Pgood 5V/div Vo 1V/div lin 0.5A/div Ilx 2.5A/div 1ms/div Rev. 1.1 June 2012 100μs/div www.aosmd.com Page 8 of 17 AOZ1231-01 Detailed Description The AOZ1231-01 is a high-efficiency, easy-to-use, synchronous buck regulators optimized for notebook computers. The regulator is capable of supplying 4A of continuous output current with an output voltage adjustable down to 0.8V. The programmable operating frequency range of 100kHz to 1MHz enables optimizing the configuration for PCB area and efficiency. The input voltage range for the AOZ1231-01 is 4.5V to 28V. The constant on-time PWM with input feed-forward control scheme results in ultra-fast transient response while maintaining relatively constant switching frequency over the entire input range. The true AC current mode control scheme guarantees the regulator is stable with ceramic output capacitors. The switching frequency can be externally programmed up to 1MHz. Protection features include VCC under-voltage lockout, valley current limit, output over voltage protection, under voltage protection, short-circuit protection, and thermal shutdown. The AOZ1231-01 is available in a 30-pin 5mm × 5mm QFN package. Input Power Architecture The AOZ1231-01 integrates an internal linear regulator to generate 5.3V VCC from input. If the input voltage is lower than 5.3V, the linear regulator operates in low dropoutput mode where the VCC voltage is equal to the input voltage minus the drop-output voltage of the internal linear regulator. Enable and Soft Start The AOZ1231-01 has an external soft start feature to limit in-rush current and ensure the output voltage smoothly ramps up to regulation voltage. The soft start process begins when VCC rises to 4.1V and voltage on the EN pin is HIGH. An internal current source charges the external soft-start capacitor and the FB voltage follows the voltage of the soft-start pin (VSS) when it is lower than 0.8V. When VSS is higher than 0.8V, the FB voltage is regulated by the internal precise band-gap voltage (0.8V). The soft-start time can be calculated by with the following formula: TSS(s) = 330 x CSS(nF) If CSS is 1nF, the soft-start time will be 330µs. If CSS is 10nF, the soft-start time will be 3.3ms. Rev. 1.1 June 2012 Constant-On-Time PWM Control with Input Feed-Forward The control algorithm of the AOZ1231-01 is constant-on-time PWM Control with input feed-forward. The simplified control schematic is shown in Figure 1. IN PWM – Programmable One-Shot FB Voltage/ AC Current Information Comp + 0.8V Figure 1. Simplified Control Schematic of AOZ1231-01 The high-side switch on-time is determined solely by a one-shot with a pulse width that can be programmed by one external resistor and is inversely proportional to the input voltage (IN). The one-shot is triggered when the internal 0.8V is lower than the combined information of FB voltage and the AC current information of inductor, which is processed and obtained through the sensed lower-side MOSFET current once it turns-on. The added AC current information can help the stability of constant-on time control even with pure ceramic output capacitors, which have a very low ESR. The AC current information has no DC offset, which does not cause offset with output load change, which is fundamentally different from other V2 constant-on time control schemes. The constant-on-time PWM control architecture is a pseudo-fixed frequency with input voltage feed-forward. The internal circuit of the AOZ1231-01 sets the on-time of high-side switch inversely proportional to the IN voltage: – 12 26.3 10 R TON T ON = ---------------------------------------------------------------V IN V (1) To achieve the flux balance of inductor, the buck converter has the equation: V OUT F SW = --------------------------V IN T ON (2) Once the product of VIN x TON is constant, the switching frequency keeps constant and is independent with input voltage. www.aosmd.com Page 9 of 17 AOZ1231-01 An external resistor between the IN and TON pin sets the switching frequency according to the following equation: 12 V OUT 10 F SW = --------------------------------26.3 R TON (3) voltages. The current limit will keep the low-side MOSFET on and will not allow another high-side on-time, until the current in the low-side MOSFET reduces below the current limit. During the current limit, the inductor current is shown in Figure 2. A further simplified equation will be: 38000 V OUT V F SW kHz = ----------------------------------------------R TON k (4) Inductor Current If VOUT is 1.8V, RTON is 137k, the switching frequency will be 500kHz. This algorithm results in a nearly constant switching frequency despite the lack of a fixed-frequency clock generator. True Current Mode Control The constant-on-time control scheme is intrinsically unstable if the output capacitor’s ESR is not large enough to use as an effective current-sense resistor. Ceramic capacitors usually can not be used as an output capacitor. The AOZ1231-01 senses the low-side MOSFET current and processes it into DC current and AC current information using an Alpha & Omega proprietary technique. The AC current information is decoded and added on the FB pin on phase. With AC current information, the stability of the constant-on-time control is significantly improved even without the help of the output capacitor’s ESR. Thus a pure ceramic capacitor solution can be used. The pure ceramic capacitor solution can significantly reduce the output ripple (no ESR caused overshoot and undershoot) and uses less PCB board area. Valley Current-Limit Protection The AOZ1231-01 provides valley current-limit protection by using the RDS(ON) of the lower MOSFET current sensing. To detect real current information, a minimum constant off (250ns typical) is implemented after a constant-on time. If the current exceeds the valley current-limit threshold, the PWM controller is not allowed to initiate a new cycle. The actual peak current is greater than the valley current-limit threshold by an amount equal to the inductor ripple current. Therefore, the exact current-limit characteristic and maximum load capability are a function of the inductor value and input and output Rev. 1.1 June 2012 Ilim Time Figure 2. Inductor Current After 128s (typical), the AOZ1231-01 considers this as a true fail condition, turns off both high-side and low-side MOSFETs and latches off. Only triggering the enable can restart the AOZ1231-01. Output Voltage Under-voltage Protection If the output voltage is reduced 10% by over-current or short circuit, AOZ1231-01 will wait for 128s (typical), turns off both high-side and low-side MOSFETs and latches off. Only triggering the enable can restart the AOZ1231-01. Output Voltage Over-voltage Protection The threshold of OVP is set to 15% higher than 800mV. When the Vfb voltage exceeds the OVP threshold, the high-side MOSFET is turned off and the low-side MOSFETs is turned on until Vfb voltage is less than 800mV. Power Good Output The power good (PGOOD) output, which is an open drain output, requires the pull-up resistor. When the output voltage is 10% below the nominal regulation voltage for 50s (typical), PGOOD is pulled low. When the output voltage is 15% higher than the nominal regulation voltage, PGOOD is also pulled low. When combined with the under-voltage-protection circuit, this current-limit method is effective in almost every circumstance. In forced-PWM mode, the AOZ1231-01 also implements a negative current limit to prevent excessive reverse inductor currents when VOUT is sinking current. www.aosmd.com Page 10 of 17 AOZ1231-01 Application Information The basic AOZ1231-01 application circuits is shown in pages 2 and 3. Component selection is explained below. Input Capacitor The input capacitor must be connected to the IN pins and PGND pins of the AOZ1231-01 to maintain steady input voltage and filter out the pulsing input current. A small decoupling capacitor, usually 1F, should be connected to the VCC pin and AGND pins for stable operation of the AOZ1231-01. The voltage rating of the input capacitor must be greater than the maximum input voltage plus ripple voltage. The input ripple voltage can be approximated by equation below: Inductor The inductor is used to supply constant current to output when it is driven by a switching voltage. For a given input and output voltage, inductance and switching frequency together decide the inductor ripple current, which is: VO VO IO V IN = ----------------- 1 – --------- --------V IN V IN f C IN Since the input current is discontinuous in a buck converter, the current stress on the input capacitor is another concern when selecting the capacitor. For a buck circuit, the RMS value of the input capacitor current can be calculated by: VO VO I CIN_RMS = I O --------- 1 – --------- V IN V IN VO VO I L = ----------- 1 – --------- V IN fL The peak inductor current is: I L I Lpeak = I O + -------2 if let m equal the conversion ratio: VO -------- = m V IN The relationship between the input capacitor RMS current and voltage conversion ratio is calculated and shown in Figure 3. It can be seen that when VO is half of VIN, CIN is under the worst current stress. The worst current stress on CIN is 0.5 x IO. 0.5 High inductance provides low inductor ripple current but requires a larger size inductor to avoid saturation. Low ripple current reduces inductor core losses. It also reduces RMS current through the inductor and switches, which results in less conduction loss. Usually, peak to peak ripple current on inductor is designed to be 30% to 50% of output current. When selecting the inductor, make sure it is able to handle the peak current without saturation even at the highest operating temperature. The inductor takes the highest current in a buck circuit. The conduction loss on inductor needs to be checked for thermal and efficiency requirements. 0.4 Surface mount inductors in different shape and styles are available from Coilcraft, Elytone and Murata. Shielded inductors are small and radiate less EMI noise. They also cost more than unshielded inductors. The choice depends on EMI requirement, price and size. ICIN_RMS(m) 0.3 IO 0.2 0.1 0 For reliable operation and best performance, the input capacitors must have a current rating higher than ICIN_RMS at the worst operating conditions. Ceramic capacitors are preferred as input capacitors because of their low ESR and high ripple current rating. Depending on the application circuits, other low ESR tantalum capacitors or aluminum electrolytic capacitors may be used. When selecting ceramic capacitors, X5R or X7R type dielectric ceramic capacitors are preferred for their better temperature and voltage characteristics. Note that the ripple current rating from capacitor manufacturers is based on a certain life time. Further de-rating may be necessary for practical design requirements. 0 0.5 m 1 Figure 3. ICIN vs. Voltage Conversion Ratio Rev. 1.1 June 2012 www.aosmd.com Page 11 of 17 AOZ1231-01 Output Capacitor The output capacitor is selected based on the DC output voltage rating, output ripple voltage specification and ripple current rating. The selected output capacitor must have a higher rated voltage specification than the maximum desired output voltage including ripple. De-rating needs to be considered for long term reliability. Output ripple voltage specification is another important factor for selecting the output capacitor. In a buck converter circuit, output ripple voltage is determined by inductor value, switching frequency, output capacitor value and ESR. It is calculated by the equation below: 1 V O = I L ESR CO + ------------------------- 8fC O where, CO is output capacitor value and ESRCO is the Equivalent Series Resistor of the output capacitor. When a low ESR ceramic capacitor is used as the output capacitor, the impedance of the capacitor at the switching frequency dominates. Output ripple is mainly caused by capacitor value and inductor ripple current. The output ripple voltage calculation can be simplified to: 1 V O = I L ------------------------8 f CO If the impedance of the ESR at switching frequency dominates, the output ripple voltage is mainly decided by capacitor ESR and inductor ripple current. The output ripple voltage calculation can be further simplified to: V O = I L ESR CO For lower output ripple voltage across the entire operating temperature range, X5R or X7R dielectric type ceramic capacitors, or other low ESR tantalum are recommended to be used as output capacitors. In a buck converter, output capacitor current is continuous. The RMS current of output capacitor is decided by the peak-to-peak inductor ripple current. It can be calculated by: I L I CO_RMS = ---------12 Thermal Management and Layout Consideration In the AOZ1231-01 buck regulator circuit, high pulsing current flows through two circuit loops. The first loop starts from the input capacitors, to the IN pins, to the LX pins, to the filter inductor, to the output capacitor and load, and then returns to the input capacitor through ground. Current flows in the first loop when the high side switch is on. The second loop starts from the inductor, to the output capacitors and load, to the low side switch. Current flows in the second loop when the low side low side switch is on. In PCB layout, minimizing the board area of the two loops reduces the noise of the circuit and improves efficiency. A ground plane is strongly recommended to connect input capacitor, output capacitor, and PGND pins of the AOZ1231-01. In the AOZ1231-01 buck regulator circuit, the major power dissipating components are the AOZ1231-01 and the output inductor. The total power dissipation of the converter circuit can be measured by input power minus output power: P total_loss = V IN I IN – V O I O The power dissipation of the inductor can be approximately calculated by output current and DCR of inductor: P inductor_loss = IO2 R inductor 1.1 The actual junction temperature can be calculated with power dissipation in the AOZ1231-01 and thermal impedance from junction to ambient: T junction = P total_loss – P inductor_loss JA The maximum junction temperature of the AOZ1231-01 is 150ºC, which limits the maximum load current capability. The thermal performance of the AOZ1231-01 is strongly affected by the PCB layout. Extra care should be taken by users during design process to ensure that the IC will operate under the recommended environmental conditions. Usually, the ripple current rating of the output capacitor is a smaller issue because of the low current stress. When the buck inductor is selected to be very small and inductor ripple current is high, output capacitor could be overstressed. Rev. 1.1 June 2012 www.aosmd.com Page 12 of 17 AOZ1231-01 5. Decoupling capacitor CVCC should be connected as close as possible to VCC and AGND. Several layout tips are listed below for the best electric and thermal performance. 6. Voltage divider R1 and R2 should be placed as close as possible to FB and AGND. 1. The LX pins and pad are connected to internal low side switch drain. They are low resistance thermal conduction path and the most noisy switching node. Connect a large copper plane to the LX pins to help thermal dissipation. 7. Rton should be connected as close as possible to Pin 6 (TON pin). 8. Pin 26 (PGND) is connected to the ground plane through via. A ground plane is preferred. 2. The IN pins and pad are connected to the internal high side switch drain. They are also low resistance thermal conduction path. Connect a large copper plane to the IN pins to help thermal dissipation. 9. Keep sensitive signal traces such as the feedback trace away from the LX pins. 10. Pour copper plane on all unused board area and connect it to stable DC nodes, like VIN, GND or VOUT. 3. Do not use thermal relief connection to the PGND pins. Pour a maximized copper area to the PGND pins to help thermal dissipation. 4. Input capacitors should be connected as close as possible to the IN pins and the PGND pins to reduce the switching spikes. Vo R2 R1 Rton PFM EN PGOOD 3 2 1 AGND AGND 11 4 IN ND AGN D 10 5 IN FB 9 IN IN 6 7 8 TON AIN IN Cin 30 SS 29 AGND D 28 VCC 27 BST 26 Cvcc PGND Vcc GND Cb 25 LX 12 PGND 13 24 LX PGND 14 23 LX LX PGND 15 16 17 18 19 20 21 22 PGND PGND PGND PGND PGND LX LX LX Cout LX Vo Vo Rev. 1.1 June 2012 www.aosmd.com Page 13 of 17 AOZ1231-01 Package Dimensions, QFN 5x5, 30 Lead EP3_S D A D/2 22 B 15 23 2 14 INDEX AREA E/2 (D/2xE/2) A3/2 2x aaa C E e 30 8 1 7 2x aaa C A3 TOP VIEW A3/2 ccc C A3 C A SEATING PLANE A1 4 3 30 x b ddd C bbb M C A B SIDE VIEW PIN#1 DIA C0.35x45˚ D1 1 e e/2 L5 7 30 8 E1 E1 D2 L3 L1 L1 L4 L2 E2 2e e/2 L5 23 14 L 22 15 L5 D3/2 D3 L5 BOTTOM VIEW Notes: 1. All dimensions are in millimeters. 2. The location of the terminal #1 identifier and terminal numbering convention conforms to JEDEC publication 95 SPP-002. 3. Dimension b applies to metallized terminal and is measured between 0.20 mm and 0.35 mm from the terminal tip. If the terminal has the optional radius on the other end of the terminal, then dimension b should not be measured in that radius area. 4. Coplanarity applies to the terminals and all other bottom surface metalization. Rev. 1.1 June 2012 www.aosmd.com Page 14 of 17 AOZ1231-01 Package Dimensions, QFN 5x5, 30 Lead EP3_S (Continued) RECOMMENDED LAND PATTERN 3.66 0.27 0.27 1.83 15 22 0.30X45˚ 8 7 1 0.25 0.27 2.22 0.500 REF 1.07 2.37 2.37 UNIT: MM Dimensions in millimeters Min. A A1 A3 b D D1 0.80 0.00 0.20 D2 D3 0.97 3.56 2.12 E E1 E2 e L L1 L2 L3 L4 L5 aaa bbb ccc ddd Rev. 1.1 June 2012 Typ. 0.90 0.02 0.20 REF 0.25 5.00 BSC 2.22 1.07 3.66 0.30 0.336 — 0.29 0.66 0.17 1.394 1.896 0.50 BSC 0.40 0.436 0.066 0.39 0.76 0.27 0.15 0.10 0.10 0.08 Dimensions in inches Max. Symbols Min. 1.00 0.05 0.031 0.000 0.008 2.32 A A1 A3 b D D1 1.17 3.76 D2 D3 0.038 0.140 0.35 0.083 E 5.00 BSC 1.294 1.796 2.37 30 1.39 1.394 0.76 Symbols 0.25 0.75 0.066 1.896 0.436 0.39 2.37 14 23 0.27 0.55 0.25 1.494 1.996 0.50 0.536 0.166 0.49 0.86 0.37 E1 E2 e L L1 L2 L3 L4 L5 aaa bbb ccc ddd www.aosmd.com Typ. 0.035 0.001 0.008 REF 0.010 0.197 BSC 0.087 0.042 0.144 Max. 0.039 0.002 0.014 0.091 0.046 0.148 0.197 BSC 0.051 0.110 0.012 0.013 — 0.011 0.026 0.007 0.055 0.114 0.020 BSC 0.016 0.017 0.003 0.015 0.030 0.011 0.006 0.059 0.118 0.020 0.021 0.007 0.019 0.034 0.015 0.004 0.004 0.003 Page 15 of 17 AOZ1231-01 Tape and Reel Dimensions, QFN 5x5, 30 Lead EP3_S Carrier Tape P1 P2 D1 T E1 E2 E B0 K0 D0 P0 A0 Feeding Direction UNIT: mm Package A0 B0 K0 D0 QFN 5x5 (12mm) 5.25 ±0.10 5.25 ±0.10 1.10 ±0.10 1.50 Min. D1 1.50 +0.10/-0 E E1 E2 P0 P1 P2 T 12.00 ±0.3 1.75 ±0.10 5.50 ±0.05 8.00 ±0.10 4.00 ±0.10 2.00 ±0.05 0.30 ±0.05 Reel W1 S G N M K V R H W UNIT: mm Tape Size Reel Size 12mm ø330 M ø330.0 ±2.0 N ø79.0 ±1.0 W 12.4 +2.0/-0.0 W1 17.0 +2.6/-1.2 H ø13.0 ±0.5 K 10.5 ±0.2 S 2.0 ±0.5 G — R — V — Leader/Trailer and Orientation Trailer Tape 300mm min. or 75 Empty Pockets Rev. 1.1 June 2012 Components Tape Orientation in Pocket www.aosmd.com Leader Tape 500mm min. or 125 Empty Pockets Page 16 of 17 AOZ1231-01 Part Marking Z1231QI1 Part Number Code FAYWLT Assembly Lot Code Fab & Assembly Location Year & Week Code This datasheet contains preliminary data; supplementary data may be published at a later date. Alpha & Omega Semiconductor reserves the right to make changes at any time without notice. LIFE SUPPORT POLICY ALPHA & OMEGA SEMICONDUCTOR PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS. As used herein: 1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body or (b) support or sustain life, and (c) whose failure to perform when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury of the user. Rev. 1.1 June 2012 2. A critical component in any component of a life support, device, or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness. www.aosmd.com Page 17 of 17