AOSMD AOZ8804A

AOZ8804A
Ultra-Low Capacitance TVS Diode
General Description
Features
The AOZ8804A is a transient voltage suppressor array
designed to protect high speed data lines such as HDMI,
USB 3.0, MDDI, SATA, and Gigabit Ethernet from
damaging ESD events.
z ESD protection for high-speed data lines:
This device incorporates eight surge rated, low
capacitance steering diodes and a TVS in a single
package. During transient conditions, the steering diodes
direct the transient to either the positive side of the power
supply line or to ground.
The AOZ8804A provides a typical line to line capacitance
of 0.3pF and low insertion loss up to 6GHz providing
greater signal integrity making it ideally suited for HDMI
1.3 or USB 3.0 applications, such as Digital TVs,
DVD players, Computing, set-top boxes and MDDI
applications in mobile computing devices.
The AOZ8804A comes in a RoHS compliant and
Halogen Free 2.5mm x 1.0mm x 0.55mm DFN-10
package and is rated -40°C to +85°C junction
temperature range.
– IEC 61000-4-2, level 4 (ESD) immunity test
– Air discharge: ±15kV; contact discharge: ±15kV
– IEC61000-4-4 (EFT) 40A (5/50nS)
– IEC61000-4-5 (Lightning) 2.5A (8/20µS)
– Human Body Model (HBM) ±24kV
z Array of surge rated diodes with internal TVS diode
z Small package saves board space
z Protects four I/O lines
z Low capacitance between I/O lines: 0.3pF
z Low clamping voltage
z Low operating voltage: 5.0V
Applications
z HDMI, USB 3.0, MDDI, SATA ports
z Monitors and flat panel displays
z Set-top box
z Video graphics cards
z Digital Video Interface (DVI)
z Notebook computers
Typical Applications
AOZ8804A
AOZ8804A
AOZ8802A
D+
D-
D+
D-
TX2+
TX2-
RX2+
RX2-
TX1+
TX1-
SSRX+
SSRX-
SSRX+
SSRX-
TX0+
TX0-
RX1+
RX1HDMI
Receiver
RX0+
RX0-
SSTX+
SSTX-
SSTX+
SSTX-
CLK+
CLK-
CLK+
CLK-
USB 3.0
Transceiver
USB 3.0
Connector
HDMI
Transmitter
Connector
AOZ8804A
AOZ8804A
Figure 1. USB 3.0 Ports
Rev. 1.0 October 2010
Connector
AOZ8804A
Figure 2. HDMI Ports
www.aosmd.com
Page 1 of 11
AOZ8804A
Ordering Information
Part Number
Ambient Temperature Range
Package
Environmental
AOZ8804ADI
-40°C to +85°C
DFN-10
RoHS Compliant
Green Product
AOS Green Products use reduced levels of Halogens, and are also RoHS compliant.
Please visit www.aosmd.com/web/quality/rohs_compliant.jsp for additional information.
Pin Configuration
CH1
1
10 NC
CH2
2
9
NC
VN
3
8
VN
CH3
4
7
NC
CH4
5
6
NC
DFN-10
(Top View)
Absolute Maximum Ratings
Exceeding the Absolute Maximum ratings may damage the device.
Parameter
Rating
Storage Temperature (TS)
-65°C to +150°C
ESD Rating per IEC61000-4-2, contact
ESD Rating per IEC61000-4-2, air
(1)
±15kV
(1)
±15kV
ESD Rating per Human Body Model(2)
±24kV
Notes:
1. IEC 61000-4-2 discharge with CDischarge = 150pF, RDischarge = 330Ω.
2. Human Body Discharge per MIL-STD-883, Method 3015 CDischarge = 100pF, RDischarge = 1.5kΩ.
Maximum Operating Ratings
Parameter
Rating
Junction Temperature (TJ)
Rev. 1.0 October 2010
-40°C to +125°C
www.aosmd.com
Page 2 of 11
AOZ8804A
Electrical Characteristics
TA = 25°C unless otherwise specified. Specifications in BOLD indicate a temperature range of -40°C to +85°C.
Symbol
VRWM
VBR
Parameter
Reverse Working Voltage
Conditions
Between I/O and VN
Min.
(4)
Reverse Breakdown Voltage
IT = 1mA, between I/O and VN
IR
Reverse Leakage Current
VRWM = 5V, between I/O and VN
VF
Diode Forward Voltage
IF = 15mA
VCL
Cj
Typ.
Max.
Units
5.0
V
(3)
6.0
0.70
V
0.85
1
µA
1
V
12.0
-3.0
V
V
14.0
-5.0
V
V
16.5
-7.0
V
V
12.0
V
(5)
Channel Clamp Voltage
Positive Transients
Negative Transient
IPP = 1A, tp = 100ns, any I/O pin to Ground
Channel Clamp Voltage
Positive Transients
Negative Transient
IPP = 5A, tp = 100ns, any I/O pin to Ground(5)
Channel Clamp Voltage
Positive Transients
Negative Transient
IPP = 12A, tp = 100ns, any I/O pin to Ground(5)
Channel Clamp Voltage
Any I/O Pin to Ground
IPP = 1A, tp = 8/20µs
Channel Input Capacitance
VR = 0V, f = 1MHz, between I/O pins
0.30
0.35
pF
VR = 0V, f = 1MHz, any I/O pin to Ground
0.60
0.75
pF
Notes:
3. The working peak reverse voltage, VRWM, should be equal to or greater than the DC or continuous peak operating voltage level.
4. VBR is measured at the pulse test current IT.
5. Measurements performed using a 100ns Transmission Line Pulse (TLP) system.
Rev. 1.0 October 2010
www.aosmd.com
Page 3 of 11
AOZ8804A
Typical Performance Characteristics
Forward Voltage vs. Forward Peak Pulse Current
I/O – Gnd Insertion Loss (S21) vs. Frequency
(tperiod = 100ns, tr = 1ns)
8
0.00E+00
-5.00E+00
6
5
S21 (dB)
Forward Voltage (V)
7
4
3
-1.00E+01
-1.50E+01
-2.00E+01
2
-2.50E+01
1
-3.00E+01
0
0
2
4
6
8
10
Forward Current, IPP (A)
12
14
1
1000
10000
Analog Crosstalk (I/O–I/O) vs. Frequency
(tperiod = 100ns, tr = 1ns)
0
16
-20
Insertion Loss (dB)
Clamping Voltage, VCL (V)
100
Frequency (MHz)
Clamping Voltage vs. Peak Pulse Current
18
10
14
12
10
8
6
-40
-60
-80
-100
4
-120
2
0
2
4
6
8
10
Peak Puse Current, IPP (A)
Rev. 1.0 October 2010
12
14
1
10
100
1000
10000
Frequency (MHz)
www.aosmd.com
Page 4 of 11
AOZ8804A
TDR for HDMI 1.3
The AOZ8804A TDR test results indicates the minimal
effect the low capacitance has on the HDMI 1.3 TDR
measurements. Figure 3 and Figure 4 below are the
graphs from the TDR measurements. The two graphs
show the before and after results of the TDR differential
data line of the HDMI when the AOZ8804A was
populated onto the PCB. The use of "Skinny Traces" can
further limit the TDR to within 100Ω ± 5Ω. Below are the
TDR measurements with the use of skinny traces to
compensate the added capacitor from the AOZ8804.
Figure 3 shows the increase in impedance from the
skinny traces between M1 and M2 cursors. With the
increase in impedance the AOZ8804A added capacitor
will now reduce the TDR within the 100Ω ± 5Ω.
125
125
120
120
115
115
110
110
105
105
100
100
95
95
90
90
85
85
80
80
75
-0.2500 ns
(Step 2.56 ps)
0.2000 ns/
75
1.7500 ns
Figure 3. Compensated Stripe-Line
-0.2500 ns
(Step 2.56 ps)
0.2000 ns/
1.7500 ns
Figure 4. Compensated Stripe-Line with
AOZ8804A Device on the Board
Figure 5 shows the graphical representation of the scope
photo of the TDR and the PCB board. The cursor M1
represent the edge of the connector in which the
equipment was calibrated to. The cursor M2 represent
the leveling off of the100Ω when the signal passes
through the AOZ8804A..
Compensated Stripe-Line
M1
M1
Number of Layers
4
Copper Trace Thickness
1.4 mils
Dielectric Constant, εr
4.6
Overall Board Thickness
62 mils
Dielectric Thickness Between
Top and Ground Layer
10 mils
AOZ8804A
Figure 5. AOS HDMI Compensated Evaluation Board
Rev. 1.0 October 2010
www.aosmd.com
Page 5 of 11
AOZ8804A
High Speed PCB Layout Guidelines
Printed circuit board layout is the key to achieving the
highest level of surge immunity on power and data lines.
The location of the protection devices on the PCB is the
simplest and most important design rule to follow. The
AOZ8804A devices should be located as close as
possible to the noise source. The placement of the
AOZ8804A devices should be used on all data and
power lines that enter or exit the PCB at the I/O
connector. In most systems, surge pulses occur on data
and power lines that enter the PCB through the I/O
connector. Placing the AOZ8804A devices as close as
possible to the noise source ensures that a surge voltage
will be clamped before the pulse can be coupled into
adjacent PCB traces. In addition, the PCB should use the
shortest possible traces. A short trace length equates to
low impedance, which ensures that the surge energy will
be dissipated by the AOZ8804A device. Long signal
traces will act as antennas to receive energy from fields
that are produced by the ESD pulse. By keeping line
lengths as short as possible, the efficiency of the line to
act as an antenna for ESD related fields is reduced.
Minimize interconnecting line lengths by placing devices
with the most interconnect as close together as possible.
The protection circuits should shunt the surge voltage to
either the reference or chassis ground. Shunting the
surge voltage directly to the IC’s signal ground can cause
ground bounce. The clamping performance of TVS
diodes on a single ground PCB can be improved by
minimizing the impedance with relatively short and wide
ground traces. The PCB layout and IC package parasitic
inductances can cause significant overshoot to the TVS’s
clamping voltage. The inductance of the PCB can be
reduced by using short trace lengths and multiple layers
with separate ground and power planes. One effective
method to minimize loop problems is to incorporate a
ground plane in the PCB design.
The AOZ8804A ultra-low capacitance TVS is designed to
protect four high speed data transmission lines from
transient over-voltages by clamping them to a fixed
reference. The low inductance and construction
minimizes voltage overshoot during high current surges.
When the voltage on the protected line exceeds the
reference voltage the internal steering diodes are forward
biased, conducting the transient current away from the
sensitive circuitry. The AOZ8804A is designed for the
ease of PCB layout by allowing the traces to run
underneath the device. The pinout of the AOZ8804A is
designed to simply drop onto the IO lines of a High
Definition Multimedia Interface (HDMI) or USB 3.0 design
without having to divert the signal lines that may add
more parasitic inductance. Pins 1, 2, 4 and 5 are
connected to the internal TVS devices and pins 6, 7, 9
and 10 are no connects. The no connects was done so
the package can be securely soldered onto the PCB
surface.
Clock
Clock
SSRX+
SSRX+
Data0
Data0
SSRX–
SSRX–
Ground
Ground
Ground
Data1
Data1
SSTX+
SSTX+
Data2
Data2
SSTX–
SSTX–
Ground
Figure 6. Flow Through Layout for HDMI
Rev. 1.0 October 2010
Figure 7. Flow Through Layout for USB 3.0
www.aosmd.com
Page 6 of 11
AOZ8804A
High Speed PCB Layout Guidelines (Continued)
Based on the AOZ8804A DFN-10 package design a very
straight forward layout can be achieved. To give the TDR
an extra level of margin the traces may be compensated
to have a nominal impedance of 90Ω for USB or 100Ω
for HDMI throughout the differential pair. To make the
design perfect the added capacitance of the device will
have to be compensated by the use of “Skinny Traces”.
The skinny traces are a narrow stripe line acting to lower
the parasitic capacitance on the differential stripe line.
The differential impedance of the transmission line
becomes well centered to 90Ω or to 100Ω. A layout EM
field simulator is recommended before fabrication to
insure a perfect stripe line. With careful layout and
placement of the device, the AOZ8804A can protect the
USB 3.0 and HDMI data line effectively and safely and
meet the ESD immunity requirements of the
IEC61000-4-2, level 4, ±15kV air discharge, ±8kV contact
discharge.
Figure 8. USB 3.0 PCB Layout with Compensated Traces
Number of Layers
4
Copper Trace Thickness
1.4 mils
Dielectric Constant, εr
4.6
Overall Board Thickness
62 mils
Dielectric Thickness Between
Top and Ground Layer
10 mils
.
Rev. 1.0 October 2010
www.aosmd.com
Page 7 of 11
AOZ8804A
Figure 9. HDMI PCB Layout with Compensated Traces
Rev. 1.0 October 2010
Number of Layers
4
Copper Trace Thickness
1.4 mils
Dielectric Constant, εr
4.6
Overall Board Thickness
62 mils
Dielectric Thickness Between
Top and Ground Layer
10 mils
www.aosmd.com
Page 8 of 11
AOZ8804A
Package Dimensions, DFN-10 2.5mm x 1.0mm x 0.5mm
D
b1
b
e
E
Pin #1 Dot
by Marking
5
L
TOP VIEW
1
e
Pin #3 Identification R 0.130
BOTTOM VIEW
c
A
SIDE VIEW
A1
Dimensions in millimeters
RECOMMENDED LAND PATTERN
0.10
0.50
0.30
0.15
0.36
0.72
1.20 0.24
Min.
0.50
Nom.
0.55
Max.
0.60
Symbols
A
Min.
0.020
Nom.
0.022
Max.
0.024
A1
b
b1
0.00
0.15
—
0.20
0.40
0.05
0.25
A1
b
b1
0.000
0.006
—
0.008
0.016
0.002
0.010
0.152 Ref.
2.50
2.55
c
D
1.00
1.05
0.50 BSC
0.33
0.38
0.43
E
e
L
c
D
0.48
Dimensions in inches
Symbols
A
E
e
L
2.45
0.95
0.096
0.006 Ref.
0.098 0.100
0.037
0.039 0.041
0.020 BSC
0.013 0.015 0.017
0.20
0.40
Note:
1. Controlling dimension is millimeter. Converted inch dimensions are not necessarily exact.
Rev. 1.0 October 2010
www.aosmd.com
Page 9 of 11
AOZ8804A
Tape and Reel Dimensions, DFN-10 2.5mm x 1.0mm x 0.5mm
Carrier Tape
P2
P1
D0
D1
E1
K0
E2 E
B0
Ref 5°
P0
T
A0
A–A
Feeding Direction
UNIT: mm
Package
A0
B0
K0
DFN 2.5x1.0
1.12
±0.05
2.62
±0.05
0.70
±0.05
D0
D1
E
ø1.55 ø0.55
8.00
±0.05 ±0.05 +0.3/-0.1
Reel
E1
E2
P0
P1
P2
T
1.75
±0.1
3.50
±0.05
4.00
±0.10
4.0
±0.10
2.0
±0.05
0.25
±0.05
W1
S
M
K
N
G
R
H
W
UNIT: mm
Tape Size Reel Size
8mm
ø178
M
N
W
W1
H
S
K
E
R
ø178.0
±1.0
ø60.0
±0.5
11.80
±0.5
9.0
±0.5
ø13.0
+0.5 / –0.2
2.40
±0.10
10.25
±0.2
ø9.8
—
Leader / Trailer & Orientation
Trailer Tape
300mm Min.
Rev. 1.0 October 2010
Components Tape
Orientation in Pocket
www.aosmd.com
Leader Tape
500mm Min.
Page 10 of 11
AOZ8804A
Part Marking
AOZ8804ADI
(2.5 x 1.0 DFN)
DC12
Assembly Lot Code
Week and Year Code
Part Number Code
This datasheet contains preliminary data; supplementary data may be published at a later date.
Alpha & Omega Semiconductor reserves the right to make changes at any time without notice.
LIFE SUPPORT POLICY
ALPHA & OMEGA SEMICONDUCTOR PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL
COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS.
As used herein:
1. Life support devices or systems are devices or
systems which, (a) are intended for surgical implant into
the body or (b) support or sustain life, and (c) whose
failure to perform when properly used in accordance
with instructions for use provided in the labeling, can be
reasonably expected to result in a significant injury of
the user.
Rev. 1.0 October 2010
2. A critical component in any component of a life
support, device, or system whose failure to perform can
be reasonably expected to cause the failure of the life
support device or system, or to affect its safety or
effectiveness.
www.aosmd.com
Page 11 of 11