TPS2042, TPS2052 DUAL POWER-DISTRIBUTION SWITCHES SLVS173A – AUGUST 1998 – REVISED APRIL 1999 D D D D D D D D D D D D D 135-mΩ -Maximum (5-V Input) High-Side MOSFET Switch 500 mA Continuous Current per Channel Short-Circuit and Thermal Protection With Overcurrent Logic Output Operating Range . . . 2.7-V to 5.5-V Logic-Level Enable Input 2.5-ms Typical Rise Time Undervoltage Lockout 10 µA Maximum Standby Supply Current Bidirectional Switch Available in 8-pin SOIC and PDIP Packages Ambient Temperature Range, –40°C to 85°C 2-kV Human-Body-Model, 200-V Machine-Model ESD Protection UL Listed – File No. E169910 TPS2042 D OR P PACKAGE (TOP VIEW) GND IN EN1 EN2 1 8 2 7 3 6 4 5 OC1 OUT1 OUT2 OC2 TPS2052 D OR P PACKAGE (TOP VIEW) GND IN EN1 EN2 1 8 2 7 3 6 4 5 OC1 OUT1 OUT2 OC2 description The TPS2042 and TPS2052 dual power distribution switches are intended for applications where heavy capacitive loads and short circuits are likely to be encountered. The TPS2042 and the TPS2052 incorporate in single packages two 135-mΩ N-channel MOSFET high-side power switches for power distribution systems that require multiple power switches. Each switch is controlled by a logic enable that is compatible with 5-V logic and 3-V logic. Gate drive is provided by an internal charge pump designed to control the power-switch rise times and fall times to minimize current surges during switching. The charge pump requires no external components and allows operation from supplies as low as 2.7 V. When the output load exceeds the current-limit threshold or a short is present, the TPS2042 and TPS2052 limit the output current to a safe level by switching into a constant-current mode, pulling the overcurrent (OCx) logic output low. When continuous heavy overloads and short circuits increase the power dissipation in the switch causing the junction temperature to rise, a thermal protection circuit shuts off the switch to prevent damage. Recovery from a thermal shutdown is automatic once the device has cooled sufficiently. Internal circuitry ensures the switch remains off until valid input voltage is present. The TPS2042 and TPS2052 are designed to limit at 0.9-A load. These power distribution switches are available in 8-pin small-outline integrated circuit (SOIC) and 8-pin plastic dual-in-line packages (PDIP) and operate over an ambient temperature range of –40°C to 85°C. AVAILABLE OPTIONS TA ENABLE RECOMMENDED MAXIMUM CONTINUOUS LOAD CURRENT (A) TYPICAL SHORT-CIRCUIT SHORT CIRCUIT CURRENT LIMIT AT 25°C (A) –40°C to 85°C Active low 0.5 –40°C to 85°C Active high 0.5 PACKAGED DEVICES SOIC (D)† PDIP (P) 0.9 TPS2042D TPS2042P 0.9 TPS2052D TPS2052P † The D package is available taped and reeled. Add an R suffix to device type (e.g., TPS2042DR) Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. Copyright 1999, Texas Instruments Incorporated PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 1 TPS2042, TPS2052 DUAL POWER-DISTRIBUTION SWITCHES SLVS173A – AUGUST 1998 – REVISED APRIL 1999 TPS2042 functional block diagram OC1 Thermal Sense GND EN1 Current Limit Driver Charge Pump † CS OUT1 UVLO Power Switch † IN CS OUT2 Charge Pump Driver † Current sense Current Limit OC2 EN2 Thermal Sense Terminal Functions TERMINAL NO. NAME I/O D OR P DESCRIPTION TPS2042 TPS2052 EN1 3 – I Enable input. Logic low turns on power switch, IN-OUT1. EN2 4 – I Enable input. Logic low turns on power switch, IN-OUT2. EN1 – 3 I Enable input. Logic high turns on power switch, IN-OUT1. EN2 – 4 I Enable input. Logic high turns on power switch, IN-OUT2. GND 1 1 I Ground IN 2 2 I Input voltage OC1 8 8 O Over current. Logic output active low, for power switch, IN-OUT1 OC2 5 5 O Over current. Logic output active low, for power switch, IN-OUT2 OUT1 7 7 O Power-switch output OUT2 6 6 O Power-switch output 2 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 TPS2042, TPS2052 DUAL POWER-DISTRIBUTION SWITCHES SLVS173A – AUGUST 1998 – REVISED APRIL 1999 detailed description power switch The power switch is an N-channel MOSFET with a maximum on-state resistance of 135 mΩ (VI(IN) = 5 V). Configured as a high-side switch, the power switch prevents current flow from OUTx to IN and IN to OUTx when disabled. The power switch supplies a minimum of 500 mA per switch. charge pump An internal charge pump supplies power to the driver circuit and provides the necessary voltage to pull the gate of the MOSFET above the source. The charge pump operates from input voltages as low as 2.7 V and requires very little supply current. driver The driver controls the gate voltage of the power switch. To limit large current surges and reduce the associated electromagnetic interference (EMI) produced, the driver incorporates circuitry that controls the rise times and fall times of the output voltage. The rise and fall times are typically in the 2-ms to 4-ms range. enable (ENx or ENx) The logic enable disables the power switch and the bias for the charge pump, driver, and other circuitry to reduce the supply current to less than 10 µA when a logic high is present on ENx (TPS2042) or a logic low is present on ENx (TPS2052). A logic zero input on ENx or logic high on ENx restores bias to the drive and control circuits and turns the power on. The enable input is compatible with both TTL and CMOS logic levels. overcurrent (OCx) The OCx open-drain output is asserted (active low) when an overcurrent or overtemperature condition is encountered. The output will remain asserted until the overcurrent or overtemperature condition is removed. current sense A sense FET monitors the current supplied to the load. The sense FET measures current more efficiently than conventional resistance methods. When an overload or short circuit is encountered, the current-sense circuitry sends a control signal to the driver. The driver in turn reduces the gate voltage and drives the power FET into its saturation region, which switches the output into a constant current mode and holds the current constant while varying the voltage on the load. thermal sense The TPS2042 and TPS2052 implement a dual-threshold thermal trip to allow fully independent operation of the power distribution switches. In an overcurrent or short-circuit condition the junction temperature rises. When the die temperature rises to approximately 140°C, the internal thermal sense circuitry checks to determine which power switch is in an overcurrent condition and turns off that switch, thus isolating the fault without interrupting operation of the adjacent power switch. Hysteresis is built into the thermal sense, and after the device has cooled approximately 20 degrees, the switch turns back on. The switch continues to cycle off and on until the fault is removed. The (OCx) open-drain output is asserted (active low) when overtemperature or overcurrent occurs. undervoltage lockout A voltage sense circuit monitors the input voltage. When the input voltage is below approximately 2 V, a control signal turns off the power switch. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 3 TPS2042, TPS2052 DUAL POWER-DISTRIBUTION SWITCHES SLVS173A – AUGUST 1998 – REVISED APRIL 1999 absolute maximum ratings over operating free-air temperature range (unless otherwise noted)† Input voltage range, VI(IN) (see Note1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to 6 V Output voltage range, VO(OUTx) (see Note1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to VI(IN) + 0.3 V Input voltage range, VI(ENx) or VI(ENx) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to 6 V Continuous output current, IO(OUTx) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . internally limited Continuous total power dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Dissipation Rating Table Operating virtual junction temperature range, TJ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –40°C to 125°C Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –65°C to 150°C Lead temperature soldering 1,6 mm (1/16 inch) from case for 10 seconds . . . . . . . . . . . . . . . . . . . . . . . 260°C Electrostatic discharge (ESD) protection: Human body model MIL-STD-883C . . . . . . . . . . . . . . . . . . . . . 2 kV Machine model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0.2 kV † Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. NOTE 1: All voltages are with respect to GND. DISSIPATION RATING TABLE PACKAGE TA ≤ 25°C POWER RATING DERATING FACTOR ABOVE TA = 25°C TA = 70°C POWER RATING TA = 85°C POWER RATING D 725 mW 5.8 mW/°C 464 mW 377 mW P 1175 mW 9.4 mW/°C 752 mW 611 mW recommended operating conditions Input voltage, VI(IN) TPS2042 TPS2052 MIN MAX MIN MAX 2.7 5.5 2.7 5.5 UNIT V Input voltage, VI(ENx) or VI(ENx) 0 5.5 0 5.5 V Continuous output current, IO(OUTx) 0 500 0 500 mA –40 125 –40 125 °C Operating virtual junction temperature, TJ 4 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 TPS2042, TPS2052 DUAL POWER-DISTRIBUTION SWITCHES SLVS173A – AUGUST 1998 – REVISED APRIL 1999 electrical characteristics over recommended operating junction temperature range, VI(IN)= 5.5 V, IO = rated current, VI(ENx) = 0 V, VI(ENx) = Hi (unless otherwise noted) power switch TEST CONDITIONS† PARAMETER Static drain-source on-state resistance, 5-V operation rDS(on) DS( ) Static drain-source on-state resistance, 3.3-V operation tr Rise time time, output TPS2042 MIN TPS2052 TYP MAX MIN TYP MAX VI(IN) = 5 V, IO = 0.5 A TJ = 25°C, 80 95 80 95 VI(IN) = 5 V, IO = 0.5 A TJ = 85°C, 90 120 90 120 VI(IN) = 5 V, IO = 0.5 A TJ = 125°C, 100 135 100 135 VI(IN) = 3.3 V, IO = 0.5 A TJ = 25°C, 85 105 85 105 VI(IN) = 3.3 V, IO = 0.5 A TJ = 85°C, 100 135 100 135 VI(IN) = 3.3 V, IO = 0.5 A TJ = 125°C, 115 150 115 150 VI(IN) = 5.5 V, CL = 1 µF, TJ = 25°C, RL=10 Ω 2.5 2.5 VI(IN) = 2.7 V, CL = 1 µF, TJ = 25°C, RL=10 Ω 3 3 UNIT mΩ ms VI(IN) = 5.5 V, TJ = 25°C, 4.4 4.4 CL = 1 µF, RL=10 Ω tf Fall time, time output ms VI(IN) = 2.7 V, TJ = 25°C, 2.5 2.5 CL = 1 µF, RL=10 Ω † Pulse-testing techniques maintain junction temperature close to ambient temperature; thermal effects must be taken into account separately. enable input ENx or ENx PARAMETER VIH High-level input voltage VIL Low level input voltage Low-level II Input current ton toff Turnon time TEST CONDITIONS 2.7 V ≤ VI(IN) ≤ 5.5 V TPS2042 TPS2052 Turnoff time TPS2042 MIN TYP TPS2052 MAX 2 MIN TYP MAX 2 V 4.5 V ≤ VI(IN) ≤ 5.5 V 0.8 0.8 2.7 V≤ VI(IN) ≤ 4.5 V 0.4 0.4 VI(ENx) = 0 V or VI(ENx) = VI(IN) VI(ENx) = VI(IN) or VI(ENx) = 0 V –0.5 0.5 –0.5 CL = 100 µF, RL=10 Ω CL = 100 µF, RL=10 Ω UNIT 0.5 20 20 40 40 V µA ms current limit PARAMETER IOS Short-circuit output current TPS2042 TEST CONDITIONS† MIN VI(IN) = 5 V, OUT connected to GND, Device enable into short circuit TYP 0.7 0.9 TPS2052 MAX MIN 1.1 0.7 TYP 0.9 MAX 1.1 UNIT A † Pulse-testing techniques maintain junction temperature close to ambient temperature; thermal effects must be taken into account separately. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 5 TPS2042, TPS2052 DUAL POWER-DISTRIBUTION SWITCHES SLVS173A – AUGUST 1998 – REVISED APRIL 1999 electrical characteristics over recommended operating junction temperature range, VI(IN)= 5.5 V, IO = rated current, VI(ENx) = 0 V, VI(ENx) = Hi (unless otherwise noted) (continued) supply current PARAMETER Su ly Supply current,, low-level output t t TPS2042 TEST CONDITIONS No Load on OUT Su ly Supply current,, high-level output t t No Load on OUT MIN TJ = 25°C VI(ENx) = VI(IN) –40°C ≤ T ≤ 125°C J TPS2042 VI(EN I(ENx)) = 0 V TJ = 25°C –40°C ≤ TJ ≤ 125°C TPS2052 VI(ENx) = 0 V TJ = 25°C –40°C ≤ TJ ≤ 125°C TPS2052 Leakage g current OUT connected to ground VI(ENx) = VI(IN) –40°C ≤ TJ ≤ 125°C TPS2042 –40°C ≤ TJ ≤ 125°C TPS2052 Reverse leakage current IN = high g impedance VI(EN) = 0 V VI(ENx) = 0 V VI(EN) = Hi MIN TYP MAX 0.015 1 UNIT 1 10 µA 10 80 100 100 80 100 µA 100 100 µA 100 TPS2042 TJ = 25°C MAX 0.015 TPS2042 TJ = 25°C VI(EN I(ENx)) = VI(IN) –40°C ≤ TJ ≤ 125°C TYP TPS2052 0.3 µA TPS2052 0.3 undervoltage lockout PARAMETER TEST CONDITIONS Low-level input voltage Hysteresis TPS2042 MIN TYP 2 TJ = 25°C TPS2052 MAX MIN 2.5 2 100 TYP MAX 2.5 100 UNIT V mV overcurrent OCx PARAMETER Sink current† Output low voltage Off-state current† TEST CONDITIONS TPS2042 MIN VO = 5 V IO = 5 mA, VOL(OCx) VO = 5 V, VO = 3.3 V † Specified by design, not production tested. 6 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 TYP TPS2052 MAX MIN TYP MAX UNIT 10 10 mA 0.5 0.5 V 1 1 µA TPS2042, TPS2052 DUAL POWER-DISTRIBUTION SWITCHES SLVS173A – AUGUST 1998 – REVISED APRIL 1999 PARAMETER MEASUREMENT INFORMATION OUTx RL tf tr CL VO(OUTx) 90% 10% 90% 10% TEST CIRCUIT 50% VI(ENx) 50% toff ton 50% toff ton 90% VO(OUTx) 50% VI(ENx) 90% VO(OUTx) 10% 10% VOLTAGE WAVEFORMS Figure 1. Test Circuit and Voltage Waveforms VI(EN) (5 V/div) VI(EN) (5 V/div) VI(IN) = 5 V TA = 25°C CL = 0.1 µF VO(OUT) (2 V/div) 0 1 2 3 4 5 6 7 8 9 VI(IN) = 5 V TA = 25°C CL = 0.1 µF VO(OUT) (2 V/div) 10 0 1000 t – Time – ms 2000 3000 4000 5000 t – Time – ms Figure 2. Turnon Delay and Rise Time with 0.1-µF Load POST OFFICE BOX 655303 Figure 3. Turnoff Delay and Fall Time with 0.1-µF Load • DALLAS, TEXAS 75265 7 TPS2042, TPS2052 DUAL POWER-DISTRIBUTION SWITCHES SLVS173A – AUGUST 1998 – REVISED APRIL 1999 PARAMETER MEASUREMENT INFORMATION VI(EN) (5 V/div) VI(EN) (5 V/div) VI(IN) = 5 V TA = 25°C CL = 1 µF RL = 10 Ω VO(OUT) (2 V/div) 0 1 2 3 4 5 6 7 8 VI(IN) = 5 V TA = 25°C CL = 1 µF RL = 10 Ω VO(OUT) (2 V/div) 9 10 0 2 4 6 t – Time – ms 8 10 12 14 16 18 20 t – Time – ms Figure 4. Turnon Delay and Rise Time with 1-µF Load Figure 5. Turnoff Delay and Fall Time with 1-µF Load VI(IN) = 5 V TA = 25°C VI(IN) = 5 V TA = 25°C VI(EN) (5 V/div) VO(OUT) (2 V/div) IO(OUT) (0.5 A/div) IO(OUT) (0.2 A/div) 0 1 2 3 4 5 6 7 8 9 10 0 10 Figure 6. TPS2042, Short-Circuit Current, Device Enabled into Short 8 20 30 40 50 60 70 80 90 100 t – Time – ms t – Time – ms POST OFFICE BOX 655303 Figure 7. TPS2042, Threshold Trip Current with Ramped Load on Enabled Device • DALLAS, TEXAS 75265 TPS2042, TPS2052 DUAL POWER-DISTRIBUTION SWITCHES SLVS173A – AUGUST 1998 – REVISED APRIL 1999 PARAMETER MEASUREMENT INFORMATION VI(IN) = 5 V TA = 25°C RL = 10 Ω VI(EN) (5 V/div) VO(OC) (5 V/div) 470 µF 220 µF 100 µF VI(IN) = 5 V Load Ramp,1A/100 ms TA = 25°C IO(OUT) (0.5 A/div) IO(OUT) (o.2 A/div) 0 2 4 6 8 10 12 14 16 0 18 20 20 40 60 80 100 120 140 160 180 200 t – Time – ms t – Time – ms Figure 8. Inrush Current with 100-µF, 220-µF and 470-µF Load Capacitance Figure 9. Ramped Load on Enabled Device VI(IN) = 5 V TA = 25°C VI(IN) = 5 V TA = 25°C VO(OC) (5 V/div) VO(OC) (5 V/div) IO(OUT) (0.5 A/div) IO(OUT) (1 A/div) 0 400 800 1200 1600 2000 0 20 t – Time – µs 40 60 80 100 120 140 160 180 200 t – Time – µs Figure 10. 4-Ω Load Connected to Enabled Device POST OFFICE BOX 655303 Figure 11. 1-Ω Load Connected to Enabled Device • DALLAS, TEXAS 75265 9 TPS2042, TPS2052 DUAL POWER-DISTRIBUTION SWITCHES SLVS173A – AUGUST 1998 – REVISED APRIL 1999 TYPICAL CHARACTERISTICS TURNON DELAY vs INPUT VOLTAGE TURNOFF DELAY vs INPUT VOLTAGE 6 17 CL = 1 µF RL = 10 Ω TA = 25°C 5.5 16 CL = 1 µF RL = 10 Ω TA = 25°C Turn-Off Delay – ms Turn-On Delay – ms 15 5 4.5 4 14 13 12 11 3.5 3 2.5 10 3 3.5 4 4.5 5 5.5 3 2.5 6 3 VI – Input Voltage – V 5 3.5 4 4.5 VI – Input Voltage – V Figure 12 3.3 f t – Fall Time – ms r t – Rise Time – ms 0.9 3.5 VI(IN) = 5 V CL = 1 µF TA = 25°C 2.8 2.7 2.6 VI(IN) = 5 V TA = 25°C CL = 1 µF 3.1 2.9 2.7 0.2 0.3 0.4 0.5 0.6 0.7 IL – Load Current – A 0.8 0.9 2.5 0.1 0.2 Figure 14 10 0.8 FALL TIME vs LOAD CURRENT 3 2.5 0.1 6 Figure 13 RISE TIME vs LOAD CURRENT 2.9 5.5 0.3 0.4 0.5 0.6 0.7 IL – Load Current – A Figure 15 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 TPS2042, TPS2052 DUAL POWER-DISTRIBUTION SWITCHES SLVS173A – AUGUST 1998 – REVISED APRIL 1999 TYPICAL CHARACTERISTICS SUPPLY CURRENT, OUTPUT ENABLED vs JUNCTION TEMPERATURE SUPPLY CURRENT, OUTPUT DISABLED vs JUNCTION TEMPERATURE 1000 I I(IN) – Supply Current, Output Disabled – nA I I(IN) – Supply Current, Output Enabled – µ A 100 VI(IN) = 5.5 V VI(IN) = 5 V 90 VI(IN) = 4 V 80 VI(IN) = 2.7 V 70 VI(IN) = 3.3 V 60 50 –50 –25 75 100 125 0 25 50 TJ – Junction Temperature – °C 900 700 VI(IN) = 4 V 600 500 VI(IN) = 2.7 V 400 300 200 100 0 –100 –50 150 VI(IN) = 5.5 V VI(IN) = 5 V 800 –25 Figure 16 SUPPLY CURRENT, OUTPUT DISABLED vs INPUT VOLTAGE 100 1000 – Supply Current, Output Disabled – nA I I(IN) I I(IN) – Supply Current, Output Enabled – µ A 150 Figure 17 SUPPLY CURRENT, OUTPUT ENABLED vs INPUT VOLTAGE TJ = 125°C 90 TJ = 85°C 80 TJ = 25°C 70 TJ = 0°C TJ = –40°C 60 50 2.5 100 125 0 25 50 75 TJ – Junction Temperature – °C 3 3.5 4 4.5 5 5.5 6 TJ = 125°C 800 600 400 200 TJ = 85°C TJ = 25°C 0 TJ = –40°C –200 2.5 3 VI – Input Voltage – V Figure 18 5 3.5 4 4.5 VI – Input Voltage – V TJ = 0°C 5.5 6 Figure 19 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 11 TPS2042, TPS2052 DUAL POWER-DISTRIBUTION SWITCHES SLVS173A – AUGUST 1998 – REVISED APRIL 1999 STATIC DRAIN-SOURCE ON-STATE RESISTANCE vs JUNCTION TEMPERATURE 175 IO = 0.5 A VI(IN) = 2.7 V 150 VI(IN) = 3.3 V 125 100 VI(IN) = 4.5 V VI(IN) = 5 V 75 50 –50 –25 0 25 50 100 75 125 150 r DS(on) – Static Drain-Source On-State Resistance – mΩ r DS(on) – Static Drain-Source On-State Resistance – m Ω TYPICAL CHARACTERISTICS STATIC DRAIN-SOURCE ON-STATE RESISTANCE vs INPUT VOLTAGE 175 IO = 0.5 A 150 TJ = 125°C 125 TJ = 85°C 100 TJ = 25°C 75 TJ = 0°C TJ = –40°C 50 2.5 3 TJ – Junction Temperature – °C Figure 20 6 SHORT-CURCUIT OUTPUT CURRENT vs INPUT VOLTAGE 100 0.95 TA = 25°C I OS – Short-circuit Output Current – A VI(IN) – VI(OUTx) – Input-to-Output Voltage – mV 5.5 Figure 21 INPUT-TO-OUTPUT VOLTAGE vs LOAD CURRENT 75 VI(IN) = 2.7 V VI(IN) = 3.3 V 50 VI(IN) = 5 V 25 VI(IN) = 4.5 V 0 0.1 0.2 0.4 0.5 0.6 TJ = –40°C 0.9 TJ = 25°C TJ = 125°C 0.85 0.8 2.5 3 IL – Load Current – A Figure 22 12 3.5 4 4.5 5 VI – Input Voltage – V 4.5 5 3.5 4 VI – Input Voltage – V Figure 23 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 5.5 6 TPS2042, TPS2052 DUAL POWER-DISTRIBUTION SWITCHES SLVS173A – AUGUST 1998 – REVISED APRIL 1999 TYPICAL CHARACTERISTICS THRESHOLD TRIP CURRENT vs INPUT VOLTAGE SHORT CIRCUIT OUTPUT CURRENT vs JUNCTION TEMPERATURE 1.2 0.95 I OS – Short-circuit Output Current – A Threshold Trip Current – A TA = 25°C Load Ramp = 1 A/10 ms 1.175 1.15 1.125 1.1 2.5 3 4.5 5 3.5 4 VI – Input Voltage – V 5.5 VI(IN) = 5 V 0.9 VI(IN) = 4 V VI(IN) = 2.7 V 0.85 0.8 –50 6 –25 75 100 0 25 50 TJ – Junction Temperature – °C Figure 24 Figure 25 UNDERVOLTAGE LOCKOUT vs JUNCTION TEMPERATURE CURRENT-LIMIT RESPONSE vs PEAK CURRENT 2.5 500 VI(IN) = 5 V TA = 25°C 450 2.4 Current Limit Response – µ s UVLO – Undervoltage Lockout – V 125 Start Threshold 2.3 Stop Threshold 2.2 2.1 400 350 300 250 200 150 100 50 2 –50 0 –25 100 125 0 25 50 75 TJ – Junction Temperature – °C 150 0 2.5 5 7.5 10 12.5 Peak Current – A Figure 26 Figure 27 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 13 TPS2042, TPS2052 DUAL POWER-DISTRIBUTION SWITCHES SLVS173A – AUGUST 1998 – REVISED APRIL 1999 TYPICAL CHARACTERISTICS OVERCURRENT RESPONSE TIME (OCx) vs PEAK CURRENT 8 VI(IN) = 5 V TA = 25°C Response Time – µ s 6 4 2 0 0 2.5 5 7.5 10 12.5 Peak Current – A Figure 28 APPLICATION INFORMATION TPS2042 Power Supply 2.7 V to 5.5 V 2 IN 0.1 µF OUT1 8 3 5 4 7 Load 0.1 µF 22 µF 0.1 µF 22 µF OC1 EN1 6 Load OUT2 OC2 EN2 GND 1 Figure 29. Typical Application power-supply considerations A 0.01-µF to 0.1-µF ceramic bypass capacitor between INx and GND, close to the device, is recommended. Placing a high-value electrolytic capacitor on the output pin(s) is recommended when the output load is heavy. This precaution reduces power-supply transients that may cause ringing on the input. Additionally, bypassing the output with a 0.01-µF to 0.1-µF ceramic capacitor improves the immunity of the device to short-circuit transients. 14 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 TPS2042, TPS2052 DUAL POWER-DISTRIBUTION SWITCHES SLVS173A – AUGUST 1998 – REVISED APRIL 1999 APPLICATION INFORMATION overcurrent A sense FET checks for overcurrent conditions. Unlike current-sense resistors, sense FETs do not increase the series resistance of the current path. When an overcurrent condition is detected, the device maintains a constant output current and reduces the output voltage accordingly. Complete shutdown occurs only if the fault is present long enough to activate thermal limiting. Three possible overload conditions can occur. In the first condition, the output has been shorted before the device is enabled or before VI(IN) has been applied (see Figure 6). The TPS2042 and TPS2052 sense the short and immediately switch into a constant-current output. In the second condition, the short occurs while the device is enabled. At the instant the short occurs, very high currents may flow for a short time before the current-limit circuit can react. After the current-limit circuit has tripped (reached the overcurrent trip threshhold) the device switches into constant-current mode. In the third condition, the load has been gradually increased beyond the recommended operating current. The current is permitted to rise until the current-limit threshold is reached or until the thermal limit of the device is exceeded (see Figure 7). The TPS2042 and TPS2052 are capable of delivering current up to the current-limit threshold without damaging the device. Once the threshold has been reached, the device switches into its constant-current mode. OC response The OC open-drain output is asserted (active low) when an overcurrent or overtemperature condition is encountered. The output will remain asserted until the overcurrent or overtemperature condition is removed. Connecting a heavy capacitive load to an enabled device can cause momentary false overcurrent reporting from the inrush current flowing through the device, charging the downstream capacitor. An RC filter of 500 µs (see Figure 30) can be connected to the OC pin to reduce false overcurrent reporting. Using low-ESR electrolytic capacitors on the output lowers the inrush current flow through the device during hot-plug events by providing a low impedance energy source, thereby reducing erroneous overcurrent reporting. V+ V+ TPS2042 GND Rpullup TPS2042 Rpullup Rfilter OC1 GND OC1 IN OUT1 IN OUT1 EN1 OUT2 EN1 OUT2 EN2 OC2 EN2 OC2 To USB Controller Cfilter Figure 30. Typical Circuit for OC Pin and RC Filter for Damping Inrush OC Responses POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 15 TPS2042, TPS2052 DUAL POWER-DISTRIBUTION SWITCHES SLVS173A – AUGUST 1998 – REVISED APRIL 1999 APPLICATION INFORMATION power dissipation and junction temperature The low on-resistance on the n-channel MOSFET allows small surface-mount packages, such as SOIC, to pass large currents. The thermal resistances of these packages are high compared to that of power packages; it is good design practice to check power dissipation and junction temperature. The first step is to find rDS(on) at the input voltage and operating temperature. As an initial estimate, use the highest operating ambient temperature of interest and read rDS(on) from Figure 21. Next, calculate the power dissipation using: PD + rDS(on) I2 Finally, calculate the junction temperature: TJ Where: + PD R qJA ) TA TA = Ambient Temperature °C RθJA = Thermal resistance SOIC = 172°C/W, PDIP = 106°C/W Compare the calculated junction temperature with the initial estimate. If they do not agree within a few degrees, repeat the calculation, using the calculated value as the new estimate. Two or three iterations are generally sufficient to get a reasonable answer. thermal protection Thermal protection prevents damage to the IC when heavy-overload or short-circuit faults are present for extended periods of time. The faults force the TPS2042 and TPS2052 into constant current mode, which causes the voltage across the high-side switch to increase; under short-circuit conditions, the voltage across the switch is equal to the input voltage. The increased dissipation causes the junction temperature to rise to high levels. The protection circuit senses the junction temperature of the switch and shuts it off. Hysteresis is built into the thermal sense circuit, and after the device has cooled approximately 20 degrees, the switch turns back on. The switch continues to cycle in this manner until the load fault or input power is removed. The TPS2042 and TPS2052 implement a dual thermal trip to allow fully independent operation of the power distribution switches. In an overcurrent or short-circuit condition the junction temperature will rise. Once the die temperature rises to approximately 140°C, the internal thermal sense circuitry checks which power switch is in an overcurrent condition and turns that power switch off, thus isolating the fault without interrupting operation of the adjacent power switch. Should the die temperature exceed the first thermal trip point of 140°C and reach 160°C, both switches turn off. The OC open-drain output is asserted (active low) when overtemperature or overcurrent occurs. undervoltage lockout (UVLO) An undervoltage lockout ensures that the power switch is in the off state at power up. Whenever the input voltage falls below approximately 2 V, the power switch will be quickly turned off. This facilitates the design of hot-insertion systems where it is not possible to turn off the power switch before input power is removed. The UVLO will also keep the switch from being turned on until the power supply has reached at least 2 V, even if the switch is enabled. Upon reinsertion, the power switch will be turned on with a controlled rise time to reduce EMI and voltage overshoots. 16 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 TPS2042, TPS2052 DUAL POWER-DISTRIBUTION SWITCHES SLVS173A – AUGUST 1998 – REVISED APRIL 1999 APPLICATION INFORMATION universal serial bus (USB) applications The universal serial bus (USB) interface is a 12-Mb/s, or 1.5-Mb/s, multiplexed serial bus designed for low-to-medium bandwidth PC peripherals (e.g., keyboards, printers, scanners, and mice). The four-wire USB interface is conceived for dynamic attach-detach (hot plug-unplug) of peripherals. Two lines are provided for differential data, and two lines are provided for 5-V power distribution. USB data is a 3.3-V level signal, but power is distributed at 5 V to allow for voltage drops in cases where power is distributed through more than one hub across long cables. Each function must provide its own regulated 3.3 V from the 5-V input or its own internal power supply. The USB specification defines the following five classes of devices, each differentiated by power-consumption requirements: D D D D D Hosts/self-powered hubs (SPH) Bus-powered hubs (BPH) Low-power, bus-powered functions High-power, bus-powered functions Self-powered functions Self-powered and bus-powered hubs distribute data and power to downstream functions. The TPS2042 and TPS2052 can provide power-distribution solutions for many of these classes of devices. host/self-powered and bus-powered hubs Hosts and self-powered hubs have a local power supply that powers the embedded functions and the downstream ports (see Figure 31). This power supply must provide from 5.25 V to 4.75 V to the board side of the downstream connection under full-load and no-load conditions. Hosts and SPHs are required to have current-limit protection and must report overcurrent conditions to the USB controller. Typical SPHs are desktop PCs, monitors, printers, and stand-alone hubs. Power Supply 3.3 V Downstream USB Ports 5V TPS2042 2 IN 0.1 µF † OUT1 † D– 7 0.1 µF 8 3 USB Control D+ 5 4 68 µF VBUS GND OC1 EN1 D+ OC2 EN2 D– 6 OUT2 GND 0.1 µF 68 µF VBUS GND 1 † May need RC filter (see Figure 36) Figure 31. Typical Two-Port USB Host/Self-Powered Hub POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 17 TPS2042, TPS2052 DUAL POWER-DISTRIBUTION SWITCHES SLVS173A – AUGUST 1998 – REVISED APRIL 1999 APPLICATION INFORMATION host/self-powered and bus-powered hubs (continued) Bus-powered hubs obtain all power from upstream ports and often contain an embedded function. The hubs are required to power up with less than one unit load. The BPH usually has one embedded function, and power is always available to the controller of the hub. If the embedded function and hub require more than 100 mA on power up, the power to the embedded function may need to be kept off until enumeration is completed. This can be accomplished by removing power or by shutting off the clock to the embedded function. Power switching the embedded function is not necessary if the aggregate power draw for the function and controller is less than one unit load. The total current drawn by the bus-powered device is the sum of the current to the controller, the embedded function, and the downstream ports, and it is limited to 500 mA from an upstream port. low-power bus-powered functions and high-power bus-powered functions Both low-power and high-power bus-powered functions obtain all power from upstream ports; low-power functions always draw less than 100 mA, and high-power functions must draw less than 100 mA at power up and can draw up to 500 mA after enumeration. If the load of the function is more than the parallel combination of 44 Ω and 10 µF at power up, the device must implement inrush current limiting (see Figure 32). Power Supply D+ 3.3 V TPS2042 D– VBUS GND 2 10 µF 0.1 µF IN OUT1 7 0.1 µF 8 USB Control 3 5 4 OC1 EN1 OC2 6 EN2 OUT2 GND 0.1 µF 1 Figure 32. High-Power Bus-Powered Function 18 10 µF Internal Function POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 10 µF Internal Function TPS2042, TPS2052 DUAL POWER-DISTRIBUTION SWITCHES SLVS173A – AUGUST 1998 – REVISED APRIL 1999 APPLICATION INFORMATION USB power-distribution requirements USB can be implemented in several ways, and, regardless of the type of USB device being developed, several power-distribution features must be implemented. D D D Hosts/self-powered hubs must: – Current-limit downstream ports – Report overcurrent conditions on USB VBUS Bus-powered hubs must: – Enable/disable power to downstream ports – Power up at <100 mA – Limit inrush current (<44 Ω and 10 µF) Functions must: – Limit inrush currents – Power up at <100 mA The feature set of the TPS2042 and TPS2052 allows them to meet each of these requirements. The integrated current-limiting and overcurrent reporting is required by hosts and self-powered hubs. The logic-level enable and controlled rise times meet the need of both input and output ports on bus-power hubs, as well as the input ports for bus-power functions (see Figure 33). POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 19 TPS2042, TPS2052 DUAL POWER-DISTRIBUTION SWITCHES SLVS173A – AUGUST 1998 – REVISED APRIL 1999 APPLICATION INFORMATION TUSB2040 Hub Controller Upstream Port SN75240 BUSPWR A C B D GANGED D+ D– DP0 DP1 DM0 DM1 Tie to TPS2041 EN Input D+ A C B D GND OC 5V IN DM2 5 V Power Supply EN GND 5V 33 µF† DM3 A C B D 1 µF TPS76333 4.7 µF SN75240 D+ D– Ferrite Beads GND DP4 IN 3.3 V 4.7 µF VCC DM4 5V TPS2042 GND GND 48-MHz Crystal D– DP3 OUT 0.1 µF Ferrite Beads SN75240 DP2 TPS2041 Downstream Ports PWRON1 EN1 OUT1 OVRCUR1 OC1 OUT2 PWRON2 EN2 OVRCUR2 OC2 33 µF† D+ IN 0.1 µF XTAL1 D– Ferrite Beads GND TPS2042 Tuning Circuit XTAL2 OCSOFF PWRON3 EN1 OUT1 OVRCUR3 OC1 OUT2 PWRON4 EN2 OVRCUR4 OC2 5V 33 µF† IN D+ 0.1 µF GND Ferrite Beads D– GND 5V 33 µF† † USB rev 1.1 requires 120 µF per hub. Figure 33. Hybrid Self/Bus-Powered Hub Implementation 20 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 TPS2042, TPS2052 DUAL POWER-DISTRIBUTION SWITCHES SLVS173A – AUGUST 1998 – REVISED APRIL 1999 APPLICATION INFORMATION generic hot-plug applications (see Figure 34) In many applications it may be necessary to remove modules or pc boards while the main unit is still operating. These are considered hot-plug applications. Such implementations require the control of current surges seen by the main power supply and the card being inserted. The most effective way to control these surges is to limit and slowly ramp the current and voltage being applied to the card, similar to the way in which a power supply normally turns on. Due to the controlled rise times and fall times of the TPS2042 and TPS2052, these devices can be used to provide a softer start-up to devices being hot-plugged into a powered system. The UVLO feature of the TPS2042 and TPS2052 also ensures the switch will be off after the card has been removed, and the switch will be off during the next insertion. The UVLO feature guarantees a soft start with a controlled rise time for every insertion of the card or module. PC Board Power Supply TPS2042 OC1 GND IN OUT1 2.7 V to 5.5 V 1000 µF Optimum 0.1 µF EN1 OUT2 EN2 OC2 Block of Circuitry Block of Circuitry Overcurrent Response Figure 34. Typical Hot-Plug Implementation By placing the TPS2042 and TPS2052 between the VCC input and the rest of the circuitry, the input power will reach these devices first after insertion. The typical rise time of the switch is approximately 2.5 ms, providing a slow voltage ramp at the output of the device. This implementation controls system surge currents and provides a hot-plugging mechanism for any device. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 21 PACKAGE OPTION ADDENDUM www.ti.com 28-Aug-2010 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Drawing Pins Package Qty Eco Plan (2) Lead/ Ball Finish MSL Peak Temp (3) Samples (Requires Login) TPS2042D NRND SOIC D 8 75 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM Replaced by TPS2042BD TPS2042DG4 NRND SOIC D 8 75 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM Samples Not Available TPS2042DR NRND SOIC D 8 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM Replaced by TPS2042BDR TPS2042DRG4 NRND SOIC D 8 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM Samples Not Available TPS2042P NRND PDIP P 8 50 Pb-Free (RoHS) CU NIPDAU N / A for Pkg Type Samples Not Available TPS2042PE4 NRND PDIP P 8 50 Pb-Free (RoHS) CU NIPDAU N / A for Pkg Type TPS2052D NRND SOIC D 8 75 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM Replaced by TPS2052BD TPS2052DG4 NRND SOIC D 8 75 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM Samples Not Available TPS2052DR NRND SOIC D 8 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM Replaced by TPS2052BDR TPS2052DRG4 NRND SOIC D 8 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM Samples Not Available Samples Not Available (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) Addendum-Page 1 PACKAGE OPTION ADDENDUM www.ti.com (3) 28-Aug-2010 MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. 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Addendum-Page 2 PACKAGE MATERIALS INFORMATION www.ti.com 19-Mar-2008 TAPE AND REEL INFORMATION *All dimensions are nominal Device Package Package Pins Type Drawing SPQ Reel Reel Diameter Width (mm) W1 (mm) A0 (mm) B0 (mm) K0 (mm) P1 (mm) W Pin1 (mm) Quadrant TPS2042DR SOIC D 8 2500 330.0 12.4 6.4 5.2 2.1 8.0 12.0 Q1 TPS2052DR SOIC D 8 2500 330.0 12.4 6.4 5.2 2.1 8.0 12.0 Q1 Pack Materials-Page 1 PACKAGE MATERIALS INFORMATION www.ti.com 19-Mar-2008 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) TPS2042DR SOIC D 8 2500 340.5 338.1 20.6 TPS2052DR SOIC D 8 2500 340.5 338.1 20.6 Pack Materials-Page 2 IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, modifications, enhancements, improvements, and other changes to its products and services at any time and to discontinue any product or service without notice. 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