DS8906 AM/FM Digital Phase-Locked Loop Synthesizer General Description The DS8906 is a PLL synthesizer designed specifically for use in AM/FM radios. It contains the reference oscillator, a phase comparator, a charge pump, a 120 MHz ECL/I2L dual modulus programmable divider, and a 20-bit shift register/latch for serial data entry. The device is designed to operate with a serial data controller generating the necessary division codes for each frequency, and logic state information for radio function inputs/outputs. The Colpitts reference oscillator for the PLL operates at 4 MHz. A chain of dividers is used to generate a 500 kHz clock signal for the external controller. Additional dividers generate a 12.5 kHz reference signal for FM and a 500 Hz reference signal for AM/SW. One of these reference signals is selected by the data from the controller for use by the phase comparator. Additional dividers are used to generate a 50 Hz timing signal used by the controller for ‘‘time-ofday’’. Data is transferred between the frequency synthesizer and the controller via a 3 wire bus system. This consists of a data input line, an enable line and a clock line. When the enable line is low, data can be shifted from the controller into the frequency synthesizer. When the enable line is transitioned from low to high, data entry is disabled and data present in the shift register is latched. From the controller 22-bit data stream, the first 2 bits address the device permitting other devices to share the same bus. Of the remaining 20-bit data word, the next 14-bits are used for the PLL divide code. The remaining 6 bits are connected via latches to output pins. These 6 bits can be used to drive radio functions such as gain, mute, FM, AM, LW and SW only. These outputs are open collector. Bit 18 is used internally to select the AM or FM local oscillator input and to select between the 500 Hz and 12.5 kHz reference. A high level at bit 18 indicates FM and a low level indicates AM. The PLL consists of a 14-bit programmable I2L divider, an ECL phase comparator, an ECL dual modulus (p/p a 1) prescaler, and a high speed charge pump. The programmable divider divides by (N a 1), N being the number loaded into the shift register (bits 1–14 after address). It is clocked by the AM input via an ECL d 7/8 prescaler, or through a d 63/64 prescaler from the FM input. The AM input will work at frequencies up to 8 MHz, while the FM input works up to 120 MHz. The AM band is tuned with a frequency resolution of 500 Hz and the FM band is tuned with a resolution of 12.5 kHz. The buffered AM and FM inputs are self-biased and can be driven directly by the VCO thru a capacitor. The ECL phase comparator produces very accurate resolution of the phase difference between the input signal and the reference oscillator. The high speed charge pump consists of a switchable constant current source (b0.3 mA) and a switchable constant current sink ( a 0.3 mA). If the VCO frequency is low, the charge pump will source current, and sink current if the VCO frequency is high. A separate VCCM pin (typically drawing 1.5 mA) powers the oscillator and reference chain to provide controller clocking frequencies when the balance of the PLL is powered down. Features Y Y Y Y Y Y Y Uses inexpensive 4 MHz reference crystal FIN capability greater than 120 MHz allows direct synthesis at FM frequencies FM resolution of 12.5 kHz allows usage of 10.7 MHz ceramic filter distribution Serial data entry for simplified control 50 Hz output for ‘‘time-of-day’’ reference with separate low power supply (VCCM) 6-open collector buffered outputs for band switching and other radio functions Separate AM and FM inputs. AM input has 15 mV (typical) hysteresis Connection Diagram Dual-In-Line Package TL/F/5775 – 1 Top View Order Number DS8906N See NS Package Number N20A TRI-STATEÉ is a registered trademark of National Semiconductor Corp. C1995 National Semiconductor Corporation TL/F/5775 RRD-B30M105/Printed in U. S. A. DS8906 AM/FM Digital Phase-Locked Loop Synthesizer July 1986 Absolute Maximum Ratings (Note 1) b 65§ C to a 150§ C Storage Temperature Range Lead Temperature (Soldering, 4 seconds) 260§ C If Military/Aerospace specified devices are required, please contact the National Semiconductor Sales Office/Distributors for availability and specifications. Operating Conditions Supply Voltage (VCC1) (VCCM) Input Voltage Output Voltage 7V 7V 7V 7V Supply Voltage, VCC VCC1 VCCM Temperature, TA Min Max Units 4.75 4.5 0 5.25 6.0 70 V V §C DC Electrical Characteristics (Notes 2 and 3) Symbol Parameter Conditions Min VIH Logical ‘‘1’’ Input Voltage IIH Logical ‘‘1’’ Input Current VIL Logical ‘‘0’’ Input Voltage IIL Logical ‘‘0’’ Input Current Data, Clock and ENABLE INPUTS, VIN e 0V IOH Logical ‘‘1’’ Output Current All Bit Outputs, 50 Hz Output VOH e 5.25V 500 kHz Output VOL Logical ‘‘0’’ Output Voltage All Bit Outputs Typ Max Units 0 10 mA 0.7 V b5 b 25 mA 50 mA b 250 mA 0.5 V 2.1 VIN e VCC1 V VOH e 2.4V, VCCM e 4.5V IOL e 5 mA 50 Hz Output, 500 kHz Output IOL e 250 mA ICC1 Supply Current (VCC1) All Bit Outputs High 90 ICCM(STANDBY) VCCM Supply Current VCCM e 6.0V, All Other Pins Open IOUT 1.2VsVOUTsVCCMb1.2V VCCMs6.0V Charge Pump Output Current Pump Up Pump Down V 160 mA 1.5 4.0 mA b 0.10 b 0.30 b 0.6 mA 0.10 0.30 0.6 mA 0 g 100 nA 2.5 6.0 mA TRI-STATEÉ ICCM(OPERATE) VCCM Supply Current b 0.5 VCCM e 6.0V, VCC1 e 5.25V, All Other Pins Open AC Electrical Characteristics VCC e 5V, TA e 25§ C, tr s 10 ns, tf s 10 ns Symbol Parameter Conditions Min Typ Max Units 20 100 mV (rms) VIN(MIN)(F) FIN Minimum Signal Input AM and FM Inputs, 0§ C s TA s 70§ C VIN(MAX)(F) FIN Maximum Signal Input AM and FM Inputs, 0§ C s TA s 70§ C FOPERATE Operating Frequency Range (Sine Wave Input) VIN e 100 mV rms 0§ C s TA s 70§ C RIN (FM) AC Input Resistance, FM 120 MHz, VIN e 100 mV rms 300 X RIN (AM) AC Input Resistance, AM 2 MHz, VIN e 100 mV rms 1000 X CIN Input Capacitance, FM and AM VIN e 120 MHz 6 10 pF tEN1 Minimum ENABLE High Pulse Width 625 1250 ns tEN0 Minimum ENABLE Low Pulse Width 375 750 ns tCLKEN0 Minimum Time before ENABLE Goes Low that CLOCK must be Low b 50 0 ns Minimum Time after ENABLE Goes Low that CLOCK must Remain Low 275 550 ns Minimum Time before ENABLE Goes High that Last Positive CLOCK Edge May Occur 300 600 ns tEN0CLK tCLKEN1 2 AM FM 1000 1500 0.4 60 3 mV (rms) 8 120 MHz MHz AC Electrical Characteristics VCC e 5V, TA e 25§ C, tr s 10 ns, tf s 10 ns (Continued) Symbol Parameter tEN1CLK Typ Max Units Minimum Time After ENABLE Goes High Before an Unused Positive CLOCK Edge May Occur 175 350 ns tCLKH Minimum CLOCK High Pulse Width 275 550 ns tCLKL Minimum CLOCK Low Pulse Width 400 800 ns tDS Minimum DATA Setup Time, Minimum Time Before CLOCK that DATA Must be Valid 150 300 ns Minimum DATA Hold Time, Minimum Time After CLOCK that DATA Must Remain Valid 400 800 ns tDH Conditions Min Note 1: ‘‘Absolute Maximum Ratings’’ are those values beyond which the safety of the device cannot be guaranteed. Except for ‘‘Operating Temperature Range’’ they are not meant to imply that the devices should be operated at these limits. The table of ‘‘Electrical Characteristics’’ provides conditions for actual device operation. Note 2: Unless otherwise specified min/max limits apply across the 0§ C to a 70§ C temperature range for the DS8906. Note 3: All currents into device pins shown as positive, out of device pins as negative, all voltages referenced to ground unless otherwise noted. All values shown as max or min on absolute value basis. Schematic Diagrams (DS8906 AM/FM PLL Typical Input/Output Schematics) TL/F/5775 – 3 TL/F/5775 – 2 TL/F/5775 – 4 TL/F/5775 – 6 TL/F/5775 – 5 3 Schematic Diagrams (DS8906 AM/FM PLL Typical Input/Output Schematics) (Continued) TL/F/5775–7 TL/F/5775 – 8 Timing Diagrams* ENABLE vs CLOCK TL/F/5775 – 9 CLOCK vs DATA TL/F/5775 – 10 AM/FM Frequency Synthesizer (Scan Mode) *Timing diagrams are not drawn to scale. Scale within any one drawing may not be consistent, and intervals are defined positive as drawn. 4 TL/F/5775 – 11 Applications Information Note that until this time, the states of the internal data latches have remained unchanged. These data bits are interpreted as follows: DATA BIT POSITION DATA INTERPRETATION Last Bit 20 Output (Pin 2) 2nd to Last Bit 19 Output (Pin 1) 3rd to Last Bit 18 Output (FM/AM) (Pin 20) 4th to Last Bit 17 Output (Pin 19) 5th to Last Bit 16 Output (Pin 18) 6th to Last Bit 15 Output (Pin 17) 7th to Last MSB of N (213) 8th to Last (212) 9th to Last (211) 10th to Last (210) 11th to Last (29) 12th to Last (28) 13th to Last (27) dN 14th to Last (26) 15th to Last (25) 16th to Last (24) 17th to Last (23) 18th to Last (22) 19th to Last (21) 20th to Last LSB of N (20) SERIAL DATA ENTRY INTO THE DS8906 Serial information entry into the DS8906 is enabled by a low level on the ENABLE input. One binary bit is then accepted from the DATA input with each positive transition of the CLOCK input. The CLOCK input must be low for the specified time preceding and following the negative transition of the ENABLE input. The first 2 bits accepted following the negative transition of the ENABLE input are interpreted as address. If these address bits are not 1,1, no further information will be accepted from the DATA inputs, and the internal data latches will not be changed when ENABLE returns high. If these first 2 bits are 1,1, then all succeeding bits are accepted as data, and are shifted successively into the internal shift register as long as ENABLE remains low. Any data bits preceding the 20th to last bit will be shifted out, and are thus irrelevant. Data bits are counted as any bits following 2 valid (1,1) address bits with the ENABLE low. When the ENABLE input returns high, any further serial data input is inhibited. Upon this positive transition of the ENABLE, the data in the internal shift register is transferred into the internal data latches. - Note. The actual divide code is N a 1, i.e., the number loaded plus 1. 5 Typical Application Electronically Tuned Radio Controller System; Direct Drive LED TL/F/5775 – 12 6 Logic Diagram AM/FM PLL Synthesizer TL/F/5775 – 13 *Sections operating from VCCM supply **Address (1, 1) 7 DS8906 AM/FM Digital Phase-Locked Loop Synthesizer Physical Dimensions inches (millimeters) Molded Dual-In-Line Package (N) Order Number DS8906N NS Package Number N20A LIFE SUPPORT POLICY NATIONAL’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF NATIONAL SEMICONDUCTOR CORPORATION. As used herein: 1. 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