DM2502, DM2503, DM2504 Successive Approximation Registers General Description The DM2502, DM2503 and DM2504 are 8-bit and 12-bit TTL registers designed for use in successive approximation A/D converters. These devices contain all the logic and control circuits necessary in combination with a D/A converter to perform successive approximation analog-to-digital conversions. The DM2502 has 8 bits with serial capability and is not expandable. The DM2503 has 8 bits and is expandable without serial capability. The DM2504 has 12 bits with serial capability and expandability. All three devices are available in ceramic DIP, ceramic flatpak, and molded Epoxy-B DIPs. The DM2502, DM2503 and DM2504 operate over b55§ C to a 125§ C; the DM2502C, DM2503C and DM2504C operate over 0§ C to a 70§ C. Features Y Y Y Y Y Y Y Complete logic for successive approximation A/D converters 8-bit and 12-bit registers Capable of short cycle or expanded operation Continuous or start-stop operation Compatible with D/A converters using any logic code Active low or active high logic outputs Use as general purpose serial-to-parallel converter or ring counter Logic Diagram Connection Diagrams (Dual-In-Line and Flat Packages) DM2502, DM2503 DM2504 Order Number DM2502J, DM2502CJ, DM2503J or DM2503CJ See NS Package J16A Order Number DM2502CN or DM2503CN See NS Package N16A Order Number DM2502W, DM2502CW, DM2503W, or DM2503CW See NS Package W16A Order Number DM2504F or DM2504CJ See NS Package F24D Order Number DM2504J or DM2504CJ See NS Package J24A Order Number DM2504CN See NS Package N24A TL/F/5702 – 1 C1995 National Semiconductor Corporation TL/F/5702 RRD-B30M115/Printed in U. S. A. DM2502, DM2503, DM2504 Successive Approximation Registers November 1995 Absolute Maximum Ratings Operating Conditions (Note 1) Supply Voltage 7V Input Voltage Supply Voltage, VCC DM2502C, DM2503C, DM2504C 5.5V Output Voltage 5.5V b 65§ C to a 150§ C Storage Temperature Range Lead Temperature (Soldering, 10 seconds) 300§ C DM2502, DM2503, DM2504 Min Max Units 4.75 5.25 V 4.5 5.5 V 0 a 70 §C b 55 a 125 §C Temperature, TA DM2502C, DM2503C, DM2504C DM2502, DM2503 DM2504 Electrical Characteristics (Notes 2 and 3) VCC e 5.0V, TA e 25§ C, CL e 15 pF, unless otherwise specified. Parameter Conditions Logical ‘‘1’’ Input Voltage (VIH) VCC e Min Logical ‘‘1’’ Input Current (IIH) CP Input D, E, S Inputs All Inputs VCC e Max VIH e 2.4V VIH e 2.4V VIH e 5.5V Max VCC e Min VCC e Max VIL e 0.4V VIL e 0.4V Logical ‘‘1’’ Output Voltage (VOH) VCC e Min, IOH e 0.48 mA Output Short Circuit Current (Note 4) (IOS) VCC e Max; VOUT e 0.0V; Output High; CP, D, S, High; E Low Logical ‘‘0’’ Output Voltage (VOL) VCC e Min, IOL e 9.6 mA Supply Current (ICC) DM2502C DM2502 DM2503C DM2503 DM2504C DM2504 VCC e Max, All Outputs Low b 1.0 b 1.0 Propagation Delay to a Logical ‘‘0’’ From CP to Any Output (tpd0) 40 80 1.0 mA mA mA 0.8 V b 1.6 b 3.2 mA mA 2.4 3.6 b 10 b 20 b 45 mA 0.2 0.4 V 65 65 60 60 90 90 95 85 90 80 124 110 mA mA mA mA mA mA 18 28 ns 16 24 ns 26 38 ns 13 19 ns 10 CP High, S Low DM2503, DM2503C, DM2504, DM2504C Only Propagation Delay to a Logical ‘‘1’’ From CP to Any Output (tpd1) Units V 6 6 Logical ‘‘0’’ Input Current (IIL) CP, S Inputs D, E Inputs Propagation Delay to a Logical ‘‘1’’ From E to Q7 (Q11) Output (tpd1) Typ 2.0 Logical ‘‘0’’ Input Voltage (VIL) Propagation Delay to a Logical ‘‘0’’ From E to Q7 (Q11) Output (tpd0) Min 10 CP High, S Low DM2503, DM2503C, DM2504, DM2504C Only V Set-Up Time Data Input (ts(D)) b 10 4 8 ns Set-Up Time Start Input (ts(S) 0 9 16 ns Minimum Low CP Width (tPWL) 30 42 ns Minimum High CP Width (tPWH) 17 24 Maximum Clock Frequency (fMAX) 15 21 ns MHz Note 1: ‘‘Absolute Maximum Ratings’’ are those values beyond which the safety of the device cannot be guaranteed. Except for ‘‘Operating Temperature Range’’ they are not meant to imply that the devices should be operated at these limits. The table of ‘‘Electrical Characteristics’’ provides conditions for actual device operation. Note 2: Unless otherwise specified min/max limits apply across the b 55§ C to a 125§ C temperature range for the DM2502, DM2503 and DM2504, and across the 0§ C to a 70§ C range for the DM2502C, DM2503C and DM2504C. All typicals are given for VCC e 5.0V and TA e 25§ C. Note 3: All currents into device pins shown as positive, out of device pins as negative, all voltages referenced to ground unless otherwise noted. All values shown as max or min on absolute value basis. Note 4: Only one output at a time should be shorted. 2 Application Information OPERATION very slow dV/dt rates at the clock input (such as from relatively weak comparator outputs), improper logic operation will not result. The registers consist of a set of master latches that act as the control elements in the device and change state on the input clock high-to-low transition and a set of slave latches that hold the register data and change on the input clock low-to-high transition. Externally the device acts as a special purpose serial-to-parallel converter that accepts data at the D input of the register and sends the data to the appropriate slave latch to appear at the register output and the DO output on the DM2502 and DM2504 when the clock goes from low-to-high. There are no restrictions on the data input; it can change state at any time except during a short interval centered about the clock low-to-high transition. At the same time that data enters the register bit the next less significant bit register is set to a low ready for the next iteration. The register is reset by holding the S (Start) signal low during the clock low-to-high transition. The register synchronously resets to the state Q7 (11) low, and all the remaining register outputs high. The QCC (Conversion Complete) signal is also set high at this time. The S signal should not be brought back high until after the clock low-to-high transition in order to guarantee correct resetting. After the clock has gone high resetting the register, the S signal must be removed. On the next clock low-to-high transition the data on the D input is set into the Q7 (11) register bit and the Q6 (10) register bit is set to a low ready for the next clock cycle. On the next clock low-to-high transition data enters the Q6 (10) register bit and Q5 (9) is set to a low. This operation is repeated for each register bit in turn until the register has been filled. When the data goes into Q0, the QCC signal goes low, and the register is inhibited from further change until reset by a Start signal. The DM2502, DM2503 and DM2504 have a specially tailored two-phase clock generator to provide nonoverlapping two-phase clock pulses (i.e., the clock waveforms intersect below the thresholds of the gates they drive). Thus, even at LOGIC CODES All three registers can be operated with various logic codes. Two’s complement code is used by offsetting the comparator (/2 full range a (/2 LSB and using the complement of the MSB (Q7 or Q11) with a binary D/A converter. Offset binary is used in the same manner but with the MSB (Q7 or Q11). BCD D/A converters can be used with the addition of illegal code suppression logic. ACTIVE HIGH OR ACTIVE LOW LOGIC The register can be used with either D/A converters that require a low voltage level to turn on, or D/A converters that require a high voltage level to turn the switch on. If D/A converters are used which turn on with a low logic level, the resulting digital output from the register is active low. That is, a logic ‘‘1’’ is represented as a low voltage level. If D/A converters are used that turn on with a high logic level then the digital output is active high; a logic ‘‘1’’ is represented as a high voltage level. EXPANDED OPERATION An active low enable input, E, on the DM2503 and DM2504 allows registers to be connected together to form a longer register by connecting the clock, D, and S inputs in parallel and connecting the QCC output of one register to the E input of the next less significant register. When the start resets the register, the E signal goes high, forcing the Q7 (11) bit high and inhibiting the register from accepting data until the previous register is full and its QCC goes low. If only one register is used the E input should be held at a low logic level. Timing Diagram DM2502, DM2503 TL/F/5702 – 2 3 Application Information (Continued) Definition of Terms SHORT CYCLE If all bits are not required, the register may be truncated and conversion time saved by using a register output going low rather then the QCC signal to indicate the end of conversion. If the register is truncated and operated in the continuous conversion mode, a lock-up condition may occur on power turn-on. This condition can be avoided by making the start input the OR function of QCC and the appropriate register output. CP: The clock input of the register. D: The serial data input of the register. DO: The serial data out. (The D input delayed one bit). E: The register enable. This input is used to expand the length of the register and when high forces the Q7 (11) register output high and inhibits conversion. When not used for expansion the enable is held at a low logic level (ground). Qi i e 7 (11) to 0: The outputs of the register. QCC: The conversion complete output. This output remains high during a conversion and goes low when a conversion is complete. Q7 (11): The true output of the MSB of the register. Q7 (11): The complement output of the MSB of the register. COMPARATOR BIAS To minimize the digital error below g (/2 LSB, the comparator must be biased. If a D/A converter is used which requires a low voltage level to turn on, the comparator should be biased a (/2 LSB. If the D/A converter requires a high logic level to turn on, the comparator must be biased b(/2 LSB. S: The start input. If the start input is held low for at least a clock period the register will be reset to Q7 (11) low and all the remaining outputs high. A start pulse that is low for a shorter period of time can be used if it meets the set-up time requirements of the S input. Truth Table DM2502, DM2503 Time Outputs1 Inputs tn D S E2 D03 Q7 Q6 Q5 Q4 Q3 Q2 Q1 Q0 QCC 0 1 2 3 4 5 6 7 8 9 10 X D7 D6 D5 D4 D3 D2 D1 D0 X X L H H H H H H H H H X L L L L L L L L L L L X X D7 D6 D5 D4 D3 D2 D1 D0 X X L D7 D7 D7 D7 D7 D7 D7 D7 D7 X H L D6 D6 D6 D6 D6 D6 D6 D6 X H H L D5 D5 D5 D5 D5 D5 D5 X H H H L D4 D4 D4 D4 D4 D4 X H H H H L D3 D3 D3 D3 D3 X H H H H H L D2 D2 D2 D2 X H H H H H H L D1 D1 D1 X H H H H H H H L D0 D0 X H H H H H H H H L L X X H X H NC NC NC NC NC NC NC NC Note 1: Truth table for DM2504 is extended to include 12 outputs. H e High Voltage Level Note 2: Truth table for DM2502 does not include E column or last line in truth table shown. L e Low Voltage Level Note 3: Truth table for DM2503 does not include D0 column. X e Don’t Care NC e No Change Typical Applications BCD Illegal Code Suppression Active High Active Low TL/F/5702 – 3 4 Typical Applications (Continued) Fast Precision Analog-to-Digital Converter INPUT RANGES Unipolar 0 to 10 0 to 5 0 to 20 Switching Time Waveforms Bipolar g5 g 2.5 g 10 Equiv. Connect DAC ZOUT Input to A 2.36 kX Input to A 1.90 kX Input to B 3.08 kX B to DAC OUT TL/F/5702 – 4 TL/F/5702 – 5 5 Physical Dimensions inches (millimeters) Order Number DM2504F or DM2504CF NS Package Number F24D Order Number DM2502J, DM2502CJ, DM2503J or DM2503CJ NS Package Number J16A 6 Physical Dimensions inches (millimeters) (Continued) Order Number DM2504J or DM2504CJ NS Package Number J24A Order Number DM2502CM or DM2503CN NS Package Number N16A 7 DM2502, DM2503, DM2504 Successive Approximation Registers Physical Dimensions inches (millimeters) (Continued) Order Number DM2504CN NS Package Number N24A Order Number DM2502W, DM2502CW, DM2503W, or DM2503CW NS Package Number W16A LIFE SUPPORT POLICY NATIONAL’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF NATIONAL SEMICONDUCTOR CORPORATION. As used herein: 1. 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