EM47FM3288SBB
16Gb (64M×8Bank×32) Double DATA RATE 3 Stack SDRAM
Features
Description
• JEDEC Standard VDD/VDDQ = 1.5V±0.075V.
• All inputs and outputs are compatible with SSTL_15
interface.
• Fully differential clock inputs (CK, /CK) operation.
• Eight Banks
• Posted CAS by programmable additive latency
• Bust length: 4 with Burst Chop (BC) and 8.
• CAS Write Latency (CWL): 5,6,7,8
• CAS Latency (CL): 6,7,8,9,10,11
• Write Latency (WL) =Read Latency (RL) -1.
• Bi-directional Differential Data Strobe (DQS).
• Data inputs on DQS centers when write.
• Data outputs on DQS, /DQS edges when read.
• On chip DLL align DQ, DQS and /DQS transition
with CK transition.
• DM mask write data-in at the both rising and falling
edges of the data strobe.
• Sequential & Interleaved Burst type available both
for 8 & 4 with BC.
• Multi Purpose Register (MPR) for pre-defined
pattern read out
• On Die Termination (ODT) options: Synchronous
ODT, Dynamic ODT, and Asynchronous ODT
• Auto Refresh and Self Refresh
• 8,192 Refresh Cycles / 64ms
• Refresh Interval: 7.8us Tcase between 0°C ~ 85°C
• Refresh Interval: 3.9us Tcase between 85°C ~ 95°C
• RoHS Compliance
• Driver Strength:RZQ/7, RZQ/6 (RZQ=240Ω)
• High Temperature Self-Refresh rate enable
• ZQ calibration for DQ drive and ODT
• RESET pin for initialization and reset function
The EM47FM3288SBB is a high speed stack
Jul. 2012
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multi-chip package integrated 4Gbits x4 DDR3
SDRAM and fabricated with ultra high performance
CMOS process containing 16G bits which organized
as 64Mbits x 8 banks by 32 bits. This synchronous
device achieves high speed double-data-rate transfer
rates of up to 1600 Mb/sec/pin (DDR3-1600) for
general applications. The chip is designed to comply
with the following key DDR3 SDRAM features: (1)
posted CAS with additive latency, (2) write latency =
read latency -1, (3) On Die Termination (4)
programmable driver strength data,(5) seamless BL4
access. All of the control and address inputs are
synchronized with a pair of externally supplied
differential clocks. Inputs are latched at the cross
point of differential clocks (CK rising and /CK falling).
All I/Os are synchronized with a pair of bidirectional
differential data strobes (DQS and /DQS) in a source
synchronous fashion. The address bus is used to
convey row, column and bank address information in
a /RAS and /CAS multiplexing style. The 16Gb DDR3
devices operates with a single power supply: 1.5V ±
0.075V VDD and VDDQ. Available package with
RoHS compliance: FBGA-168Ball (14 x 12 x 1.4
mm3)
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EM47FM3288SBB
Ordering Information
Organization
Part No
Max. Freq
Package
Grade
EM47FM3288SBB-150
512M X 32
DDR3-1333H (9-9-9)
FBGA-168B
Commercial
EM47FM3288SBB-125
512M X 32
DDR3-1600K (11-11-11)
FBGA-168B
Commercial
Note: Speed ( t CK *) is in order of CL-t RCD -t RP
Parts Naming Rule
EM 47 FM 32 8 8 S B B - X E
Grade
EOREX Memory
: commercial temp.
DDR3 SDRAM
Density
FM: 512 Mega
EM: 256 Mega
DM: 128 Mega
CM: 64 Mega
BM: 32 Mega
Organization
Min Cycle Time (Max Freq.)
-150: 1.5ns, 667MHz (DDR3-1333)
-125: 1.25ns, 800MHz (DDR3-1600)
32: x32
16: x16
08: x8
Revision
A: 1st
Package
Refresh
B: BGA
8: 8K
Interface
Bank
8: 8Bank
S: 1.5V
* EOREX reserves the right to change products or specification without notice.
Jul. 2012
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EM47FM3288SBB
Ball Assignment: Top View
1
2
3
4
VDD
VSS
VSSQ
DQ1
VDDQ
DQ0
VSSQ
VDDQ
DQ2
VSSQ
5
6
7
8
9
10
11
12
A
DQ9
VSSQ
VSS
VDD
DQ3
B
DQ11
VSSQ
DQ8
VDDQ
VSSQ
DM0
C
DM1
VSSQ
DQ10
VDDQ
VDDQ
DQS0
/DQS0
D
/DQS1
DQS1
VDDQ
VSSQ
VSSQ
DQ4
VDDQ
DQ5
VSS
VSS
E
VSS
VSS
DQ13
VDDQ
DQ12
VSSQ
VSS
DQ6
VDDQ
DQ7
VSS
VSS
F
VSS
VSS
DQ15
VDDQ
DQ14
VSS
VDD
ZQ2
CAS
RAS
VSS
VSS
G
VSS
VSS
CK
CK
CKE
VDD
RESET
BA2
ODT
CS
VSS
VSS
H
VSS
VSS
A10
A14
A15
ZQ3
VREFDQ
VSS
ZQ0
WE
A1
ZQ1
VSS
VREFCA
BA0
A9
A2
A0
VSS
VSS
K
VSS
VSS
A4
A6
A12/ BC
BA1
VDD
A7
A5
A3
VSS
VSS
L
VSS
VSS
A8
A11
A13
VDD
VSS
DQ24
VDDQ
DQ25
VSS
VSS
M
VSS
VSS
DQ17
VDDQ
DQ16
VSS
VSSQ
DQ26
VDDQ
DQ27
VSS
VSS
N
VSS
VSS
DQ19
VDDQ
DQ18
VSSQ
VSSQ
VDDQ
DQS3
/DQS3
P
/DQS2
DQS2
VDDQ
VSSQ
VDDQ
DQ28
VSSQ
DM3
R
DM2
VSSQ
DQ20
VDDQ
VDDQ
DQ30
VSSQ
DQ29
T
DQ21
VSSQ
DQ22
VDDQ
VDD
VSS
VSSQ
DQ31
U
DQ23
VSSQ
VSS
VDD
J
168 Ball FBGA
Note: E5~E8, F5~F8, G5~G8, H5~H8, K5~K8, L5~L8, M5~M8, N5~N8 must be connected to ground.
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EM47FM3288SBB
Ball Description (Simplified)
Pin
Name
Function
(System Clock)
G9,G10
CK, CK
CK and CK are differential clock inputs. All address and control
input signals are sampled on the crossing of the positive edge of
CK and negative edge of CK . Output (read) data is referenced to
the crossings of CK and CK (both directions of crossing).
(Chip Select)
H4
All commands are masked when CS is registered HIGH.
CS
CS provides for external Rank selection on systems with
multiple Ranks. CS is considered part of the command code.
G11
CKE
(Clock Enable)
CKE high activates and CKE low deactivates internal clock
signals and device input buffers and output drivers. Taking CKE
low provides precharge power-down and self- refresh operation
(all banks idle), or active power-down (row active in any bank).
CKE is asynchronous for self refresh exit. After VREFCA has
become stable during the power on and initialization sequence, it
must be maintained during all operations (including self-refresh).
CKE must be maintained high throughout read and write
accesses. Input buffers, excluding CK, CK , ODT and CKE are
disabled during power-down. Input buffers, excluding CKE, are
disabled during self -refresh.
(Address)
K4,J9,K3,L4,
K9,L3,K10,L2,
A0~A9,A10/AP,
L9,K2,H9,L10,
A11,A12( BC ),
K11,L11,H10,
H11
A13, A14, A15
Provided the row address (RA0 – RA15) for active commands
and the column address (CA0-CA9) and auto precharge bit for
read/write commands to select one location out of the memory
array in the respective bank. A10 is sampled during a precharge
command to determine whether the precharge applies to one
bank (A10 LOW) or all banks (A10 HIGH). The address inputs
also provide the op-code during Mode Register Set commands.
A12 is sampled during read and write commands to determine if
burst chop (on-the-fly) will be performed. (HIGH: no burst chop,
LOW: burst chopped). See command truth table for details.
(Bank Address)
K1,K12,H2
H3
BA0, BA1,BA2
ODT
BA0 – BA2 define to which bank an active, read, write or
precharge command is being applied. Bank address also
determines if the mode register is to be accessed during a MRS
cycle.
(On Die Termination)
ODT (registered HIGH) enables termination resistance internal to
the DDR3 SDRAM. When enabled, ODT is applied to each DQ,
DQS, DQS , DMU and DML signal. The ODT pin will be ignored if
the Mode Register MR1 is programmed to disable ODT.
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EM47FM3288SBB
Ball Description (Continued)
D3,D10,P10,P3
D4,D9,P9,P4
G4,G3,J4
DQS0~3,
/DQS0~3
RAS , CAS
, WE
C4,C9,R9,R4
B2,A4,C2,B4,E2,E4,F
2,F4,B11,A9,C11,B9,
E11,E9,F11,F9,M11,
M9,N11,N9,R11,T9,T
11,U9,M2,M4,N2,N4,
R2,T4,T2,U4
A1,G1,L1,U1,A12,
G12,L12,U12,/F1,M1,
A2,J2,U2,A11,J11,
U11,F12,M12
B1,C1,R1,T1,D2,P2,
E3,F3,M3,N3,E10,F1
0,M10,N10,D11,P11,
B12,C12,R12,T12/D1
,E1,N1,P1,A3,B3,C3,
R3,T3,U3,
A10,B10,C10,R10,T1
0,U10,D12,E12,N12,
P12
J3,J10,G2,H12
DM0 ~MD3
(Data Strobe)
Output with read data, input with write data. Edge aligned with read
data, centered with write data. The data strobes DQS are paired
with differential signals /DQS, respectively, to provide differential
pair signaling to the system during both reads and writes. DDR3
SDRAM supports differential data strobe only and does not support
single-ended.
(Command Inputs)
RAS , CAS & WE (along with CS ) define the command being
entered.
(Input Data Mask)
DM is input mask signal for write data. Input data is masked when
DM are sampled HIGH coincident with that input data during a write
access. DM is sampled on both edges of DQS.
(Data Input/Output)
Data inputs and outputs are on the same pin.
DQ0~31
VDD/VSS
(Power Supply/Ground)
VDD and VSS are power supply for internal circuits.
(DQ Power Supply/DQ Ground)
VDDQ and VSSQ are power supply for the output buffers.
VDDQ/
VSSQ
ZQ0 ~ZQ3
(ZQ Calibration)
Reference pin for ZQ calibration
(Active Low Asynchronous Reset)
Reset is active when RESET is LOW, and inactive when RESET
H1
RESET
J1
VREFDQ
J12
VREFCA
is HIGH. RESET must be HIGH during normal operation.
RESET is a CMOS rail to rail signal with DC high and low at 80%
and 20% of VDD, i.e. 1.20V for DC high and 0.30V for DC low.
(Reference Voltage)
Reference voltage for DQ
(Reference Voltage)
Reference voltage for CA
Note: Input pins only BA0-BA2, A0-A13, RAS , CAS , WE , CS , CKE, ODT and RESET do not supply
termination.
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EM47FM3288SBB
Absolute Maximum Rating
Symbol
Item
Rating
Units
VIN, VOUT
Input, Output Voltage
-0.4 ~ +1.975
V
VDD
Power Supply Voltage
-0.4 ~ +1.975
V
VDDQ
Power Supply Voltage
-0.4 ~ +1.975
V
TOP
Operating Temperature Range
TSTG
Storage Temperature Range
-55 ~ +100
°C
V REFCA
Reference Voltage for Control
-0.4 ~ 0.6*VDD
V
V REFDQ
Reference Voltage for DQ
-0.4 ~ 0.6*VDDQ
V
Commercial
0 ~ +70
°C
Note: Caution Exposing the device to stress above those listed in Absolute Maximum Ratings
could cause permanent damage. The device is not meant to be operated under conditions
outside the limits described in the operational section of this specification.
Recommended DC Operating Conditions
Symbol
Parameter
Min.
Typ.
Max.
Units
VDD
Power Supply Voltage
1.425
1.5
1.575
V
VDDQ
Power Supply for I/O Voltage
1.425
1.5
1.575
V
Single-Ended AC and DC Input Levels for Command and Address
Symbol
Parameter
Min.
Max.
Units
VIHCA (DC100)
DC input logic high
VREF+0.100
VDD
V
VILCA (DC100)
DC input logic low
VSS
VREF-0.100
V
VIHCA (AC175)
AC input logic high
VREF+0.175
-
V
VILCA (AC175)
AC input logic low
-
VREF-0.175
V
VIHCA (AC150)
AC input logic high
VREF+0.150
-
V
VILCA (AC150)
AC input logic low
-
VREF-0.150
V
0.49*VDD
0.51*VDD
V
Min.
Max.
Units
VREFCA (DC)
Reference voltage for ADD, CMD
Single-Ended AC and DC Input Levels for DQ and DM
Symbol
Parameter
VIHDQ (DC100)
DC input logic high
VREF+0.100
VDD
V
VILDQ (DC100)
DC input logic low
VSS
VREF-0.100
V
VIHDQ (AC175)
AC input logic high
VREF+0.150
-
V
VILDQ (AC175)
AC input logic low
-
VREF-0.150
V
VIHDQ (AC150)
AC input logic high
VREF+0.150
-
V
VILDQ (AC150)
AC input logic low
-
VREF-0.150
V
VREFDQ (DC)
Reference voltage for DQ, DM
0.49*VDD
0.51*VDD
V
Note1. For input pins except /RESET: VREF= VREFCA (DC) or VREF= VREFDQ (DC).
Note2. The AC peak noise on VREF may not allow VREF to deviate from VREFCA (DC) or VREF= VREFDQ (DC)
by more than ±1% VDD (for reference: approx. ±15mV.
Note3. For reference voltage = VDD/2 ±15mV.
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EM47FM3288SBB
Pin Capacitance
Symbol
Parameters
Pins
Min.
Max.
Unit
Notes
CCK
Input pin capacitance, CK, /CK
CK, /CK
0.8
1.4
pF
1,3
CDCK
Delta input pin capacitance, CK,
/CK
0
0.15
pF
1,2
CIN_CTRL
Input pin capacitance, control pins
0.75
1.3
pF
1
CDIN_CTRL
Delta input pin capacitance,
control pins
-0.4
0.2
pF
1,4
CIN_ADD_CMD
Input pin capacitance, address
and command pins
0.75
1.3
pF
1
CDIN_ADD_CMD
Delta input pin capacitance,
address and command pins
-0.4
0.4
pF
1,5
CIO
Input/output pins capacitance
1.5
2.5
pF
1,6
CDIO
Delta input/output pins
capacitance
DQ,DQSU,/DQSU
DQSL,/DQSL,
DMU, DML
-0.5
0.3
pF
1,7,8
CDDQS
Delta input/output pins
capacitance
DQS, /DQS
0
0.15
pF
1,10
CZQ
Input/output pin capacitance, ZQ
ZQ
-
3
pF
1,9
/CS,CKE,ODT
/RAS,/CAS,/WE,
Address
Notes1. VDD, VDDQ, VSS, VSSQ applied and all other pins (except the pin under test) floating.
VDD = VDDQ =1.5V, VBIAS=VDD/2.
Notes2. Absolute value of CCK(CK-pin) - CCK(/CK-pin).
Notes3. CCK (min.) will be equal to CIN (min.)
Notes4. CDIN_CTRL = CIN_CTRL - 0.5*(CCK(CK-pin) + CCK(/CK-pin))
Notes5. CDIN_ADD_CMD = CIN_ADD_CMD - 0.5*(CCK(CK-pin) + CCK(/CK-pin))
Notes6. Although the DMU and DML pins have different functions, the loading matches DQ and DQS.
Notes7. DQ should be in high impedance state.
Notes8. CDIO = CIO (DQ, DM) - 0.5*(CIO(DQS-pin) + CIO(/DQS-pin)).
Notes9. Maximum external load capacitance on ZQ pin is 5pF.
Notes10. Absolute value of CIO(DQS) - CIO(/DQS).
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EM47FM3288SBB
AC and DC Logic Input Levels for Differential Signals
Differential signals definition
Differential AC and DC Input Levels
Parameter
Min.
Max.
Units
Note
VIHdiff
Differential input high
+0.2
See Note3
V
1
VILdiff
Differential input low
See Note3
-0.2
V
1
Symbol
VIHdiff (AC)
AC Differential input high
2x(VIH(AC)-VREF)
See Note3
V
2
VILdiff (AC)
AC Differential input low
See Note3
2x(VIL(AC)-VREF)
V
2
Note1. It is used to define a differential signal slew-rate.
Note2. For CK - /CK use VIH/VIL(AC) of address/command and VREFCA; for strobes (DQS, DQS) use VIH/VIL(AC) of
DQs and VREFDQ; if a reduced ac-high or ac-low level is used for a signal group, then the reduced level applies
also here.
Note3. These values are not defined, however they single-ended signals CK, /CK, DQS, /DQS need to be
within the respective limits (VIH(DC) max, VIL(DC)min) for single-ended signals.
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EM47FM3288SBB
Differential swing requirements for clock (CK - /CK) and strobe (DQS - /DQS)
- Allowed time before ringback (tDVAC) for CK - /CK and DQS - /DQS
Slew Rate [V/ns]
tDVAC [ps] @ |VIH/Ldiff(ac)| = 350mV
tDVAC [ps] @ |VIH/Ldiff(ac)| = 300mV
-
Min
Max
Min
Max
>4.0
75
-
175
-
4.0
57
-
170
-
3.0
50
-
167
-
2.0
38
-
163
-
1.8
34
-
162
-
1.6
29
-
161
-
1.4
22
-
159
-
1.2
13
-
155
-
1.0
0
-
150
-
<1.0
0
-
150
-
Single-ended requirements for differential signals
Each individual component of a differential signal (CK, DQS, /CK, /DQS) has also to comply with certain
requirements for single-ended signals.
CK and /CK have to approximately reach VSEHmin / VSELmax (approximately equal to the ac-levels
(VIH(AC) / VIL(AC) ) for Address/Command signals) in every half-cycle.
DQS, /DQS have to reach VSEHmin / VSELmax [approximately the ac-levels (VIH(AC) / VIL(AC) ) for DQ
signals] in every half-cycle preceding and following a valid transition.
Note that the applicable AC-levels for Address/Command and DQ’s might be different per speed-bin etc. E.g., if
VIHCA(AC150)/VILCA(AC150) is used for Address/Command signals, then these AC-levels apply also for the
single-ended components of differential CK and /CK.
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EM47FM3288SBB
Note that while Address/command and DQ signal requirements are with respect to VREF, the single-ended
components of differential signals have a requirement with respect to VDD/2; this is nominally the same.
The transition of single-ended signals through the AC-levels is used to measure setup time. For singleended
components of differential signals the requirement to reach VSEL max, VSEH min has no bearing on timing, but
adds a restriction on the common mode characteristics of these signals.
Single-ended levels for CK, DQS, /CK, /DQS
Symbol
VSEH
VSEL
Min.
Max.
Units
Note
Single-ended high-level for strobes
(VDD/2)+0.175
See Note3
V
1,2
Single-ended high-level for CK, /CK
(VDD/2)+0.175
See Note3
V
1,2
Single-ended low-level for strobes
See Note3
(VDD/2)-0.175
V
1,2
Single-ended low-level for CK, /CK
See Note3
(VDD/2)-0.175
V
1,2
Parameter
Note1. For CK, /CK use VIH/VIL(AC) of address/command; for strobes (DQS, DQS) use VIH/VIL(AC) of DQs.
Note2. VIH(AC)/VIL(AC) for DQs is based on VREFDQ; VIH(AC)/VIL(AC) for address/command is based on
VREFCA; if a reduced AC-high or AC-low level is used for a signal group, then the reduced level
applies also here.
Note3. These values are not defined, however the single-ended components of differential signals CK, /CK,
DQS, /DQS need to be within the respective limits (VIH(DC) max, VIL(DC) min) for single-ended signals
as well as the limitations for overshoot and undershoot.
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EM47FM3288SBB
AC and DC Output Measurement Levels
Symbol
Parameter
VOH(DC)
Note
Specification
Units
DC output high measurement level (for IV curve linearity)
0.8*V DDQ
V
VOM(DC)
DC output middle measurement level (for IV curve linearity)
0.5*V DDQ
V
VOL(DC)
DC output low measurement level (for IV curve linearity)
0.2*V DDQ
V
VOH(AC)
AC output high measurement level (for output slew rate)
VTT+0.1*V DDQ
V
1
VOL(AC)
AC output low measurement level (for output slew rate)
VTT-0.1*V DDQ
V
1
VOHdiff(DC)
AC differential output high measurement level (for output
slew rate)
0.2*V DDQ
V
VOLdiff(DC)
AC differential output low measurement level (for output
slew rate)
-0.2*V DDQ
V
2
2
Notes1. The swing of ±0.1 × VDDQ is based on approximately 50% of the static single-ended output high or
low swing with a driver impedance of 34Ω and an effective test load of 25Ω to VTT = VDDQ/2 at each of the
differential outputs.
Notes2. The swing of ±0.2 × VDDQ is based on approximately 50% of the static single-ended output high or
low swing with a driver impedance of 34Ω and an effective test load of 25Ω to VTT = VDDQ/2 at each of the
differential outputs.
DQS Output Crossing Voltage - VOX (DDR3-1600 or Higher Speed Bin)
DQS, /DQS differential slew rate
Symbol
Parameters
5V/ns 6V/ns 7V/ns 8V/ns 9V/ns
Deviation
of
DQS,
V OX
(AC)
+100 +120 +140 +160 +180
/DQS output
max.
cross point
V OX (AC) min. voltage from
-100
-120
-140
-160
-180
0.5*V DDQ
DQS Output Crossing Voltage - VOX (DDR3-1333 or Lower Speed Bin)
DQS, /DQS differential slew rate
Symbol
Parameters
5V/ns 6V/ns 7V/ns 8V/ns 9V/ns
Deviation
of
DQS,
V OX
(AC)
+125 +150 +175 +200 +225
/DQS output
max.
cross point
V OX (AC) min. voltage from
-125
-150
-175
-200
-225
0.5*V DDQ
Unit
10V/ns
11V/ns
12V/ns
+200
+200
+200
mV
-200
-200
-200
mV
10V/ns
11V/ns
12V/ns
+225
+225
+225
mV
-225
-225
-225
mV
Unit
Notes1. Measured using an effective test load of 25Ω to 0.5* VDDQ at each of the differential outputs.
Notes2. For a differential slew rate in between the listed values, the VOX value may be obtained by linear
interpolation.
Notes3. The DQS, /DQS pins under test are not required to be able to drive each of the slew rates listed in the
table; the pins under test will provide one VOX value when tested with specified test condition. The DQS and
/DQS differential slew rate when measuring VOX determines which VOX limits to use.
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EM47FM3288SBB
ZQ Calibration Commands
ZQ Calibration command is used to calibrate DRAM Ron & ODT values. DDR3 SDRAM needs longer
time to calibrate output driver and on-die termination circuits at initialization and relatively smaller
time to perform periodic calibrations.
ZQCL command is used to perform the initial calibration during power-up initialization sequence. This
command may be issued at any time by the controller depending on the system environment. ZQCL
command triggers the calibration engine inside the DRAM and, once calibration is achieved, the
calibrated values are transferred from the calibration engine to DRAM IO, which gets reflected as
updated output driver and on-die termination values.
The first ZQCL command issued after reset is allowed a timing period of tZQinit to perform the full
calibration and the transfer of values. All other ZQCL commands except the first ZQCL command
issued after RESET are allowed a timing period of tZQoper.
ZQCS command is used to perform periodic calibrations to account for voltage and temperature
variations. A shorter timing window is provided to perform the calibration and transfer of values as
defined by timing parameter tZQCS. One ZQCS command can effectively correct a minimum of 0.5
% (ZQ Correction) of RON and RTT impedance error within 64 nCK for all speed bins assuming the
maximum sensitivities specified in the ‘Output Driver Voltage and Temperature Sensitivity’ and ‘ODT
Voltage and Temperature Sensitivity’ tables. The appropriate interval between ZQCS commands can
be determined from these tables and other application-specific parameters. One method for
calculating the interval between ZQCS commands, given the temperature (Tdriftrate) and voltage
(Vdriftrate) drift rates that the SDRAM is subject to in the application, is illustrated. The interval could
be defined by the following formula:
ZQCorrection
(TSens x Tdriftrate) + (VSens x Vdriftrate)
where TSens = max(dRTTdT, dRONdTM) and VSens = max(dRTTdV, dRONdVM) define the
SDRAM temperature and voltage sensitivities.
For example, if TSens = 1.5% / oC, VSens = 0.15% / mV, Tdriftrate = 1 oC / sec and Vdriftrate = 15
mV /sec, then the interval between ZQCS commands is calculated as:
0.5/(1.5x1)+(0.15x15) = 0.133 ≈ 128 ms
No other activities should be performed on the DRAM channel by the controller for the duration of
tZQinit, tZQoper, or tZQCS. The quiet time on the DRAM channel allows accurate calibration of
output driver and on-die termination values. Once DRAM calibration is achieved, the DRAM should
disable ZQ current consumption path to reduce power.
All banks must be precharged and tRP met before ZQCL or ZQCS commands are issued by the
controller. See “[BA=Bank Address, RA=Row Address, CA=Column Address, BC#=Burst Chop,
X=Don’t Care, V=Valid]” on page 33 for a description of the ZQCL and ZQCS commands.
ZQ calibration commands can also be issued in parallel to DLL lock time when coming out of self
Jul. 2012
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EM47FM3288SBB
refresh. Upon Self-Refresh exit, DDR3 SDRAM will not perform an IO calibration without an explicit
ZQ calibration command. The earliest possible time for ZQ Calibration command (short or long) after
self refresh exit is tXS.
In systems that share the ZQ resistor between devices, the controller must not allow any overlap of
tZQoper, tZQinit, or tZQCS between the devices.
ZQ Calibration Timing
ZQ Calibration Method
The ZQ calibration in DDR3 is used both for the output driver and the ODT. The ZQ ball of each DRAM is
connected to an external precision (±1%) 240Ω resistor. This resistor may be shared among devices as long as
the controller does not overlap any timing associated with the calibration and as long as the capacitive loading
does not exceed specification.
Pull-up Calibration
The calibration control block consists of an analog-to-digital converter (ADC), comparators, a majority filter, an
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EM47FM3288SBB
internal reference voltage generator, and an approximation register. The 240Ω legs in the calibration control
block are matched to the pull-up legs used in the output driver and termination options. The pull-up leg uses a
polyresistor that is slightly larger than 240Ω. It employs several P-channel devices to reduce the resistance of
the legs and to tune the polyresistor to 240Ω. This resistor is used to archive a more linear pull-up and
pull-down curve for improved signal integrity at the system level. The pull-down leg is similar to the pull-up leg.
It uses a large polyresistor with multiple N-channel devices for tuning.
When a ZQ calibration command is given, the pull-up line is driven LOW, and the pullup leg is pulled to VDDQ.
The voltage pull-up (VPULL-UP) line is used to compare the voltage at the XRES point to an internally generated
reference voltage (VDDQ/2) by using the comparator inside the DQ calibration control block. The P-channel
tuning devices are individually tuned using the VOH signals until the voltage at XRES equals the internally
generated reference voltage (VDDQ/2). The VOH codes are stored in the internal approximation register and
sent to each of the pull-up legs of the output drivers and termination. After all the pull-up devices have been
calibrated to the external resistor, the comparator is again used to compare the voltage on the pull-down
(VPULL-DOWN) line to the reference voltage set at VDDQ/2. This process generates the VOL codes and updates
the pull-down devices at the appropriate time, completing the calibration process.
Jul. 2012
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EM47FM3288SBB
Recommended DC Operating Conditions
(VDD,VDDQ=1.5V±0.075V)
Symbol
-125
Parameter & Test Conditions
-150
Max
Units
Operating One Bank Active-Read-Precharge Current:
IDD1
CKE: High; External clock: On; tCK, nRC, nRAS, nRCD, CL: see
timing used table; BL: 81; AL: 0; /CS: High between ACT, RD and
PRE; Command, Address, Data IO: partially toggling; DM:stable at 0;
Bank Activity: Cycling with one bank active at a time; Output Buffer
and RTT: Enabled in Mode Registers; ODT Signal: stable at 0
TBD
TBD
mA
TBD
TBD
mA
TBD
TBD
mA
TBD
TBD
mA
TBD
TBD
mA
TBD
TBD
mA
TBD
TBD
mA
Precharge Power-Down Current Fast Exit:
IDD2P1
CKE: Low; External clock: On; tCK, CL: see timing used table; BL: 8;
AL: 0; /CS: stable at 1; Command, Address: stable at 0; Data IO:
FLOATING; DM: stable at 0; Bank Activity: all banks closed; Output
Buffer and RTT: Enabled in Mode Registers; ODT Signal: stable at 0;
Pre-charge Power Down Mode: Fast Exit
Precharge Standby Current:
IDD2N
CKE: High; External clock: On; tCK, CL: see timing used table; BL: 8;
AL: 0; /CS: stable at 1; Command, Address: partially toggling; Data
IO: FLOATING; DM:stable at 0; Bank Activity: all banks closed;
Output Buffer and RTT: Enabled in Mode Registers; ODT Signal:
stable at 0
Active Power-Down Current:
IDD3P
CKE: Low; External clock: On; tCK, CL: see timing used table; BL: 8;
AL: 0; /CS: stable at 1; Command, Address: stable at 0; Data IO:
FLOATING; DM: stable at 0; Bank Activity: all banks open; Output
Buffer and RTT: Enabled in Mode Registers; ODT Signal: stable at 0
Operating Burst Write Current:
IDD4W
CKE: High; External clock: On; tCK, CL: see timing used table; BL: 8;
AL: 0; /CS: High between WR; Command, Address: partially toggling;
Data IO: seamless write data burst with different data between one
burst and the next one; DM: stable at 0; Bank Activity: all banks open,
WR commands cycling through banks: 0,0,1,1,2,2,...; Output Buffer
and RTT: Enabled in Mode Registers; ODT Signal: stable at HIGH
Operating Burst Read Current:
IDD4R
CKE: High; External clock: On; tCK, CL: see timing used table; BL: 8;
AL: 0; /CS: High between RD; Command, Address: par-tially toggling;
Data IO: seamless read data burst with different data between one
burst and the next one; DM: stable at 0; Bank Activity: all banks open,
RD commands cycling through banks: 0,0,1,1,2,2,...; Output Buffer
and RTT: Enabled in Mode Registers; ODT Signal: stable at 0
Burst Refresh Current:
IDD5B
Jul. 2012
CKE: High; External clock: On; tCK, CL, nRFC: see timing used
table; BL: 8; AL: 0; /CS: High between REF; Command, Address:
partially toggling; Data IO: FLOATING; DM: stable at 0; Bank Activity:
REF command every nRFC; Output Buffer and RTT: Enabled in
Mode Registers; ODT Signal: stable at 0
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EM47FM3288SBB
-125
-150
Symbol
Parameter & Test Conditions
IDD6
Self Refresh Current: Normal Temperature Range; TCASE: 085°C; Auto Self-Refresh (ASR): Disabled; Self-Refresh
Temperature Range (SRT): Normal; CKE: Low; External clock: Off;
CK and /CK: LOW; CL: see timing used table; BL: 8; AL: 0; CS,
Command, Address, Data IO: FLOATING; DM: stable at 0; Bank
Activity: Self-Refresh operation; Output Buffer and RTT: Enabled in
Mode Registers; ODT Signal: FLOATING
TBD
TBD
mA
IDD7
Operating Bank Interleave Read Current; CKE: High; External
clock: On; tCK, nRC, nRAS, nRCD, nRRD, nFAW, CL: see timing
used table; BL: 8; AL: CL-1; CS: High between ACT and RDA;
Command, Address: partially toggling; Data IO: read data bursts
with different data between one burst and the next one; DM: stable
at 0; Bank Activity: two times interleaved cycling through banks (0,
1, ...7) with different addressing; Output Buffer and RTT: Enabled in
Mode Registers; ODT Signal: stable at 0
TBD
TBD
mA
Max
Units
Note 1: Burst Length: BL8 fixed by MRS: set MR0 A[1,0]=00B
Note 2: Output Buffer Enable: set MR1 A[12] = 0B; set MR1 A[5,1] = 01B; RTT_Nom enable: set MR1 A[9,6,2]
= 011B; RTT_Wr enable: set MR2 A[10,9] = 10B
Note 3: Precharge Power Down Mode: set MR0 A12=0B for Slow Exit or MR0 A12=1B for Fast Exit
Note 4: Auto Self-Refresh (ASR): set MR2 A6 = 0B to disable or 1B to enable feature
Note 5: Self-Refresh Temperature Range (SRT): set MR2 A7=0B for normal or 1B for extended temperature
range
Note 6: Refer to DRAM supplier data sheet and/or DIMM SPD to determine if optional features or requirements
are supported by DDR3 SDRAM
Note 7: Read Burst type: Nibble Sequential, set MR0 A[3]=0B
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EM47FM3288SBB
Block Diagram
DM0,DM1,DM2,DM3
Auto/ Self
Refresh Counter
DQM
Control
A0
CLK, /CLK
A1
A2
A6
A7
A8
A9
Row Decoder
Address Register
A4
A5
DQS
Generator
Row Add. Buffer
A3
Memory
Array
Driver
S/ A & I/ O Gating
A10
DLL
Write
FIFO
CLK, /CLK
A11
Col. Decoder
A12
A13
Receiver
A14
Col. Add. Buffer
A15
BA0
Data In
BA1
Mode Register Set
BA2
Data Out
Col Add. Counter
Burst Counter
DIO
Timing Register
DQS0~3, /DQS0~3
/CLK
Jul. 2012
CLK
CKE
/CS
/RAS
/CAS
17/41
/WE
/RESET
ODT
ZQ
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EM47FM3288SBB
AC Operating Test Characteristics
DDR3-1333 & DDR3-1600 Speed Bins
(VDD, VDDQ=1.5V±0.075V)
Symbol
Speed Bin
-125
(DDR3-1600)
-150
(DDR3-1333)
CL-nRCD-nRP
11-11-11
9-9-9
Parameter
Min.
Max.
Min.
Max.
Units
Notes
tAA
Internal read command to first data
13.125
20
13.5
20
ns
8
tRCD
Active to read or write delay
13.125
-
13.5
-
ns
8
tRP
Precharge command period
13.125
-
13.5
-
ns
8
tRC
Active to active/auto refresh command
48.75
-
49.5
-
ns
8
tRAS
Active to precharge command period
35
9*tREFI
36
9*tREFI
ns
7
tCK (AVG)
Average Clock Cycle, CL=6, CWL=5
2.5
3.3
2.5
3.3
ns
1,2,3,5
.6
tCK (AVG)
Average Clock Cycle, CL=7, CWL=6
1.875
2.5
1.875
2.5
ns
1,2,3,4
,5,6
tCK (AVG)
Average Clock Cycle, CL=8, CWL=6
1.875
2.5
1.875
2.5
ns
1,2,3,5
,6
tCK (AVG)
Average Clock Cycle, CL=9, CWL=7
1.5
1.875
1.5
1.875
ns
1,2,3,4
,6
tCK (AVG)
Average Clock Cycle, CL=10, CWL=7
1.5
1.875
1.5
1.875
ns
1,2,3,6
tCK (AVG)
Average Clock Cycle, CL=11, CWL=8
1.25
1.5
-
-
ns
1,2,3
-
Support CL Settings
6,7,8,9,10,11
6,7,8,9,10
nCK
-
Support CWL Settings
5,6,7,8
5,6,7
nCK
Notes1. The CL setting and CWL setting result in tCK (avg) (min.) and tCK (avg) (max.) requirements. When
making a selection of tCK (avg), both need to be fulfilled: Requirements from CL setting as well as
requirements from CWL setting.
Notes2. tCK (avg) (min.) limits: Since /CAS latency is not purely analog - data and strobe output are
synchronized by the DLL - all possible intermediate frequencies may not be guaranteed. An application
should use the next smaller JEDEC standard tCK (avg) value (2.5, 1.875, 1.5, or 1.25ns) when
calculating CL (nCK) = tAA (ns) / tCK (avg)(ns), rounding up to the next ‘Supported CL’.
Notes3. tCK (avg) (max.) limits: Calculate tCK (avg) + tAA (max.)/CL selected and round the resulting tCK (avg)
down to the next valid speed bin (i.e. 3.3ns or 2.5ns or 1.875ns or 1.25ns). This result is tCK (avg)
(max.) corresponding to CL selected.
Notes4. ‘Reserved’ settings are not allowed. User must program a different value.
Notes5. Any DDR3-1333 speed bin also supports functional operation at lower frequencies as shown in the
table DDR3-1333 Speed Bins which is not subject to production tests but verified by
design/characterization.
Notes6. Any DDR3-1600 speed bin also supports functional operation at lower frequencies as shown in the
table DDR3-1600 Speed Bins which is not subject to production tests but verified by
design/characterization.
Notes7. tREFI depends on operating case temperature (TC).
Notes8. For devices supporting optional down binning to CL = 7 and CL = 9, tAA/tRCD/tRP(min.) must be
13.125 ns or lower. SPD settings must be programmed to match.
Jul. 2012
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EM47FM3288SBB
AC Operating Test Characteristics
(VDD, VDDQ=1.5V±0.075V)
Symbol
Speed Bin
-125
(DDR3-1600)
-150
(DDR3-1333)
CL-nRCD-nRP
11-11-11
9-9-9
Parameter
tCK
Minmum clock cycle, DLL-off mode
Units
Notes
6
Min.
Max.
Min.
Max.
8
-
8
-
ns
tCH, tCL (AVG)
Average CK high/low level width
0.47
0.53
0.47
0.53
ns
tRRD
Active bank A to active bank B
command period (1KB page size)
6
-
6
-
ns
4
-
4
-
nCK
tFAW
Four Activate Window
30
-
30
-
ns
tIH(base)
DC100
Address and Control input hold time
(VIH/VIL(DC100) levels)
120
-
140
-
ps
16
tIS(base)
AC175
Address and Control input setup time
(VIH/VIL(AC175) levels)
45
-
65
-
ps
16
tIS(base)
AC150
Address and Control input setup time
(VIH/VIL(AC150) levels)
45+125
-
65+125
-
ps
16,24
tDH(base)
DQ and DM input hold time
(VIH/VIL(DC) levels)
45
-
65
-
ps
17
tDS(base)
DQ and DM input setup time
(VIH/VIL(AC) levels)
10
-
30
-
ps
17
tIPW
Address and control input pulse width
for each input
560
-
620
-
ps
25
tDIPW
DQ and DM input pulse width for
each input
360
-
400
-
ps
25
tHZ(DQ)
DQ high impedance time
-
225
-
250
ps
13,14
tLZ(DQ)
DQ low impedance time
-450
225
-500
250
ps
13,14
-
225
-
250
ps
13,14
-450
225
-500
250
ps
13,14
12,13
tHZ(DQS)
tLZ(DQS)
DQS,/DQS high impedance time
RL+BL/2 reference
DQS,/DQS low impedance time
RL-1 reference
tDQSQ
DQS,/DQS to DQ skew per group,
per access
-
100
-
125
ps
tCCD
/CAS to /CAS command delay
4
-
4
-
nCK
tQH
DQ output hold time from DQS, /DQS
0.38
-
0.38
-
tCK
(avg)
12,13
tDQSCK
DQS,/DQS rising edge output access
time from rising CK,/CK
-225
225
-255
255
ps
12,13
tDQSS
DQS latch rising transitions to
associated clock edges
-0.27
0.27
-0.25
0.25
tCK
(avg)
tDQSH
DQS input high pulse width
0.45
0.55
0.45
0.55
tCK
(avg)
Jul. 2012
19/41
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EM47FM3288SBB
AC Operating Test Characteristics
(VDD, VDDQ=1.5V±0.075V)
Symbol
Speed Bin
-125
(DDR3-1600)
-150
(DDR3-1333)
CL-nRCD-nRP
11-11-11
9-9-9
Parameter
Min.
Max.
Min.
Max.
Units
Notes
tDSH
DQS falling edge hold time from
rising CK
0.18
-
0.2
-
tCK
(avg)
29
tDSS
DQS falling edge setup time to rising
CK
0.18
-
0.2
-
tCK
(avg)
29
tDQSL
DQS input low pulse width
0.45
0.55
0.45
0.55
tCK
(avg)
26,28
tQSH
DQS output high time
0.40
-
0.40
-
tCK
(avg)
12,13
tQSL
DQS output low time
0.40
-
0.40
-
tCK
(avg)
12,13
tMRD
Mode register set command cycle
4
-
4
-
nCK
tMOD
Mode register set command update
delay
15
-
15
-
ns
12
-
12
-
nCK
tRPRE
Read preamble time
0.9
-
0.9
-
tCK
(avg)
13,19
tRPST
Read postamble time
0.3
-
0.3
-
tCK
(avg)
11,13
tWPRE
Write preamble time
0.9
-
0.9
-
tCK
(avg)
1
tWPST
Write postamble time
0.3
-
0.3
-
tCK
(avg)
1
Write recovery time
15
-
15
-
ns
Auto precharge write recovery +
precharge time
WR + roundup[tRP / tCK(avg)]
tMPRR
Multi purpose register recovery time
1
-
1
-
nCK
tWTR
Internal write to read command delay
7.5
-
7.5
-
ns
4
-
4
-
nCK
tRTP
Internal read to precharge command
delay
7.5
-
7.5
-
ns
4
-
4
-
nCK
tCKE (min)
+1
-
tCKE (min)
+1
-
nCK
tWR
tDAL(min)
nCK
tCKESR
Minimum CKE low width for selfrefresh entry to exit
tCKSRE
Valid clock requirement after selfrefresh entry or power-down entry
10
-
10
-
ns
5
-
5
-
nCK
tCKSRX
Valid clock requirement before selfrefresh exit or power-down exit
10
-
10
-
ns
5
-
5
-
nCK
Jul. 2012
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22
18
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EM47FM3288SBB
AC Operating Test Characteristics
(VDD, VDDQ=1.5V±0.075V)
Symbol
Speed Bin
-125 (DDR3-1600)
-150 (DDR3-1333)
CL-nRCD-nRP
11-11-11
9-9-9
Parameter
tXS
tXSDLL
Exit self-refresh to commands not
requiring a locked DLL
Exit self-refresh to commands
requiring a locked DLL
Units
Min.
Max.
Min.
Max.
tRFC(min)
+ 10
-
tRFC(min)
+ 10
-
ns
5
-
5
-
nCK
tDLL(min)
-
tDLL(min)
-
nCK
160
-
160
-
ns
tRFC
Auto-refresh to active/auto-refresh
command
tREFI
Average periodic refresh interval
0℃≦TC≦+85℃
-
7.8
-
7.8
µs
tREFI
Average periodic refresh interval
+85℃≦TC≦+95℃
-
3.9
-
3.9
µs
tCKE
CKE minimum high and low pulse
width
5
-
5.625
-
ns
3
-
3
-
nCK
tXPR
Exit reset from CKE high to a valid
command
tRFC(min)
+ 10
-
tRFC(min)
+ 10
-
ns
5
-
5
-
nCK
512
-
512
-
nCK
tCKE(min)
9*tREFI
tCKE(min)
9*tREFI
24
-
24
-
ns
10
-
10
-
nCK
6
-
6
-
ns
3
-
3
-
nCK
tDLLK
tPD
tXPDLL
tXP
tWRPDEN
(min)
tWRPDEN
(min)
tWRAPDEN
DLL locking time
Power-down entry to exit time
Exit precharge power-down with
DLL frozen to commands requiring
a locked DLL
Timing of WR command to powerdown entry
WL + 4 + [tWR / tCK(avg)]
nCK
(BL8OTF, BL8MRS, BL4OTF)
9
Timing of WR command to powerdown entry
WL + 2 + [tWR / tCK(avg)]
nCK
(BC4MRS)
Timing of WRA command to powerdown entry
Timing of WRA command to powerdown entry
(BC4MRS)
Jul. 2012
15
2
Exit power-down with DLL on to any
valid command; Exit precharge
power-down with DLL frozen to
commands not requiring a locked
DLL
(BL8OTF, BL8MRS, BL4OTF)
tWRAPDEN
Notes
WL + 4 +
WR + 1
-
WL + 4 +
WR + 1
-
nCK
10
WL + 2 +
WR + 1
-
WL + 2 +
WR + 1
-
nCK
10
21/41
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EM47FM3288SBB
AC Operating Test Characteristics
(VDD, VDDQ=1.5V±0.075V)
Symbol
Speed Bin
-125
(DDR3-1600)
-150
(DDR3-1333)
CL-nRCD-nRP
11-11-11
9-9-9
Parameter
Min.
Max.
Min.
Max.
Units
Notes
nCK
20,21
tREFPDEN
Timing of REF command to powerdown entry
1
-
1
-
tMRSPDEN
Timing of MRS command to powerdown entry
tMOD
(min)
-
tMOD
(min)
-
Command pass disable delay
1
-
1
-
nCK
tACTPDEN
Timing of ACT command to powerdown entry
1
-
1
-
nCK
20
tPRPDEN
Timing of PRE command to powerdown entry
1
-
1
-
nCK
20
tRDPDEN
Timing of RD/RDA command to
power-down entry
RL + 4
+1
-
RL + 4
+1
-
nCK
-225
225
-250
250
ps
2
8.5
2
8.5
ns
0.3
0.7
0.3
0.7
tCK
(avg)
Asynchronous RTT turn-off delay
(Power-down with DLL frozen)
2
8.5
2
8.5
ns
ODTH4
ODT high time without write command
or with write command and BC4
4
-
4
-
nCK
ODTH8
ODT high time with write command
and BL8
6
-
6
-
nCK
tCPDED
tAON
tAONPD
tAOF
tAOFPD
RTT turn-on
Asynchronous RTT turn-on delay
(Power-down with DLL frozen)
RTT_Nom and RTT_WR turn-off time
from ODTLoff reference
7
8
tADC
RTT dynamic change skew
0.3
0.7
0.3
0.7
tCK
(avg)
tZQinit
Power-up and reset calibration time
512
-
512
-
nCK
tZQoper
Normal operation full calibration time
256
-
256
-
nCK
tZQCS
Normal operation short calibration time
64
-
64
-
nCK
23
tWLMRD
First DQS pulse rising edge after write
leveling mode is programmed
40
-
40
-
nCK
3
DQS./DQS delay after write leveling
mode is programmed
25
-
25
-
nCK
3
-
RL +
tCCD/2 +
2nCK-W
L
-
-
-
tWLDQSEN
tRTW
Read to write command delay
(BC4MRS, BC4OTF)
RL + tCCD/2
+
2nCK-WL
tRTW
Read to write command delay
(BL8MRS, BL8OTF)
RL + tCCD/2
+
2nCK-WL
-
RL +
tCCD/2 +
2nCK-W
L
tRAP
Active to read with auto precharge
command delay
tRCD min
-
tRCD
min
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EM47FM3288SBB
AC Operating Test Characteristics
(VDD, VDDQ=1.5V±0.075V)
Symbol
Speed Bin
-125 (DDR3-1600)
-150 (DDR3-1333)
CL-nRCD-nRP
11-11-11
9-9-9
Parameter
Units
Min.
Max.
Min.
Max.
tWLS
Write leveling setup time from
rising CK,/CK crossing to rising
DQS,/DQS crossing
165
-
195
-
ps
tWLH
Write leveling hold time from
rising DQS,/DQS crossing to
rising CK,/CK crossing
165
-
195
-
ps
tWLO
Write leveling output delay
0
7.5
0
9
ns
tWLOE
Write leveling output error
0
2
0
2
ns
tCK (avg)min+
tJIT(per)min
tCK (avg)max+
tJIT (per)max
tCK (avg)min+
tJIT (per)min
tCK (avg)max+
tJIT (per)max
ps
Notes
tCK (abs)
Absolute clock period
tCH (abs)
Absolute clock high pulse width
0.43
-
0.43
-
tCK
(avg)
30
tCL (abs)
Absolute clock low pulse width
0.43
-
0.43
-
tCK
(avg)
31
tJIT (per)
Clock period jitter
-70
70
-80
80
ps
Clock period jitter during DLL
locking period
-60
60
-70
70
ps
Cycle to cycle period jitter
-
140
-
160
ps
tJIT (cc,lck)
Cycle to cycle period jitter during
DLL locking period
-
120
-
140
ps
tERR (2per)
Cumulative error across 2 cycles
-103
103
-118
118
ps
tERR (3per)
Cumulative error across 3 cycles
-122
122
-140
140
ps
tERR (4per)
Cumulative error across 4 cycles
-136
136
-155
155
ps
tERR (5per)
Cumulative error across 5 cycles
-147
147
-168
168
ps
tERR (6per)
Cumulative error across 6 cycles
-155
155
-177
177
ps
tERR (7per)
Cumulative error across 7 cycles
-163
163
-186
186
ps
tERR (8per)
Cumulative error across 8 cycles
-169
169
-193
193
ps
tERR (9per)
Cumulative error across 9 cycles
-175
175
-200
200
ps
tERR (10per)
Cumulative error across 10
cycles
-180
180
-205
205
ps
tERR (11per)
Cumulative error across 11
cycles
-184
184
-210
210
ps
tERR (12per)
Cumulative error across 12
cycles
-188
188
-215
215
ps
tJIT (per,lck)
tJIT (cc)
tERR (nper)
Jul. 2012
Cumulative error across
tERR (nper)min=(1+0.68ln(n))*tJIT (per)min
n= 13,14,… 49,50 cycles
tERR (nper)max=(1+0.68ln(n))*tJIT (per)max
23/41
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EM47FM3288SBB
AC Operating Test Characteristics
(VDD, VDDQ=1.5V±0.075V)
Symbol
Speed Bin
-125 (DDR3-1600)
-150 (DDR3-1333)
CL-nRCD-nRP
11-11-11
9-9-9
Parameter
Units
Min.
Max.
Min.
Max.
ODT to power-down entry/ exit
latency
WL–1
-
WL–1
-
nCK
ODTLon
ODT turn on latency
WL–2
WL–2
WL–2
WL–2
nCK
ODTLoff
ODT turn off latency
WL–2
WL–2
WL–2
WL–2
nCK
ODTLcnw
ODT latency for changing from
RTT_Nom to RTT_WR
WL–2
WL–2
WL–2
WL–2
nCK
ODTLcwn4
ODT latency for changing from
RTT_WR to RTT_Nom (BC4)
-
4+ODTLoff
-
4+ODTLoff
nCK
ODTLcwn8
ODT latency for changing from
RTT_WR to RTT_Nom (BL8)
-
6+ODTLoff
-
6+ODTLoff
nCK
tANPD
Notes
Note 1: Actual value dependant upon measurement level definitions which are TBD.
Note 2: Commands requiring a locked DLL are: READ (and READA) and synchronous ODT commands.
Note 3: The max values are system dependent.
Note 4: WR as programmed in mode register.
Note 5: Value must be rounded-up to next higher integer value.
Note 6: There is no maximum cycle time limit besides the need to satisfy the refresh interval, tREFI.
Note 7: ODT turn on time (min.) is when the device leaves high impedance and ODT resistance begins to turn
on. ODT turn on time (max.) is when the ODT resistance is fully on. Both are measured from ODTLon.
Note 8: ODT turn-off time (min.) is when the device starts to turn-off ODT resistance. ODT turn-off time (max.)
is when the bus is in high impedance. Both are measured from ODTLoff.
Note 9: tWR is defined in ns, for calculation of tWRPDEN it is necessary to round up tWR / tCK to the next
integer.
Note 10: WR in clock cycles as programmed in MR0.
Note 11: The maximum read postamble is bound by tDQSCK(min) plus tQSH(min) on the left side and
tHZ(DQS)max on the right side.
Note 12: Output timing deratings are relative to the SDRAM input clock. When the device is operated with input
clock jitter, this parameter needs to be derated by TBD.
Note 13: Value is only valid for RON34.
Note 14: Single ended signal parameter. Refer to the section of tLZ(DQS), tLZ(DQ), tHZ(DQS), tHZ(DQ) Notes
for definition and measurement method.
Note 15: tREFI depends on operating case temperature (Tc).
Note 16: tIS(base) and tIH(base) values are for 1V/ns command/ addresss single-ended slew rate and 2V/ns
CK, /CK differential slew rate, Note for DQ and DM signals, VREF(DC) = VREFDQ(DC). For input only pins
except RESET, VREF(DC) = VREFCA(DC). See Address / Command Setup, Hold and Derating section.
Note 17: tDS(base) and tDH(base) values are for 1V/ns DQ single-ended slew rate and 2V/ns DQS, /DQS
differential slew rate. Note for DQ and DM signals, VREF(DC)= VREFDQ(DC). For input only pins except
RESET, VREF(DC) = VREFCA(DC). See Data Setup, Hold and and Slew Rate Derating section.
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EM47FM3288SBB
Note 18: Start of internal write transaction is defined as follows ;
For BL8 (fixed by MRS and on-the-fly, OTF) : Rising clock edge 4 clock cycles after WL.
For BC4 (on-the-fly, OTF) : Rising clock edge 4 clock cycles after WL.
For BC4 (fixed by MRS) : Rising clock edge 2 clock cycles after WL.
Note 19: The maximum read preamble is bound by tLZDQS(min) on the left side and tDQSCK(max) on the
right side.
Note 20: CKE is allowed to be registered low while operations such as row activation, precharge, auto
precharge or refresh are in progress, but power-down IDD spec will not be applied until finishing those
operation.
Note 21: Although CKE is allowed to be registered LOW after a REFRESH command once tREFPDEN(min) is
satisfied, there are cases where additional time such as tXPDLL(min) is also required.
Note 22: Defined between end of MPR read burst and MRS which reloads MPR or disables MPR function.
Note 23: One ZQCS command can effectively correct a minimum of 0.5 % (ZQCorrection) of RON and RTT
impedance error within 64 nCK for all speed bins assuming the maximum sensitivities specified in the “Output
Driver Voltage and Temperature Sensitivity” and “ODT Voltage and Temperature Sensitivity” tables. The
appropriate interval between ZQCS commands can be determined from these tables and other application
specific parameters. One method for calculating the interval between ZQCS commands, given the temperature
(Tdriftrate) and voltage (Vdriftrate) drift rates that the SDRAM is subject to in the application, is illustrated. The
interval could be defined by the following formula:
ZQCorrection
(TSens x Tdriftrate ) + (VSens x Vdriftrate)
where TSens = max(dRTTdT, dRONdTM) and VSens = max(dRTTdV, dRONdVM) define the SDRAM
temperature and voltage sensitivities.
Note 24: The tIS(base) AC150 specifications are adjusted from the tIS(base) specification by adding an
additional 100 ps of derating to accommodate for the lower alternate threshold of 150 mV and another 25 ps to
account for the earlier reference point [(175 mv - 150 mV) / 1 V/ns].
Note 25: Pulse width of a input signal is defined as the width between the first crossing of VREF(DC) and the
consecutive crossing of VREF(DC).
Note 26: tDQSL describes the instantaneous differential input low pulse width on DQS - /DQS, as measured
from one falling edge to the next consecutive rising edge.
Note 27: tDQSH describes the instantaneous differential input high pulse width on DQS - /DQS, as measured
from one rising edge to the next consecutive falling edge.
Note 28: tDQSH,act + tDQSL,act = 1 tCK,act ; with tXYZ,act being the actual measured value of the respective
timing parameter in the application.
Note 29: tDSH,act + tDSS,act = 1 tCK,act ; with tXYZ,act being the actual measured value of the respective
timing parameter in the application.
Note 30: tCH(abs) is the absolute instantaneous clock high pulse width, as measured from one rising edge to
the following falling edge.
Note 31: tCL(abs) is the absolute instantaneous clock low pulse width, as measured from one falling edge to
the following rising edge.
Note 32: n = from 13 cycles to 50 cycles. This row defines 38 parameters.
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Simplified State Diagram
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1. Command Truth Table
Command
Symbol
CKE
n-1
N
H
H
/CS
/RAS
/CAS
/WE
BA0~
BA2
A10
A12,
A10~A0
H
X
X
X
X
X
X,X
Device Deselect
DES
No Operation
NOP
H
H
L
H
H
H
V
V
V,V
RD
H
H
L
H
L
H
BA
L
V,CA
Read (BC4, OTF)
RDS4
H
H
L
H
L
H
BA
L
L,CA
Read (BL8, OTF)
RDS8
H
H
L
H
L
H
BA
L
H,CA
Read with Auto Precharge (fixed BL8/BC4)
RDA
H
H
L
H
L
H
BA
H
V,CA
RDAS4
H
H
L
H
L
H
BA
H
L,CA
RDAS8
H
H
L
H
L
H
BA
H
H,CA
Read (fixed BL8/BC4)
Read with Auto Precharge (BC4, OTF)
Read with Auto Precharge (BL8, OTF)
Write (fixed BL8/BC4)
WR
H
H
L
H
L
L
BA
L
V,CA
Write (BC4, OTF)
WRS4
H
H
L
H
L
L
BA
L
L,CA
Write (BL8,OTF)
WRS8
H
H
L
H
L
L
BA
L
H,CA
Write with Auto Precharge (fixed BL8/BC4)
WRA
H
H
L
H
L
L
BA
H
V,CA
H
H
L
H
L
L
BA
H
L,CA
H
H
L
H
L
L
BA
H
H,CA
H
H
L
L
H
H
BA
PRE
H
H
L
L
H
L
BA
L
V,V
Pre-charge All Banks
PREA
H
H
L
L
H
L
V
H
V,V
Mode Register Set
MRS
H
H
L
L
L
L
BA
Refresh
REF
H
H
L
L
L
H
V
V
V,V
Self Refresh entry
SRE
H
L
L
L
L
H
V
V
V,V
Self Refresh Exit
SRX
L
H
Power Down Entry
PDE
H
Power Down Exit
PDX
Write with Auto Precharge (BC4, OTF)
Write with Auto Precharge (BL8, OTF)
Bank Activate
Pre-charge Single Bank
WRAS
4
WRAS
8
ACT
RA
OP Code
H
X
X
X
X
X
X,X
L
H
H
H
V
V
V,V
L
H
X
X
X
X
X
X,X
H
L
L
H
H
H
V
V
V,V
L
H
H
X
X
X
X
X
X,X
L
H
L
H
H
H
V
V
V,V
ZQ Calibration Long
ZQCL
H
H
L
H
H
L
X
H
X,X
ZQ Calibration Short
ZQCS
H
H
L
H
H
L
X
L
X,X
H = High level, L = Low level, X = Don't care, V = Valid, BA=Bank Address, CA=Column Address, RA=Row Address
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Note1. All DDR3 SDRAM commands are defined by states of /CS, /RAS, /CAS, /WE and CKE at the rising
edge of the clock. The MSB of BA, RA and CA are device density and configuration dependant.
Note2. /RESET is low enable command which will be used only for asynchronous reset so must be maintained
HIGH during any function.
Note3. Bank addresses (BA) determine which bank is to be operated upon. For (E)MRS BA selects an
(Extended) Mode Register.
Note4. “V” means “H or L (but a defined logic level)” and “X” means either “defined or undefined (like floating)
logic level”.
Note5. Burst reads or writes cannot be terminated or interrupted and Fixed/on-the-Fly (OTF) BL will be defined
by MRS.
Note6. The Power Down Mode does not perform any refresh operation.
Note7. The state of ODT does not affect the states described in this table. The ODT function is not available
during Self Refresh.
Note8. Self Refresh Exit is asynchronous.
Note9. VREF(Both VREFDQ and VREFCA) must be maintained during Self Refresh operation. VREFDQ
supply may be turned OFF and VREFDQ may take any value between VSS and VDD during Self
Refresh operation, provided that VREFDQ is valid and stable prior to CKE going back high and that first
Write operation or first Write Leveling Activity may not occur earlier than 512 nCK after exit from Self
Refresh.
Note10. The No Operation command should be used in cases when the DDR3 SDRAM is in an idle or wait
state. The purpose of the No Operation command (NOP) is to prevent the DDR3 SDRAM from
registerng any unwanted commands between operations. A No Operation command will not terminate
a pervious operation that is still executing, such as a burst read or write cycle.
Note11. The Deselect command performs the same function as No Operation command.
Note12. Refer to the CKE Truth Table for more detail with CKE transition.
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2. CKE Truth Table
CKE
Current State
Command (n)
Action (n)
Notes
X
Maintain power down
14,15
H
DESELECT or NOP
Power down exit
11,14
L
L
X
Maintain self refresh
15,16
L
H
DESELECT or NOP
Self refresh exit
8,12,16
Bank Active
H
L
DESELECT or NOP
Active power down entry
11,13,14
Reading
H
L
DESELECT or NOP
Power down entry
11,13,14,17
Writing
H
L
DESELECT or NOP
Power down entry
11,13,14,17
Precharging
H
L
DESELECT or NOP
Power down entry
11,13,14,17
Refreshing
H
L
DESELECT or NOP
Precharge power down entry
11
H
L
DESELECT or NOP
Precharge power down entry
11,13,14,18
H
L
REFRESH
Self refresh
9,13,18
Power Down
Self Refresh
All Banks Idle
n-1
n
/RAS, /CAS, /WE, /CS
L
L
L
For more details with all signals, see “Command Truth Table”
10
Note1. CKE (n) is the logic state of CKE at clock edge n; CKE (n-1) was the state of CKE at the previous clock
edge.
Note2. Current state is defined as the state of the DDR3 SDRAM immediately prior to clock edge n.
Note3. Command (n) is the command registered at clock edge n, and ACTION (n) is a result of Command (n),
ODT is not included here.
Note4. All states and sequences not shown are illegal or reserved unless explicitly described elsewhere in this
document.
Note5. The state of ODT does not affect the states described in this table. The ODT function is not available
during Self-Refresh.
Note6. During any CKE transition (registration of CKE H->L or CKE L->H) the CKE level must be maintained
until 1nCK prior to tCKEmin being satisfied (at which time CKE may transition again).
Note7. DESELECT and NOP are defined in the “Command Truth Table”.
Note8. On self-refresh exit DESELECT or NOP commands must be issued on every clock edge occurring
during the tXS period. Read or ODT commands may be issued only after tXSDLL is satisfied.
Note9. Self-Refresh mode can only be entered from the All Banks Idle state.
Note10. It must be a legal command as defined in the “Command Truth Table”.
Note11. Valid commands for power-down entry and exit are NOP and DESELECT only.
Note12. Valid commands for self-refresh exit are NOP and DESELECT only.
Note13. Self-Refresh can not be entered during Read or Write operations.
Note14. The Power-Down does not perform any refresh operations.
Note15. “X” means “don’t care“ (including floating around VREF) in Self-Refresh and Power-Down. It also
applies to Address pins.
Note16. VREF (Both VREFDQ and VREFCA) must be maintained during Self-Refresh operation. VREFDQ
supply may be turned OFF and VREFDQ may take any value between VSS and VDD during Self Refresh
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operation, provided that VREFDQ is valid and stable prior to CKE going back high and that first write operation
or first write Leveling activity may not occur earlier than 512 nCK after exit from Self Refresh.
Note17. If all banks are closed at the conclusion of the read, write or precharge command, then Precharge
Power-Down is entered, otherwise Active Power-Down is entered.
Note18. ‘Idle state’ is defined as all banks are closed (tRP, tDAL, etc. satisfied), no data bursts are in progress,
CKE is high, and all timings from previous operations are satisfied (tMRD, tMOD, tRFC, tZQinit, tZQoper,
tZQCS, etc.) as well as all self-refresh exit and power-down exit parameters are satisfied (tXS, tXP, tXPDLL,
etc).
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Initialization
The following sequence is required for power-up and initialization and is shown in below Figure:
1. Apply power (/RESET is recommended to be maintained below 0.2 x VDD; all other inputs may be
undefined). /RESET needs to be maintained for minimum 200 us with stable power. CKE is pulled “Low”
anytime before /RESET being de-asserted (min. time 10 ns). The power voltage ramp time between 300 mv to
VDDmin must be no greater than 200 ms; and during the ramp, VDD > VDDQ and (VDD - VDDQ) < 0.3 volts.
• VDD and VDDQ are driven from a single power converter output, AND
• The voltage levels on all pins other than VDD, VDDQ, VSS, VSSQ must be less than or equal to
VDDQ and VDD on one side and must be larger than or equal to VSSQ and VSS on the other side. In
addition, VTT is limited to 0.95 V max once power ramp is finished, AND
• Vref tracks VDDQ/2. OR
• Apply VDD without any slope reversal before or at the same time as VDDQ.
• Apply VDDQ without any slope reversal before or at the same time as VTT & Vref.
• The voltage levels on all pins other than VDD, VDDQ, VSS, VSSQ must be less than or equal to
VDDQ and VDD on one side and must be larger than or equal to VSSQ and VSS on the other side.
2. After /RESET is de-asserted, wait for another 500 us until CKE becomes active. During this time, the DRAM
will start internal state initialization; this will be done independently of external clocks.
3. Clocks (CK, /CK) need to be started and stabilized for at least 10 ns or 5 tCK (which is larger) before CKE
goes active. Since CKE is a synchronous signal, the corresponding set up time to clock (tIS) must be met. Also,
a NOP or Deselect command must be registered (with tIS set up time to clock) before CKE goes active. Once
the CKE is registered “High” after Reset, CKE needs to be continuously registered “High” until the initialization
sequence is finished, including expiration of tDLLK and tZQinit.
4. The DDR3 SDRAM keeps its on-die termination in high-impedance state as long as /RESET is asserted.
Further, the SDRAM keeps its on-die termination in high impedance state after /RESET de-assertion until CKE
is registered HIGH. The ODT input signal may be in undefined state until tIS before CKE is registered HIGH.
When CKE is registered HIGH, the ODT input signal may be statically held at either LOW or HIGH. If
RTT_NOM is to be enabled in MR1, the ODT input signal must be statically held LOW. In all cases, the ODT
input signal remains static until the power up initialization sequence is finished, including the expiration of
tDLLK and tZQinit.
5. After CKE is being registered high, wait minimum of Reset CKE Exit time, tXPR, before issuing the first MRS
command to load mode register. (tXPR=max (tXS ; 5 x tCK)
6. Issue MRS Command to load MR2 with all application settings. (To issue MRS command for MR2, provide
“Low” to BA0 and BA2, “High” to BA1.)
7. Issue MRS Command to load MR3 with all application settings. (To issue MRS command for MR3, provide
“Low” to BA2, “High” to BA0 and BA1.)
8. Issue MRS Command to load MR1 with all application settings and DLL enabled. (To issue "DLL Enable"
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command, provide "Low" to A0, "High" to BA0 and "Low" to BA1 – BA2).
9. Issue MRS Command to load MR0 with all application settings and “DLL reset”. (To issue DLL reset
command, provide "High" to A8 and "Low" to BA0-2).
10. Issue ZQCL command to starting ZQ calibration.
11. Wait for both tDLLK and tZQinit completed.
12. The DDR3 SDRAM is now ready for normal operation.
Reset and Power up initialization sequence
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Mode Register Definition
Mode Register MR0
The Mode Register MR0 stores the data for controlling various operating modes of DDR3 SDRAM. It controls
burst length, read burst type, CAS latency, test mode, DLL reset, WR and DLL control for precharge
power-down, which include various vendor specific options to make DDR3 SDRAM useful for various
applications. The mode register is written by asserting low on /CS, /RAS, /CAS, /WE, BA0, BA1 and BA2, while
controlling the states of address pins according to the table below.
BA2
BA1
0
BA0
00
A13
A12
0
PPD
A11
A10
A9
WR
A8
A7
DLL
TM
A6
A5
A4
CAS Latency
A3
A2
RBT
CL
A1
A0
BL
DLL Control
(for precharge PD)
A12
DLL Reset
A8
Mode
A7
No
0
Normal
0
Read Burst Type
A3
Slow exit (DLL off)
0
Yes
1
Test
1
Nibble sequential
0
Fast exit (DLL on)
1
Interleave
1
MRS Mode
BA1
BA0
BL
A1
A0
MR0
0
0
8
0
0
MR1
0
1
4 or 8 (OTF)
0
1
MR2
1
0
4
1
0
MR3
1
1
Reserved
1
1
WR for autoprecharge
A11
A10
A9
CAS Latency
A6
A5
A4
A2
Reserved
0
0
0
Reserved
0
0
0
0
5
0
0
1
Reserved
0
0
1
0
6
0
1
0
6
0
1
0
0
7
0
1
1
7
0
1
1
0
8
1
0
0
8
1
0
0
0
10
1
0
1
9
1
0
1
0
12
1
1
0
10
1
1
0
0
Reserved
1
1
1
11
1
1
1
0
Note1. BA2 and A13 are reserved for future use and must be programmed to 0 during MRS.
Note2. WR (write recovery for autoprecharge) min in clock cycles is calculated by dividing tWR (in ns) by tCK (in
ns) and rounding up to the next integer: WRmin[cycles] = Roundup(tWR[ns]/tCK[ns]). The WR value in
the mode register must be programmed to be equal or larger than WRmin. The programmed WR value
is used with tRP to determine tDAL.
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Burst Type (A3)
Burst Length
4 (chop)
8
R/W
A2
A1
A0
Sequential Addressing, A3=0
Interleave Addressing, A3=1
R
0
0
0
0123TTTT
0123TTTT
R
0
0
1
1230TTTT
1032TTTT
R
0
1
0
2301TTTT
2301TTTT
R
0
1
1
3012TTTT
3210TTTT
R
1
0
0
4567TTTT
4567TTTT
R
1
0
1
5674TTTT
5476TTTT
R
1
1
0
6745TTTT
6745TTTT
R
1
1
1
7456TTTT
7654TTTT
W
0
V
V
0123XXXX
0123XXXX
W
1
V
V
4567XXXX
4567XXXX
R
0
0
0
01234567
01234567
R
0
0
1
12305674
10325476
R
0
1
0
23016745
23016745
R
0
1
1
30127456
32107654
R
1
0
0
45670123
45670123
R
1
0
1
56741230
54761032
R
1
1
0
67452301
67452301
R
1
1
1
74563012
76543210
W
V
V
V
01234567
01234567
Note1. In case of burst length being fixed to 4 by MR0 setting, the internal write operation starts two clock
cycles earlier than for the BL8 mode. This means that the starting point for tWR and tWTR will be pulled
in by two clocks. In case of burst length being selected on-the-fly via A12 (/BC), the internal write
operation starts at the same point in time like a burst of 8 write operation. This means that during
on-the-fly control, the starting point for tWR and tWTR will not be pulled in by two clocks.
Note2. 0...7 bit number is value of CA[2:0] that causes this bit to be the first read during a burst.
Note3. T: Output driver for data and strobes are in high impedance.
Note4. V: a valid logic level (0 or 1), but respective buffer input ignores level on input pins.
Note5. X: Don’t Care.
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CAS Latency
The CAS Latency is defined by MR0 (bits A9-A11). CAS Latency is the delay, in clock cycles, between the
internal Read command and the availability of the first bit of output data. DDR3 SDRAM does not support any
half-clock latencies. The overall Read Latency (RL) is defined as Additive Latency (AL) + CAS Latency (CL); RL
= AL + CL.
Test Mode
The normal operating mode is selected by MR0 (bit A7 = 0) and rest bits set to the desired values.
Programming bit A7 to a ‘1’ places the DDR3 SDRAM into a test mode that is only used by the DRAM factory
and should NOT be used. No operations or functionality is specified if A7 = 1.
DLL Reset
The DLL Reset bit is self-clearing, meaning that it returns back to the value of ‘0’ after the DLL reset function
has been issued. Once the DLL is enabled, a subsequent DLL Reset should be applied. Any time that the DLL
reset function is used, tDLLK must be met before any functions that require the DLL can be used (i.e., Read
commands or ODT synchronous operations).
Write Recovery
The programmed WR value MR0 (bits A9, A10, and A11) is used for the auto precharge feature along with tRP
to determine tDAL. WR (write recovery for auto-precharge) min in clock cycles is calculated by dividing tWR (in
ns) by tCK (in ns) and rounding up to the next integer: WRmin[cycles] = Roundup(tWR[ns]/ tCK[ns]). The WR
must be programmed to be equal to or larger than tWR(min).
Precharge PD DLL
MR0 (bit A12) is used to select the DLL usage during precharge power-down mode. When MR0 (A12 = 0), or
‘slow-exit’, the DLL is frozen after entering precharge power-down (for potential power savings) and upon exit
requires tXPDLL to be met prior to the next valid command. When MR0 (A12 = 1), or ‘fast-exit’, the DLL is
maintained after entering precharge power-down and upon exiting power-down requires tXP to be met prior to
the next valid command.
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Mode Register MR1
The Mode Register MR1 stores the data for enabling or disabling the DLL, output driver strength, RTT_Nom
impedance, additive latency, write leveling enable and Qoff. The Mode Register 1 is written by asserting low on
/CS, /RAS, /CAS, /WE, high on BA0, low on BA1 and BA2, while controlling the states of address pins
according to the table below.
BA2
BA1
0
BA0
A13
A12
A11
A10
A9
A8
A7
A6
A5
0
Qoff
0
0
Rtt
0
Level
Rtt
D.I.C
01
Qoff
A12
Write leveling enable
A4
A3
AL
A2
A1
A0
Rtt
D.I.C
DLL
Output Driver
Impedance Control
A5
A1
RZQ/6
0
0
RZQ/7
0
1
A7
Reserved
1
0
Reserved
1
1
Output buffer enabled
0
Disabled
0
Output buffer disabled
1
Enabled
1
DLL Enable
A0
Enable
0
Disable
1
MRS Mode
BA1
BA0
Rtt_Nom
A9
A6
A2
Additive Latency
A4
A3
MR0
0
0
ODT disabled
0
0
0
AL disabled
0
0
MR1
0
1
RZQ/4
0
0
1
CL - 1
0
1
MR2
1
0
RZQ/2
0
1
0
CL - 2
1
0
MR3
1
1
RZQ/6
0
1
1
Reserved
1
1
RZQ/12
1
0
0
RZQ/8
1
0
1
Reserved
1
1
0
Reserved
1
1
1
Note1. BA2, A8, A10 and A13 are reserved for future use (RFU) and must be programmed to 0 during MRS.
Note2. Qoff: Outputs disabled - DQs, DQSs, /DQSs.
Note3. In Write leveling Mode (MR1[bit7] = 1) with MR1[bit12] = 1, all RTT_Nom settings are allowed; in Write
Leveling Mode (MR1[bit7] = 1) with MR1[bit12] = 0, only RTT_Nom settings of RZQ/2, RZQ/4 and
RZQ/6 are allowed.
DLL Enable
The DLL must be enabled for normal operation. DLL enable is required during power up initialization, and upon
returning to normal operation after having the DLL disabled. During normal operation (DLL-on) with MR1 (A0 =
0), the DLL is automatically disabled when entering self-refresh operation and is automatically re-enabled upon
exit of self-refresh operation. Any time the DLL is enabled and subsequently reset, tDLLK clock cycles must
occur before a read or synchronous ODT command can be issued to allow time for the internal clock to be
synchronized with the external clock. Failing to wait for synchronization to occur may result in a violation of the
tDQSCK, tAON or tAOF parameters. During tDLLK, CKE must continuously be registered high. DDR3 SDRAM
does not require DLL for any Write operation, except when RTT_WR is enabled and the DLL is required for
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proper ODT operation. For more detailed information on DLL Disable operation refers to “DLL-off Mode”.
The direct ODT feature is not supported during DLL-off mode. The on-die termination resistors must be
disabled by continuously registering the ODT pin low and/or by programming the RTT_Nom bits MR1{A9,A6,A2}
to {0,0,0} via a mode register set command during DLL-off mode. The dynamic ODT feature is not supported at
DLL-off mode. User must use MRS command to set Rtt_WR, MR2 {A10, A9} = {0,0}, to disable Dynamic ODT
externally.
ODT Rtt Values
DDR3 SDRAM is capable of providing two different termination values (Rtt_Nom and Rtt_WR). The nominal
termination value Rtt_Nom is programmed in MR1. A separate value (Rtt_WR) may be programmed in MR2 to
enable a unique RTT value when ODT is enabled during writes. The Rtt_WR value can be applied during writes
even when Rtt_Nom is disabled.
Additive Latency
Additive Latency (AL) operation is supported to make command and data bus efficient for sustainable
bandwidths in DDR3 SDRAM. In this operation, It allows a read or write command (either with or without
auto-precharge) to be issued immediately after the active command. The command is held for the time of the
Additive Latency (AL) before it is issued inside the device. The Read Latency (RL) is controlled by the sum of
the AL and CAS Latency (CL) register settings. Write Latency (WL) is controlled by the sum of the AL and CAS
Write Latency (CWL) register settings.
Write Leveling
For better signal integrity, DDR3 memory module adopted fly-by topology for the commands, addresses, control
signals, and clocks. The fly-by topology has the benefit of reducing the number of stubs and their length, but it
also causes flight time skew between clock and strobe at every DRAM on the DIMM. This makes it difficult for
the Controller to maintain tDQSS, tDSS, and tDSH specification. Therefore, the DDR3 SDRAM supports a
‘write leveling’ feature to allow the controller to compensate for skew.
Output Disable
The outputs may be enabled/disabled by MR1 (bit A12). When this feature is enabled (A12 = 1), all output pins
(DQs, DQS, /DQS, etc.) are disconnected from the device, thus removing any loading of the output drivers.
For normal operation, A12 should be set to ‘0’.
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Mode Register MR2
The Mode Register MR2 stores the data for controlling refresh related features, including RTT_WR impedance
and CAS write latency (CWL). The Mode Register 2 is written by asserting low on /CS, /RAS, /CAS, /WE, high
on BA1, low on BA0 and BA2, while controlling the states of address pins according to the table below.
BA2
BA1
BA0
A13
A12
A11
0
1
0
0
0
0
A10
A9
A8
A7
A6
0
SRT
ASR
Self refresh temp. range
A7
Normal operating temp. range
0
Extended temp. self refresh
1
Rtt_WR
Auto Self Refresh
A6
Manual SR reference
0
ASR Enabled
A5
A4
A3
A2
A1
CWL
A0
PASR
Partial Array Self Refresh
A2
A1
A0
Full Array
0
0
0
Half (BA[2:0]=000,001,010 & 011)
0
0
1
Quarter (BA[2:0]=000 & 001)
0
1
0
1/8th (BA[2:0]=000)
0
1
1
3/4th (BA[2:0]= 010,011,100,101,110 & 111)
1
0
0
Half (BA[2:0]=100,101,110 & 111)
1
0
1
Quarter (BA[2:0]=110 & 111)
1
1
0
1/8th (BA[2:0]=111)
1
1
1
1
MRS Mode
BA1
BA0
Rtt_WR
A10
A9
MR0
0
0
Dynamic ODT off
0
0
MR1
0
1
RZQ/4
0
1
CAS write latency (CWL)
A6
A4
A3
5 (tCK (avg) ≧ 2.5ns)
0
0
0
MR2
1
0
RZQ/2
1
0
MR3
1
1
Reserved
1
1
6 (2.5ns＞tCK (avg) ≧ 1.875ns)
0
0
1
7 (1.875ns＞ tCK (avg) ≧ 1.5ns)
0
1
0
8 (1.5ns＞tCK (avg) ≧ 1.25ns)
0
1
1
Reserved
1
0
0
Reserved
1
0
1
Reserved
1
1
0
Reserved
1
1
1
Note1. BA2, A8, A11 ~ A13 are RFU and must be programmed to 0 during MRS.
Note2. The Rtt_WR value can be applied during writes even when Rtt_Nom is disabled. During write leveling,
Dynamic ODT is not available.
CAS Write Latency (CWL)
The CAS Write Latency is defined by MR2 (bits A3-A5). CAS Write Latency is the delay, in clock cycles,
between the internal Write command and the availability of the first bit of input data. DDR3 SDRAM does not
support any half-clock latencies. The overall Write Latency (WL) is defined as Additive Latency (AL) + CAS
Write Latency (CWL); WL = AL + CWL.
Dynamic ODT (Rtt_WR)
DDR3 SDRAM introduces a new feature “Dynamic ODT”. In certain application cases and to further enhance
signal integrity on the data bus, it is desirable that the termination strength of the DDR3 SDRAM can be
changed without issuing an MRS command. MR2 Register locations A9 and A10 configure the Dynamic ODT
settings. In Write leveling mode, only RTT_Nom is available.
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Mode Register MR3
The Mode Register MR3 controls Multi Purpose Registers (MPR). The Mode Register 3 is written by asserting
low on CS, RAS, CAS, WE, high on BA1 and BA0, and low on BA2 while controlling the states of address pins
according to the table below.
BA2
BA1
BA0
A13
A12
A11
A10
A9
A8
A7
A6
A5
A4
A3
A2
0
1
1
0
0
0
0
0
0
0
0
0
0
0
MPR
MPR Operation
A2
Normal operation
0
Dataflow from MPR
1
A1
A0
MPR Location
MRS Mode
BA1
BA0
MPR Location
A1
A0
MR0
0
0
Predefined pattern
0
0
MR1
0
1
Reserved
0
1
MR2
1
0
Reserved
1
0
MR3
1
1
Reserved
1
1
Note1. BA2, A3 - A13 are reserved for future use (RFU) and must be programmed to 0 during MRS.
Note2. The predefined pattern will be used for read synchronization.
Note3. When MPR control is set for normal operation, MR3 A[2] = 0, MR3 A[1:0] will be ignored
Multi Purpose Register (MPR)
The Multi Purpose Register (MPR) function is used to Read out a predefined system timing calibration bit
sequence. To enable the MPR, a MODE Register Set (MRS) command must be issued to MR3 Register with
bit A2 = 1. Prior to issuing the MRS command, all banks must be in the idle state (all banks precharged and
tRP met). Once the MPR is enabled, any subsequent RD or RDA commands will be redirected to the Multi
Purpose Register. When the MPR is enabled, only RD or RDA commands are allowed until a subsequent MRS
command is issued with the MPR disabled (MR3 bit A2 = 0). Power-down mode, self-refresh and any other
non-RD/RDA command is not allowed during MPR enable mode. The RESET function is supported during
MPR enable mode.
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Package Description: 168Ball-FBGA
Solder ball: Lead free (Sn-Ag-Cu)
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Revision History
Revision 0.1 (Jul. 2012)
-First release.
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