24C04A, 24C08A, 24C16A Two-Wire Serial EEPROM 4K, 8K and 16K (8-bit wide) FEATURES Low voltage and low power operations: FT24C04A/08A/16A: VCC = 1.8V to 5.5V Maximum Standby current < 1µA (typically 0.02µA and 0.06µA @ 1.8V and 5.5V respectively). 16 bytes page write mode. Partial page write operation allowed. Internally organized: 512 8 (4K), 1024 8 (8K), 2048 8 (16K). Standard 2-wire bi-directional serial interface. Schmitt trigger, filtered inputs for noise protection. Self-timed Write Cycle (5ms maximum). 1 MHz (5V), 400 kHz (1.8V, 2.5V, 2.7V) Compatibility. Automatic erase before write operation. Write protect pin for hardware data protection. High reliability: typically 1, 000,000 cycles endurance. 100 years data retention. Industrial temperature range (-40o C to 85o C). Standard 8-pin DIP/SOP/TSSOP/DFN/MSOP and 5-pin SOT-23/TSOT-23 Pb-free packages. DESCRIPTION The FT24C04A/08A/16A series are 4096/8192/16384 bits of serial Electrical Erasable and Programmable Read Only Memory, commonly known as EEPROM. They are organized as 512/1024/2048 words of 8 bits (1 byte) each. The devices are fabricated with proprietary advanced CMOS process for low power and low voltage applications. These devices are available in standard 8-lead DIP, 8-lead SOP, 8-lead TSSOP, 8-lead DFN, 8-lead MSOP, and 5-lead SOT23/TSOT-23 packages. A standard 2-wire serial interface is used to address all read and write functions. Our extended VCC range (1.8V to 5.5V) devices enables wide spectrum of applications. PIN CONFIGURATION Pin Name A2, A1, A0 SDA SCL WP NC Pin Function Device Address Inputs Serial Data Input / Open Drain Output Serial Clock Input Write Protect No-Connect © 2009 Fremont Micro Devices Inc. DS3001M-page1 24C04A, 24C08A, 24C16A All these packaging types come in conventional or Pb-free certified. FT24C04A/08A/16A A0 A1 A2 GND 1 8 2 7 3 6 4 5 8L DIP 8L SOP 8L TSSOP 8L DFN 8L MSOP VCC WP SCL SDA FT24C04A/08A/16A SCL GND SDA 1 5 WP 4 VCC 2 3 SOT-23-5 TSOT-23-5 ABSOLUTE MAXIMUM RATINGS Industrial operating temperature: Storage temperature: Input voltage on any pin relative to ground: Maximum voltage: ESD protection on all pins: -40oC to 85oC -50oC to 125oC -0.3V to VCC + 0.3V 8V >2000V * Stresses exceed those listed under “Absolute Maximum Rating” may cause permanent damage to the device. Functional operation of the device at conditions beyond those listed in the specification is not guaranteed. Prolonged exposure to extreme conditions may affect device reliability or functionality. DS3001M-page2 © 2009 Fremont Micro Devices Inc. 24C04A, 24C08A, 24C16A PIN DESCRIPTIONS (A) SERIAL CLOCK (SCL) The rising edge of this SCL input is to latch data into the EEPROM device while the falling edge of this clock is to clock data out of the EEPROM device. (B) DEVICE / CHIP SELECT ADDRESSES (A2, A1, A0) These are the chip select input signals for the serial EEPROM devices. Typically, these signals are hardwired to either VIH or VIL. If left unconnected, they are internally recognized as VIL. FT24C04A has A0 pin as no-connect. FT24C08A has both A0 and A1 pins as no-connect. For FT24C16A, all device address pins (A0-A2) are noconnect. (C) SERIAL DATA LINE (SDA) SDA data line is a bi-directional signal for the serial devices. It is an open drain output signal and can be wiredOR with other open-drain output devices. (D) WRITE PROTECT (WP) The FT24C04A/08A/16A devices have a WP pin to protect the whole EEPROM array from programming. Programming operations are allowed if WP pin is left un-connected or input to VIL. Conversely all programming functions are disabled if WP pin is connected to VIH or VCC. Read operations is not affected by the WP pin’s input level. Table A Device Chip Select/Device Address Pins Used No-Connect Pins Max number of similar devices on the same bus FT24C04A A2, A1 A0 4 FT24C08A A2, A1, A0 2 FT24C16A (None) A2, A1, A0 1 MEMORY ORGANIZATION The FT24C04A/08A/16A devices have 32/64/128 pages respectively. Since each page has 16 bytes, random word addressing to FT24C04A/08A/16A will require 9/10/11 bits data word addresses respectively. DEVICE OPERATION (A) SERIAL CLOCK AND DATA TRANSITIONS The SDA pin is typically pulled to high by an external resistor. Data is allowed to change only when Serial clock SCL is at VIL. Any SDA signal transition may interpret as either a START or STOP condition as described below. (B) START CONDITION With SCL VIH, a SDA transition from high to low is interpreted as a START condition. All valid commands must begin with a START condition. © 2009 Fremont Micro Devices Inc. DS3001M-page3 24C04A, 24C08A, 24C16A (C) STOP CONDITION With SCL VIH, a SDA transition from low to high is interpreted as a STOP condition. All valid read or write commands end with a STOP condition. The device goes into the STANDBY mode if it is after a read command. A STOP condition after page or byte write command will trigger the chip into the STANDBY mode after the selftimed internal programming finish. (D) ACKNOWLEDGE The 2-wire protocol transmits address and data to and from the EEPROM in 8 bit words. The EEPROM acknowledges the data or address by outputting a "0" after receiving each word. The ACKNOWLEDGE signal occurs on the 9th serial clock after each word. (E) STANDBY MODE The EEPROM goes into low power STANDBY mode after a fresh power up, after receiving a STOP bit in read mode, or after completing a self-time internal programming operation. Figure 1: Timing diagram for START and STOP conditions SCL SDA START Condition Data Valid Data Transition STOP Condition Figure 2: Timing diagram for output ACKNOWLEDGE START Condition SCL Data in Data out DS3001M-page4 ACK © 2009 Fremont Micro Devices Inc. 24C04A, 24C08A, 24C16A DEVICE ADDRESSING The 2-wire serial bus protocol mandates an 8 bits device address word after a START bit condition to invoke valid read or write command. The first four most significant bits of the device address must be 1010, which is common to all serial EEPROM devices. The next three bits are device address bits. These three device address bits (5th, 6th and 7th) are to match with the external chip select/address pin states. If a match is made, the EEPROM device outputs an ACKNOWLEDGE signal after the 8th read/write bit, otherwise the chip will go into STANDBY mode. However, matching may not be needed for some or all device address bits (5th, 6th and 7th) as noted below. The last or 8th bit is a read/write command bit. If the 8th bit is at VIH then the chip goes into read mode. If a “0” is detected, the device enters programming mode. FT24C04A uses A2 (5th) and A1 (6th) device address bits. Only four FT24C04A devices can be wired-OR on the same 2-wire bus. Their corresponding chip select address pins A2 and A1 must be hard wired and coded from 00 (b) to 11 (b). Chip select address pin A0 is not used. FT24C08A uses only A2 (5th) device address bit. Only two FT24C08A devices can be wired-OR on the same 2-wire bus. Their corresponding chip select address pin A2 must be hard-wired and coded from 0 (b) to 1 (b). Chip select address pins A1 and A0 are not used. FT24C16A does not use any device address bit. Only one FT24C16A device can be used on the on 2-wire bus. Chip Select address pins A2, A1, and A0 are not used. WRITE OPERATIONS (A) BYTE WRITE A byte write operation starts when a micro-controller sends a START bit condition, follows by a proper EEPROM device address and then a write command. If the device address bits match the chip select address, the EEPROM device will acknowledge at the 9th clock cycle. The micro-controller will then send the rest of the lower 8 bits word address. At the 18th cycle, the EEPROM will acknowledge the 8-bit address word. The micro-controller will then transmit the 8 bit data. Following an ACKNOWLDEGE signal from the EEPROM at the 27th clock cycle, the micro-controller will issue a STOP bit. After receiving the STOP bit, the EEPROM will go into a self-timed programming mode during which all external inputs will be disabled. After a programming time of TWC, the byte programming will finish and the EEPROM device will return to the STANDBY mode. (B) PAGE WRITE A page write is similar to a byte write with the exception that one to sixteen bytes can be programmed along the same page or memory row. All FT24C04A/08A/16A are organized to have 16 bytes per memory row or page. With the same write command as the byte write, the micro-controller does not issue a STOP bit after sending the 1st byte data and receiving the ACKNOWLEDGE signal from the EEPROM on the 27th clock cycle. Instead it sends out a second 8-bit data word, with the EEPROM acknowledging at the 36th cycle. This data sending and EEPROM acknowledging cycle repeats until the micro-controller sends a STOP bit after the n 9th clock cycle. After which the EEPROM device will go into a self-timed partial or full page programming mode. After the page programming completes after a time of TWC, the devices will return to the STANDBY mode. © 2009 Fremont Micro Devices Inc. DS3001M-page5 24C04A, 24C08A, 24C16A The least significant 4 bits of the word address (column address) increments internally by one after receiving each data word. The rest of the word address bits (row address) do not change internally, but pointing to a specific memory row or page to be programmed. The first page write data word can be of any column address. Up to 16 data words can be loaded into a page. If more then 16 data words are loaded, the 17th data word will be loaded to the 1st data word column address. The 18th data word will be loaded to the 2nd data word column address and so on. In other word, data word address (column address) will “roll” over the previously loaded data. (C) ACKNOWLEDGE POLLING ACKNOWLEDGE polling may be used to poll the programming status during a self-timed internal programming. By issuing a valid read or write address command, the EEPROM will not acknowledge at the 9th clock cycle if the device is still in the self-timed programming mode. However, if the programming completes and the chip has returned to the STANDBY mode, the device will return a valid ACKNOWLEDGE signal at the 9th clock cycle. READ OPERATIONS The read command is similar to the write command except the 8th read/write bit in address word is set to “1”. The three read operation modes are described as follows: (A) CURRENT ADDRESS READ The EEPROM internal address word counter maintains the last read or write address plus one if the power supply to the device has not been cut off. To initiate a current address read operation, the micro-controller issues a START bit and a valid device address word with the read/write bit (8th) set to “1”. The EEPROM will response with an ACKNOWLEDGE signal on the 9th serial clock cycle. An 8-bit data word will then be serially clocked out. The internal address word counter will then automatically increase by one. For current address read the microcontroller will not issue an ACKNOWLEDGE signal on the 18th clock cycle. The micro-controller issues a valid STOP bit after the 18th clock cycle to terminate the read operation. The device then returns to STANDBY mode. (B) SEQUENTIAL READ The sequential read is very similar to current address read. The micro-controller issues a START bit and a valid device address word with read/write bit (8th) set to “1”. The EEPROM will response with an ACKNOWLEDGE signal on the 9th serial clock cycle. An 8-bit data word will then be serially clocked out. Meanwhile the internally address word counter will then automatically increase by one. Unlike current address read, the micro-controller sends an ACKNOWLEDGE signal on the 18th clock cycle signaling the EEPROM device that it wants another byte of data. Upon receiving the ACKNOWLEDGE signal, the EEPROM will serially clocked out an 8-bit data word based on the incremented internal address counter. If the micro-controller needs another data, it sends out an ACKNOWLEDGE signal on the 27th clock cycle. Another 8-bit data word will then be serially clocked out. This sequential read continues as long as the micro-controller sends an ACKNOWLEDGE signal after receiving a new data word. When the internal address counter reaches its maximum valid address, it rolls over to the beginning of the memory array address. Similar to current address read, the micro-controller can terminate the sequential read by not acknowledging the last data word received, but sending a STOP bit afterwards instead. (C) RANDOM READ Random read is a two-steps process. The first step is to initialize the internal address counter with a target read address using a “dummy write” instruction. The second step is a current address read. To initialize the internal address counter with a target read address, the micro-controller issues a START bit first, follows by a valid device address with the read/write bit (8th) set to “0”. The EEPROM will then acknowledge. The micro-controller will then send the address word. Again the EEPROM will acknowledge. Instead of sending a valid written data to the EEPROM, the micro-controller performs a current address read instruction to read the data. Note that once a START bit is issued, the EEPROM will reset the internal programming process and continue to execute the new instruction - which is to read the current address. DS3001M-page6 © 2009 Fremont Micro Devices Inc. 24C04A, 24C08A, 24C16A © 2009 Fremont Micro Devices Inc. DS3001M-page7 24C04A, 24C08A, 24C16A Figure 8: SCL and SDA Bus Timing AC CHARACTERISTICS Symbol 1.8 V Parameter Min fSCL tLOW tHIGH tI tAA Clock frequency, SCL tHD.STA tSU.STA tHD.DAT tSU.DAT tR tF tSU.STO tDH 1.3 Clock pulse width high 0.6 0.3 µs 0.4 0.2 120 µs ns 0.55 µs µs 0.6 0.25 µs START set-up time 0.6 0.25 µs 0 0 µs 100 100 ns Input fall time 0.9 kHz 0.5 (1) 0.3 0.3 µs (1) 300 100 ns Input rise time STOP set-up time 0.6 0.25 µs Date out hold time 50 50 ns Write cycle time Endurance 1000 0.4 180 Unit Max 1.3 Data in set-up time (1) Min Clock low to data out valid Time the bus must be free before a new transmission can start(1) START hold time Data in hold time WR Max 400 Clock pulse width low Noise suppression time(1) tBUF 2.5-5.0 V o 25 C, Page Mode, 3.3V 5 5 1,000,000 ms Write Cycles Notes: 1. This Parameter is expected by characterization but are not fully screened by test. 2. AC Measurement conditions: RL (Connects to Vcc): 1.3KΩ Input Pulse Voltages: 0.3Vcc to 0.7Vcc Input and output timing reference Voltages: 0.5Vcc DS3001M-page8 © 2009 Fremont Micro Devices Inc. 24C04A, 24C08A, 24C16A DC CHARACTERISTICS Symbol Parameter Test Conditions Min Typical 1.8 Max Units 5.5 V VCC1 24CA supply VCC ICC Supply read current VCC @ 5.0V SCL = 400 kHz 0.5 1.0 mA ICC Supply write current VCC @ 5.0V SCL = 400 kHz 2.0 3.0 mA ISB1 Supply current VCC @ 1.8V, VIN = VCC or VSS 1.0 µA ISB2 Supply current VCC @ 2.5V, VIN = VCC or VSS 1.0 µA ISB3 Supply current VCC @ 5.0V, VIN = VCC or VSS 1.0 µA IIL Input leakage current VIN = VCC or VSS 3.0 µA ILO Output leakage current VIN = VCC or VSS 3.0 µA VIL Input low level -0.6 VCC 0.3 V VIH Input high level VCC0.7 VCC + 0.5 V VOL1 Output low level VCC @ 1.8V, IOL = 0.15 mA 0.2 V VOL2 Output low level VCC @ 3.0V, IOL = 2.1 mA 0.4 V © 2009 Fremont Micro Devices Inc. 0.07 DS3001M-page9 24C04A, 24C08A, 24C16A ORDER CODE: FT24CXXA – XXX - X Packaging B: Tube T: Tape and Reel Temperature Range U: -40 to 85 oC Package D: DIP S: SOP M: MSOP T: TSSOP L: SOT23 P: TSOT23 N: DFN Option G: Green Package RoHS Compliant R: RoHS Compliant ORDER INFORMATION Order code FT24C04A-UDG-B FT24C04A-UDR-B FT24C04A-USG-B FT24C04A-USG-T FT24C04A-USR-B FT24C04A-USR-T FT24C04A-UTG-B FT24C04A-UTG-T FT24C04A-UTR-B FT24C04A-UTR-T FT24C04A-ULG-T FT24C04A-ULR-T FT24C04A-UPG-T FT24C04A-UPR-T DS3001M-page10 Vcc Temperature Range Package DIP8 SOP8 1.8v-5.5v -40-850C TSSOP8 SOT23-5 TSOT23-5 Option Green Package RoHS Green Package Green Package RoHS RoHS Green Package Green Package RoHS RoHS Green Package RoHS Green Package RoHS Packaging Tube Tube Tube T/R Tube T/R Tube T/R Tube T/R T/R T/R T/R T/R © 2009 Fremont Micro Devices Inc. 24C04A, 24C08A, 24C16A ORDER INFORMATION（CONTINUED） Order code FT24C08A-UDG-B FT24C08A-UDR-B FT24C08A-USG-B FT24C08A-USG-T FT24C08A-USR-B FT24C08A-USR-T FT24C08A-UTG-B FT24C08A-UTG-T FT24C08A-UTR-B FT24C08A-UTR-T FT24C08A-ULG-T FT24C08A-ULR-T FT24C08A-UPG-T FT24C08A-UPR-T FT24C16A-UDG-B FT24C16A-UDR-B FT24C16A-USG-B FT24C16A-USG-T FT24C16A-USR-B FT24C16A-USR-T FT24C16A-UTG-B FT24C16A-UTG-T FT24C16A-UTR-B FT24C16A-UTR-T FT24C16A-ULG-T FT24C16A-ULR-T FT24C16A-UPG-T FT24C16A-UPR-T Vcc Temperature Range Package DIP8 SOP8 TSSOP8 SOT23-5 1.8v-5.5v © 2009 Fremont Micro Devices Inc. -40-850C TSOT23-5 DIP8 SOP8 TSSOP8 SOT23-5 TSOT23-5 Option Green Package RoHS Green Package Green Package RoHS RoHS Green Package Green Package RoHS RoHS Green Package RoHS Green Package RoHS Green Package RoHS Green Package Green Package RoHS RoHS Green Package Green Package RoHS RoHS Green Package RoHS Green Package RoHS Packaging Tube Tube Tube T/R Tube T/R Tube T/R Tube T/R T/R T/R T/R T/R Tube Tube Tube T/R Tube T/R Tube T/R Tube T/R T/R T/R T/R T/R DS3001M-page11 24C04A, 24C08A, 24C16A DIP8 PACKAGE OUTLINE DIMENSIONS Symbol A A1 A2 B B1 C D E E1 e L E2 DS3001M-page12 Dimensions In Millimeters Dimensions In Inches Min Max Min Max 3.710 0.510 3.200 0.380 4.310 0.146 0.020 0.126 0.015 0.170 3.600 0.570 1.524（BSC） 0.360 9.400 6.600 7.920 2.540 (BSC) 3.000 3.600 8.400 9.000 0.204 9.000 6.200 7.320 0.142 0.022 0.060（BSC） 0.008 0.354 0.244 0.288 0.014 0.370 0.260 0.312 0.100（BSC） 0.118 0.331 0.142 0.354 © 2009 Fremont Micro Devices Inc. 24C04A, 24C08A, 24C16A SOP8 PACKAGE OUTLINE DIMENSIONS Dimensions In Millimeters Dimensions In Inches Symbol A Min Max Min Max 1.350 1.750 0.053 0.069 A1 0.100 0.250 0.004 0.010 A2 1.350 1.550 0.053 0.061 b 0.330 0.510 0.013 0.020 c 0.170 0.250 0.006 0.010 D 4.700 5.100 0.185 0.200 E 3.800 4.000 0.150 0.157 E1 5.800 6.200 0.228 e 1.270 (BSC) 0.244 0.050 (BSC) L 0.400 1.270 0.016 0.050 θ 0° 8° 0° 8° © 2009 Fremont Micro Devices Inc. DS3001M-page13 24C04A, 24C08A, 24C16A TSSOP8 PACKAGE OUTLINE DIMENSIONS Symbol D E b c E1 A A2 A1 e L H θ Dimensions In Millimeters Dimensions In Inches Min Max Min Max 2.900 4.300 0.190 0.090 6.250 3.100 4.500 0.300 0.200 6.550 1.100 1.000 0.150 0.114 0.169 0.007 0.004 0.246 0.122 0.177 0.012 0.008 0.258 0.043 0.039 0.006 0.800 0.020 0.031 0.001 0.65 (BSC) 0.500 0.026 (BSC) 0.700 0.020 0.25 (TYP) 1° 0.028 0.01 (TYP) 7° 1° 7° MSOP8 PACKAGE OUTLINE DIMENSIONS DS3001M-page14 © 2009 Fremont Micro Devices Inc. 24C04A, 24C08A, 24C16A Dimensions In Millimeters Dimensions In Inches Symbol Min Max Min Max A A1 A2 b c D e E E1 L θ 0.820 0.020 0.750 0.250 0.090 2.900 1.100 0.150 0.950 0.380 0.230 3.100 0.320 0.001 0.030 0.010 0.004 0.114 0.043 0.006 0.037 0.015 0.009 0.122 3.100 5.050 0.800 6° 0.114 0.187 0.016 0° 0.65 (BSC) 2.900 4.750 0.400 0° 0.026 (BSC) 0.122 0.199 0.031 6° DFN8 PACKAGE OUTLINE DIMENSIONS © 2009 Fremont Micro Devices Inc. DS3001M-page15 24C04A, 24C08A, 24C16A Symbol A A1 b c D D2 e Nd E E2 L h L/F Surface Electroplate Dimension（mil） DS3001M-page16 Min Dimensions In Millimeters Nom Max 0.70 0.18 0.18 1.90 0.75 0.02 0.25 0.20 2.00 0.80 0.05 0.03 0.25 2.10 2.90 1.50REF 0.50BSC 1.50BSC 3.00 1.60REF 0.40 0.25 3.10 0.30 0.20 0.50 0.30 NIPdAu (Nickel, Pd, Metal) 67*75 © 2009 Fremont Micro Devices Inc. 24C04A, 24C08A, 24C16A SOT-23-5 PACKAGE OUTLINE DIMENSIONS Symbol Dimensions In Millimeters Dimensions In Inches Min Max Min Max A A1 A2 b c D E E1 e e1 L 1.050 0.000 1.050 0.300 0.100 2.820 1.500 2.650 1.250 0.100 1.150 0.500 0.200 3.020 1.700 2.950 0.041 0.000 0.041 0.012 0.004 0.111 0.059 0.104 0.049 0.004 0.045 0.020 0.008 0.119 0.067 0.116 1.800 0.300 2.000 0.600 0.071 0.012 0.079 0.024 0° 8° 0° 6° 0.95 (BSC) © 2009 Fremont Micro Devices Inc. 0.037 (BSC) DS3001M-page17 24C04A, 24C08A, 24C16A TSOT-23-5 PACKAGE OUTLINE DIMENSIONS Symbol A A1 A2 b c D E E1 e e1 L DS3001M-page18 Dimensions In Millimeters Dimensions In Inches Min Max Min Max 0.700 0.000 0.700 0.350 0.080 2.820 1.600 2.650 0.900 0.100 0.800 0.500 0.200 3.020 1.700 2.950 0.028 0.000 0.028 0.014 0.003 0.111 0.063 0.104 0.035 0.004 0.031 0.020 0.008 0.119 0.067 0.116 0.95 (BSC) 1.90 (BSC) 0.037 (BSC) 0.075 (BSC) 0.300 0.600 0.012 0.024 0° 8° 0° 8° © 2009 Fremont Micro Devices Inc. 24C04A, 24C08A, 24C16A © 2009 Fremont Micro Devices Inc. DS3001M-page19 24C04A, 24C08A, 24C16A Information furnished is believed to be accurate and reliable. However, Fremont Micro Devices.,Ltd.(FMD) assumes no responsibility for the consequences of use of such information or for any infringement of patents of other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent rights of Fremont Micro Devices.,Ltd.(FMD). Specifications mentioned in this publication are subject to change without notice. This publication supersedes and replaces all information previously supplied. Fremont Micro Devices.,Ltd.(FMD) products are not authorized for use as critical components in life support devices or systems without express written approval of Fremont Micro Devices.,Ltd.(FMD). The FMD logo is a registered trademark of Fremont Micro Devices.,Ltd. All other names are the property of their respective owners ©2007Fremont Micro Devices.,Ltd.-All rights reserved www.fremontmicro.com DS3001M-page20 © 2009 Fremont Micro Devices Inc.