DATASHEET ICS664-03 DIGITAL VIDEO CLOCK SOURCE Description Features The ICS664-03 provides clock generation and conversion for clock rates commonly needed in HDTV digital video equipment. The ICS664-03 uses the latest PLL technology to provide excellent phase noise and long term jitter performance for superior synchronization and S/N ratio. • • • • • • • • • The ICS664-03 is suitable for Digital Video STB and DTV applications. For Transmitter application use ICS664-01 or ICS664-02. For audio sampling clocks generated from 27 MHz, use the ICS661. Packaged in 16-pin TSSOP Pb (lead) free package, RoHS compliant Clock or crystal input provides flexibility Low phase noise supports enhanced SNR Lowest jitter in class at 100 ps Exact (0 ppm) multiplication ratios Power-down mode lowers power consumption Improved phase noise over ICS660 Provides High definition Video clocks for 720p, 1080i and 1080p YUV standards Please contact IDT if you have a requirement for an input and output frequency not included in this document. IDT can rapidly modify this product to meet special requirements. Block Diagram VDD (P2) VDD (P3) VDDO VDD (P14) X2 Crystal Oscillator X1/REFIN SELIN S3:0 PLL Clock Synthesis CLK 4 GND (P5) GND (P6) IDT™ / ICS™ DIGITAL VIDEO CLOCK SOURCE 1 GND (P13) ICS664-03 REV D 051310 ICS664-03 DIGITAL VIDEO CLOCK SOURCE CLOCK SYNTHESIZER Pin Assignment Output Clock Selection Table 1 27 27 (passthrough) 1 0 27 74.25 1 1 27 74.175824 1 0 0 13.5 74.25 1 0 1 13.5 74.175824 0 1 1 0 27 148.5000 0 1 1 1 27 148.351648 1 0 0 0 74.25 54 1 0 0 1 74.175824 54 1 0 1 0 74.25 27 1 0 1 1 74.175824 27 1 1 0 0 54 74.25 1 1 0 1 54 74.175824 1 1 1 0 54 13.5 1 1 1 1 27 13.5 S1 S0 0 0 0 0 0 0 0 GND 0 0 0 0 SELIN 0 0 16 X2 VDD 2 15 N/C VDD 3 14 VDD S0 4 13 12 5 Output Frequency (MHz) S2 1 GND Input Frequency (MHz) S3 X1/REFIN GND 6 11 VDDO S3 7 10 S1 S2 8 9 CLK 16-pin TSSOP Power down Pin Descriptions Pin Number Pin Name Pin Type 1 X1/REFIN Input 2 VDD Power Power supply for crystal oscillator. 3 VDD Power Power supply for PLL. Pin Description Connect this pin to a crystal or clock input 4 S0 Input Output frequency selection. Determines output frequency per table above. Internal pull-up. 5 GND Power Ground for PLL. 6 GND Power Ground for PLL for Crystal Osillator. 7 S3 Input Output frequency selection. Determines output frequency per table above. Internal pull-up. Output frequency selection. Determines output frequency per table above. Internal pull-up. 8 S2 Input 9 CLK Output Clock output. 10 S1 Input Output frequency selection. Determines output frequency per table above. Internal pull-up. 11 VDDO Power Power supply for output stage. 12 SEL Input Low for clock input, high for crystal. Internal pull-up. 13 GND Power Ground for Output. 14 VDD Power Power supply. 15 NC — 16 X2 Input No connect. Do not connect to anything. Connect this pin to a crystal. Leave open if using a clock input. IDT™ / ICS™ DIGITAL VIDEO CLOCK SOURCE 2 ICS664-03 REV D 051310 ICS664-03 DIGITAL VIDEO CLOCK SOURCE CLOCK SYNTHESIZER Application Information Series Termination Resistor Crystal Load Capacitors Clock output traces should use series termination. To series terminate a 50Ω trace (a commonly used trace impedance), place a 33Ω resistor in series with the clock line, as close to the clock output pin as possible. The nominal impedance of the clock output is 20Ω. If a crystal is used, the device crystal connections should include pads for capacitors from X1 to ground and from X2 to ground. These capacitors are used to adjust the stray capacitance of the board to match the nominally required crystal load capacitance. To reduce possible noise pickup, use very short PCB traces (and no vias) been the crystal and device. Decoupling Capacitors As with any high-performance mixed-signal IC, the ICS664-03 must be isolated from system power supply noise to perform optimally. The value of the load capacitors can be roughly determined by the formula C = 2(CL - 6) where C is the load capacitor connected to X1 and X2, and CL is the specified value of the load capacitance for the crystal. A typical crystal CL is 18 pF, so C = 2(18 - 6) = 24 pF. Because these capacitors adjust the stray capacitance of the PCB, check the output frequency using your final layout to see if the value of C should be changed. Decoupling capacitors of 0.01µF must be connected between each VDD and the PCB ground plane. To further guard against interfering system supply noise, the ICS664-03 should use one common connection to the PCB power plane as shown in the diagram on the next page. The ferrite bead and bulk capacitor help reduce lower frequency noise in the supply that can lead to output clock phase modulation. PCB Layout Recommendations For optimum device performance and lowest output phase noise, the following guidelines should be observed. Recommended Power Supply Connection for Optimal Device Performance 1) Each 0.01µF decoupling capacitor should be mounted on the component side of the board as close to the VDD pin as possible. No vias should be used between decoupling capacitor and VDD pin. The PCB trace to VDD pin should be kept as short as possible, as should the PCB trace to the ground via. Distance of the ferrite bead and bulk decoupling from the device is less critical. V D D P in C onnection to 3.3V P ow er P lane Ferrite Bead B ulk D ecoupling C apacitor (such as 1 F Tantalum ) 0.01 V D D P in V D D P in 2) The external crystal should be mounted next to the device with short traces. The X1 and X2 traces should not be routed next to each other with minimum spaces, instead they should be separated and away from other traces. F D ecoupling C apacitors 3) To minimize EMI and obtain the best signal integrity, the 33Ω series termination resistor should be placed close to the clock output. All power supply pins must be connected to the same voltage, except VDDO, which may be connected to a lower voltage in order to change the output level. 4) An optimum layout is one with all components on the same side of the board, minimizing vias through other signal layers (the ferrite bead and bulk decoupling capacitor can be mounted on the back). Other signal traces should be routed away from the ICS664-03. This includes signal traces just underneath the device, or on layers adjacent to the ground plane layer used by the device. To achieve the absolute minimum jitter, power the part with a dedicated LDO regulator, which will provide high isolation from power supply noise. Many companies produce very small, inexpensive regulators; an example is the National Semiconductor LP2985. IDT™ / ICS™ DIGITAL VIDEO CLOCK SOURCE 3 ICS664-03 REV D 051310 ICS664-03 DIGITAL VIDEO CLOCK SOURCE CLOCK SYNTHESIZER Absolute Maximum Ratings Stresses above the ratings listed below can cause permanent damage to the ICS664-03. These ratings, which are standard values for IDT commercially rated parts, are stress ratings only. Functional operation of the device at these or any other conditions above those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods can affect product reliability. Electrical parameters are guaranteed only over the recommended operating temperature range. Item Rating Supply Voltage, VDD 5.5 V All Inputs and Outputs -0.5 V to VDD+0.5 V Ambient Operating Temperature 0 to +70° C Storage Temperature -65 to +150° C Junction Temperature 125° C Soldering Temperature 260° C Recommended Operation Conditions Parameter Min. Ambient Operating Temperature Power Supply Voltage (measured in respect to GND) Typ. Max. Units 0 +70 °C +3.0 +3.6 V DC Electrical Characteristics Unless stated otherwise, VDD = 3.3 V ±10%, Ambient Temperature 0 to +70° C Parameter Symbol Conditions VDD Operating Voltage Min. Typ. 3.0 VDDO 2.5 Units 3.6 V VDD IDD Input High Voltage VIH Input Low Voltage VIL Output High Voltage VOH IOH = -4 mA VDD-0.4 V Output High Voltage VOH IOH = -20 mA 2.4 V Output Low Voltage VOL IOL = 20 mA Short Circuit Current IOS Each output CIN Internal Pull-up Resistor RPU mA 2 V 0.8 ZOUT Input Capacitance IDT™ / ICS™ DIGITAL VIDEO CLOCK SOURCE 35 V Supply Current Nominal Output Impedance No Load Max. Input pins 4 0.4 ±65 V V mA 20 Ω 7 pF 120 kΩ ICS664-03 REV D 051310 ICS664-03 DIGITAL VIDEO CLOCK SOURCE CLOCK SYNTHESIZER AC Electrical Characteristics Unless stated otherwise, VDD = 3.3 V ±10%, Ambient Temperature 0 to +70° C Parameter Symbol Conditions Min. Typ. Crystal Frequency Max. Units 28 MHz Output Clock Rise Time tOR 20% to 80%, 15 pF load 1.5 ns Output Clock Fall Time tOF 80% to 20%, 15 pF load 1.5 ns Output Duty Cycle tOD at VDD/2, 15 pF load 60 % Power-up Time tPU Valid power on to valid output 1 ms Power-down Time tPD Power off to clock disable 10 µs 100 ps p-p 40 Jitter, short term 49 to 51 Jitter, long term 10 µs delay 200 ps p-p Single Sideband Phase Noise 10 kHz offset -120 dBc 0 ppm Actual Mean Frequency Error versus Target Thermal Characteristics Parameter Thermal Resistance Junction to Ambient Thermal Resistance Junction to Case IDT™ / ICS™ DIGITAL VIDEO CLOCK SOURCE Symbol Conditions Min. Typ. Max. Units θJA Still air 78 ° C/W θJA 1 m/s air flow 70 ° C/W θJA 3 m/s air flow 68 ° C/W 37 ° C/W θJC 5 ICS664-03 REV D 051310 ICS664-03 DIGITAL VIDEO CLOCK SOURCE CLOCK SYNTHESIZER Package Outline and Package Dimensions (16-pin TSSOP, 4.40 mm Body, 0.65 mm Pitch) Package dimensions are kept current with JEDEC Publication No. 95, MO-153 Millimeters 16 Symbol E1 A A1 A2 b C D E E1 e L α aaa E IN D EX AR EA 1 2 D A 2 Min Inches Max -1.20 0.05 0.15 0.80 1.05 0.19 0.30 0.09 0.20 4.90 5.1 6.40 BASIC 4.30 4.50 0.65 Basic 0.45 0.75 0° 8° -0.10 Min Max -0.047 0.002 0.006 0.032 0.041 0.007 0.012 0.0035 0.008 0.193 0.201 0.252 BASIC 0.169 0.177 0.0256 Basic 0.018 0.030 0° 8° -0.004 A A 1 c -C e b S E A TIN G P LA N E L aaa C Ordering Information Part / Order Number Marking Shipping Packaging Package Temperature 664G-03LF 664G03LF Tubes 16-pin TSSOP 0 to +70° C 664G-03LFT 664G03LF Tape and Reel 16-pin TSSOP 0 to +70° C “LF” denotes Pb (lead) free package. While the information presented herein has been checked for both accuracy and reliability, Integrated Device Technology (IDT) assumes no responsibility for either its use or for the infringement of any patents or other rights of third parties, which would result from its use. No other circuits, patents, or licenses are implied. This product is intended for use in normal commercial applications. Any other applications such as those requiring extended temperature range, high reliability, or other extraordinary environmental requirements are not recommended without additional processing by IDT. IDT reserves the right to change any circuitry or specifications without notice. IDT does not authorize or warrant any IDT product for use in life support devices or critical medical instruments. IDT™ / ICS™ DIGITAL VIDEO CLOCK SOURCE 6 ICS664-03 REV D 051310 ICS664-03 DIGITAL VIDEO CLOCK SOURCE CLOCK SYNTHESIZER Innovate with IDT and accelerate your future networks. Contact: www.IDT.com For Sales For Tech Support 800-345-7015 408-284-8200 Fax: 408-284-2775 www.idt.com/go/clockhelp Corporate Headquarters Integrated Device Technology, Inc. www.idt.com © 2006 Integrated Device Technology, Inc. All rights reserved. Product specifications subject to change without notice. IDT and the IDT logo are trademarks of Integrated Device Technology, Inc. Accelerated Thinking is a service mark of Integrated Device Technology, Inc. All other brands, product names and marks are or may be trademarks or registered trademarks used to identify products or services of their respective owners. Printed in USA