RFM TRC104

TRC104
Product Overview
TRC104 is a single chip, multi-channel, low power RF transceiver. It is an
ideal fit for low cost, high volume, two-way short range wireless applications
operating in the worldwide unlicensed 2.4 GHz ISM band. The TRC104 is
FCC & ETSI certifiable. All critical RF and base-band functions are integrated
in the TRC104, minimizing external component count and simplifying designin. Only a microcontroller, crystal and several passive components are
needed to create a complete, robust radio function. The TRC104 includes a
set of low-power states to reduce overall current consumption and extend
battery life. The small size and low power requirements of the TRC104 make
it ideal for a wide variety of short range radio applications. The TRC104
complies with Directive 2002/95/EC (RoHS).
2.4 GHz
RF Transceiver
Pb
Key Features
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Modulation: GFSK with frequency hopping
spread spectrum capability
Frequency range: 2401-2527 MHz
127 Channels
High sensitivity: -95 dBm @ 250 kb/s
High data rate: Up to 1 Mb/s
Low current consumption Receive current: 18 mA
Transmit current: 13 mA @ 0 dBm
Up to 1 mW transmit power
Wide operating supply voltage: 1.9 to 3.6 V
Low sleep current: 0.4 µA
Integrated PLL, IF and base-band circuitry
Integrated data & clock recovery
Programmable RF output power
32-byte Transmit/receive FIFO
Programmable TX/RX FIFO depth
Continuous & protocol modes
Packet destination and sender addressing
Packet handling features Packet address filtering
Error detection
SPI configuration & data interface
TTL/CMOS compatible I/O pins
Low-cost crystal reference
Integrated RSSI
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Integrated crystal oscillator
Host microcontroller interrupt outputs
Programmable data rate
Integrated 16-bit packet CRC
Integrated DC-balanced data scrambling
Integrated voltage regulators
Four power-saving operating states
Very low external component count
Small plastic package: 24-pin QFN
Standard 13 inch reel, 3K pieces
Applications
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Wireless keyboards
Wireless mice
Wireless game controllers
Wireless headsets
Wireless Toys
Active RFID tags
Security systems
Two-way remote keyless entry
Automobile immobilizers
Sports and performance monitoring
Low power two-way telemetry systems
Wireless modules
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TRC104 - 08/13/09
Table of Contents
1 Pin Configuration........................................................................................................................................ 4
1.1 Pin Description.................................................................................................................................. 4
2 Electrical Characteristics ............................................................................................................................ 5
2.1 DC Electrical Characteristics ............................................................................................................ 5
2.2 AC Electrical Characteristics ............................................................................................................ 6
3 Architecture ................................................................................................................................................ 8
3.1 RF Port.............................................................................................................................................. 8
3.2 Transmitter Power Amplifier ............................................................................................................. 8
3.3 PLL.................................................................................................................................................. 10
3.4 Crystal Oscillator............................................................................................................................. 10
3.5 On-chip Regulators ......................................................................................................................... 11
3.6 Receiver.......................................................................................................................................... 11
3.7 RSSI ............................................................................................................................................... 11
4 Operating Modes ...................................................................................................................................... 12
4.1 Sleep Mode..................................................................................................................................... 12
4.2 Stop Mode....................................................................................................................................... 13
4.3 Standby Mode................................................................................................................................. 13
4.4 Configuration Mode ........................................................................................................................ 13
4.5 Transmit/Receive Mode.................................................................................................................. 13
5 Data Transfer Modes................................................................................................................................ 14
5.1 Continuous Data Modes................................................................................................................. 14
5.1.1 Continuous Transmit Mode ................................................................................................... 14
5.1.2 Continuous Receive Mode .................................................................................................... 14
5.2 Burst Packet Modes........................................................................................................................ 15
5.2.1 Burst Transmit Mode ............................................................................................................. 15
5.2.2 Burst Receive Mode .............................................................................................................. 16
6 Burst Packet Mode Configuration ............................................................................................................ 17
6.1 FIFO Configuration ......................................................................................................................... 18
6.2 Preamble Configuration .................................................................................................................. 18
6.3 Addressing ...................................................................................................................................... 18
6.3.1 Sender (Local Device) Address ............................................................................................ 18
6.3.2 Destination Address .............................................................................................................. 18
6.4 DC-Balanced Scrambling ............................................................................................................... 18
6.5 CRC Error Detection ...................................................................................................................... 19
7 Serial Interface ......................................................................................................................................... 19
7.1 Configuration Registers Access...................................................................................................... 20
7.2 Transmit/Receive FIFO Access ...................................................................................................... 21
8 Configuration Registers ........................................................................................................................... 21
8.1 T/R Mode and Channel Frequency Control.................................................................................... 22
8.2 Transmit Power and Crystal Frequency Control............................................................................. 22
8.3 Data Function Control..................................................................................................................... 23
8.4 RSSI Function Control .................................................................................................................... 23
8.5 RSSI Value ..................................................................................................................................... 24
8.6 Data Format Control ....................................................................................................................... 24
8.7 Preamble Control ............................................................................................................................ 25
8.8 Transmitter Rise/Fall Time Control ................................................................................................. 25
8.9 Address Length Control .................................................................................................................. 26
8.10 Destination Address...................................................................................................................... 26
8.11 Sender (Local Device) Address .................................................................................................... 27
8.12 Reserved....................................................................................................................................... 27
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TRC104 - 08/13/09
8.13 PLL Turn-on Control ..................................................................................................................... 27
8.14 PLL Lock Time Control ................................................................................................................. 28
8.15 Reserved....................................................................................................................................... 28
8.16 Option Control............................................................................................................................... 28
8.17 Reserved....................................................................................................................................... 28
8.18 Default Overrides for Enhanced Performance.............................................................................. 28
9 Configuration Example ............................................................................................................................. 29
9.1 Burst Packet Mode Initialization...................................................................................................... 29
9.2 Burst Packet Transmission ............................................................................................................. 31
9.3 Burst Packet Reception .................................................................................................................. 31
10 Burst Packet Mode Serial Port Message Examples .............................................................................. 32
10.1 Destination Address from Configuration Registers, No Sender Address ..................................... 32
10.2 Destination Address Written by Host, No Sender Address .......................................................... 32
10.3 Destination and Sender Addresses from Configuration Registers ............................................... 32
10.4 Destination Address Written by Host, Sender Address from Configuration Register................... 32
11 Package Dimensions.............................................................................................................................. 33
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TRC104 - 08/13/09
1 Pin Configuration
T R C 1 0 4 P in O u t - V ie w
N C
R S S ID
IN T
N C
R S S IA
N C
M O D E
2 4
T h ro u g h T o p
2 3
2 2
2 1
2 0
1 9
1
S C L K
2
1 8
G N D IF
1 7
V C C R F
1 6
G N D R F
1 5
R F -
S D A T
3
C S
4
V C C D
5
1 4
R F +
G N D D
6
1 3
V D D R F
D IE P A D - G N D
1 1
1 2
V C C V C O
X T L O U T
1 0
G N D V C O
V D D D
9
P M O D E
8
X T L IN
7
Figure 1
1.1 Pin Description
PIN
TYPE
1
I
NAME
MODE
DESCRIPTION
2
I/O
SCLK
3
I/O
SDAT
4
I
CS
Operating mode select input - used with PMODE and CS
Serial clock input for burst mode, serial data output for continuous mode, and
SPI/FIFO clock signal
Serial data input/output for SPI mode and TX/RX active mode
SPI serial interface select, active high
5
VCCD
External digital power input, 3.0 V typical
6
GNDD
Digital ground
7
VDDD
8
O
XTLOUT
9
I
XTLIN
10
I
PMODE
11
GNDVCO
12
VCCVCO
13
VDDRF
Regulated digital output voltage
Crystal oscillator output
Crystal oscillator input
Power mode select input - used with MODE to select standby or sleep mode
VCO ground pin
External VCO power input , 3.0 V typical
Regulated supply output for RF power amplifier
14
RFIO
RF+
Differential RF I/O pin
15
RFIO
RF-
Differential RF I/O pin
16
GNDRF
17
VCCRF
External RF power input, 3.0 V typical
18
GNDIF
IF ground
RSSIA
Analog RSSI output - continuous mode only
19
O
20
RF ground
NC
No connection - not used
Transmit or receive complete interrupt output
21
O
INT
22
O
RSSID
RSSI threshold interrupt output
23
NC
No connection - not used
24
NC
No connection - not used
P
-
DIE PAD
IC die pad on bottom of package - ground
Table 1
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TRC104 - 08/13/09
2 Electrical Characteristics
Absolute Maximum Ratings
SYMBOL
PARAMETER
MIN
MAX
UNITS
Vcc
Supply Voltage
NOTES
-0.4
+3.6
V
TSTG
Storage Temperature
-55
+125
°C
RFIN
RF Input Level
0
dBm
Table 2
Recommended Operating Range
SYMBOL
PARAMETER
MIN
MAX
UNITS
Vcc
Supply Voltage
NOTES
+1.9
+3.6
V
TOP
Operating Temperature
-40
+85
°C
Table 3
2.1 DC Electrical Characteristics
Minimum/maximum values are valid over the recommended operating range Vcc = 1.9-3.6 V. Typical conditions: TO = 25°C; VCC = 3.3 V.
The electrical specifications given below are valid when using an RFM XTL1021 or equivalent crystal.
PARAMETER
SYM
Sleep Mode Current
NOTES
MIN
ISL
TYP
MAX
UNITS
0.4
µA
Stop Mode Current
IST
1.4
µA
Standby Mode Current
ISB
crystal oscillator running
22
µA
Configuration Mode Current
ICM
crystal oscillator running
15
mA
Receiver Mode Current
IRX
250 kb/s
18
1 Mb/s
19
Pout = 0 dBm
13
Pout = -10 dBm
9
Transmitter Mode Current
ITX
RSSI Analog Output Level
Test Conditions
16 MHz crystal
mA
mA
500
1500
mV
Digital Input Low Level
VIL
-0.4
0.8
V
Digital Input High Level
VIH
0.7*Vcc
Vcc+0.4
V
Digital Input Current Low
IIL
1
µA
VIL = 0 V
Digital Input Current High
IIH
1
µA
VIH = Vcc
Digital Output Low Level
VOL
0.4
V
IOL = -1 mA
Digital Output High Level
VOH
-
V
IOH = +1 mA
Vcc-0.4
Table 4
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TRC104 - 08/13/09
2.2 AC Electrical Characteristics
Minimum/maximum values are valid over the recommended operating range Vcc = 1.9-3.6 V. Typical conditions: TO = 25°C; VCC = 3.3 V.
The electrical specifications given below are valid when using an RFM XTL1021 or equivalent crystal.
RECEIVER
PARAMETER
SYM
NOTES
MIN
RF Input Impedance
TYP
MAX
200
RF Input Power
0
Receiver Bandwidth
Blocking Immunity
Co-channel Rejection
Image Rejection
250 kb/s
-95
1 Mb/s
-90
250 kb/s
9
1 Mb/s
5
250 kb/s
-20
1 Mb/s
1
250 kb/s
-26
1 Mb/s
-26
FSK Bit Rate
250
RSSI Accuracy
4-bit value
RSSI Dynamic Range
Test Conditions
ohms
differential
dBm
MHz
1.5
Receiver Sensitivity
UNITS
dBm
dB
10-3 BER
10-3 BER
1 MHz offset,
unmodulated
dB
dB
1000
kb/s
±3
dB
40
dB
NRZ
Table 5
TRANSMITTER
PARAMETER
SYM
NOTES
MIN
RF Output Impedance
RF Output Power
RF Output Power Range
TYP
UNITS
Test Condition
200
ohms
differential
0
dBm
-20
MAX
0
dBm
programmable
2nd Adjacent Channel Power
2 MHz channel offset
-20
dBm
1 Mb/s data rate,
0 dBm TX power
3rd Adjacent Channel Power
3 MHz channel offset
-40
dBm
1 Mb/s data rate,
0 dBm TX power
-54
dBm
0 dBm TX power
-46
dBm
0 dBm TX power
±160
kHz
fixed for both
data rates
1
MHz
2nd Harmonic
rd
3 Harmonic
FSK Deviation
20 dB Modulation BW
Table 6
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TRC104 - 08/13/09
TIMING
PARAMETER
SYM
NOTES
MIN
TYP
MAX
UNITS
TX to RX Switch Time
oscillator & PLL running
200
µs
RX to TX Switch Time
oscillator & PLL running
200
µs
120
ms
120
ms
Sleep to Stop Mode
120
ms
Stop to Standby Mode
1.5
ms
Sleep to Receive
serial command to RX bit
Sleep to Transmit
serial command to TX bit
Standby to Receive
oscillator running
200
µs
µs
Standby to Transmit
oscillator running
200
Frequency Hop Time
channel switching time
200
µs
10/5
µs/step
10
mV/µs
Transmit Rise/Fall Time
RSSI Rise Time
Test Condition
programmable
no external
filter capacitor
Table 7
PLL CHARACTERISTICS
PARAMETER
SYM
NOTES
MIN
Crystal Oscillator Frequency
4
TYP
MAX
UNITS
16
20
MHz
170
µs
PLL Step Resolution
1
MHz
Crystal Load Capacitance
12
pF
Crystal Oscillator Start time
1.5
ms
PLL Lock Time
settling to less than 10 kHz
Frequency Range
2401
2527
Test Condition
from sleep mode
MHz
Table 8
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TRC104 - 08/13/09
3 Architecture
The TRC104 is a single-chip FSK transceiver that operates in the worldwide 2.4 GHz ISM band. The TRC104’s
highly integrated architecture requires a minimum of external components. Advanced features including the
TX/RX FIFO and the burst packet data mode significantly reduce the TRC104’s load on the host microcontroller.
As shown in Figure 2, the TRC104 utilizes a dual-conversion superheterodyne receiver architecture with an
image-reject second mixer. The VCO operates directly at the output frequency when transmitting, and is
modulated by a Gaussian-filtered bit stream.
T R C 1 0 4 B lo c k D ia g r a m
P o w e r
A m p
R e g u la to r
V D D R F
A n tia lia s in g
F ilte r
D A C
T X D a ta
G a u s s ia n
L o w -p a s s
F ilte r
T X C lo c k
A m p litu d e C o n tr o l
R F +
P o w e r
A m p
R F -
P L L
L o o p
F ilte r
V C O
T X
S w itc h
C h a rg e
P u m p
P h a s e
F re q u e n c y
D e te c to r
P M O D E
M O D E
R e f F re q u e n c y
C S
S C L K
F r e q u e n c y S e le c t
D iv id e
b y 8
C lo c k ,
C o n tr o l,
C o n fig
R e g is te r s
a n d F IF O
D iv id e
b y N
R S S I
R S S I
S u m m e r
R X L O 2 -I
R e c e iv e r
B a n d -p a s s
F ilte r
IN T
R S S ID
R S S IA
X T L IN
X T L O U T
R X L O 1
L N A
S D A T
R X L O 2 -Q
C o m p le x
IF F ilte r
IF A m p /L im ite r
F S K
D e te c to r
D a ta &
C lo c k
R e c o v e ry
C lo c k
D a ta
Figure 2
3.1 RF Port
The TRC104 has a differential RF port that is capable of delivering the required transmitter output power at low
supply voltages. The differential RF port also provides common mode signal rejection to enhance receiver
interference immunity. A simple L-C balun can be used to convert the differential port to a single-ended output to
drive an unbalanced antenna, as shown in Figure 3.
3.2 Transmitter Power Amplifier
The power amplifier controls the output power level of the transmitter. The power amplifier has four programmable
power levels. The power level is set by the PWR bits in configuration register 0x01.
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TRC104 - 08/13/09
T R C 1 0 4 A p p lic a tio n C ir c u it
V C C R F
2 3
X
2 4
N C
+ 3 V
X
N C
1 7
2 0
N C
X
P M O D E
2 2 p F
M O D E
1 5
S C L K
3 .9 n H
S D A T
R F +
T R C 1 0 4
1 .0 p F
IN T
5 .6 n H
R S S ID
1 3
V D D R F
2 2 n F
4
2
H o s t
M ic r o c o n tr o lle r
3
2 1
2 2
1 9
0 .1 µ F
1 2
V C C V C O
8
V C C D
9
1 8 1 6 1 1
1 M
6
5
+ 3 V
2 2 p F
V D D D
G N D D
D IE P A D
G N D R F
G N D V C O
X T L O U T
2 2 p F
G N D IF
+ 3 V
R S S IA
X T L IN
2 2 p F
1
C S
R F -
1 .0 p F
1 4
1 0
P
7
1 .0 µ F
1 6 M H z
2 2 p F
2 2 p F
Figure 3
For Burst Transmit Mode, the TRC104 RF output ramp-up and ramp-down times are configurable, controlling
excessive transmitter bandwidth due to fast rise and fall times of the transmitter RF envelope. After the PLL is
locked for transmission, the power amplifier is ramped up stage by stage beginning with the lowest power level
until the power level that is specified by the PWR bits in register 0x01 is reached. Once the transmission is
complete, the power amplifier is ramped down stage-by-stage until it is completely disabled.
The ramp-up/ramp-down function increases or decreases the output power stage-by-stage as specified by the
PA_RU and PA_RD bits of register 0x07, respectively. Figure 4 shows the timing for the ramp-up/ramp-down.
P o w e r A m p lifie r R a m p U p /D o w n T im in g
M O D E
-5 d B
R F P o w e r
-1 0 d B
-2 0 d B
O F F
D a ta
O N
R U
R D
A N
: R
: R
: R
: A
R F D a ta T r a n s m is s io n
F P
F P
F P
n a lo
o w
o w
o w
g
e r
e r
e r
C ir
A m p
R a m
R a m
c u itr y
lifie r O n
p U p In te rv a l
p D o w n In te rv a l
O N
O N
R U
R U
R U
R U
A N
R D
R D
R D
Figure 4
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TRC104 - 08/13/09
3.3 PLL
The PLL channel is set with the Ch_Num bits in configuration register 0x00. In transmit mode, the PLL is normally
turned on with the falling edge of the MODE input. The TRC104 transmits the data after the PLL locks and the
power amplifier has ramped up to its programmed level. PLL lock time is typically 170 µs. It is possible to enable
and lock the PLL before the falling edge of MODE input. This can provides a shorter transition time to transmit.
The PLL pre-start delay time is adjustable from 20 µs up to 5 ms. The value of PLL_ON in register 0x14 sets this
time. The pre-start delay timer is triggered on the rising edge of MODE as shown in Figure 5. The value of
PLL_ON determines the delay time from the rising edge of MODE before the PLL is enabled. Care must be taken
to carefully calculate the write time of the data packet into the transmit FIFO so that the TRC104 does not enable
the transmitter and begin sending data before the data packet is fully written to the FIFO, in which case the
TRC104 will discard the current packet.
P L L P r e -s ta r t T im in g
M O D E
P L L S ta te
P L L O F F
P L L O N
P L L L O C K IN G
P L L O F F
R F D a ta T r a n s m is s io n
D a ta
D E L A Y
D E L A Y : P r e - s ta r t d e la y in te r v a l
Figure 5
3.4 Crystal Oscillator
At the 1 Mb/s RF data rate, the TRC104 uses a 16 MHz crystal. At the 250 kb/s RF data rate, the TRC104 can
use any one of five standard crystal frequencies: 4, 8, 12, 16, or 20 MHz. The crystal frequency is configured by
setting the FXTAL bits in register 0x01. At the 250 kb/s data rate, the TRC104’s power consumption is reduced by
using one of the lower crystal frequencies. The total load capacitance CL seen between the XTLIN and XTLOUT
terminals is composed primarily of CIN and COUT in series, as shown if Figure 6:
CL = 1/((1/CIN) + (1/COUT) ) + CSTRAY, where CSTRAY is the capacitance associated with the PCB layout
X T L IN
X T L O U T
T R C 1 0 4 C r y s ta l O s c illa to r Im p le m e n ta tio n
9
8
C
IN
C
O U T
Figure 6
A typical value for CSTRAY is 1 pF. The values of CIN and COUT should be approximately equal and chosen so that
CL matches the load capacitance specified for the crystal. A typical CL value for a 16 MHz crystal is 12 pF. The
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TRC104 - 08/13/09
maximum recommended value for CL is 20 pF. The required crystal frequency tolerance for the TRC104 is
±30 ppm maximum including temperature and aging drift. A typical ESR for the crystal is 35 ohms, and the
maximum static capacitance is 7 pF. RFM recommends the 16 MHz XTL1021 for use with the TRC104.
3.5 On-chip Regulators
The TRC104 has on-chip regulators used to power the VCO, the digital circuitry, and for biasing of the RF port.
Power pins with a VCC designation are external power inputs to the on-chip regulators. Power pins with a VDD
designation are regulated power outputs that are filtered by external capacitors or are used to power external
TRC104 functions.
3.6 Receiver
As shown in Figure 2, the TRC104 receiver chain starts with a 2.4 GHz differential input LNA, followed by an onchip 2.4 GHz band-pass filter. The output of the band-pass filter drives the first mixer, which converts the RF input
to the first IF frequency. The output of the first mixer is applied to the second-conversion I and Q mixers, which
are driven by I and Q LO signals 1/8 the frequency of the first LO. The outputs of the I and Q mixers are
processed by a 5 MHz complex IF filter, which provides both band-pass filtering and Hilbert transform phasing
between the I and Q channels. The phased I and Q channels are summed, nulling the unwanted image response.
The output from the complex IF filter is applied to a limiting IF amplifier, which also generates inter-stage outputs
that drive the RSSI signal summer. The limited output from the IF amplifier drives an FSK detector. The FSK
detector output is applied to a data slicer and then a data and clock recovery circuit. The recovered data and
clock signals are processed by the TRC104 control logic according to the receiver mode of operation.
3.7 RSSI
The RSSI signal is an indication of received signal strength. A diagram of the RSSI implementation is shown in
Figure 7. Once the RSSI signal is enabled by setting the RSSIA_rfsh bit of register 0x03 to 1, the TRC104 will
begin to detect the strength of incoming signals. The RSSIA pin outputs an analog voltage corresponding to the
strength of the received signal. Once the RSSI sample is complete, the RSSIA_rfsh bit resets to 0. Any reading
of the RSSIA pin or RSSID pin should be taken after the RSSIA_rfsh bit resets to 0.
T R C 1 0 4 R S S I Im p le m e n ta tio n
R S S IA
D IG IT A L
C O M P A R A T O R
R S S I
S u m m e r
IF
F ilte r
IF A m p /L im ite r
A D C
F S K
D e te c to r
R S S ID
R S S IT H
R E G IS T E R
R S S IV A L
R E G IS T E R
Figure 7
The analog RSSI signal is applied to an ADC to obtain a digital RSSI value, RSSID. The digital value is stored in
the RSSI_val of register 0x04. The RSSI covers two ranges of signal strength, based on the state of the RSSI_G
bit in configuration register 0x04. If RSS_G is 0, the RSSI covers the received signal strength range of -95 to
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TRC104 - 08/13/09
-42 dBm. If RSS_G is 1, the RSSI covers the received signal strength range of -55 to -2 dBm. The RSSID value
is also compared to the RSSI_thr threshold value of register 0x03.
If the digital value is greater than the threshold value, the RSSID pin is asserted according to the configuration of
the LVLDRSSI bit of register 0x17. If the LVLDRSSI bit is set to 1, the RSSID pin is asserted high, otherwise the
pin is asserted low. The output state of the RSSID pin is disabled while MODE is asserted. The RSSI function is
only available in continuous mode, as discussed below.
4 Operating Modes
The TRC104 can operate in one of five modes: Sleep, Stop, Stand-by, Configuration or Active TX/RX. Figure 8
details the state transitions between the operating modes.
T R C 1 0 4 O p e r a tin g M o d e S ta te D ia g r a m
T X /R X
S le e p
S ta n d b y
S to p
C o n fig
Figure 8
There are three input pins that determine the operating mode for the TRC104. The states of these pins are shown
in Table 9 and associated timing diagrams are provided in the Sections below where needed.
Pin State
Operating Mode
PMODE
CS
Sleep Mode
0
X
MODE
1
Stop Mode
0
0
0
Standby Mode
1
0
0
Configuration Mode
1
1
0
Transmit Load/Receive Mode
1
0
1
Burst Transmit
1
0
1→0
X – Don’t Care
Table 9
4.1 Sleep Mode
Sleep Mode provides the lowest TRC104 current consumption, typically less than 0.4 µA. No serial transactions
can occur while in Sleep Mode. The contents of the FIFO and the internal configuration registers are not
maintained in Sleep Mode. When waking from Sleep Mode the TRC104 executes a power-up reset, which takes
120 ms. Any operation to the TRC104 must wait until the reset period is complete. Following a sleep cycle,
configuration registers must be rewritten to utilize operating parameters other than the power on default settings.
Figure 9 demonstrates the states of the mode control pins and the timing related to Sleep Mode. For minimum
current consumption, hold the SDAT, SCLK, INT and RSSID pins low in this mode. 100K pull-down resistors can
be used for this purpose.
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TRC104 - 08/13/09
S le e p M o d e C o n fig u r a to n T im in g
S le e p M o d e
P M O D E
M O D E
C S
R e s e t
1 2 0 m s
Figure 9
4.2 Stop Mode
In Stop Mode the contents of the TRC104 configuration registers are maintained, and the digital voltage regulator
and parts of the digital circuitry are enabled. The remaining digital and analog circuitry is disabled to minimize
current consumption, which is typically 1.4 µA. No serial transaction can occur in Stop Mode. The typical turn-on
time from Stop Mode is 1.5 ms. Any operation to the TRC104 must wait until the turn on period is complete.
Figure 10 demonstrates the states of the mode control pins and the timing related to Stop Mode.
S to p M o d e C o n fig u r a to n T im in g
S to p M o d e
P M O D E
M O D E
C S
1 .5 m s
Figure 10
4.3 Standby Mode
Stand-by Mode is a low current mode that provides a very low transition time to configuration, transmit or receive
modes. In Standby Mode circuit blocks that are not being utilized are shutdown to minimize current usage. When
the TRC104 is set to Transmit, Receive or Configuration Mode, there is no start-up delay and the next action may
occur immediately. The power consumption of Standby Mode is dictated mainly by the crystal frequency used.
4.4 Configuration Mode
Configuration Mode allows access to the TRC104’s configuration registers. Serial data is applied to the SDAT pin
and serial clock is applied to the SCLK pin. See Section 5 for additional details.
4.5 Transmit/Receive Mode
This mode is enabled to load the transmit FIFO or receive data. The mode function, transmit or receive, is set
before enabling this mode. The mode function is selected by the C_Mode bit in configuration register 0x00. See
Section 5 for descriptions and timing of the various data transfer modes.
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5 Data Transfer Modes
The TRC104 supports two data transfer modes - Continuous Data Mode and Burst Data Mode. The data transfer
mode is selected by the D_Mode bit in configuration register 0x02.
5.1 Continuous Data Mode
Continuous Data Mode is selected when the D_Mode bit of register 0x02 is set to 0. Continuous Receive Mode
routes demodulated data directly to the SDAT pin and the associated clock to the SCLK pin. In Continuous
transmit mode the data bit stream is applied directly to the SDAT pin. The internal FIFOs and the automatic
packet features are disabled in Continuous Data Mode. It is the responsibility of the TRC104 host microcontroller
to handle these functions.
5.1.1 Continuous Transmit Mode
Continuous Transmit Mode is enabled when the C_Mode bit of register 0x00 is set to 1 and the D_Mode bit of
register 0x02 is set to 0. In Continuous Transmit Mode, the transmit FIFO and all automatic packet features
including preamble generation, addressing, DC-balanced data scrambling and CRC generation are disabled. The
TRC104 host microcontroller must handle these functions for Continuous Transmit Mode. Specifically, the host
microcontroller must generate a 1-0-1-0 … preamble sequence of at least 16 bits followed immediately by the
destination address for the transmission (called the sender or local device address at the destination node).
Also for this mode, it is the responsibility of the host microcontroller to maintain correct bit timing to an accuracy of
1% as there is no bit clock output for transmit timing. The host microcontroller must be powerful enough to
accurately support the selected serial data rate (250 kb/s or 1 Mb/s) in addition to other functions required for the
end application. Figure 11and Table 10 show the timing for transmitting data on SDAT. Note that three 1 dummy
bits must be sent prior to sending the preamble and the rest of the packet.
C o n tin u o u s M o d e T r a n s m it T im in g
T 3
M O D E
T 2
T 1
S D A T
D u m m y
D u m m y
D u m m y
P r e a m b le /A d d r e s s /D a ta B its
Figure 11
Item
Description
Min
st
T1
MODE to 1 Bit Time
T2
Dummy Bits
T3
RF Transmission Time
Typ
Max
250
Unit
µs
3
bit
4
ms
Table 10
The TRC104 should not be active for more than 4 ms at a time to allow for internal auto-calibration. Typical
calibration time is 200 µs.
5.1.2 Continuous Receive Mode
Continuous Receive Mode is enabled when the C_Mode bit of register 0x00 is set to 0 and the D_Mode bit of
register 0x02 is set to 0. In Continuous Receive Mode, the receive FIFO and automatic packet features except
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address detection are disabled. The TRC104 host microcontroller must handle functions such as DC-balanced
data scrambling and CRC generation for Continuous Receive Mode. Note that a valid sender (local device)
address is required for address detection and proper Continuous Receive Mode operation. This address is
configured by writing the address byte(s) into configuration registers 0x0E - 0x12, according to the address length
specified by the ADDR_len bits in configuration register 0x08. The sender address is written least significant byte
first, starting in register 0x0E.
The host microcontroller must be powerful enough to handle the chosen serial data rate (250 kb/s or 1 Mb/s) in
addition to the other functions required for the end application. Data is read from the SDAT pin. To assist in data
recovery, a bit clock is available on the SCLK pin. The state of the SDAT pin is read on the rising edge of SCLK to
recover the demodulated data. Figure 12 and Table 11 show the timing for reading data from SDAT.
C o n tin u o u s M o d e R e c e iv e T im in g
M O D E
T 1
D 7
S D A T
D 6
D 2
D 5
D 1
D 0
S C L K
T 2
T 3
Figure 12
Item
Description
T1
MODE to SCLK Time
250
µs
T2
Bit Delay Time
15
ns
SCLK Cycle Time for 1 Mb/s
1
SCLK Cycle Time for 250 kb/s
4
T3
Min
Typ
Max
Unit
µs
Table 11
5.2 Burst Packet Modes
Burst Packet Mode is enabled when the D_Mode bit of register 0x02 is set to 1. Burst Packet Mode handles
automatic packet features such as preamble generation, address insertion and filtering, DC-balanced data
scrambling/descrambling, and CRC generation and error detection. In Burst Packet Mode the FIFO is enabled
and used for transmitting or receiving packets. In Burst Packet Mode, the host microcontroller does not have the
heavy overhead of bit, byte and packet processing as is the case with the Continuous Mode.
5.2.1 Burst Transmit Mode
Burst Transmit Mode is enabled when the C_Mode bit of configuration register 0x00 is set to 1 and the D_Mode
bit of register 0x02 is set to 1. In Burst Transmit Mode, data is written to the TRC104 before being transmitted,
most significant bit or each byte first. The automatic packet features listed in Section 5.2 are available in Burst
Mode. Once the FIFO is loaded, three additional dummy bits (any value) are clocked in. The MODE pin is then
de-asserted (low) and the packet transmission starts. At the end of the transmission the INT flag is asserted. The
INT flag resets when the TRC104 is placed in another mode. Figure 13 and Table 12 show the serial port timing
parameters for Burst Transmit Mode.
In Burst Mode, the FIFO length is set to match the number of payload data bytes. When transmitting a packet ,
the destination address may obtained from one of two sources, either automatically from configuration registers
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0x09 - 0x0D, or by writing it directly before the payload data bytes. The source for the destination address is
chosen by the DesADD_ref bit in configuration register 0x05. When writing the destination address directly, the
most significant address byte is written first. Sender (local device) addressing is optional. If used, the sender
address is automatically loaded from configuration registers 0x0E - 0x12. The destination address can be from
one to five bytes in length. If used, the sender address must be the same length as the destination address.
S e r ia l P o r t B u r s t T r a n s m it M o d e T im in g
M O D E
T 5
IN T
T 6
T 3
T 1
S D A T
T 4
S C L K
T 2
Figure 13
Item
Description
Min
T1
MODE to 1st Bit Time
20
T2
SCLK Cycle Time
500
T3
Setup Time
Typ
Max
µs
ns
15
T4
Hold Time
T5
Address & Payload Data
T6
Dummy Bit Writes
Unit
ns
15
8
ns
296
bits
3
bits
Table 12
5.2.2 Burst Receive Mode
Burst Receive Mode is enabled when the C_Mode bit of register 0x00 is set to 0 and the D_Mode bit of register
0x02 is set to 1. In Burst Receive Mode, the FIFO is loaded with the payload data part of a received packet. The
automatic packet features listed in Section 5.2 are available for use in Burst Receive Mode. Using these features
frees up the host microcontroller to perform other tasks.
As a packet is received, the TRC104 uses the preamble to lock to the incoming data rate and then determines if
the packet is for it by testing the address following the preamble for a match to its own device address. If the
addresses match, the TRC104 receives the remainder of the packet, including the sender address if present, the
payload data and CRC. The TRC104 then performs a CRC calculation and compares the result with the received
CRC value. If the CRC’s match, the INT flag is asserted according to the interrupt polarity as configured by the
LVLINT bit of configuration register 0x17. Otherwise, the packet is discarded unless this default is overridden.
Upon assertion of the INT flag, the host microcontroller clocks out and discards two dummy bits, and then clocks
out received bits, checking the INT flag after each group of 8 bits. The INT flag will de-assert when the next-to-last
payload data byte in the FIFO is read. The host microcontroller then completes the read transaction by clocking
out the last FIFO byte followed by clocking out and discarding three more dummy bits. When the INT flag is
asserted the host microcontroller should read the data quickly so as not to delay listening for the next packet. If
the data has not been completely read when the next packet is transmitted, reception will not occur and the
transmitted data will be missed. Figure 14 and Table 13 show the serial port timing parameters for Burst Receive
Mode.
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S e r ia l P o r t B u r s t R e c e iv e M o d e T im in g
M O D E
T 1
IN T
T 2
T 5
T 4
T 6
T 7
S D A T
S C L K
T 3
Figure 14
Item
Description
Min
Typ
Max
Unit
T1
MODE to INT Time
0
T2
INT to 1st Bit
0
ns
T3
SCLK Cycle Time
500
ns
T4
Dummy Bit Reads
T5
Address & Payload Data Except Last Byte
0
T6
Last Payload Data Byte
8
T7
Dummy Bit Reads
ns
2
bits
288
bits
bits
3
bits
Table 13
6 Burst Packet Mode Configuration
In Burst Packet Mode, the following packet features are available :
•
•
•
•
•
•
•
•
Configurable FIFO length up to 32 bytes
Configurable preamble length up to 16 bits
Configurable address filtering
Configurable sender/destination address length up to 5 bytes
Configurable sender (local device) address
Configurable destination address
Configurable DC-balanced data scrambling/descrambling
Configurable CRC generation and error detection
The configuration details of these features are covered below in Sections 6.1 through 6.4. Figure 15 shows the
general format of a TRC104 packet.
T R C 1 0 4 F ix e d L e n g th P a c k e t F o r m a t
P r e a m b le
4 to 1 6 B its
D e s tin a
A d d re
(r e q u ir
1 to 5 B
tio n
s s
e d )
y te s
S e n d e r
A d d re s s
(o p tio n a l)
1 to 5 B y te s
P a y lo a d D a ta
1 to 3 2 B y te s
F IF O
W h e n u s e d , th e s e n d e r a d d r e s s m u s t b e th e s a m e le n g th a s th e d e s tin a tio n a d d r e s s . T h e F IF O
C R C
L e n g th
m u s t b e c o m p le te ly fille d w ith p a y lo a d d a ta b y te s .
Figure 15
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6.1 FIFO Configuration
The transmit/receive FIFO length is set with the FIFO_len bits in configuration register 0X05. The length can be
set from one to 32 bytes. The FIFO must be long enough to hold all payload data bytes. All TRC104 radios in a
network must use the same FIFO length. The FIFO must be completely filled on every transmission. Padding
bytes (user selected value) are used to fill up the transmit FIFO when payload data bytes do not completely fill it.
6.2 Preamble Configuration
The preamble is a 1-0-1-0… sequence of bits sent at the beginning of a packet to allow the receiver data and
clock recovery function to lock to the packet bit stream. The preamble is discarded by the receiver. The preamble
length is programmable up to 16 bits. The length is configurable in 4-bit segments by setting the Pream_len bits
in configuration register 0x06. A 16-bit preamble is recommended for most applications.
6.3 Addressing
In Burst Packet mode, the destination address allows a TRC104 to determine if a packet is for it. The sender
address can be optionally added to a packet, and is especially useful in networks consisting of more than two
radios. The length of the destination addresses is configurable from 1 to 5 bytes. The sender address length is
automatically set to the same length. All TRC104 radios in a network must use the same address length. The
destination address is stripped off by the receiver and is not included in the read out from the FIFO. The sender
address may be output before the payload data in a received packet. This feature is enabled through
configuration register 0x05, bits 7..6. To avoid random noise causing frequent false detections of a destination
address, an address length of at least two bytes is recommended, and three to five bytes is preferred.
6.3.1 Sender (Local Device) Address
The sender (local device) address is configured by writing the address byte(s) into configuration registers 0x0E 0x12, according to the address length specified by the ADDR_len bits in configuration register 0x08. The sender
address is written least significant byte first, starting in register 0x0E. The sender address is automatically added
to a transmit packet by setting the DevADD_En bit to 0 in configuration register 0x05. The sender address may
be optionally read out before the payload data in a received packet. This is useful when receiving messages from
multiple sources. This option is enabled by setting the SADDR_pos bit to 0 in configuration register 0x05.
6.3.2 Destination Address
The destination address is the first field sent after the preamble. If the destination address in a received packet
does not match the address stored in the sender (local device) address configuration registers, the packet is
discarded and the host microcontroller does not receive an INT flag. The destination address is configured by
writing the address byte(s) into configuration registers 0x09 - 0x0D, according to the address length specified by
the ADDR_len bits in configuration register 0x08. The destination address is written least significant byte first,
starting in register 0x09. When transmitting a packet, the destination address may obtained from one of two
sources, either automatically from configuration registers 0x09 - 0x0D, or by writing it directly in the packet
destination address field. The source for the destination address is chosen by the DesADD_ref bit in
configuration register 0x05.
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6.4 DC-Balanced Scrambling
The TRC104 is equipped with a scrambling/descrambling function to improve the DC-balance of a transmitted bit
stream. The implementation is show in Figure 16. This function is enabled by setting the SCR_En bit in
configuration register 0x02 to 1. The scrambling/descramble function is only available in Burst Packet Mode.
T R C 1 0 4 D a ta S c r a m b lin g Im p le m e n ta tio n
X 7 + X 4 + 1
X O R
S R 6
S R 4
S R 3
S R 0
S C R A M B L E D
D A T A O U T P U T
X O R
D A T A IN P U T
A ll 7 s h ift r e g is te r s s e t to 1 b e fo r e e a c h s c r a m b lin g ( D C b a la n c in g ) c a lc u la tio n
Figure 16
6.4 CRC Error Detection
The CRC error detection option is enabled by setting the CRC_En bit in configuration register 0x02 to 1. A twobyte CRC is automatically calculated on the payload field and appended to the end of the transmitted packet. On
the receive side, the CRC is recalculated on the payload field and compared to the received CRC. If the CRC
match fails, the received packet is handled according to the setting of the CRC_ERR bit in configuration register
0x02. Otherwise, a good CRC match generates a flag on the INT pin, and the received CRC is discarded. The
polarity of the INT flag is configured by the LVLINT bit in configuration register 0x17. There is no interrupt
generation for a failed packet. The CRC calculation is based on the CCITT polynomial as shown in Figure 17.
T R C 1 0 4 C R C Im p le m e n ta tio n
X 16 + X 12 + X 5 + 1
D A T A
IN P U T
X O R
S R 1 5
S R 1 2
X O R
S R 1 1
X O R
S R 5
A ll 1 6 s h ift r e g is te r s s e t to 1 b e fo r e e a c h C R C
S R 4
S R 0
c a lc u la tio n
Figure 17
7 Serial Interface
The serial interface provides two-wire serial communication between the TRC104 and its host microcontroller, as
shown in Figure 18. All FIFO and configuration parameters are accessible through the serial interface. The FIFO
and configuration data pass through the bidirectional SDAT pin with host microcontroller clocking on the SCLK
pin. The CS pin state selects whether the FIFO (Burst Packet Mode only) or the internal configuration registers
are accessed.
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T R C 1 0 4 - M ic r o c o n tr o lle r S ig n a l C o n n e c tio n s
P M O D E
M O D E
C S
S C L K
T R C 1 0 4
H o s t
M ic r o c o n tr o lle r
S D A T
IN T
R S S ID
Figure 18
The serial interface is enabled for read/write transactions with the configuration registers by holding the CS pin
high. The CS pin must remain high during the transmission of both the address and data bytes or the data will be
corrupted. Between each configuration register read/write transaction the serial interface must be reset by pulling
the CS pin low. Pulling CS high again re-enables the serial interface for a new configuration register read/write
transaction. Back-to-back configuration register read/writes are not possible as the configuration register address
is not automatically incremented. Refer to Sections 7.1 for additional configuration register access details.
The serial interface is enabled for read/write transactions with the FIFO by holding the CS pin low. Data and
clocking are handled through the SDAT and SCLK pins, respectively.
7.1 Configuration Registers Access
The most significant bit of each byte is sent first. The rising SCLK edge is used to sample the received bit, and the
falling SCLK edge shifts the data inside the shift register. The most significant bit of the first byte specifies a read
or write command followed by seven address bits. The following byte contains the read/write data.
Two bytes are required for each configuration register transaction. The first byte contains the R/W bit (0 = read,
1 = write) and the 7-bit configuration register address. The second byte contains the configuration value to be
written or read from the address specified in the first byte. Figure 19 and Table 14 show the timing for a
configuration read sequence from the TRC104.
C o n fig u r a tio n B y te R e a d T im in g
C S
T 1
S D A T
R /W
A 6
A 5
A 1
A 0
D 7
D 6
D 5
D 1
D 0
S C L K
T 2
T 3
T 4
T 5
T 6
Figure 19
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Item
Description
Min
T1
CS to 1st Bit Time
20
Typ
Max
Unit
T2
SCLK Cycle Time
200
ns
T3
Setup Time
10
ns
T4
Hold Time
10
T5
Data Bit Hold Time
T6
Last Bit to CS Time
µs
ns
20
ns
50
ns
Table 14
Figure 20 and Table 5 show the timing for a configuration write sequence to the TRC104.
C o n fig u r a tio n B y te W r ite T im in g
C S
T 1
S D A T
R /W
A 6
A 5
A 1
A 0
D 7
D 6
D 5
D 1
D 0
S C L K
T 2
T 4
T 3
T 5
Figure 20
Item
Description
Min
Typ
Max
Unit
T1
st
CS to 1 bit time
20
µs
T2
SCLK cycle time
200
ns
T3
Setup time
10
ns
T4
Hold time
10
ns
T5
Last bit to CS time
50
ns
Table 15
7.2 Transmit/Receive FIFO Access
Serial data is sent or received through the FIFO according to the TRC104 mode of operation. If the TRC104 is
configured for Burst Receive Mode, a FIFO read transaction is implemented on the serial interface. If the TRC104
is configured for Burst Transmit Mode, a FIFO write transaction is implemented on the serial interface. The CS pin
must be held low during FIFO transactions. If the CS is allowed to go high, the TRC104 will interpret the data as a
register configuration transaction and possibly corrupt the device configuration. See Sections 5.2.1 and 5.2.2 for
details on Burst Transmit Mode and Burst Receive Mode using the FIFO.
8 Configuration Registers
The TRC104’s user configuration registers are mapped in the address range of 0x00 through 0x18. Sections 8.1
through 8.17 below provide the details for each configuration register. Power-up default settings for the
configuration register bit and byte patterns are shown in bold.
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8.1 T/R Mode and Channel Frequency Control
0x00 [default 0x28]
Address
Name
Bits
R/W
C_Mode
7
r/w
Chip Mode:
0 → Receive Mode
1 → Transmit Mode
Ch_Num
6..0
r/w
Channel Frequency:
FRF = 2400 + (Ch_Num ) in MHz, 1 ≤ Ch_Num ≤ 127
[default is 00101000b]
0X00
Description
Table 16
8.2 Transmitter Power and Crystal Frequency Control
0x01 [default 0x03]
Address
Name
-
PWR
Bits
R/W
7..5
r/w
Reserved, always set to 000b
r/w
Transmitter Output Power:
00 → -20 dBm
01 → -10 dBm
10 → -5 dBm
11 → 0 dBm
r/w
Crystal Frequency Selection:
000 → 4 MHz
001 → 8 MHz
010 → 12 MHz
011 → 16 MHz
100 → 20 MHz
4..3
0X01
FXTAL
2..0
Description
Table 17
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8.3 Data Function Control
0x02 [default 0x78]
Address
0X02
Name
Bits
R/W
-
7
r/w
Reserved, always set to 0b
D_Mode
6
r/w
Data Mode Select:
0 → Continuous Mode
1 → Burst Mode
DR
5
r/w
Data Rate Select:
0 → 250 kb/s
1 →1 Mb/s
r/w
DC-balanced Data Scrambling Enable bit (Burst Mode only):
0 → Disable Data Scrambling
1 → Enable Data Scrambling
Scramble Polynomial = X7 + X4 + 1
3
r/w
CRC-16 Enable bit (Burst Mode only):
0 → Disable CRC
1 → Enable CRC
CRC Polynomial = X16 + X12 + X5 + 1
2..1
r/w
Reserved, always set to 0b
0
r/w
Controls clearing the FIFO in Burst Receive Mode if the CRC fails for the current packet
0 → Discard on CRC error
1 → Do not discard on CRC error
Ciph_En
CRC_En
CRC_ERR
4
Description
Table 18
8.4 RSSI Function Control
0x03 [default 0x87]
Address
Name
-
0X03
RSSIA_Rfsh
RSSIA_thr
Bits
R/W
Description
7..5
r/w
Reserved, always set to 000b
4
r/w
Analog RSSI refresh control bit (Continuous Mode only):
0 → Do not refresh RSSI value
1 → Refresh RSSI value
See Section 3.7 for details of RSSI operation
3..0
r/w
DRSSI threshold: when the RSSIA level exceeds RSSIA_thr, the RSSID pin is set high
default is 0111b
Table 19
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8.5 RSSI Value
0x04 [default 0x20]
Address
Name
-
Bits
R/W
Description
7..6
r/w
Reserved, always set to 00b
AGC_En
5
r/w
Automatic Gain Control Enable (Continuous Mode only):
0 → Disable AGC
1 → Enable AGC
AGC should be left enabled for most applications
RSSI_G
4
r/w
RSSI Gain Mode Selection (Continuous Mode only):
0 → High gain mode
1 → Low gain mode
RSSI_val
3..0
r/w
4-bit digital value of RSSI level after A/D conversion.
0X04
Table 20
8.6 Data Format Control
0x05 [default 0x0F]
Address
Name
Bits
R/W
Description
DevAdd_En
7
r/w
Insert sender (local device) address in transmit packet (Burst Mode only):
0 → Insert sender address
1 → Do not insert sender address
DevAdd_pos
6
r/w
Output received sender address before payload data on receive (Burst Mode only):
0 → Output sender address
1 → Do not output sender address
DesAdd_ref
5
r/w
Destination address reference (Burst Mode only):
0 → Registers 0x09 - 0x0D
1 → Provided by the host microcontroller before data is written to FIFO
r/w
FIFO length (number of payload data bytes, Burst Mode only):
00000 → 1 byte
00001 → 2 bytes
…
11111 → 32 bytes
Payload data bytes = FIFO_len + 1
where 0 ≤ FIFO_len ≤ 31
default is 01111b
0X05
FIFO_len
4..0
Table 21
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8.7 Preamble Control
0x06 [default 0x30, override to 0xB0]
Address
Name
-
0X06
Pream_len
-
Bits
R/W
Description
7..6
r/w
Reserved, always set to 10b
5..4
r/w
Preamble length (Burst Mode only):
00 → 4 bits
01 → 8 bits
10 → 12 bits
11 → 16 bits
3..0
r/w
Reserved, always set to 0000b
Table 22
8.8 Transmitter Rise/Fall Time Control
0x07 [default 0x21]
Address
Name
-
PA_RU
Bits
R/W
7..6
r/w
Reserved, always set to 00b
r/w
Power amplifier ramp-up time (Burst Mode only), reduces transmit bandwidth
00 → 0 µs
01 → 10 µs
10 → 20 µs
11 → 30 µs
r/w
Power amplifier ramp-down time (Burst Mode only), reduces transmit bandwidth
00 → 5 µs
01 → 10 µs
10 → 20 µs
11 → 30 µs
r/w
Power amplifier turn-on delay time (Burst Mode only)
00 → 0 µs
01 → 50 µs
10 → 100 µs
11 → 150 µs
5..4
0X07
PA_RD
PA_ON
3..2
1..0
Description
Table 23
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8.9 Address Length Control
0x08 [default 0X03]
Addr
Name
-
Bits
R/W
Description
7..3
r/w
Reserved, always set to 00000b
r/w
Address length of device and destination address (Burst Mode only):
000 → Invalid, do not use
001 → 1 byte
010 → 2 bytes
...
101 → 5 bytes
110 - 111 → Invalid, do not use
default is 011b
0X08
ADDR_len
2..0
Table 24
8.10 Destination Address
0x09 [default 0X00]
Address
0X09
Name
Dest_ADDR1
Bits
7..0
R/W
r/w
Description
Destination address 1
Table 25
0x0A [default 0X00]
Address
0X0A
Name
Dest_ADDR2
Bits
7..0
R/W
r/w
Description
Destination address 2
Table 26
0x0B [default 0X00]
Address
0X0B
Name
Dest_ADDR3
Bits
7..0
R/W
r/w
Description
Destination address 3
Table 27
0x0C [default 0X00h]
Address
0X0C
Name
Dest_ADDR4
Bits
7..0
R/W
Description
r/w
Destination address 4
Table 28
0x0D [default 0X00h]
Address
0X0D
Name
Dest_ADDR5
Bits
7..0
R/W
r/w
Description
Destination address 5
Table 29
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8.11 Sender (Local Device) Address
0x0E [default 0X00]
Address
0X0E
Name
Dev_ADDR1
Bits
7..0
R/W
r/w
Description
Local device address 1
Table 30
0x0F [default 0X00]
Address
0X0F
Name
Dev_ADDR2
Bits
7..0
R/W
r/w
Description
Local device address 2
Table 31
0x10 [default 0X00]
Address
0X10
Name
Dev_ADDR3
Bits
7..0
R/W
r/w
Description
Local device address 3
Table 32
0x11 [default 0X00h]
Address
0X11
Name
Dev_ADDR4
Bits
7..0
R/W
Description
r/w
Local device address 4
Table 33
0x12 [default 0X00h]
Address
0X12
Name
Dev_ADDR5
Bits
7..0
R/W
r/w
Description
Local device address 5
Table 34
8.12 Reserved
Do not write to this configuration register address 0x13. It should retain its power-on default value.
8.13 PLL Turn-on Control
0x14 [default 0X00]
Address
0X14
Name
PLL_ON
Bits
7..0
R/W
r/w
Description
PLL pre start time:
0000000 → No pre turn-on time
PLL pre start time = PLL_ON * 20 µs, where 0 < PLL_ON < 255
Table 35
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8.14 Analog Turn-On Control
0x15 [default 0XB4]
Address
Name
-
0X15
ANA_ON
-
Bits
R/W
Description
7..6
r/w
Reserved, always set to 10b
5..4
r/w
Analog circuitry turn-on time (Burst Mode only):
00 → 0 µs
01 → 10 µs
10 → 20 µs
11 → 40 µs
Note: default value is suitable for most applications
3..0
r/w
Reserved, always set to 0100b
Table 36
8.15 Reserved
Do not write to configuration register address 0x16. It should retain its power-on default value.
8.16 Option Control
0x17 – [default 22h]
Address
Name
Bits
-
R/W
Description
7..2
r/w
Reserved, always set to 0010 00b
LVLINT
1
r/w
Active edge for INT pin (Burst Mode only):
0 → Falling edge active (active low)
1 → Rising edge active (active high)
LVLDRSSI
0
r/w
Active edge for DRSSI pin (Continuous Mode only):
0 → Falling edge active (active low)
1 → Rising edge active (active high)
0X17
Table 37
8.17 Reserved
Do not write to configuration registers addresses 0x18 and higher, except as discussed in Section 8.18.
8.18 Default Overrides for Enhanced Performance
TRC104 operation can be enhanced by overriding several default values in register addresses shown in Table 38.
These override values should be written before the TRC104 is first placed in a transmit or receive mode.
Register Address
Power-on Default
Default Override
0X06
0X30
0XB0
0X2C
0X19
0X18
0X39
0XBB
0XB9
0X4F
0X26
0X66
0X77
0X7C
0X5C
Table 38
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9 Configuration Example
This example details the configuration of a TRC104 application with the following specifications:
Radios in System
Base and remote
Operating Frequency and Power
2408 MHz, 0 dBm
RF Data Rate
1 Mb/s
Address Length
2 bytes
Base Address
0XAA01
Remote Address
0XAA02
Destination Address
Auto-insert
Sender Address Option
Enabled, auto-insert
Sender Address Output on Receive
Enabled
Payload Data Length
4 bytes
DC-Balanced Data Scrambling
Enabled
CRC Error Detection
Enabled
Packet Error Handling
Discard
PLL Pre-start
Enabled
Power Amplifier Ramp Up/Down Timing
10/5 µs
INT Flag Assertion State
High
Host Serial Clocking Rate
1 Mb/s
9.1 Burst Packet Mode Initialization
The following table of 16-bit register configuration constants are used to initialize and control the radios. The most
significant bit of the first byte is the configuration write bit. The next seven bits specify the register address. The
second byte specifies the register configuration.
Label
Hex Constant
Configuration Register Detail
Ch_8_RX
0X8008
T/R and Channel Control 0X00: RX, 2408 MHz
Ch_8_TX
0X8088
T/R and Channel Control 0X00: TX, 2408 MHz
TX_Pwr
0x811B
TX Power and Crystal Frequency Control 0X01: 0 dBm, 16 MHz
FIFO_Sz
0X8503
Data Format Control 0x05: auto-insert destination in TX, auto-insert sender in TX, output
sender with RX, 4 byte FIFO
Pre_Ctl
0x86B0
Preamble Control 0X06: default override for enhanced performance
Addr_Len
0X8802
Address Length Control 0X08: 2-byte addressing
Bs_Snd_Lo
0X8E01
Base Sender (Local Device) Low Address 0X0E: base low address byte
Bs_Snd_Hi
0X8FAA
Base Sender (Local Device) High Address 0X0F: base high address byte
Bs_Dst_Lo
0X8902
Base Destination Low Address 0X09: remote low address byte
Bs_Dst_Hi
0X8AAA
Base Destination High Address 0X0A: remote high address byte
Rm_Snd_Lo
0X8E02
Remote Sender (Local Device) Low Address 0X0E: remote low address byte
Rm_Snd_Hi
0X8FAA
Remote Sender (Local Device) High Address 0X0F: remote high address byte
Rm_Dst_Lo
0X8901
Remote Destination Low Address 0X09: base low address byte
Rm_Dst_Hi
0X8AAA
Remote Destination High Address 0X0A: base high address byte
PLL_Del
0X9401
PLL Turn-on Control Address 0X14: 20 µs delay
Ovr_2C
0XAC18
Register 0x2C: default override for enhanced performance
Ovr_39
0XB9B9
Register 0x39: default override for enhanced performance
Ovr_4F
0XCF66
Register 0x4F: default override for enhanced performance
Ovr_77
0XF75C
Register 0x77: default override for enhanced performance
Table 39
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To support the specified configuration, 14 of the configuration register default values must be initialized to new
values. Only two calculations are required to determine the configuration register constants. The first calculation
is determining the value of Ch_Num in control register 0X00. The calculation is simple:
FRF = 2400 + Ch_Num, 1 ≤ Ch_Num ≤ 127, in MHz
or
Ch_Num = FRF - 2400
for 2408 MHz channel operation:
Ch_Num = 2408 - 2400 = 8
The second calculation determines the best PLL pre-start delay time. Ideally the PLL turn-on delay time as shown
in Figure 5 plus the 170 µs PLL lock time should equal the Burst Transmit Mode FIFO write time. Referring to
Figure 13 and Table 12, the FIFO write time for a 1 Mb/s serial clock rate is:
20 µs MODE to FIFO write
32 µs to write 4 bytes
3 µs to write the final three dummy bits
55 µs total
Given the short FIFO length and the 1 Mb/s serial write rate, the FIFO write time is shorter than the PLL lock time,
so no delay is necessary. A minimum delay of 20 µs must be set in the PLL Turn-on Control register to enable
PLL Pre-start function. Using the 20 µs delay value provides a net Pre-start time of:
55 - 20 = 35 µs, shorting the transmit turn on latency from to 170 - 35 = 135 µs
If the FIFO was larger and/or the serial rate slower, the PLL Pre-start function would provide a bigger benefit.
1. To initialize each TRC104, enter Sleep Mode by setting control line PMODE to 0 and control line
MODE to 1. Hold this state for 100 ms.
2. Enter Configuration Mode by setting control line MODE to 0, and control lines CS and PMODE to 1.
Hold for 120 ms to allow the radio to reset, which loads the power-on default values in all configuration
registers.
3. Following the 120 ms reset period and holding the control lines in Configuration Mode, write the Ch_8_RX
configuration constant 0X8008 to the TRC104 (base or remote). Set the CS control line to 0 for at least
5 µs, and then set the CS control line back to 1.
4. For the base TRC104, write the following additional configuration constants to the radio, cycling the CS
control line to 0 for at least 5 µs between each write:
TX_Pwr → 0X811B
FIFO_Sz → 0X8503
Pre_Ctl → 0X86B0
Addr_len → 0X8802
Bs_Snd_Lo → 0X8E01
Bs_Snd_Hi → 0X8FAA
Bs_Dst_Lo → 0X8902
Bs_Dst_Hi → 0X8AAA
PLL_Del → 0X9401
Ovr_2C → 0XAC18
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Ovr_39 → 0xB9B9
Ovr_4F → 0XCF66
Ovr_77 → 0XF75C
5. For the remote TRC104, write the following additional configuration constants to the radio, cycling the
CS control line to 0 for at least 5 µs between each write:
TX_Pwr → 0X811B
FIFO_Sz → 0X8503
Pre_Ctl → 0X86B0
Addr_len → 0X8802
Rm_Snd_Lo → 0X8E02
Rm_Snd_Hi → 0X8FAA
Rm_Dst_Lo → 0X8901
Rm_Dst_Hi → 0X8AAA
PLL_Del → 0X9401
Ovr_2C → 0XAC18
Ovr_39 → 0xB9B9
Ovr_4F → 0XCF66
Ovr_77 → 0XF75C
6. Enter Standby Mode by setting control line PMODE to 1, and control lines CS and MODE to 0. This
mode, Stop Mode, Configuration Mode, Transmit Load/Receive Mode or Burst Transmit Mode can
be used without re-initialization. Re-initialization is always required following Sleep Mode or Power-up.
9.2 Burst Packet Transmission
1. To transmit, enter Configuration Mode by setting control line MODE to 0, and control lines CS
and PMODE to 1.
2. Write the Ch_8_TX configuration register constant 0X8088 to the TRC104. Then set the CS control
line to 0 for at least 5 µs.
3. With CS still 0, set control lines PMODE and MODE to 1 to enter Transmit Load/Receive Mode.
4. The host microcontroller will clock the transmit bits into of the FIFO.
5. After a 20 µs delay, begin clocking transmit bits into the FIFO, loading the four payload data bytes.
6. Count each bit input to the transmit FIFO until the FIFO is completely filled (4 bytes = 32 bits).
7. Then add three additional clock cycles. The bits on these three clock cycles can be any value.
Internally the radio replaces the placeholder bytes with the destination and sender addresses.
8. Set the MODE control line to 0. This initiates the RF transmission.
9. The INT flag is asserted when the RF transmission is complete.
10. Placing the TRC104 in another operating mode, such as Transmit Load/Receive Mode, will
reset the INT flag.
9.3 Burst Packet Reception
1. To receive, enter Configuration Mode by setting control line MODE to 0, and lines CS and PMODE to 1.
2. Write the Ch_8_RX configuration register constant 0X8008 to the TRC104. Then set the CS control
line to 0 for at least 5 µs.
3. With CS still 0, set control lines PMODE and MODE to 1 to enter Transmit Load/Receive Mode.
4. In receive, the INT flag is asserted to indicate there are received bits in the FIFO.
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5. The host microcontroller will clock the received bits out of the FIFO.
6. Clocking bits out of the receive FIFO begins with two dummy clock cycles. The bits on these two clock
cycles are discarded.
7. The first bit from the FIFO is output on the third clock. After clocking out a group of eight bits, check the
INT flag line. The flag will reset after the next-to-last byte is clocked from the FIFO. At this point clock the
final eight bits from the FIFO.
8. All bytes have now been clocked from the FIFO. In this example, the two
Sender address bytes and the four payload data bytes will be output.
9. Three more clock cycles must follow the final FIFO byte in order to reset the TRC104
to receive the next packet. The bits on these three clock cycles are discarded.
10 Burst Packet Mode Serial Port Message Examples
Sections 10.1 through 10.4 below provide examples of Burst Packet Mode serial port transmit and receive
messages. In each example the payload data bytes consist of the following ASCII string:
(stx)TRC104 Range Test Demo(etx)
This 24 byte string in hexadecimal is:
02 54 52 43 31 30 34 20 52 61 6E 67 65 20 54 65 73 74 20 44 65 6D 6F 03
The FIFO length is set to 24 bytes, or 0X18. The two-byte destination address used is 0XAA02, and the sender
(local device) address used is 0XAA01. Where sender address transmission is enabled, the TRC104 is also
configured to output the sender address in front of the received payload data bytes (see Section 8.6, Table 21).
10.1 Destination Address from Configuration Registers, No Sender Address
Transmit hex message: 02 54 52 43 31 30 34 20 52 61 6E 67 65 20 54 65 73 74 20 44 65 6D 6F 03
Receive hex message: 02 54 52 43 31 30 34 20 52 61 6E 67 65 20 54 65 73 74 20 44 65 6D 6F 03
10.2 Destination Address Written by Host, No Sender Address
Transmit hex message: AA 02 02 54 52 43 31 30 34 20 52 61 6E 67 65 20 54 65 73 74 20 44 65 6D 6F 03
Receive hex message: 02 54 52 43 31 30 34 20 52 61 6E 67 65 20 54 65 73 74 20 44 65 6D 6F 03
10.3 Destination and Sender Addresses from Configuration Registers
Transmit hex message: 02 54 52 43 31 30 34 20 52 61 6E 67 65 20 54 65 73 74 20 44 65 6D 6F 03
Receive hex message: AA 01 02 54 52 43 31 30 34 20 52 61 6E 67 65 20 54 65 73 74 20 44 65 6D 6F 03
10.4 Destination Address Written by Host, Sender Address from Configuration Register
Transmit hex message: AA 02 02 54 52 43 31 30 34 20 52 61 6E 67 65 20 54 65 73 74 20 44 65 6D 6F 03
Receive hex message: AA 01 02 54 52 43 31 30 34 20 52 61 6E 67 65 20 54 65 73 74 20 44 65 6D 6F 03
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11 Package Dimensions
4 x 4 m m
Q F N P a c k a g e D im e n s io n s
T o p V ie w
A
B
B o tto m
F
V ie w
C
E
D
G
H
S id e V ie w
J
I
K
Figure 21
Dimension
Millimeters
Inches
Min
Nom
Max
Min
Nom
Max
A
3.900
4.000
4.100
0.154
0.157
0.161
B
3.900
4.000
4.100
0.154
0.157
0.161
C
2.550
2.650
2.750
0.100
0.104
0.108
D
2.550
2.650
2.750
0.100
0.104
0.108
E
-
0.500
-
-
0.020
-
F
-
2.540
-
-
0.100
-
G
0.350
0.400
0.550
0.014
0.016
0.022
H
0.180
0.230
0.280
0.007
0.009
0.011
I
0.800
0.850
1.000
0.028
0.030
0.031
J
0.195
0.203
0.211
0.008
0.008
0.008
K
0.000
0.025
0.050
0.000
0.001
0.002
Table 40
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