TM SPANSION Flash Memory Data Sheet September 2003 TM This document specifies SPANSION memory products that are now offered by both Advanced Micro Devices and Fujitsu. Although the document is marked with the name of the company that originally developed the specification, these products will be offered to customers of both AMD and Fujitsu. Continuity of Specifications There is no change to this datasheet as a result of offering the device as a SPANSION revisions will occur when appropriate, and changes will be noted in a revision summary. TM product. Future routine Continuity of Ordering Part Numbers AMD and Fujitsu continue to support existing part numbers beginning with "Am" and "MBM". To order these products, please use only the Ordering Part Numbers listed in this document. For More Information Please contact your local AMD or Fujitsu sales office for additional information about SPANSION solutions. TM memory FUJITSU SEMICONDUCTOR DATA SHEET DS05-20888-6E FLASH MEMORY CMOS 8 M (1 M × 8/512 K × 16) BIT MBM29LV800TE60/70/90/MBM29LV800BE60/70/90 ■ DESCRIPTION The MBM29LV800TE/BE are a 8 M-bit, 3.0 V-only Flash memory organized as 1 M bytes of 8 bits each or 512 Kwords of 16 bits each. The MBM29LV800TE/BE are offered in a 48-pin TSOP (1) , 48-pin CSOP and 48ball FBGA package. These devices are designed to be programmed in a system with the standard system 3.0 V VCC supply. 12.0 V VPP and 5.0 V VCC are not required for write or erase operations. The devices can also be reprogrammed in standard EPROM programmers. (Continued) ■ PRODUCT LINE UP Part No. MBM29LV800TE/BE VCC = 3.3 V +0.3 V −0.3 V 60 VCC = 3.0 V +0.6 V −0.3 V 70 90 Max Address Access Time (ns) 60 70 90 Max CE Access Time (ns) 60 70 90 Max OE Access Time (ns) 30 30 35 Ordering Part No. ■ PACKAGES 48-pin Plastic TSOP (1) 48-pin Plastic CSOP 48-ball Plastic FBGA (FPT-48P-M19) (LCC-48P-M03) (BGA-48P-M20) MBM29LV800TE/BE60/70/90 (Continued) The standard MBM29LV800TE/BE offer access times 60 ns, 70 ns and 90 ns, allowing operation of high-speed microprocessors without wait state. To eliminate bus contention, the devices have separate chip enable (CE) , write enable (WE) , and output enable (OE) controls. The MBM29LV800TE/BE are pin and command set compatible with JEDEC standard E2PROMs. Commands are written to the command register using standard microprocessor write timings. Register contents serve as input to an internal state-machine which controls the erase and programming circuitry. Write cycles also internally latch addresses and data needed for the programming and erase operations. Reading data out of the devices is similar to reading from 5.0 V and 12.0 V Flash or EPROM devices. The MBM29LV800TE/BE are programmed by executing the program command sequence. This will invoke the Embedded Program Algorithm which is an internal algorithm that automatically times the program pulse widths and verifies proper cell margin. Typically, each sector can be programmed and verified in about 0.5 seconds. Erase is accomplished by executing the erase command sequence. This will invoke the Embedded Erase Algorithm which is an internal algorithm that automatically preprograms the array if it is not already programmed before executing the erase operation. During erase, the devices automatically time the erase pulse widths and verify proper cell margin. A sector is typically erased and verified in 1.0 second. (If already completely preprogrammed.) The devices also feature a sector erase architecture. The sector mode allows each sector to be erased and reprogrammed without affecting other sectors. The MBM29LV800TE/BE are erased when shipped from the factory. The devices feature single 3.0 V power supply operation for both read and write functions. Internally generated and regulated voltages are provided for the program and erase operations. A low VCC detector automatically inhibits write operations on the loss of power. The end of program or erase is detected by Data Polling of DQ7, by the Toggle Bit feature on DQ6, or the RY/BY output pin. Once the end of a program or erase cycle has been completed, the devices internally resets to the read mode. The MBM29LV800TE/BE also have hardware RESET pins. When this pin is driven low, execution of any Embedded Program Algorithm or Embedded Erase Algorithm is terminated. The internal state machine is then reset to the read mode. The RESET pin may be tied to the system reset circuitry. Therefore, if a system reset occurs during the Embedded Program Algorithm or Embedded Erase Algorithm, the device is automatically reset to the read mode and will have erroneous data stored in the address locations being programmed or erased. These locations need re-writing after the Reset. Resetting the device enables the system’s microprocessor to read the boot-up firmware from the Flash memory. Fujitsu’s Flash technology combines years of Flash memory manufacturing experience to produce the highest levels of quality, reliability, and cost effectiveness. The MBM29LV800TE/BE memory electrically erase all bits within a sector simultaneously via Fowler-Nordhiem tunneling. The bytes/words are programmed one byte/word at a time using the EPROM programming mechanism of hot electron injection. 2 MBM29LV800TE/BE60/70/90 ■ FEATURES • 0.23 µm Process Technology • Single 3.0 V Read, Program, and Erase Minimized system level power requirements • Compatible with JEDEC-standard Commands Use the same software commands as E2PROMs • Compatible with JEDEC-standard World-wide Pinouts 48-pin TSOP (1) (Package suffix : TN Normal Bend Type) 48-pin CSOP (Package suffix : PCV) 48-ball FBGA (Package suffix : PBT) • Minimum 100,000 Program/Erase Cycles • High Performance 70 ns maximum access time • Sector Erase Architecture One 8 Kwords, two 4 Kwords, one 16 Kwords, and fifteen 32 Kwords sectors in word mode One 16 Kbytes, two 8 Kbytes, one 32 Kbytes, and fifteen 64 Kbytes sectors in byte mode Any combination of sectors can be concurrently erased, and also supports full chip erase. • Boot Code Sector Architecture T = Top sector B = Bottom sector • Embedded EraseTM* Algorithm Automatically pre-programs and erases the chip or any sector. • Embedded ProgramTM* Algorithm Automatically writes and verifies data at specified address. • Data Polling and Toggle Bit Feature for Detection of Program or Erase Cycle Completion • Ready/Busy Output (RY/BY) Hardware method for detection of program or erase cycle completion • Automatic Sleep Mode When addresses remain stable, MBM29LV800TE/BE automatically switch themselves to low power mode. • Low VCC Write Inhibit ≤ 2.5 V • Erase Suspend/Resume Suspends the erase operation to allow a read data and/or program in another sector within the same device. • Sector Protection Hardware method disables any combination of sectors from program or erase operations. • Sector Protection Set Function by Extended Sector Protection Command • Fast Programming Function by Extended Command • Temporary Sector Unprotection Temporary sector unprotection via the RESET pin * : Embedde EraseTM and Embedded ProgramTM are trademarks of Advanced Micro Devices, Inc. 3 MBM29LV800TE/BE60/70/90 ■ PIN ASSIGNMENTS TSOP (1) A15 1 A14 2 48 A16 47 BYTE A13 A12 3 46 VSS 4 45 DQ15/A-1 A11 5 44 DQ7 A10 6 43 DQ14 A9 7 42 DQ6 A8 8 41 DQ13 N.C. 9 40 DQ5 N.C. 10 39 DQ12 38 DQ4 37 VCC (Marking Side) MBM29LV800TE/MBM29LV800BE Normal Bend WE 11 RESET 12 N.C. 13 36 DQ11 N.C. 14 35 DQ3 RY/BY 15 34 DQ10 A18 16 33 DQ2 A17 17 32 DQ9 A7 18 31 DQ1 A6 19 30 DQ8 A5 20 29 DQ0 A4 21 28 OE A3 22 27 VSS A2 23 26 CE A1 24 25 A0 (FPT-48P-M19) (Continued) 4 MBM29LV800TE/BE60/70/90 CSOP (TOP VIEW) 48 A0 2 47 CE A3 3 46 VSS A4 4 45 OE A5 5 44 DQ0 A6 6 43 DQ8 A7 7 42 DQ1 A17 8 41 DQ9 A18 9 40 DQ2 RY/BY 10 39 DQ10 N.C. 11 38 DQ3 N.C. 12 37 DQ11 RESET 13 36 VCC WE 14 35 DQ4 N.C. 15 34 DQ12 N.C. 16 33 DQ5 A8 17 32 DQ13 A9 18 31 DQ6 A10 19 30 DQ14 A11 20 29 DQ7 A12 21 28 DQ15/A-1 A13 22 27 VSS A14 23 26 BYTE A15 24 25 A16 A1 1 A2 (Marking side) (LCC-48P-M03) (Continued) 5 MBM29LV800TE/BE60/70/90 (Continued) FBGA (TOP VIEW) Marking side A1 A2 A3 A4 A5 A6 B1 B2 B3 B4 B5 B6 C1 C2 C3 C4 C5 C6 D1 D2 D3 D4 D5 D6 E1 E2 E3 E4 E5 E6 F1 F2 F3 F4 F5 F6 G1 G2 G3 G4 G5 G6 H1 H2 H3 H4 H5 H6 (BGA-48P-M20) 6 A1 A3 A2 A7 A3 RY/BY A4 WE A5 A9 A6 A13 B1 A4 B2 A17 B3 N.C. B4 RESET B5 A8 B6 A12 C1 A2 C2 A6 C3 A18 C4 N.C. C5 A10 C6 A14 D1 A1 D2 A5 D3 N.C. D4 N.C. D5 A11 D6 A15 E1 A0 E2 DQ0 E3 DQ2 E4 DQ5 E5 DQ7 E6 A16 F1 CE F2 DQ8 F3 DQ10 F4 DQ12 F5 DQ14 F6 BYTE G1 OE G2 DQ9 G3 DQ11 G4 VCC G5 DQ13 G6 DQ15/A-1 H1 VSS H2 DQ1 H3 DQ3 H4 DQ4 H5 DQ6 H6 VSS MBM29LV800TE/BE60/70/90 ■ PIN DESCRIPTION Pin name Function A18 to A0, A-1 Address Inputs DQ15 to DQ0 Data Inputs/Outputs CE Chip Enable OE Output Enable WE Write Enable RY/BY Ready/Busy Output RESET Hardware Reset Pin/Temporary Sector Unprotection BYTE Selects 8-bit or 16-bit mode N.C. No Internal Connection VSS Device Ground VCC Device Power Supply 7 MBM29LV800TE/BE60/70/90 ■ BLOCK DIAGRAM RY/BY Buffer RY/BY DQ15 to DQ0 VCC VSS Erase Voltage Generator WE BYTE RESET Input/Output Buffers State Control Command Register Program Voltage Generator Chip Enable Output Enable Logic CE STB Data Latch OE Y-Decoder STB Low VCC Detector Timer for Program/Erase Address X-Decoder Latch A18 to A0 A-1 ■ LOGIC SYMBOL A-1 19 A18 to A0 16 or 8 DQ15 to DQ0 CE OE WE RESET BYTE 8 RY/BY Y-Gating Cell Matrix MBM29LV800TE/BE60/70/90 ■ DEVICE BUS OPERATION MBM29LV800TE/BE User Bus Operations (BYTE = VIH) CE OE WE A0 A1 A6 A9 DQ15 to DQ0 RESET L L H L L L VID Code H L L H H L L VID Code H L L H A0 A1 A6 A9 DOUT H Standby H X X X X X X High-Z H Output Disable L H H X X X X High-Z H L H L A0 A1 A6 A9 DIN H Enable Sector Protection * * L VID L H L VID X H Verify Sector Protection *2, *4 L L H L H L VID Code H Temporary Sector Unprotection*5 X X X X X X X X VID Reset (Hardware) /Standby X X X X X X X High-Z L Operation Auto-Select Manufacturer Code *1 1 Auto-Select Device Code * Read * 3 Write (Program/Erase) 2, 4 Legend : L = VIL, H = VIH, X = VIL or VIH, = Pulse input. See “■ DC CHARACTERISTICS” for voltage levels. *1: Manufacturer and device codes may also be accessed via a command register write sequence. See “Sector Address Tables (MBM29LV800BE) ” in “■ FLEXIBLE SECTOR-ERASE ARCHITECTURE”. *2: Refer to Sector Protection. *3: WE can be VIL if OE is VIL, OE at VIH initiates the write operations. *4: VCC = 3.0 V to 3.6 V (MBM29LV800TE/BE 60) = 2.7 V to 3.6 V (MBM29LV800TE/BE 70/90) *5: Also used for the extended sector protection. 9 MBM29LV800TE/BE60/70/90 MBM29LV800TE/BE User Bus Operations (BYTE = VIL) CE OE WE DQ15/ A-1 A0 A1 A6 A9 L L H L L L L VID Code H L L H L H L L VID Code H L L H A-1 A0 A1 A6 A9 DOUT H Standby H X X X X X X X High-Z H Output Disable L H H X X X X X High-Z H L H L A-1 A0 A1 A6 A9 DIN H Enable Sector Protection * * L VID L L H L VID X H Verify Sector Protection *2, *4 L L H L L H L VID Code H Temporary Sector Unprotection *5 X X X X X X X X X VID Reset (Hardware) /Standby X X X X X X X X High-Z L Operation Auto-Select Manufacturer Code *1 1 Auto-Select Device Code * Read * 3 Write (Program/Erase) 2, 4 Legend : L = VIL, H = VIH, X = VIL or VIH, DQ7 to DQ0 RESET = Pulse input. See “■ DC CHARACTERISTICS” for voltage levels. *1: Manufacturer and device codes may also be accessed via a command register write sequence. See “Sector Address Tables (MBM29LV800BE) ” in “■ FLEXIBLE SECTOR-ERASE ARCHITECTURE”. *2: Refer to Sector Protection. *3: WE can be VIL if OE is VIL, OE at VIH initiates the write operations. *4: VCC = 3.0 V to 3.6 V (MBM29LV800TE/BE 60) = 2.7 V to 3.6 V (MBM29LV800TE/BE 70/90) *5: Also used for the extended sector protection. 10 MBM29LV800TE/BE60/70/90 MBM29LV800TE/BE Command Definitions Command Sequence Read/Reset*1 Read/Reset*1 Autoselect Program Chip Erase Sector Erase Word Byte Word Byte Word Byte Word Byte Word Byte Word Byte Second Fourth Bus Bus First Bus Third Bus Fifth Bus Sixth Bus Bus Read/Write Write Write Cycle Write Cycle Write Cycle Write Cycle Write Cycle Cycle Cycles Req’d Addr. Data Addr. Data Addr. Data Addr. Data Addr. Data Addr. Data 1 3 3 4 6 6 XXXh F0h 555h AAAh 555h AAAh 555h AAAh 555h AAAh 555h AAAh AAh AAh AAh AAh AAh 2AAh 555h 2AAh 555h 2AAh 555h 2AAh 555h 2AAh 555h 55h 55h 55h 55h 55h 555h AAAh 555h AAAh 555h AAAh 555h AAAh 555h AAAh F0h RA*5 RD*5 90h IA*5 ID*5 A0h PA PD 80h 80h 555h AAAh 555h AAAh AAh AAh 2AAh 555h 2AAh 555h 55h 555h AAAh 10h 55h SA 30h Erase Suspend 1 XXXh B0h Erase Resume 1 XXXh 30h 20h Set to Fast Mode Word Fast Program*2 Word Reset from Fast Mode*2 Word Extended Sector Protection*3 Word Byte Byte Byte Byte 3 2 2 3 555h AAAh XXXh XXXh XXXh XXXh AAh 2AAh 555h 555h AAAh PD *4 XXXh F0h A0h 90h 55h PA XXXh XXXh 60h SPA 60h SPA 40h SPA*5 SD*5 *1 : Both of these reset commands are equivalent. *2 : This command is valid during Fast Mode. *3 : This command is valid while RESET = VID (except during HiddenROM MODE) . *4 : The data “00h” is also acceptable. *5 : The fourth bus cycle is only for read. Notes : • Address bits A18 to A11 = X = “H” or “L” for all address commands except or Program Address (PA) and Sector Address (SA) . • Bus operations are defined in “MBM29LV800TE/BE User Bus Operations (BYTE = VIH)” and “MBM29LV800TE/BE User Bus Operations (BYTE = VIL)”. • RA = Address of the memory location to be read. IA = Autoselect read address that sets A6, A1, A0. PA = Address of the memory location to be programmed. Addresses are latched on the falling edge of the WE pulse. SA = Address of the sector to be erased. The combination of A18, A17, A16, A15, A14, A13, and A12 will uniquely select any sector. 11 MBM29LV800TE/BE60/70/90 • RD = Data read from location RA during read operation. ID = Device code/manufacture code for the address located by IA. PD = Data to be programmed at location PA. Data is latched on the rising edge of WE. • SPA = Sector address to be protected. Set sector address (SA) and (A6, A1, A0) = (0, 1, 0) . SD = Sector protection verify data. Output 01h at protected sector addressed and output 00h at unprotected sector addresses. • The system should generate the following address patterns : Word Mode : 555h or 2AAh to addresses A10 to A0 Byte Mode : AAAh or 555h to addresses A10 to A-1 • Both Read/Reset commands are functionally equivalent, resetting the device to the read mode. • The command combinations not described in Command Definitions are illegal. MBM29LV800TE/BE Sector Protection Verify Autoselect Codes Type A18 to A12 A6 A1 A0 A-1*1 Code (HEX) X VIL VIL VIL VIL 04h X VIL VIL VIH VIL DAh X 22DAh X VIL VIL VIH VIL 5Bh X 225Bh Sector Addresses VIL VIH VIL VIL 01h*2 Manufacture’s Code MBM29LV800TE Device Code MBM29LV800BE Byte Word Byte Word Sector Protection *1 : A-1 is for Byte mode. At Byte mode, DQ14 to DQ8 are High-Z and DQ15 is A-1, the lowest address. *2 : Outputs 01h at protected sector addresses and outputs 00h at unprotected sector addresses. Expanded Autoselect Code Table Type Code DQ15 DQ14 DQ13 DQ12 DQ11 DQ10 DQ9 DQ8 DQ7 DQ6 DQ5 DQ4 DQ3 DQ2 DQ1 DQ0 Manufacturer’s Code MBM29 Device LV800TE Code MBM29 LV800BE Sector Protection* (B) 04h A-1/0 DAh (W) 22DAh (B) 5Bh (W) 225Bh 0 0 0 0 0 1 0 0 A-1 HI-Z HI-Z HI-Z HI-Z HI-Z HI-Z HI-Z 1 1 0 1 1 0 1 0 1 1 0 1 1 0 1 0 A-1 HI-Z HI-Z HI-Z HI-Z HI-Z HI-Z HI-Z 0 1 0 1 1 0 1 1 0 0 01h A-1/0 0 0 0 1 0 0 0 0 0 0 0 1 0 0 0 1 0 0 0 1 0 0 1 0 1 1 0 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 * : At Byte mode, DQ14 to DQ8 are High-Z and DQ15 is A-1, the lowest address. (B) : Byte mode (W) : Word mode HI-Z : High-Z 12 MBM29LV800TE/BE60/70/90 ■ FLEXIBLE SECTOR-ERASE ARCHITECTURE Sector Address Tables (MBM29LV800TE) Sector Address A18 A17 A16 A15 A14 A13 A12 ×8) Address Range (× ×16) Address Range (× SA0 0 0 0 0 X X X 00000h to 0FFFFh 00000h to 07FFFh SA1 0 0 0 1 X X X 10000h to 1FFFFh 08000h to 0FFFFh SA2 0 0 1 0 X X X 20000h to 2FFFFh 10000h to 17FFFh SA3 0 0 1 1 X X X 30000h to 3FFFFh 18000h to 1FFFFh SA4 0 1 0 0 X X X 40000h to 4FFFFh 20000h to 27FFFh SA5 0 1 0 1 X X X 50000h to 5FFFFh 28000h to 2FFFFh SA6 0 1 1 0 X X X 60000h to 6FFFFh 30000h to 37FFFh SA7 0 1 1 1 X X X 70000h to 7FFFFh 38000h to 3FFFFh SA8 1 0 0 0 X X X 80000h to 8FFFFh 40000h to 47FFFh SA9 1 0 0 1 X X X 90000h to 9FFFFh 48000h to 4FFFFh SA10 1 0 1 0 X X X A0000h to AFFFFh 50000h to 57FFFh SA11 1 0 1 1 X X X B0000h to BFFFFh 58000h to 5FFFFh SA12 1 1 0 0 X X X C0000h to CFFFFh 60000h to 67FFFh SA13 1 1 0 1 X X X D0000h to DFFFFh 68000h to 6FFFFh SA14 1 1 1 0 X X X E0000h to EFFFFh 70000h to 77FFFh SA15 1 1 1 1 0 X X F0000h to F7FFFh 78000h to 7BFFFh SA16 1 1 1 1 1 0 0 F8000h to F9FFFh 7C000h to 7CFFFh SA17 1 1 1 1 1 0 1 FA000h to FBFFFh 7D000h to 7DFFFh SA18 1 1 1 1 1 1 X FC000h to FFFFFh 7E000h to 7FFFFh 13 MBM29LV800TE/BE60/70/90 Sector Address Tables (MBM29LV800BE) Sector Address 14 A18 A17 A16 A15 A14 A13 A12 ×8) Address Range (× ×16) Address Range (× SA0 0 0 0 0 0 0 X 00000h to 03FFFh 00000h to 01FFFh SA1 0 0 0 0 0 1 0 04000h to 05FFFh 02000h to 02FFFh SA2 0 0 0 0 0 1 1 06000h to 07FFFh 03000h to 03FFFh SA3 0 0 0 0 1 X X 08000h to 0FFFFh 04000h to 07FFFh SA4 0 0 0 1 X X X 10000h to 1FFFFh 08000h to 0FFFFh SA5 0 0 1 0 X X X 20000h to 2FFFFh 10000h to 17FFFh SA6 0 0 1 1 X X X 30000h to 3FFFFh 18000h to 1FFFFh SA7 0 1 0 0 X X X 40000h to 4FFFFh 20000h to 27FFFh SA8 0 1 0 1 X X X 50000h to 5FFFFh 28000h to 2FFFFh SA9 0 1 1 0 X X X 60000h to 6FFFFh 30000h to 37FFFh SA10 0 1 1 1 X X X 70000h to 7FFFFh 38000h to 3FFFFh SA11 1 0 0 0 X X X 80000h to 8FFFFh 40000h to 47FFFh SA12 1 0 0 1 X X X 90000h to 9FFFFh 48000h to 4FFFFh SA13 1 0 1 0 X X X A0000h to AFFFFh 50000h to 57FFFh SA14 1 0 1 1 X X X B0000h to BFFFFh 58000h to 5FFFFh SA15 1 1 0 0 X X X C0000h to CFFFFh 60000h to 67FFFh SA16 1 1 0 1 X X X D0000h to DFFFFh 68000h to 6FFFFh SA17 1 1 1 0 X X X E0000h to EFFFFh 70000h to 77FFFh SA18 1 1 1 1 X X X F0000h to FFFFFh 78000h to 7FFFFh MBM29LV800TE/BE60/70/90 • One 16 Kbytes, two 8 Kbytes, one 32 Kbytes, and fifteen 64 Kbytes • Individual-sector, multiple-sector, or bulk-erase capability • Individual or multiple-sector protection is user definable. (×8) (×16) FFFFFh 7FFFFh (×8) (×16) FFFFFh 7FFFFh EFFFFh 77FFFh DFFFFh 6FFFFh CFFFFh 67FFFh BFFFFh 5FFFFh AFFFFh 57FFFh 9FFFFh 4FFFFh 8FFFFh 47FFFh 7FFFFh 3FFFFh 6FFFFh 37FFFh 5FFFFh 2FFFFh 4FFFFh 27FFFh 3FFFFh 1FFFFh 2FFFFh 17FFFh 1FFFFh 0FFFFh 0FFFFh 07FFFh 07FFFh 03FFFh 05FFFh 02FFFh 03FFFh 01FFFh 00000h 00000h 64 Kbyte 16 Kbyte FBFFFh 7DFFFh 64 Kbyte 8 Kbyte F9FFFh 7CFFFh 64 Kbyte 8 Kbyte F7FFFh 7BFFFh 64 Kbyte 32 Kbyte EFFFFh 77FFFh 64 Kbyte 64 Kbyte DFFFFh 6FFFFh 64 Kbyte 64 Kbyte CFFFFh 67FFFh 64 Kbyte 64 Kbyte BFFFFh 5FFFFh 64 Kbyte 64 Kbyte AFFFFh 57FFFh 64 Kbyte 64 Kbyte 9FFFFh 4FFFFh 64 Kbyte 64 Kbyte 8FFFFh 47FFFh 64 Kbyte 64 Kbyte 7FFFFh 3FFFFh 64 Kbyte 64 Kbyte 6FFFFh 37FFFh 64 Kbyte 64 Kbyte 5FFFFh 2FFFFh 64 Kbyte 64 Kbyte 4FFFFh 27FFFh 64 Kbyte 64 Kbyte 3FFFFh 1FFFFh 32 Kbyte 64 Kbyte 2FFFFh 17FFFh 8 Kbyte 64 Kbyte 1FFFFh 0FFFFh 8 Kbyte 64 Kbyte 0FFFFh 07FFFh 64 Kbyte 16 Kbyte 00000h 00000h MBM29LV800TE Sector Architecture MBM29LV800BE Sector Architecture 15 MBM29LV800TE/BE60/70/90 ■ FUNCTIONAL DESCRIPTION Read Mode The MBM29LV800TE/BE have two control functions which must be satisfied in order to obtain data at the outputs. CE is the power control and should be used for a device selection. OE is the output control and should be used to gate data to the output pins if a device is selected. Address access time (tACC) is equal to delay from stable addresses to valid output data. The chip enable access time (tCE) is the delay from stable addresses and stable CE to valid data at the output pins. The output enable access time is the delay from the falling edge of OE to valid data at the output pins (Assuming the addresses have been stable for at least tACC-tOE time) . When reading out data without changing addresses after power-up, it is necessary to input hardware reset or change CE pin from “H” or “L” Standby Mode There are two ways to implement the standby mode on the MBM29LV800TE/BE devices, one using both the CE and RESET pins; the other via the RESET pin only. When using both pins, a CMOS standby mode is achieved with CE and RESET inputs both held at VCC ± 0.3 V. Under this condition, the current consumed is less than 5 µA. The device can be read with standard access time (tCE) from either of these standby modes. During Embedded Algorithm operation, VCC active current (ICC2) is required even CE = “H”. When using the RESET pin only, a CMOS standby mode is achieved with RESET input held at VSS ± 0.3 V (CE = “H” or “L”) . Under this condition the current consumed is less than 5 µA. Once the RESET pin is taken high, the device requires tRH as wake up time for outputs to be valid for read access. In the standby mode, the outputs are in the high impedance state, independently of the OE input. Automatic Sleep Mode There is a function called automatic sleep mode to restrain power consumption during read-out of MBM29LV800TE/BE data. This mode can be useful in the application such as handy terminal which requires low power consumption. To activate this mode, MBM29LV800TE/BE automatically switches themselves to low power mode when MBM29LV800TE/BE addresses remain stable during access time of 150 ns. It is not necessary to control CE, WE, and OE on the mode. Under the mode, the current consumed is typically 1 µA (CMOS Level) . Since the data are latched during this mode, the data are read-out continuously. If the addresses are changed, the mode is canceled automatically, and MBM29LV800TE/BE read-out the data for changed addresses. Output Disable With the OE input at a logic high level (VIH) , the output from the devices is disabled. This will cause the output pins to be in a high impedance state. Autoselect The autoselect mode allows the reading out of a binary code from the devices and will identify its manufacturer and type. This mode is intended for use by programming equipment for the purpose of automatically matching the devices to be programmed with its corresponding programming algorithm. This mode is functional over the entire temperature range of the devices. To activate this mode, the programming equipment must force VID (11.5 V to 12.5 V) on address pin A9. Two identifier bytes may then be sequenced from the devices outputs by toggling address A0 from VIL to VIH. All addresses are DON’T CARES except A0, A1, A6, and A-1. (See “MBM29LV800TE/BE Sector Protection Verify Autoselect Codes” in “ DEVICE BUS OPERATION”.) The manufacturer and device codes may also be read via the command register, for instances when the MBM29LV800TE/BE are erased or programmed in a system without access to high voltage on the A9 pin. The command sequence is illustrated in “MBM29LV800TE/BE Command Definitions” in “ DEVICE BUS OPERATION”. (Refer to Autoselect Command section.) 16 MBM29LV800TE/BE60/70/90 Word 0 (A0 = VIL) represents the manufacturer’s code (Fujitsu = 04h) and (A0 = VIH) represents the device identifier code (MBM29LV800TE = DAh and MBM29LV800BE = 5Bh for × 8 mode; MBM29LV800TE = 22DAh and MBM29LV800BE = 225Bh for × 16 mode) . These two bytes/words are given in “MBM29LV800TE/BE Sector Protection Verify Autoselect Codes” and “Expanded Autoselect Code Table” in “ DEVICE BUS OPERATION”. All identifiers for manufactures and device will exhibit odd parity with DQ7 defined as the parity bit. In order to read the proper device codes when executing the autoselect, A1 must be VIL. (See “MBM29LV800TE/BE Sector Protection Verify Autoselect Codes” and “Expanded Autoselect Code Table” in “ DEVICE BUS OPERATION”.) Write Device erasure and programming are accomplished via the command register. The contents of the register serve as inputs to the internal state machine. The state machine outputs dictate the function of the device. The command register itself does not occupy any addressable memory location. The register is a latch used to store the commands, along with the address and data information needed to execute the command. The command register is written by bringing WE to VIL, while CE is at VIL and OE is at VIH. Addresses are latched on the falling edge of WE or CE, whichever happens later; while data is latched on the rising edge of WE or CE, whichever happens first. Standard microprocessor write timings are used. Refer to AC Write Characteristics and the Erase/Programming Waveforms for specific timing parameters. Sector Protection The MBM29LV800TE/BE feature hardware sector protection. This feature will disable both program and erase operations in any number of sectors (0 through 18) . The sector protection feature is enabled using programming equipment at the user’s site. The devices are shipped with all sectors unprotected. Alternatively, Fujitsu may program and protect sectors in the factory prior to shiping the device. To activate this mode, the programming equipment must force VID on address pin A9 and control pin OE, (suggest VID = 11.5 V) , CE = VIL, and A6 = VIL. The sector addresses (A18, A17, A16, A15, A14, A13, and A12) should be set to the sector to be protected. “Sector Address Tables (MBM29LV800TE)” and “Sector Address Tables (MBM29LV800BE) ” in “ FLEXIBLE SECTOR-ERASE ARCHITECTURE” define the sector address for each of the nineteen (19) individual sectors. Programming of the protection circuitry begins on the falling edge of the WE pulse and is terminated with the rising edge of the same. Sector addresses must be held constant during the WE pulse. See “Sector Protection Timing Diagram” in “ TIMING DIAGRAM” and “Sector Protection Algorithm” in “ FLOW CHART” for sector protection waveforms and algorithm. To verify programming of the protection circuitry, the programming equipment must force VID on address pin A9 with CE and OE at VIL and WE at VIH. Scanning the sector addresses (A18, A17, A16, A15, A14, A13, and A12) while (A6, A1, A0) = (0, 1, 0) will produce a logical “1” code at device output DQ0 for a protected sector. Otherwise the devices will read 00h for unprotected sector. In this mode, the lower order addresses, except for A0, A1, and A6 are DON’T CARES. Address locations with A1 = VIL are reserved for Autoselect manufacturer and device codes. A-1 requires to apply to VIL on byte mode. It is also possible to determine if a sector is protected in the system by writing an Autoselect command. Performing a read operation at the address location XX02h, where the higher order addresses (A18, A17, A16, A15, A14, A13, and A12) are the desired sector address will produce a logical “1” at DQ0 for a protected sector. See “MBM29LV800TE/BE Sector Protection Verify Autoselect Codes” and “Expanded Autoselect Code Table” in “ DEVICE BUS OPERATION” for Autoselect codes. Temporary Sector Unprotection This feature allows temporary unprotection of previously protected sectors of the MBM29LV800TE/BE devices in order to change data. The Sector Unprotection mode is activated by setting the RESET pin to high voltage (VID) . During this mode, formerly protected sectors can be programmed or erased by selecting the sector addresses. Once the VID is taken away from the RESET pin, all the previously protected sectors will be protected again. See “Temporary Sector Unprotection Timing Diagram” in “ TIMING DIAGRAM” and “Temporary Sector Unprotection Algorithm” in “ FLOW CHART”. 17 MBM29LV800TE/BE60/70/90 Extended Sector Protection In addition to normal sector protection, the MBM29LV800TE/BE have Extended Sector Protection as extended function. This function enables to protect sector by forcing VID on RESET pin and write a commnad sequence. Unlike conventional procedure, it is not necessary to force VID and control timing for control pins. The only RESET pin requires VID for sector protection in this mode. The extended sector protect requires VID on RESET pin. With this condition the operation is initiated by writing the set-up command (60h) into the command register. Then the sector addresses pins (A18, A17, A16, A15, A14, A13 and A12) and (A6, A1, A0) = (0, 1, 0) should be set to be protected (recommend to set VIL for the other addresses pins) , and write extended sector protect command (60h) . A sector is generally protected in 250 µs. To verify programming of the protection circuitry, the sector addresses pins (A18, A17, A16, A15, A14, A13 and A12) and (A6, A1, A0) = (0, 1, 0) should be set and write a command (40h) . Following the command write, a logical “1” at device output DQ0 produces for protected sector in the read operation. If the output is logical “0”, repeat to write extended sector protect command (60h) again. To terminate the operation, it is necessary to set RESET pin to VIH (refer to “Extended Sector Protection Algorithm” in “■ FLOW CHART”) . RESET Hardware Reset The MBM29LV800TE/BE devices may be reset by driving the RESET pin to VIL. The RESET pin has pulse requirement and has to be kept low (VIL) for at least “tRP” in order to properly reset the internal state machine. Any operation in the process of being executed is terminated and the internal state machine is reset to the read mode “tREADY” after the RESET pin goes low. Furthermore once the RESET pin goes high, the devices require an additional tRH before it will allow read access. When the RESET pin is low, the devices will be in the standby mode for the duration of the pulse and all the data output pins will be tri-stated. If hardware reset occurs during program or erase operation, the data at that particular location is corrupted. Note that the RY/BY output signal should be ignored during the RESET pulse. See “RESET, RY/BY Timing Diagram” in “■ TIMING DIAGRAM” for the timing diagram. Refer to Temporary Sector Unprotection for additional functionality. If hardware reset occurs during Embedded Erase Algorithm, the erasing sector (s) cannot be used. 18 MBM29LV800TE/BE60/70/90 ■ COMMAND DEFINITIONS Device operations are selected by writing specific address and data sequences into the command register. “MBM29LV800TE/BE Command Definitions” in “■ DEVICE BUS OPERATION” defines the valid register command sequences. Note that the Erase Suspend (B0h) and Erase Resume (30h) commands are valid only while the Sector Erase operation is in progress. Furthermore both Read/Reset commands are functionally equivalent, resetting the device to the read mode. Note that commands are always written at DQ7 to DQ0 and DQ15 to DQ8 bits are ignored. Read/Reset Command In order to return from Autoselect mode or Exceeded Timing Limits (DQ5 = 1) to read/reset mode, the read/reset operation is initiated by writing the Read/Reset command sequence into the command register. Microprocessor read cycles retrieve array data from the memory. The devices remain enabled for reads until the command register contents are altered. The devices will automatically power-up in the read/reset state. In this case, a command sequence is not required to read data. Standard microprocessor read cycles will retrieve array data. This default value ensures that no spurious alteration of the memory content occurs during the power transition. Refer to the AC Read Characteristics and Waveforms for the specific timing parameters. Autoselect Command Flash memories are intended for use in applications where the local CPU alters memory contents. As such manufacture and device codes must be accessible while the devices reside in the target system. PROM programmers typically access the signature codes by raising A9 to a high voltage. However multiplexing high voltage onto the address lines is not generally desired system design practice. The device contains an Autoselect command operation to supplement traditional PROM programming methodology. The operation is initiated by writing the Autoselect command sequence into the command register. Following the command write, a read cycle from address XX00h retrieves the manufacture code of 04h. A read cycle from address XX01h for ×16 (XX02h for ×8) returns the device code (MBM29LV800TE = DAh and MBM29LV 800BE = 5Bh for ×8 mode; MBM29LV800TE = 22DAh and MBM29LV800BE = 225Bh for ×16 mode) . (See “MBM29LV800TE/BE Sector Protection Verify Autoselect Codes” and “Expanded Autoselect Code Table” in “■ DEVICE BUS OPERATION”.) All manufacturer and device codes will exhibit odd parity with DQ7 defined as the parity bit. Sector state (protection or unprotection) will be informed by address XX02h for ×16 (XX04h for ×8). Scanning the sector addresses (A18, A17, A16, A15, A14, A13, and A12) while (A6, A1, A0) = (0, 1, 0) will produce a logical “1” at device output DQ0 for a protected sector. The programming verification should be performed margin mode on the protected sector. (See “MBM29LV800TE/BE User Bus Operations (BYTE = VIH)” and “MBM29LV 800TE/BE User Bus Operations (BYTE = VIL)” in “■ DEVICE BUS OPERATION”.) To terminate the operation, it is necessary to write the Read/Reset command sequence into the register. To execute the Autoselect command during the operation, writing Read/Reset command sequence must precede the Autoselect command. Byte/Word Programming The devices are programmed on a byte-by-byte (or word-by-word) basis. Programming is a four bus cycle operation. There are two “unlock” write cycles. These are followed by the program set-up command and data write cycles. Addresses are latched on the falling edge of CE or WE, whichever happens later and the data is latched on the rising edge of CE or WE, whichever happens first. The rising edge of CE or WE (whichever happens first) begins programming. Upon executing the Embedded Program Algorithm command sequence, the system is not required to provide further controls or timings. The device will automatically provide adequate internally generated program pulses and verify the programmed cell margin. The automatic programming operation is completed when the data on DQ7 is equivalent to data written to this bit at which time the devices return to the read mode and addresses are no longer latched. (See “Hardware Sequence Flags”.) Therefore, the devices require that a valid address to the devices be supplied by the system at this particular instance of time. Hence, Data Polling must be performed at the memory location which is being programmed. 19 MBM29LV800TE/BE60/70/90 If hardware reset occurs during the programming operation, it is impossible to guarantee the data are being written. Programming is allowed in any sequence and across sector boundaries. Beware that a data “0” cannot be programmed back to a “1”. Attempting to do so may either hang up the device or result in an apparent success according to the data polling algorithm but a read from read/reset mode will show that the data is still “0”. Only erase operations can convert “0”s to “1”s. “Embedded ProgramTM Algorithm” in “■ FLOW CHART” illustrates the Embedded ProgramTM Algorithm using typical command strings and bus operations. Chip Erase Chip erase is a six bus cycle operation. There are two “unlock” write cycles. These are followed by writing the “set-up” command. Two more “unlock” write cycles are then followed by the chip erase command. Chip erase does not require the user to program the device prior to erase. Upon executing the Embedded Erase Algorithm command sequence the devices will automatically program and verify the entire memory for an all zero data pattern prior to electrical erase (Preprogram function) . The system is not required to provide any controls or timings during these operations. The automatic erase begins on the rising edge of the last WE pulse in the command sequence and terminates when the data on DQ7 is “1” (See Write Operation Status section.) at which time the device returns to read the mode. Chip Erase Time; Sector Erase Time × All sectors + Chip Program Time (Preprogramming) “Embedded EraseTM Algorithm” in “■ FLOW CHART” illustrates the Embedded EraseTM Algorithm using typical command strings and bus operations. Sector Erase Sector erase is a six bus cycle operation. There are two “unlock” write cycles. These are followed by writing the “set-up” command. Two more “unlock” write cycles are then followed by the Sector Erase command. The sector address (any address location within the desired sector) is latched on the falling edge of WE, while the command (Data = 30h) is latched on the rising edge of WE. After time-out of “tTOW” from the rising edge of the last sector erase command, the sector erase operation will begin. Multiple sectors may be erased concurrently by writing the six bus cycle operations on “MBM29LV800TE/BE Command Definitions” in “■ DEVICE BUS OPERATION”. This sequence is followed with writes of the Sector Erase command to addresses in other sectors desired to be concurrently erased. The time between writes must be less than “tTOW” otherwise that command will not be accepted and erasure will not start. It is recommended that processor interrupts be disabled during this time to guarantee this condition. The interrupts can be reenabled after the last Sector Erase command is written. A time-out of “tTOW” from the rising edge of the last WE will initiate the execution of the Sector Erase command (s) . If another falling edge of the WE occurs within the “tTOW” time-out window the timer is reset. (Monitor DQ3 to determine if the sector erase timer window is still open, see section DQ3, Sector Erase Timer.) Once execution has begun resetting the devices will corrupt the data in the sector. In that case, restart the erase on those sectors and allow them to complete. (Refer to the Write Operation Status section for Sector Erase Timer operation.) Loading the sector erase buffer may be done in any sequence and with any number of sectors (0 to 18) . Sector erase does not require the user to program the devices prior to erase. The devices automatically program all memory locations in the sector (s) to be erased prior to electrical erase (Preprogram function) . When erasing a sector or sectors the remaining unselected sectors are not affected. The system is not required to provide any controls or timings during these operations. The automatic sector erase begins after the “tTOW” time out from the rising edge of the WE pulse for the last sector erase command pulse and terminates when the data on DQ7 is “1” (See Write Operation Status section.) at which time the devices return to the read mode. Data polling must be performed at an address within any of the sectors being erased. Multiple Sector Erase Time; [Sector Erase Time + Sector Program Time (Preprogramming) ] × Number of Sector Erase 20 MBM29LV800TE/BE60/70/90 “Embedded EraseTM Algorithm” in “■ FLOW CHART” illustrates the Embedded EraseTM Algorithm using typical command strings and bus operations. Erase Suspend/Resume The Erase Suspend command allows the user to interrupt a Sector Erase operation and then perform data reads from or programs to a sector not being erased. This command is applicable ONLY during the Sector Erase operation which includes the time-out period for sector erase. Writting the Erase Suspend command during the Sector Erase time-out results in immediate termination of the time-out period and suspension of the erase operation. Writing the Erase Resume command resumes the erase operation. The addresses are DON’T CARES when writing the Erase Suspend or Erase Resume command. When the Erase Suspend command is written during the Sector Erase operation, the device will take a maximum of “tSPD” to suspend the erase operation. When the devices have entered the erase-suspended mode, the RY/ BY output pin and the DQ7 bit will be at logic “1”, and DQ6 will stop toggling. The user must use the address of the erasing sector for reading DQ6 and DQ7 to determine if the erase operation has been suspended. Further writes of the Erase Suspend command are ignored. When the erase operation has been suspended, the devices default to the erase-suspend-read mode. Reading data in this mode is the same as reading from the standard read mode except that the data must be read from sectors that have not been erase-suspended. Successively reading from the erase-suspended sector will cause DQ2 to toggle while the device is in the erase-suspend-read mode (See the section on DQ2) . After entering the erase-suspend-read mode, the user can program the device by writing the appropriate command sequence for Program. This program mode is known as the erase-suspend-program mode. Again, programming in this mode is the same as programming in the regular Program mode except that the data must be programmed to sectors that are not erase-suspended. Successively reading from the erase-suspended sector while the devices are in the erase-suspend-program mode will cause DQ2 to toggle. The end of the erasesuspended Program operation is detected by the RY/BY output pin, Data polling of DQ7, or by the Toggle Bit I (DQ6) which is the same as the regular Program operation. Note that DQ7 must be read from the Program address while DQ6 can be read from any address. To resume the operation of Sector Erase, the Resume command (30h) should be written. Any further writes of the Resume command at this point will be ignored. Another Erase Suspend command can be written after the chip has resumed erasing. Extended Command (1) Fast Mode MBM29LV800TE/BE have Fast Mode function. This mode dispenses with the initial two unclock cycles required in the standard program command sequence by writing Fast Mode command into the command register. In this mode, the required bus cycle for programming is two cycles instead of four bus cycles in standard program command. In Fast Mode, do not write any command other than the fast program/fast mode reset command. The read operation is also executed after exiting this mode. To exit this mode, it is necessary to write Fast Mode Reset command into the command register (Refer to “Embedded Programming Algorithm for Fast Mode” in “■ FLOW CHART”) . The VCC active current is required even CE = VIH during Fast Mode. (2) Fast Programming During Fast Mode, the programming can be executed with two bus cycles operation. The Embedded Program Algorithm is executed by writing program set-up command (A0h) and data write cycles (PA/PD) (Refer to “Embedded Programming Algorithm for Fast Mode” in “■ FLOW CHART”) . 21 MBM29LV800TE/BE60/70/90 Write Operation Status Hardware Sequence Flags Status Embedded Program Algorithm Embedded Erase Algorithm In Progress Erase Suspend Read (Erase Suspended Sector) Erase Erase Suspend Read Suspended (Non-Erase Suspended Sector) Mode Erase Suspend Program (Non-Erase Suspended Sector) Embedded Program Algorithm Embedded Erase Algorithm Exceeded Time Limits Erase Erase Suspend Program Suspended (Non-Erase Suspended Sector) Mode DQ7 DQ6 DQ5 DQ3 DQ2 DQ7 Toggle 0 0 1 0 Toggle 0 1 Toggle 1 1 0 0 Toggle Data Data Data Data Data DQ7 Toggle*1 0 0 1*2 DQ7 Toggle 1 0 1 0 Toggle 1 1 N/A DQ7 Toggle 1 0 N/A *1 : Performing successive read operations from any address will cause DQ6 to toggle. *2 : Reading the byte address being programmed while in the erase-suspend program mode will indicate logic “1” at the DQ2 bit. However, successive reads from the erase-suspended sector will cause DQ2 to toggle. Notes : • DQ1 and DQ0 are reserved pins for future use. • DQ4 is Fujitsu internal use only. DQ7 Data Polling The MBM29LV800TE/BE devices feature Data Polling as a method to indicate to the host that the Embedded Algorithms are in progress or completed. During the Embedded Program Algorithm, an attempt to read devices will produce a complement of data last written to DQ7. Upon completion of the Embedded Program Algorithm, an attempt to read device will produce true data last written to DQ7. During the Embedded Erase Algorithm, an attempt to read device will produce a “0” at the DQ7 output. Upon completion of the Embedded Erase Algorithm an attempt to read device will produce a “1” on DQ7. The flowchart for Data Polling (DQ7) is shown in “Data Polling Algorithm” in “■ FLOW CHART”. For chip erase and sector erase, the Data Polling is valid after the rising edge of the sixth WE pulse in the six write pulse sequence. Data Polling must be performed at sector address of sectors being erased, not protected sectors. Otherwise, the status may be invalid. Once the Embedded Algorithm operation is close to completion, MBM29LV800TE/BE data pins (DQ7) may change asynchronously while the output enable (OE) is asserted low. This means that devices are driving status information on DQ7 at one instant of time and then that byte’s valid data at the next instant of time. Depending on when the system samples the DQ7 output, it may read the status or valid data. Even if device has completed the Embedded Algorithm operation and DQ7 has a valid data, data outputs on DQ6 to DQ0 may be still invalid. The valid data on DQ7 to DQ0 will be read on the successive read attempts. The Data Polling feature is active only during the Embedded Programming Algorithm, Embedded Erase Algorithm or sector erase time-out. See “Data Polling during Embedded Algorithm Operation Timing Diagram” in “■ TIMING DIAGRAM” for the Data Polling timing specifications and diagrams. 22 MBM29LV800TE/BE60/70/90 DQ6 Toggle Bit I The MBM29LV800TE/BE also feature the “Toggle Bit I” as a method to indicate to the host system that the Embedded Algorithms are in progress or completed. During Embedded Program or Erase Algorithm cycle, successive attempts to read (OE toggling) data from the devices will result in DQ6 toggling between one and zero. Once the Embedded Program or Erase Algorithm cycle is completed, DQ6 will stop toggling and valid data will be read on the next successive attempts. During programming, the Toggle Bit I is valid after the rising edge of the fourth WE pulses in the four write pulse sequence. For chip erase and sector erase, the Toggle Bit I is valid after the rising edge of the sixth WE pulse in the six write pulses sequence. The Toggle Bit I is active during the sector time out. In programming, if the sector being written is protected, the toggle bit will toggle for about 2 µs and then stop toggling with data unchanged. In erase, devices will erase all selected sectors except for ones that are protected. If all selected sectors are protected, the chip will toggle the toggle bit for about 200 µs and then drop back into read mode, having data unchanged. Either CE or OE toggling will cause DQ6 to toggle. In addition, an Erase Suspend/Resume command will cause DQ6 to toggle. See “Taggle Bit I during Embedded Algorithm Operation Timing Diagram” in “■ TIMING DIAGRAM” for the Toggle Bit I timing specifications and diagrams. DQ5 Exceeded Timing Limits DQ5 will indicate if the program or erase time has exceeded the specified limits (internal pulse count) . Under these conditions, DQ5 will produce a “1”. This is a failure condition which indicates that the program or erase cycle was not successfully completed. Data Polling is the only operating function of devices under this condition. The CE circuit will partially power down device under these conditions (to approximately 2 mA) . The OE and WE pins will control the output disable functions as described in “MBM29LV800TE/BE User Bus Operations (BYTE = VIH)” and “MBM29LV800TE/BE User Bus Operations (BYTE = VIL)” in “■ DEVICE BUS OPERATION”. The DQ5 failure condition may also appear if a user tries to program a non blank location without pre-erase. In this case, the devices lock out and never complete the Embedded Algorithm operation. Hence, the system never read valid data on DQ7 bit and DQ6 never stop toggling. Once devices have exceeded timing limits, the DQ5 bit will indicate a “1.” Please note that this is not a device failure condition since devices were incorrectly used. If this occurs, reset device with command sequence. DQ3 Sector Erase Timer After completion of the initial sector erase command sequence, sector erase time-out will begin. DQ3 will remain low until the time-out is completed. Data Polling and Toggle Bit are valid after the initial sector erase command sequence. If Data Polling or the Toggle Bit I indicates device has been written with a valid erase command, DQ3 may be used to determine if the sector erase timer window is still open. If DQ3 is high (“1”) the internally controlled erase cycle has begun : If DQ3 is low (“0”) , the device will accept additional sector erase commands. To insure the command has been accepted, the system software should check the status of DQ3 prior to and following each subsequent Sector Erase command. If DQ3 were high on the second status check, the command may not have been accepted. See “Hardware Sequence Flags”. 23 MBM29LV800TE/BE60/70/90 DQ2 Toggle Bit II This toggle bit II, along with DQ6, can be used to determine whether the devices are in the Embedded Erase Algorithm or in Erase Suspend. Successive reads from the erasing sector will cause DQ2 to toggle during the Embedded Erase Algorithm. If the devices are in the erase-suspended-read mode, successive reads from the erase-suspended sector will cause DQ2 to toggle. When the devices are in the erase-suspended-program mode, successive reads from the byte address of the non-erase suspended sector will indicate a logic “1” at the DQ2 bit. DQ6 is different from DQ2 in that DQ6 toggles only when the standard program or Erase, or Erase Suspend Program operation is in progress. The behavior of these two status bits, along with that of DQ7, is summarized as follows : For example, DQ2 and DQ6 can be used together to determine if the erase-suspend-read mode is in progress. (DQ2 toggles while DQ6 does not.) See also “Hardware Sequence Flags” and “DQ2 vs. DQ6” in “■ TIMING DIAGRAM”. Furthermore, DQ2 can also be used to determine which sector is being erased. When device is in the erase mode, DQ2 toggles if this bit is read from an erasing sector. Toggle Bit Status DQ7 DQ6 DQ2 DQ7 Toggle 1 Erase 0 Toggle Toggle Erase-Suspend Read (Erase-Suspended Sector) *1 1 1 Toggle DQ7 Toggle *1 1 *2 Mode Program Erase-Suspend Program *1 : Performing successive read operations from any address will cause DQ6 to toggle. *2 : Reading the byte address being programmed while in the erase-suspend program mode will indicate logic “1” at the DQ2 bit. However, successive reads from the erase-suspended sector will cause DQ2 to toggle. RY/BY Ready/Busy MBM29LV800TE/BE provide a RY/BY open-drain output pin as a way to indicate to the host system that Embedded Algorithms are either in progress or has been completed. If output is low, devices are busy with either a program or erase operation. If output is high, devices are ready to accept any read/write or erase operation. If MBM29LV800TE/BE are placed in an Erase Suspend mode, RY/BY output will be high. During programming, RY/BY pin is driven low after the rising edge of the fourth WE pulse. During an erase operation, RY/BY pin is driven low after the rising edge of the sixth WE pulse. RY/BY pin will indicate a busy condition during RESET pulse. Refer to “RY/BY Timing Diagram during Program/Erase Operation Timing Diagram” and “RESET, RY/BY Timing Diagram” in “■ TIMING DIAGRAM” for a detailed timing diagram. RY/BY pin is pulled high in standby mode. Since this is an open-drain output, RY/BY pins can be tied together in parallel with a pull-up resistor to VCC. 24 MBM29LV800TE/BE60/70/90 Byte/Word Configuration BYTE pin selects byte (8-bit) mode or word (16-bit) mode for MBM29LV800TE/BE devices. When this pin is driven high, devices operate in word (16-bit) mode. Data is read and programmed at DQ15 to DQ0. When this pin is driven low, devices operates in byte (8-bit) mode. Under this mode, the DQ15/A-1 pin becomes the lowest address bit, and DQ14 to DQ8 bits are tri-stated. However, the command bus cycle is always an 8-bit operation and hence commands are written at DQ7 to DQ0 and DQ15 to DQ8 bits are ignored. Refer to “Timing Diagram for Word Mode Configuration”, “Timing Diagram for Byte Mode Configuration” and “BYTE Timing Diagram for Write Operations” in “■ TIMING DIAGRAM” for the timing diagram. Data Protection MBM29LV800TE/BE are designed to offer protection against accidental erasure or programming caused by spurious system level signals that may exist during power transitions. During power up, devices automatically reset internal state machine in Read mode. Also, with its control register architecture, alteration of memory contents only occurs after successful completion of specific multi-bus cycle command sequences. Devices also incorporate several features to prevent inadvertent write cycles resulting form VCC power-up and power-down transitions or system noise. Low VCC Write Inhibit To avoid initiation of a write cycle during VCC power-up and power-down, a write cycle is locked out for VCC less than VLKO (Min) . If VCC < VLKO, the command register is disabled and all internal program/erase circuits are disabled. Under this condition, the device will reset to the read mode. Subsequent writes will be ignored until the VCC level is greater than VLKO. It is the users responsibility to ensure that the control pins are logically correct to prevent unintentional writes when VCC is above VLKO (Min) . If Embedded Erase Algorithm is interrupted, there is possibility that the erasing sector (s) cannot be used. Write Pulse “Glitch” Protection Noise pulses of less than 3 ns (typical) on OE, CE, or WE will not initiate a write cycle. Logical Inhibit Writing is inhibited by holding any one of OE = VIL, CE = VIH, or WE = VIH. To initiate a write cycle, CE and WE must be a logical zero while OE is a logical one. Power-Up Write Inhibit Power-up of the devices with WE = CE = VIL and OE = VIH will not accept commands on the rising edge of WE. The internal state machine is automatically reset to the read mode on power-up. 25 MBM29LV800TE/BE60/70/90 ■ ABSOLUTE MAXIMUM RATINGS Parameter Symbol Rating Unit Min Max Tstg −55 +125 °C TA −40 +85 °C VIN, VOUT −0.5 VCC + 0.5 V Power Supply Voltage *1 VCC −0.5 +5.5 V A9, OE, and RESET *1, *3 VIN −0.5 +13.0 V Storage Temperature Ambient Temperature with Power Applied Voltage with Respect to Ground All pins except A9, OE, RESET *1, *2 *1 : Voltage is defined on the basis of VSS = GND = 0 V. *2 : Minimum DC voltage on input or l/O pins is −0.5 V. During voltage transitions, inputs or I/O pins may undershoot VSS to −2.0 V for periods of up to 20 ns. Maximum DC voltage on input or l/O pins is VCC + 0.5 V. During voltage transitions, inputs or I/O pins may overshoot to VCC + 2.0 V for periods of up to 20 ns. *3 : Minimum DC input voltage on A9, OE, and RESET pins is −0.5 V. During voltage transitions, A9, OE, and RESET pins may undershoot VSS to −2.0 V for periods of up to 20 ns. Voltage difference between input and supply voltage (VIN − VCC) does not exceed + 9.0 V. Maximum DC input voltage on A9, OE, and RESET pins is +13.0 V which may overshoot to +14.0 V for periods of up to 20 ns. WARNING: Semiconductor devices can be permanently damaged by application of stress (voltage, current, temperature, etc.) in excess of absolute maximum ratings. Do not exceed these ratings. ■ RECOMMENDED OPERATING CONDITIONS Parameter Symbol Ambient Temperature TA Power Supply Voltage* VCC Part No. Value Unit Min Typ Max MBM29LV800TE/BE 60 −20 +70 °C MBM29LV800TE/BE 70/90 −40 +85 °C MBM29LV800TE/BE 60 +3.0 +3.6 V MBM29LV800TE/BE 70/90 +2.7 +3.6 V * : Voltage is defined on the basis of VSS = GND = 0 V. Note : Operating ranges define those limits between which the functionality of the device is guaranteed. WARNING: The recommended operating conditions are required in order to ensure the normal operation of the semiconductor device. All of the device’s electrical characteristics are warranted when the device is operated within these ranges. Always use semiconductor devices within their recommended operating condition ranges. Operation outside these ranges may adversely affect reliability and could result in device failure. No warranty is made with respect to uses, operating conditions, or combinations not represented on the data sheet. Users considering application outside the listed conditions are advised to contact their FUJITSU representatives beforehand. 26 MBM29LV800TE/BE60/70/90 ■ MAXIMUM OVERSHOOT/MAXIMUM UNDERSHOOT +0.6 V 20 ns 20 ns −0.5 V −2.0 V 20 ns Maximum Undershoot Waveform 20 ns VCC + 2.0 V VCC + 0.5 V +2.0 V 20 ns 20 ns Maximum Overshoot Waveform 1 20 ns +14.0 V +13.0 V VCC + 0.5 V 20 ns 20 ns Note : This wave form is applied for A9, OE, and RESET. Maximum Overshoot Waveform 2 27 MBM29LV800TE/BE60/70/90 ■ DC CHARACTERISTICS Parameter Symbol Value Test Conditions Min Max Unit Input Leakage Current ILI VIN = VSS to VCC, VCC = VCC Max −1.0 +1.0 µA Output Leakage Current ILO VOUT = VSS to VCC, VCC = VCC Max −1.0 +1.0 µA A9, OE, RESET Inputs Leakage Current ILIT VCC = VCC Max, A9, OE, RESET = 12.5 V 35 µA CE = VIL, OE = VIH, f = 10 MHz VCC Active Current * 1 ICC1 CE = VIL, OE = VIH, f = 5 MHz Byte Word Byte Word 22 25 12 15 mA mA VCC Active Current *2 ICC2 CE = VIL, OE = VIH 35 mA VCC Current (Standby) ICC3 VCC = VCC Max, CE = VCC ± 0.3 V, RESET = VCC ± 0.3 V 5 µA VCC Current (Standby, Reset) ICC4 VCC = VCC Max, RESET = VSS ± 0.3 V 5 µA VCC Current (Automatic Sleep Mode) *3 ICC5 VCC = VCC Max, CE = VSS ± 0.3 V, RESET = VCC ± 0.3 V, VIN = VCC ± 0.3 V or VSS ± 0.3 V 5 µA Input Low Level VIL −0.5 0.6 V Input High Level VIH 2.0 VCC + 0.3 V Voltage for Autoselect and Sector Protection (A9, OE, RESET) *4 VID 11.5 12.5 V Output Low Voltage Level VOL IOL = 4.0 mA, VCC = VCC Min 0.45 V VOH1 IOH = −2.0 mA, VCC = VCC Min 2.4 V VOH2 IOH = −100 µA VCC − 0.4 V 2.3 2.5 V Output High Voltage Level Low VCC Lock-Out Voltage VLKO *1: ICC current listed includes both the DC operating current and the frequency dependent component (at 10 MHz) . *2: ICC is active while Embedded Algorithm (program or erase) is in progress. *3: Automatic sleep mode enables the low power mode when address remains stable for 150 ns. *4: (VID − VCC) do not exceed 9 V. 28 MBM29LV800TE/BE60/70/90 ■ AC CHARACTERISTICS • Read Only Operations Characteristics Value* Symbols Parameter Test Setup 60 JEDEC Standard 70 90 Unit Min Max Min Max Min Max Read Cycle Time tAVAV tRC 60 70 90 ns Address to Output Delay tAVQV tACC CE = VIL OE = VIL 60 70 90 ns Chip Enable to Output Delay tELQV tCE OE = VIL 60 70 90 ns Output Enable to Output Delay tGLQV tOE 30 30 35 ns Chip Enable to Output High-Z tEHQZ tDF 25 25 30 ns Output Enable to Output High-Z tGHQZ tDF 25 25 30 ns Output Hold Time From Addresses, CE or OE, Whichever Occurs First tAXQX tOH 0 0 0 ns RESET Pin Low to Read Mode tREADY 20 20 20 µs CE to BYTE Switching Low or High tELFL tELFH 5 5 5 ns * : Test Conditions : Output Load : 1 TTL gate and 30 pF (MBM29LV800TE60/BE60, MBM29LV800TE70/BE70) 1 TTL gate and 100 pF (MBM29LV800TE90/BE90) Input rise and fall times : 5 ns Input pulse levels : 0.0 V or 3.0 V Timing measurement reference level Input : 1.5 V Output : 1.5 V 3.3 V Diode = 1N3064 or equivalent 2.7 kΩ Device Under Test 6.2 kΩ CL Diode = 1N3064 or equivalent Note : CL = 30 pF including jig capacitance (MBM29LV800TE60/BE60, MBM29LV800TE70/BE70) CL = 100 pF including jig capacitance (MBM29LV800TE90/BE90) Test Conditions 29 MBM29LV800TE/BE60/70/90 • Write/Erase/Program Operations MBM29LV800TE/BE Symbol Parameter 60 70 90 Unit JEDEC Standard Min Typ Max Min Typ Max Min Typ Max Write Cycle Time tAVAV tWC 60 70 90 ns Address Setup Time tAVWL tAS 0 0 0 ns Address Hold Time tWLAX tAH 45 45 45 ns Data Setup Time tDVWH tDS 30 35 45 ns Data Hold Time tWHDX tDH 0 0 0 ns tOES 0 0 0 ns 0 0 0 ns 10 10 10 ns Output Enable Setup Time Output Enable Hold Time Read tOEH Read Recover Time Before Write tGHWL tGHWL 0 0 0 ns Read Recover Time Before Write tGHEL tGHEL 0 0 0 ns CE Setup Time tELWL tCS 0 0 0 ns WE Setup Time tWLEL tWS 0 0 0 ns CE Hold Time tWHEH tCH 0 0 0 ns WE Hold Time tEHWH tWH 0 0 0 ns Write Pulse Width tWLWH tWP 30 35 45 ns CE Pulse Width tELEH tCP 30 35 45 ns Write Pulse Width High tWHWL tWPH 25 25 25 ns CE Pulse Width High tEHEL tCPH 25 25 25 ns tWHWH1 tWHWH1 8 8 16 16 tWHWH2 tWHWH2 1 1 1 s VCC Setup Time tVCS 50 50 50 µs Rise Time to VID *2 tVIDR 500 500 500 ns tVLHT 4 4 4 µs Toggle and Data Polling Programming Operation Byte Word Sector Erase Operation *1 Voltage Transition Time *2 8 16 µs tWPP 100 100 100 µs 2 tOESP 4 4 4 µs CE Setup Time to WE Active *2 tCSP 4 4 4 µs Recover Time From RY/BY tRB 0 0 0 ns RESET Pulse Width tRP 500 500 500 ns RESET High Level Period Before Read tRH 200 200 200 ns BYTE Switching Low to Output High-Z tFLQZ 25 25 30 ns Write Pulse Width * 2 OE Setup Time to WE Active * (Continued) 30 MBM29LV800TE/BE60/70/90 (Continued) MBM29LV800TE/BE Symbol Parameter 60 70 90 Unit JEDEC Standard Min Typ Max Min Typ Max Min Typ Max BYTE Switching High to Output Active tFHQV 60 70 90 ns Program/Erase Valid to RY/BY Delay tBUSY 90 90 90 ns Delay Time from Embedded Output Enable tEOE 60 70 90 ns Erase Time-out Time tTOW 50 50 50 µs Erase Suspend Transition Time tSPD 20 20 µs 20 *1: Does not include the preprogramming time. *2: For Sector Protection operation. 31 MBM29LV800TE/BE60/70/90 ■ ERASE AND PROGRAMMING PERFORMANCE Parameter Limits Unit Comments s Excludes programming time prior to erasure µs Excludes system-level overhead 25 s Excludes system-level overhead cycle Min Typ Max Sector Erase Time 1 10 Byte Programming Time 8 300 Word Programming Time 16 360 Chip Programming Time 8.4 100,000 Erase/Program Cycle ■ TSOP (1) , FBGA, CSOP PIN CAPACITANCE Parameter Input Capacitance Symbol CIN Test Setup Typ Max Unit VIN = 0 7.5 9.5 pF Output Capacitance COUT VOUT = 0 8.0 10.0 pF Control Pin Capacitance CIN2 VIN = 0 10.0 13.0 pF Notes : • Test conditions TA = +25 °C, f = 1.0 MHz • DQ15/A-1 pin capacitance is stipulated by output capacitance. 32 MBM29LV800TE/BE60/70/90 ■ TIMING DIAGRAM • Key to Switching Waveforms WAVEFORM INPUTS OUTPUTS Must Be Steady Will Be Steady May Change from H to L Will Change from H to L May Change from L to H Will Change from L to H "H" or "L": Any Change Permitted Changing, State Unknown Does Not Apply Center Line is HighImpedance "Off" State tRC Address Address Stable tACC CE tOE tDF OE tOEH WE tOH tCE High-Z Outputs Outputs Valid High-Z Read Operation Timing Diagram 33 MBM29LV800TE/BE60/70/90 tRC Address Address Stable tACC CE tRH tRP tRH tCE RESET tOH Outputs High-Z Outputs Valid Hardware Reset/Read Operation Timing Diagram 34 MBM29LV800TE/BE60/70/90 3rd Bus Cycle Data Polling 555h Address tWC PA tAS PA tRC tAH CE tCS tCH tCE OE tGHWL tWP tOE tWPH tWHWH1 WE Data Notes : • • • • • • A0h tOH tDF tDS tDH PD DQ7 DOUT DOUT PA is the address of the memory location to be programmed. PD is the data to be programmed at word address. DQ7 is the output of the complement of the data written to the device. DOUT is the output of the data written to the device. Figure indicates the last two bus cycles out of four bus cycles sequence. These waveforms are for the × 16 mode (the addresses differ from × 8 mode). Alternate WE Controlled Program Operation Timing Diagram 35 MBM29LV800TE/BE60/70/90 3rd Bus Cycle Data Polling 555h Address tWC PA tAS PA tAH WE tWS tWH OE tGHEL tCP tCPH tWHWH1 CE tDS Data Notes : • • • • • • A0h tDH PD DQ7 DOUT PA is the address of the memory location to be programmed. PD is the data to be programmed at word address. DQ7 is the output of the complement of the data written to the device. DOUT is the output of the data written to the device. Figure indicates the last two bus cycles out of four bus cycles sequence. These waveforms are for the × 16 mode (the addresses differ from × 8 mode) . Alternate CE Controlled Program Operation Timing Diagram 36 MBM29LV800TE/BE60/70/90 555h Address tWC 2AAh tAS 555h 555h 2AAh SA* tAH CE tCS tCH OE tGHWL tWP tWPH tDS tDH WE AAh 10h for Chip Erase 55h 80h AAh 55h Data 10h/ 30h tVCS VCC * : SA is the sector address for Sector Erase. Addresses = 555h (Word) for Chip Erase. Note : These waveforms are for the × 16 mode (the addresses differ from × 8 mode) . Chip/Sector Erase Operation Timing Diagram 37 MBM29LV800TE/BE60/70/90 CE tCH tDF tOE OE tOEH WE tCE * Data DQ7 DQ7 DQ7 = Valid Data High-Z tWHWH1 or tWHWH2 DQ6 to DQ0 DQ6 to DQ0 = Outputs Flag Data tBUSY DQ6 to DQ0 Valid Data tEOE RY/BY * : DQ7 = Valid Data (The device has completed the Embedded operation) . Data Polling during Embedded Algorithm Operation Timing Diagram 38 High-Z MBM29LV800TE/BE60/70/90 CE tOEH WE tOES OE tDH DQ6 * DQ6 Data DQ7 to DQ0 Toggle DQ6 Toggle DQ6 Stop Toggling DQ7 to DQ0 Data Valid tOE * : DQ6 = Stops toggling. (The device has completed the Embedded operation.) Toggle Bit I during Embedded Algorithm Operation Timing Diagram Enter Embedded Erasing WE Erase Suspend Erase Enter Erase Suspend Program Erase Suspend Read Erase Suspend Program Erase Resume Erase Suspend Read Erase Erase Complete DQ6 DQ2* Toggle DQ2 and DQ6 with OE or CE * : DQ2 is read from the erase-suspended sector. DQ2 vs. DQ6 39 MBM29LV800TE/BE60/70/90 CE Rising edge of the last WE signal WE Entire programming or erase operations RY/BY tBUSY RY/BY Timing Diagram during Program/Erase Operation Timing Diagram WE RESET tRP tRB RY/BY tREADY RESET, RY/BY Timing Diagram 40 MBM29LV800TE/BE60/70/90 CE tCE BYTE Data Output (DQ7 to DQ0) DQ14 to DQ0 tELFH Data Output (DQ14 to DQ0) tFHQV A-1 DQ15/A-1 DQ15 Timing Diagram for Word Mode Configuration CE BYTE tELFL DQ14 to DQ0 Data Outputs (DQ7 to DQ0) Data Outputs (DQ14 to DQ0) tACC DQ15/A-1 A-1 DQ15 tFLQZ Timing Diagram for Byte Mode Configuration Falling edge of last write signal CE or WE Input Valid BYTE tAS tAH BYTE Timing Diagram for Write Operations 41 MBM29LV800TE/BE60/70/90 A18, A17, A16 A15, A14, A13 A12 SPAX SPAY A6, A0 A1 VID VIH A9 VID VIH OE tVLHT tVLHT tVLHT tVLHT tWPP WE tOESP tCSP CE 01h Data tOE tVCS VCC SPAX : Sector Address to be protected. SPAY : Next Sector Address to be protected. Note : A-1 is VIL on byte mode. Sector Protection Timing Diagram 42 MBM29LV800TE/BE60/70/90 VCC tVIDR tVCS tVLHT VID VIH RESET CE WE tVLHT Program or Erase Command Sequence tVLHT RY/BY Unprotection period Temporary Sector Unprotection Timing Diagram 43 MBM29LV800TE/BE60/70/90 VCC tVCS VID VIH RESET tVLHT tVIDR tWC Address tWC SPAX SPAX SPAY A6, A0 A1 CE OE TIME-OUT tWP WE Data 60h 60h 40h 01h tOE SPAX : Sector Address to be protected SPAY : Next Sector Address to be protected TIME-OUT : Time-Out window = 150 µs (Min) Extended Sector Protection Timing Diagram 44 60h MBM29LV800TE/BE60/70/90 ■ FLOW CHART EMBEDDED ALGORITHM Start Write Program Command Sequence (See Below) Data Polling No Increment Address No Verify Data ? Yes Embedded Program Algorithm in progress Last Address ? Yes Programming Completed Program Command Sequence (Address/Command): 555h/AAh 2AAh/55h 555h/A0h Program Address/Program Data Notes : • The sequence is applied for × 16 mode. • The addresses differ from × 8 mode. Embedded ProgramTM Algorithm 45 MBM29LV800TE/BE60/70/90 EMBEDDED ALGORITHM Start Write Erase Command Sequence (See Below) Data Polling No Data = FFh ? Yes Embedded Erase Algorithm in progress Erasure Completed Chip Erase Command Sequence (Address/Command): Individual Sector/Multiple Sector Erase Command Sequence (Address/Command): 555h/AAh 555h/AAh 2AAh/55h 2AAh/55h 555h/80h 555h/80h 555h/AAh 555h/AAh 2AAh/55h 2AAh/55h 555h/10h Sector Address /30h Sector Address /30h Sector Address /30h Notes : • The sequence is applied for × 16 mode. • The addresses differ from × 8 mode. Embedded EraseTM Algorithm 46 Additional sector erase commands are optional. MBM29LV800TE/BE60/70/90 VA = Address for programming = Any of the sector addresses within the sector being erased during sector erase or multiple erases operation. = Any of the sector addresses within the sector not being protected during sector erase or multiple sector erases operation. Start Read Byte (DQ7 to DQ0) Addr. = VA DQ7 = Data? Yes No No DQ5 = 1? Yes Read Byte (DQ7 to DQ0) Addr. = VA DQ7 = Data? * No Fail Yes Pass * : DQ7 is rechecked even if DQ5 = “1” because DQ7 may change simultaneously with DQ5. Data Polling Algorithm 47 MBM29LV800TE/BE60/70/90 Start *1 Read DQ7 to DQ0 Addr. = VIH or VIL Read DQ7 to DQ0 Addr. = VIH or VIL No DQ6 = Toggle? Yes No DQ5 = 1? Yes *1, *2 Read DQ7 to DQ0 Addr. = VIH or VIL Read DQ7 to DQ0 Addr. = VIH or VIL DQ6 = Toggle? No Yes Program/Erase Operation Not Complete.Write Reset Command Program/Erase Operation Complete *1 : Read toggle bit twice to determine whether it is toggling. *2 : Recheck toggle bit because it may stop toggling as DQ5 changes to “1”. Toggle Bit Algorithm 48 MBM29LV800TE/BE60/70/90 Start ( Setup Sector Addr. A18, A17,A16, A15, A14, A13, A12 ) PLSCNT = 1 OE = VID, A9 = VID CE = VIL, RESET = VIH A6 = A0 = VIL, A1 = VIH Activate WE Pulse Increment PLSCNT Time out 100 µs WE = VIH, CE = OE = VIL (A9 should remain VID) Read from Sector Address Addr. = SPA, A1 = VIH * A6 = A0 = VIL ( ) No PLSCNT = 25? No Data = 01h? Yes Remove VID from A9 Write Reset Command Yes Protect Another Sector ? Yes No Device Failed Remove VID from A9 Write Reset Command Sector Protection Completed * : A-1 is VIL on byte mode. Sector Protection Algorithm 49 MBM29LV800TE/BE60/70/90 Start RESET = VID *1 Perform Erase or Program Operations RESET = VIH Temporary Sector Unprotection Completed *2 *1 : All protected sectors are unprotected. *2 : All previously protected sectors are protected once again. Temporary Sector Unprotection Algorithm 50 MBM29LV800TE/BE60/70/90 Start RESET = VID Wait to 4 µs Device is Operating in Temporary Sector Unprotection Mode No Extended Sector Protection Entry? Yes To Setup Sector Protection Write XXXh/60h PLSCNT = 1 To Protect Secter Write 60h to Secter Address (A6 = A0 = VIL, A1 = VIH) Time out 150 µs To Verify Sector Protection Write 40h to Secter Address (A6 = A0 = VIL, A1 = VIH) Increment PLSCNT Read from Sector Address (Addr. = SPA, A0 = VIL, A1 = VIH, A6 = VIL) No Setup Next Sector Address No PLSCNT = 25? Data = 01h? Yes Yes Yes Protect Other Group ? Remove VID from RESET Write Reset Command No Remove VID from RESET Write Reset Command Device Failed Sector Protection Completed Extended Sector Protection Algorithm 51 MBM29LV800TE/BE60/70/90 FAST MODE ALGORITHM Start 555h/AAh Set Fast Mode 2AAh/55h 555h/20h XXXh/A0h Program Address/Program Data Data Polling In Fast Program Verify Data? No Yes Increment Address No Last Address? Yes Programming Completed XXXh/90h Reset Fast Mode XXXh/F0h Notes : • The sequence is applied for × 16 mode. • The addresses differ from × 8 mode. Embedded Programming Algorithm for Fast Mode 52 MBM29LV800TE/BE60/70/90 ■ ORDERING INFORMATION Part No. Package Access Time (ns) 48-pin plastic TSOP (1) (FPT-48P-M19) (Normal Bend) 60 70 90 MBM29LV800TE60PCV MBM29LV800TE70PCV MBM29LV800TE90PCV 48-pin plastic CSOP (LCC-48P-M03) 60 70 90 MBM29LV800TE60PBT MBM29LV800TE70PBT MBM29LV800TE90PBT 48-ball plastic FBGA (BGA-48P-M20) 60 70 90 MBM29LV800BE60TN MBM29LV800BE70TN MBM29LV800BE90TN 48-pin plastic TSOP (1) (FPT-48P-M19) (Normal Bend) 60 70 90 MBM29LV800BE60PCV MBM29LV800BE70PCV MBM29LV800BE90PCV 48-pin plastic CSOP (LCC-48P-M03) 60 70 90 MBM29LV800BE60PBT MBM29LV800BE70PBT MBM29LV800BE90PBT 48-ball plastic FBGA (BGA-48P-M20) 60 70 90 MBM29LV800TE60TN MBM29LV800TE70TN MBM29LV800TE90TN MBM29LV800 T E 60 Remarks Top Sector Bottom Sector PCV PACKAGE TYPE TN = 48-Pin Thin Small Outline Package (TSOP) Standard Pinout PCV = 48-Pin C-lead Small Outline Package (CSOP) PBT = 48-Ball Fine Pitch Ball Grid Array Package (FBGA) SPEED OPTION See Product Selector Guide Device Revision BOOT CODE SECTOR ARCHITECTURE T = Top sector B = Bottom sector DEVICE NUMBER/DESCRIPTION MBM29LV800 8 Mega-bit (1 M × 8-Bit or 512 K × 16-Bit) CMOS Flash Memory 3.0 V-only Read, Program, and Erase 53 MBM29LV800TE/BE60/70/90 ■ PACKAGE DIMENSIONS Note 1) * : Values do not include resin protrusion. Resin protrusion and gate protrusion are +0.15 (.006) Max (each side) . Note 2) Pins width and pins thickness include plating thickness. Note 3) Pins width do not include tie bar cutting remainder. 48-pin plastic TSOP (1) (FPT-48P-M19) LEAD No. 1 48 INDEX Details of "A" part 0.25(.010) 0~8˚ 0.60±0.15 (.024±.006) 24 25 * 12.00±0.20 20.00±0.20 (.787±.008) * 18.40±0.20 (.724±.008) "A" 0.10(.004) (.472±.008) +0.10 1.10 –0.05 +.004 .043 –.002 (Mounting height) +0.03 0.17 –0.08 +.001 .007 –.003 C 0.10±0.05 (.004±.002) (Stand off height) 0.50(.020) 0.22±0.05 (.009±.002) 0.10(.004) M 2003 FUJITSU LIMITED F48029S-c-6-7 Dimensions in mm (inches) . Note : The values in parentheses are reference values. (Continued) 54 MBM29LV800TE/BE60/70/90 Note 1) Note 2) Note 3) Note 4) 48-pin plastic CSOP (LCC-48P-M03) 48 *1 : Resin protrusion. (Each side : +0.15 (.006) Max) . *2 : These dimensions do not include resin protrusion. Pins width includes plating thickness. Pins width do not include tie bar cutting remainder. "A" 25 10.00±0.20 (.394±.008) *2 9.50±0.10 (.374±.004) INDEX INDEX +0.05 0.05 –0 +.002 .002 –.0 (Stand off) LEAD No. 1 24 *1 10.00±0.10(.394±.004) 0.95±0.05(.037±.002) (Mounting height) 0.22±0.035 (.009±.001) Details of "A" part 0˚~10˚ 0.40(.016) 0.08(.003) 0.65(.026) 1.15(.045) 9.20(.362)REF C 2003 FUJITSU LIMITED C48056S-c-2-2 Dimensions in mm (inches) . Note : The values in parentheses are reference values. (Continued) 55 MBM29LV800TE/BE60/70/90 (Continued) 48-ball plastic FBGA (BGA-48P-M20) +0.12 8.00±0.20(.315±.008) +.003 1.08 –0.13 .043 –.005 (Mounting height) 0.38±0.10(.015±.004) (Stand off) 5.60(.220) 0.80(.031)TYP 6 5 6.00±0.20 (.236±.008) 4 4.00(.157) 3 2 1 H (INDEX AREA) G F E D 48-ø0.45±0.05 (48-ø.018±.002) C B A ø0.08(.003) M 0.10(.004) C 2003 FUJITSU LIMITED B48020S-c-2-2 Dimensions in mm (inches) . Note : The values in parentheses are reference values. 56 MBM29LV800TE/BE60/70/90 FUJITSU LIMITED All Rights Reserved. The contents of this document are subject to change without notice. Customers are advised to consult with FUJITSU sales representatives before ordering. The information, such as descriptions of function and application circuit examples, in this document are presented solely for the purpose of reference to show examples of operations and uses of Fujitsu semiconductor device; Fujitsu does not warrant proper operation of the device with respect to use based on such information. When you develop equipment incorporating the device based on such information, you must assume any responsibility arising out of such use of the information. Fujitsu assumes no liability for any damages whatsoever arising out of the use of the information. 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Any semiconductor devices have an inherent chance of failure. You must protect against injury, damage or loss from such failures by incorporating safety design measures into your facility and equipment such as redundancy, fire protection, and prevention of over-current levels and other abnormal operating conditions. If any products described in this document represent goods or technologies subject to certain restrictions on export under the Foreign Exchange and Foreign Trade Law of Japan, the prior authorization by Japanese government will be required for export of those products from Japan. F0405 FUJITSU LIMITED Printed in Japan