ETC 74LCX541SJX

Revised March 2001
74LCX541
Low Voltage Octal Buffer/Line Driver
with 5V Tolerant Inputs and Outputs
General Description
Features
The LCX541 is an octal buffer/line driver designed to be
employed as memory and address drivers, clock drivers
and bus oriented transmitter/receivers. The LCX541 is a
non inverting option of the LCX540.
■ 5V tolerant input and outputs
This device is similar in function to the LCX244 while providing flow-through architecture (inputs on opposite side
from outputs). This pinout arrangement makes this device
especially useful as an output port for microprocessors,
allowing ease of layout and greater PC board density.
■ Power-down high impedance inputs and outputs
The LCX541 is designed for low voltage (2.5V or 3.3V) VCC
applications with capability of interfacing to a 5V signal
environment. The LCX541 is fabricated with an advanced
CMOS technology to achieve high speed operation while
maintaining CMOS low power dissipation.
■ 2.3V–3.6V VCC specifications provided
■ 6.5 ns tPD max (VCC = 3.3V), 10 µA ICC max
■ Supports live insertion/withdrawal (Note 1)
■ ±24 mA output drive (VCC = 3.0V)
■ Implements patented noise/ EMI reduction circuitry
■ Latch-up performance exceeds 500 mA
■ ESD performance:
Human body model > 2000V
Machine model > 200V
Note 1: To ensure the high-impedance state during power up or down,
OE should be tied to VCC through a pull-up resistor: the minimum value
or the resistor is determined by the current-sourcing capability of the
driver.
Ordering Code:
Order Number
Package Number
74LCX541WM
74LCX541SJ
M20B
M20D
Package Description
20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300" Wide
20-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide
74LCX541MSA
MSA20
20-Lead Shrink Small Outline Package (SSOP), EIAJ TYPE II, 5.3mm Wide
74LCX541MTC
MTC20
20-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide
Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code.
Logic Symbol
Connection Diagram
IEEE/IEC
© 2001 Fairchild Semiconductor Corporation
DS012404
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74LCX541 Low Voltage Octal Buffer/Line Driver with 5V Tolerant Inputs and Outputs
March 1995
74LCX541
Pin Descriptions
Pin Names
Description
OE1, OE2
3-STATE Output Enable Inputs
I0, I7
Inputs
O0, O7
Outputs
Truth Table
Inputs
OE1
Outputs
OE2
I
On
H
L
L
H
H
X
X
Z
X
H
X
Z
L
L
L
L
H = HIGH Voltage Level
L = LOW Voltage Level
X = Immaterial
Z = High Impedance
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2
Symbol
Parameter
Value
VCC
Supply Voltage
−0.5 to +7.0
VI
DC Input Voltage
−0.5 to +7.0
VO
DC Output Voltage
−0.5 to +7.0
Conditions
Units
V
V
Output in 3-STATE
−0.5 to VCC + 0.5
Output in HIGH or LOW State (Note 3)
IIK
DC Input Diode Current
−50
VI < GND
IOK
DC Output Diode Current
−50
VO < GND
+50
VO > VCC
V
mA
mA
IO
DC Output Source/Sink Current
±50
mA
ICC
DC Supply Current per Supply Pin
±100
mA
IGND
DC Ground Current per Ground Pin
±100
mA
TSTG
Storage Temperature
−65 to +150
°C
Recommended Operating Conditions (Note 4)
Symbol
VCC
Parameter
Supply Voltage
VI
Input Voltage
VO
Output Voltage
IOH/IOL
TA
Free-Air Operating Temperature
Input Edge Rate, VIN = 0.8V–2.0V, VCC = 3.0V
Max
2.0
3.6
Data Retention
1.5
3.6
0
5.5
HIGH or LOW State
0
VCC
3-STATE
0
5.5
Output Current
∆t/∆V
Min
Operating
VCC = 3.0V − 3.6V
±24
VCC = 2.7V − 3.0V
±12
VCC = 2.3V − 2.7V
±8
Units
V
V
V
mA
−40
85
°C
0
10
ns/V
Note 2: The Absolute Maximum Ratings are those values beyond which the safety of the device cannot be guaranteed. The device should not be operated
at these limits. The parametric values defined in the Electrical Characteristics tables are not guaranteed at the Absolute Maximum Ratings. The “Recommended Operating Conditions” table will define the conditions for actual device operation.
Note 3: IO Absolute Maximum Rating must be observed.
Note 4: Unused inputs or I/O's must be held HIGH or LOW. They may not float.
DC Electrical Characteristics
Symbol
VIH
VIL
VOH
Parameter
Conditions
HIGH Level Input Voltage
LOW Level Input Voltage
HIGH Level Output Voltage
IOH = −100µA
LOW Level Output Voltage
TA = −40°C to +85°C
(V)
Min
2.3 − 2.7
1.7
2.7 − 3.6
2.0
0.7
0.8
VCC - 0.2
2.3
1.8
IOH = −12 mA
2.7
2.2
IOH = −18 mA
3.0
2.4
3.0
2.2
2.3 − 3.6
V
V
0.2
IOL = 8mA
2.3
0.6
IOL = 12 mA
2.7
0.4
IOL = 16 mA
3.0
0.4
IOL = 24 mA
3.0
0.55
II
Input Leakage Current
0 ≤ VI ≤ 5.5V
2.3 − 3.6
±5.0
IOFF
Power-Off Leakage Current
VI or VO = 5.5V
0
10
ICC
Quiescent Supply Current
VI = VCC or GND
2.3 − 3.6
10
3.6V ≤ VI, VO ≤ 5.5V (Note 5)
2.3 − 3.6
±10
∆ICC
Increase in ICC per Input
VIH = VCC = 0.6V
2.3 − 3.6
500
3
Units
V
2.3 − 2.7
2.3 − 3.6
IOL = 100µA
Max
2.7 − 3.6
IOH = -8 mA
IOH = −24 mA
VOL
VCC
V
µA
µA
µA
µA
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74LCX541
Absolute Maximum Ratings(Note 2)
74LCX541
DC Electrical Characteristics
(Continued)
Note 5: Outputs disabled or 3-STATE only.
AC Electrical Characteristics
TA = −40°C to +85°C, RL = 500Ω
Symbol
tPHL
Parameter
Propagation Delay
tPLH
tPZL
Output Enable Time
tPZH
tPLZ
Output Disable Time
tPHZ
tOSHL
VCC = 3.3V ± 0.3V
VCC = 2.7V
VCC = 2.5V ± 0.2V
CL = 50 pF
CL = 50 pF
CL = 30 pF
Min
Max
Min
Max
Min
Max
1.5
6.5
1.5
7.5
1.5
7.8
1.5
6.5
1.5
7.5
1.5
7.8
1.5
8.5
1.5
9.5
1.5
10.5
1.5
8.5
1.5
9.5
1.5
10.5
1.5
7.5
1.5
8.5
1.5
9.0
1.5
7.5
1.5
8.5
1.5
9.0
Output to Output Skew (Note 6)
1.0
tOSLH
Units
ns
ns
ns
ns
1.0
Note 6: Skew is defined as the absolute value of the difference between the actual propagation delay for any two separate outputs of the same device. The
specification applies to any outputs switching in the same direction, either HIGH-to-LOW (tOSHL) or LOW-to-HIGH (tOSLH).
Dynamic Switching Characteristics
Symbol
VOLP
VOLV
VCC
TA = 25°C
(V)
Typical
CL = 50 pF, VIH = 3.3V, VIL = 0V
3.3
0.8
CL = 30 pF, VIH = 2.5V, VIL = 0V
2.5
0.6
CL = 50 pF, VIH = 3.3V, VIL = 0V
3.3
−0.8
CL = 30 pF, VIH = 2.5V, VIL = 0V
2.5
−0.6
Parameter
Quiet Output Dynamic Peak VOL
Quiet Output Dynamic Valley VOL
Conditions
Units
V
V
Capacitance
Typical
Units
CIN
Symbol
Input Capacitance
Parameter
VCC = Open, VI = 0V or VCC
7
pF
COUT
Output Capacitance
VCC = 3.3V, VI = 0V or VCC
8
pF
CPD
Power Dissipation Capacitance
VCC = 3.3V, VI = 0V or VCC, f = 10 MHz
25
pF
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Conditions
4
74LCX541
AC Loading and Waveforms Generic for LCX Family
FIGURE 1. AC Test Circuit
(CL includes probe and jig capacitance)
Test
Switch
tPLH, tPHL
Open
tPZL, tPLZ
6V at VCC = 3.3 ± 0.3V
VCC x 2 at VCC = 2.5 ± 0.2V
tPZH,tPHZ
GND
Waveform for Inverting and Non-Inverting Functions
3-STATE Output Low Enable and
Disable Times for Logic
Propagation Delay, Pulse Width and trec Waveforms
Setup Time, Hold TIme and Recovery TIme for Logic
3-STATE Output High Enable and
Disable Times for Logic
trise and tfall
FIGURE 2. Waveforms
(Input Pulse Characteristics; f = 1MHz, tr = tf = 3ns)
Symbol
VCC
3.3V ± 0.3V
2.7V
2.5V ± 0.2V
Vmi
1.5V
1.5V
VCC/2
Vmo
1.5V
1.5V
VCC/2
Vx
VOL + 0.3V
VOL + 0.3V
VOL + 0.15V
Vy
VOH − 0.3V
VOH − 0.3V
VOH − 0.15V
5
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74LCX541
Schematic Diagram Generic for LCX Family
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74LCX541
Physical Dimensions inches (millimeters) unless otherwise noted
20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300" Wide
Package Number M20B
7
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74LCX541
Physical Dimensions inches (millimeters) unless otherwise noted (Continued)
20-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide
Package Number M20D
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8
74LCX541
Physical Dimensions inches (millimeters) unless otherwise noted (Continued)
20-Lead Shrink Small Outline Package (SSOP), EIAJ TYPE II, 5.3mm Wide
Package Number MSA20
9
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74LCX541 Low Voltage Octal Buffer/Line Driver with 5V Tolerant Inputs and Outputs
Physical Dimensions inches (millimeters) unless otherwise noted (Continued)
20-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide
Package Number MTC20
Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and
Fairchild reserves the right at any time without notice to change said circuitry and specifications.
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FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT
DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD
SEMICONDUCTOR CORPORATION. As used herein:
2. A critical component in any component of a life support
device or system whose failure to perform can be reasonably expected to cause the failure of the life support
device or system, or to affect its safety or effectiveness.
1. Life support devices or systems are devices or systems
which, (a) are intended for surgical implant into the
body, or (b) support or sustain life, and (c) whose failure
to perform when properly used in accordance with
instructions for use provided in the labeling, can be reasonably expected to result in a significant injury to the
user.
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