ETC ATL35

ADD3X
ATL35 CMOS Gate Array
cell data sheets 1.0
DESCRIPTION: 1 bit full adder with buffered outputs
Truth Table:
P
P Q CI | SO CO
------------------0 0 0 | 0 0
0 0 1 | 1 0
0 1 0 | 1 0
0 1 1 | 0 1
1 0 0 | 1 0
1 0 1 | 0 1
1 1 0 | 0 1
1 1 1 | 1 1
SO
ADD3X
Q
CO
ATL55Cells
CI
p
P31
VDD!
P
p
p
P88
P64
N33
VDD!
n
N85
n
N61
VDD!
n
p
p
p
P82
VDD!
SO
VSS!
p
p
P91
P68
N89
n
VDD!
N65
N39
n
N54
n
N84
P38
P58
VSS!
n
n
VSS!
p
VSS!
VDD!
p
p
P7
P94
P70
VDD!
Q
n
N96
n
N11
N72
p
P77
n
CO
VSS!
VSS!
p
n
P98
CI
N79
VSS!
N100
n
/tech/common/scripts/dataSheetGenerator/createCellFolder.pl ($Revision: 1.35 $)
Mon Oct 20 15:24:00 1997
1
ADD3X
ATL35 CMOS Gate Array
cell data sheets 1.0
DESCRIPTION: 1 bit full adder with buffered outputs
SITES: Core = 10 Ring = 0 IO = 0
LOADS: CI=2.0 P=2.0 Q=2.0
TIMING TABLE 3V:
(NomProc,25degC,Nom trf)
Path
---CI -> SO
CI -> CO
P -> SO
P -> CO
Q -> SO
Q -> CO
Rise Int
-------0.36283
0.30031
0.53600
0.53227
0.63993
0.54121
Rise Slope
---------0.02771
0.02743
0.02766
0.02751
0.02750
0.02755
Fall Slope
---------0.02524
0.02534
0.02529
0.02533
0.02527
0.02530
Fall Int
-------0.34403
0.34854
0.48636
0.61277
0.47152
0.30263
ADD3X 3v 25 deg Typical Case Path Delays
CI -> SO rise
CI -> SO fall
CI -> CO rise
CI -> CO fall
P -> SO rise
P -> SO fall
P -> CO rise
P -> CO fall
Q -> SO rise
Q -> SO fall
Q -> CO rise
Q -> CO fall
Delay in (ns)
10
1
0.1
1
10
Number of unit loads
100
/tech/common/scripts/dataSheetGenerator/createCellFolder.pl ($Revision: 1.35 $)
Mon Oct 20 15:24:00 1997
2