ETC IDT74FCT16206ETPV

IDT74FCT16260AT/CT/ET
FAST CMOS 12-BIT TRI-PORT BUS EXCHANGER
INDUSTRIAL TEMPERATURE RANGE
FAST CMOS
12-BIT TRI-PORT
BUS EXCHANGER
IDT74FCT16260AT/CT/ET
FEATURES:
DESCRIPTION:
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The FCT16260T Tri-Port Bus Exchangers are high-speed 12-bit latched
bus multiplexers/transceivers for use in high-speed microprocessor applications. These Bus Exchangers support memory interleaving with latched outputs
on the B ports and address multiplexing with latched inputs on the B ports.
The Tri-Port Bus Exchanger has three 12-bit ports. Data may be transferred
between the A port and either/both of the B ports. The latch enable (LE1B, LE2B,
LEA1B and LEA2B) inputs control data storage. When a latch-enable input is
high, the latch is transparent. When a latch-enable input is low, the data at the
input is latched and remains latched until the latch enable input is returned high.
Independent output enables (OE1B and OE2B) allow reading from one port
while writing to the other port.
The FCT16260T is ideally suited for driving high capacitance loads and low
impedance backplanes. The output buffers are designed with power off disable
capability to allow "live insertion" of boards when used as backplane drivers.
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0.5 MICRON CMOS Technology
High-speed, low-power CMOS replacement for ABT functions
Typical tSK(o) (Output Skew) < 250ps
Low input and output leakage ≤ 1µA (max.)
ESD > 2000V per MIL-STD-883, Method 3015; > 200V using
machine model (C = 200pF, R = 0)
VCC = 5V ±10%
High drive outputs (–32mA IOH, 64mA IOL)
Power off disable outputs permit “live insertion”
Typical VOLP (Output Ground Bounce) < 1.0V at VCC = 5V,
TA = 25°C
Power off disable outputs permit “live insertion”
Available in SSOP and TSSOP packages
FUNCTIONAL BLOCK DIAGRAM
29
OE1B
30
LEA1B
A-1B
LATC H
1B 1:12
12
2
LE1B
1B-A
LATC H
12
SEL
12
12
28
1
OEA
A 1:12
12
M1
U
X 0
12
12
2B-A
LATC H
27
LE2B
A-2B
LATC H
55
LEA2B
12
12
2B 1:12
56
OE2B
The IDT logo is a registered trademark of Integrated Device Technology, Inc.
INDUSTRIAL TEMPERATURE RANGE
JANUARY 2002
1
© 2002 Integrated Device Technology, Inc.
DSC-5431/2
IDT74FCT16260AT/CT/ET
FAST CMOS 12-BIT TRI-PORT BUS EXCHANGER
INDUSTRIAL TEMPERATURE RANGE
ABSOLUTE MAXIMUM RATINGS(1)
PIN CONFIGURATION
OEA
LE1B
1
2
56
55
OE2B
LEA2B
Symbol
Description
Max
Unit
VTERM(2)
Terminal Voltage with Respect to GND
–0.5 to 7
V
VTERM(3)
Terminal Voltage with Respect to GND
–0.5 to VCC+0.5
V
TSTG
Storage Temperature
–65 to +150
°C
IOUT
DC Output Current
–60 to +120
mA
2B 3
3
54
2B 4
GND
4
53
GND
2B 2
5
52
2B 5
2B 1
6
51
2B 6
V CC
7
50
V CC
A1
8
49
2B 7
A2
9
48
2B 8
A3
10
47
2B 9
GND
11
46
GND
Symbol
A4
12
45
2B 10
CIN
Input Capacitance
VIN = 0V
3.5
6
pF
A5
13
44
2B 11
COUT
Output Capacitance
VOUT = 0V
3.5
8
pF
A6
14
43
2B 12
A7
15
42
1B 12
A8
16
41
1B 11
A9
17
40
1B 10
GND
18
39
GND
A 10
19
38
1B 9
A 11
20
37
1B 8
A 12
21
36
1B 7
V CC
22
35
V CC
1B 1
23
34
1B 6
1B 2
24
33
1B 5
GND
25
32
GND
1B 3
26
31
1B 4
LE2B
27
30
LEA1B
SEL
28
29
OE1B
NOTES:
1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause
permanent damage to the device. This is a stress rating only and functional operation
of the device at these or any other conditions above those indicated in the operational
sections of this specification is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect reliability.
2. All device terminals except FCT162XXX Output and I/O terminals.
3. Output and I/O terminals for FCT162XXX.
CAPACITANCE (TA = +25°C, F = 1.0MHz)
Parameter(1)
Conditions
Typ.
NOTE:
1. This parameter is measured at characterization but not tested.
SSOP/ TSSOP
TOP VIEW
2
Max.
Unit
IDT74FCT16260AT/CT/ET
FAST CMOS 12-BIT TRI-PORT BUS EXCHANGER
INDUSTRIAL TEMPERATURE RANGE
PIN DESCRIPTION
Signal
I/O
Description
A(1:12)
I/O
Bidirectional Data Port A. Usually connected to the CPU's Address/Data bus.
1B(1:12)
I/O
Bidirectional Data Port 1B. Connected to the even path or even bank of memory.
2B(1:12)
I/O
LEA1B
I
Latch Enable Input for A-1B Latch. The Latch is open when LEA1B is HIGH. Data from the A-port is latched on the HIGH to
LOW transition of LEA1B.
Bidirectional Data Port 2B. Connected to the odd path or odd bank of memory.
LEA2B
I
Latch Enable Input for A-2B Latch. The Latch is open when LEA2B is HIGH. Data from the A-Port is latched on the HIGH to
LOW transition of LEA2B.
LE1B
I
Latch Enable Input for the 1B-A Latch. The Latch is open when LE1B is HIGH. Data from the 1B port is latched on the HIGH
to LOW transition of LE1B.
LE2B
I
Latch Enable Input for the 2B-A Latch. The Latch is open when LE2B is HIGH. Data from the 2B port is latched on the HIGH
to LOW transition of LE2B.
SEL
I
1B or 2B Path Selection. When HIGH, SEL enables data transfer from 1B Port to A Port. When LOW, SEL enables data
transfer from 2B Port to A Port.
OEA
I
Output Enable for A Port (Active LOW)
OE1B
I
Output Enable for 1B Port (Active LOW)
OE2B
I
Output Enable for 2B Port (Active LOW)
FUNCTION TABLES(1)
Inputs
LE1B
H
H
L
X
X
X
X
1B
H
L
X
X
X
X
X
2B
X
X
X
H
L
X
X
SEL
H
H
H
L
L
L
X
A
H
L
H
L
H
L
X
X
X
X
X
LEA1B
H
H
H
H
L
L
L
X
X
X
X
Inputs
LEA2B
H
H
L
L
H
H
L
X
X
X
X
LE2B
X
X
X
H
H
L
X
OEA
L
L
L
L
L
L
H
Output
A
H
L
A(1)
H
L
A(1)
Z
Outputs
OE1B
L
L
L
L
L
L
L
H
L
H
L
OE2B
L
L
L
L
L
L
L
H
H
L
L
1B
H
L
H
L
B(1)
B(1)
B(1)
Z
Active
Z
Active
2B
H
L
B(1)
B(1)
H
L
B(1)
Z
Z
Active
Active
NOTES:
1. Output level before the indicated steady-state input conditions were established.
2. H = HIGH Voltage Level
L = LOW Voltage Level
X = Don't Care
Z = High-Impedance
3
IDT74FCT16260AT/CT/ET
FAST CMOS 12-BIT TRI-PORT BUS EXCHANGER
INDUSTRIAL TEMPERATURE RANGE
DC ELECTRICAL CHARACTERISTICS OVER OPERATING RANGE
Following Conditions Apply Unless Otherwise Specified:
Industrial: TA = –40°C to +85°C, VCC = 5.0V ±10%
Symbol
Test Conditions(1)
Parameter
Min.
Typ.(2)
Max.
Unit
VIH
Input HIGH Level
Guaranteed Logic HIGH Level
2
—
—
V
VIL
Input LOW Level
Guaranteed Logic LOW Level
—
—
0.8
V
IIH
Input HIGH Current (Input pins)(5)
VCC = Max.
—
—
±1
µA
—
—
±1
—
—
±1
—
—
±1
VO = 2.7V
—
—
±1
VO = 0.5V
—
—
±1
VI = VCC
Input HIGH Current (I/O pins)(5)
IIL
Input LOW Current (Input pins)(5)
VI = GND
Input LOW Current (I/O pins)(5)
IOZH
High Impedance Output Current
IOZL
(3-State Output pins)(5)
VIK
Clamp Diode Voltage
VCC = Min., IIN = –18mA
—
–0.7
–1.2
V
IOS
Short Circuit Current
VCC = Max., VO = GND(3)
–80
–140
–250
mA
VH
Input Hysteresis
—
100
—
mV
ICCL
ICCH
ICCZ
Quiescent Power Supply Current
—
5
500
µA
VCC = Max.
—
VCC = Max.
VIN = GND or VCC
µA
OUTPUT DRIVE CHARACTERISTICS
Symbol
IO
VOH
Parameter
Output Drive Current
Output HIGH Voltage
VOL
Output LOW Voltage
IOFF
Input/Output Power Off Leakage(5)
Test Conditions(1)
Min.
Typ.(2)
Max.
VCC = Max., VO = 2.5V(3)
VCC = Min.
IOH = –3mA
VIN = VIH or VIL
IOH = –15mA
IOH = –32mA(4)
VCC = Min.
IOL = 64mA
VIN = VIH or VIL
–50
2.5
2.4
2
—
—
3.5
3.5
3
0.2
–180
—
—
—
0.55
mA
VCC = 0V, VIN or VO ≤ 4.5V
—
—
±1
µA
NOTES:
1. For conditions shown as Min. or Max., use appropriate value specified under Electrical Characteristics for the applicable device type.
2. Typical values are at VCC = 5.0V, +25°C ambient.
3. Not more than one output should be shorted at one time. Duration of the test should not exceed one second.
4. Duration of the condition can not exceed one second.
5. The test limit for this parameter is ±5µA at TA = –55°C.
4
Unit
V
V
IDT74FCT16260AT/CT/ET
FAST CMOS 12-BIT TRI-PORT BUS EXCHANGER
INDUSTRIAL TEMPERATURE RANGE
POWER SUPPLY CHARACTERISTICS
Test Conditions(1)
Symbol
Parameter
∆ICC
Quiescent Power Supply Current
TTL Inputs HIGH
VCC = Max.
VIN = 3.4V(3)
ICCD
Dynamic Power Supply
Current(4)
VCC = Max.
Outputs Open
One Output Port Enabled
LExx = VCC
One Input Bit Togging
One Output Bit Toggling
50% Duty Cycle
VCC = Max.
Outputs Open
fi = 10MHz
50% Duty Cycle
One Output Port Enabled
LExx = VCC
One Input Bit Toggling
One Output Bit Toggling
VCC = Max.
Outputs Open
fi = 2.5MHz
50% Duty Cycle
One Output Port Enabled
LExx = VCC
Twelve Input Bits Toggling
Twelve Output Bits Toggling
IC
Total Power Supply Current(6)
Min.
Typ.(2)
Max.
Unit
—
0.5
1.5
mA
VIN = VCC
VIN = GND
—
60
100
µA/
MHz
VIN = VCC
VIN = GND
—
0.6
1.5
mA
VIN = 3.4V
VIN = GND
—
0.9
2.3
VIN = VCC
VIN = GND
—
1.8
3.5(5)
VIN = 3.4V
VIN = GND
—
4.8
12.5(5)
NOTES:
1. For conditions shown as Min. or Max., use appropriate value specified under Electrical Characteristics for the applicable device type.
2. Typical values are at VCC = 5.0V, +25°C ambient.
3. Per TTL driven input (VIN = 3.4V). All other inputs at VCC or GND.
4. This parameter is not directly testable, but is derived for use in Total Power Supply Calculations.
5. Values for these conditions are examples of the ICC formula. These limits are guaranteed but not tested.
6. IC = IQUIESCENT + IINPUTS + IDYNAMIC
IC = ICC + ∆ICC DHNT + ICCD (fCPNCP/2 + fiNi)
ICC = Quiescent Current (ICCL, ICCH and ICCZ)
∆ICC = Power Supply Current for a TTL High Input (VIN = 3.4V).
DH = Duty Cycle for TTL Inputs High
NT = Number of TTL Inputs at DH
ICCD = Dynamic Current caused by an Input Transition Pair (HLH or LHL)
fCP = Clock Frequency for Register Devices (Zero for Non-Register Devices)
NCP = Number of Clock Inputs at fCP
fi = Input Frequency
Ni = Number of Inputs at fi
5
IDT74FCT16260AT/CT/ET
FAST CMOS 12-BIT TRI-PORT BUS EXCHANGER
INDUSTRIAL TEMPERATURE RANGE
SWITCHING CHARACTERISTICS OVER OPERATING RANGE
FCT16260AT
Symbol
Parameter
Max.
Min.(2)
Max.
Min.(2)
Max.
Unit
1.5
5.2
1.5
4.7
1.5
3.6
ns
1.5
5.6
1.5
5
1.5
3.6
ns
1.5
5.2
1.5
4.7
1.5
4
ns
1.5
4.7
1.5
4.4
1.5
4
ns
1.5
5.2
1.5
4.7
1.5
4
ns
Propagation Delay
CL = 50pF
tPHL
Ax to 1Bx or Ax to 2Bx
RL = 500Ω
tPLH
Propagation Delay
1Bx to Ax or 2Bx to Ax
tPLH
Propagation Delay
tPHL
LExB to Ax
tPLH
Propagation Delay
tPHL
LEA1B to 1Bx or LEA2B to 2Bx
FCT16260ET
Min.(2)
tPLH
tPHL
FCT16260CT
Condition(1)
tPLH
Propagation Delay
tPHL
SEL to Ax
tPZH
tPZL
Output Enable Time
OEA to Ax, OE1B to 1Bx, or OE2B to 2Bx
1.5
5.7
1.5
5.1
1.5
4.4
ns
tPHZ
tPLZ
Output Disable Time
OEA to Ax, OE1B to 1Bx, or OE2B to 2Bx
1.5
4.4
1.5
4
1.5
4
ns
tSU
Set-up Time HIGH or LOW Data to Latch
1.5
—
1
—
1
—
ns
tH
Hold Time, Latch to Data
1
—
1
—
1
—
ns
tW
Pulse Width, Latch HIGH (4)
3
—
3
—
3
—
ns
Output Skew(3)
—
0.5
—
0.5
—
0.5
ns
tSK(o)
NOTES:
1. See test circuits and waveforms.
2. Minimum limits are guaranteed but not tested on Propagation Delays.
3. Skew between any two outputs of the same package switching in the same direction. This parameter is guaranteed by design.
4. This parameter is guaranteed but not tested.
6
IDT74FCT16260AT/CT/ET
FAST CMOS 12-BIT TRI-PORT BUS EXCHANGER
INDUSTRIAL TEMPERATURE RANGE
TEST CIRCUITS AND WAVEFORMS
V CC
SWITCH POSITION
7.0V
500 Ω
Pulse
Generator
D.U.T.
50pF
RT
Switch
Closed
All Other Tests
Open
DEFINITIONS:
CL = Load capacitance: includes jig and probe capacitance.
RT = Termination resistance: should be equal to ZOUT of the Pulse Generator.
V OU T
V IN
Test
Open Drain
Disable Low
Enable Low
500 Ω
CL
Test Circuits for All Outputs
DATA
INPUT
tH
t SU
TIMING
INPUT
ASYNCHRONOUS CONTROL
PRESET
CLEAR
ETC.
SYNCHRONOUS CONTROL
PRESET
CLEAR
CLOCK ENABLE
ETC.
tRE M
t SU
3V
1.5V
0V
3V
1.5V
0V
LOW -HIGH-LOW
PULSE
1.5V
tW
3V
1.5V
0V
HIGH-LOW -HIGH
PULSE
1.5V
3V
1.5V
0V
tH
Pulse Width
Set-up, Hold, and Release Times
ENAB LE
SAME PHASE
INPUT TRANSITION
tPLH
t PHL
OUTPUT
t PLH
OPPOSITE PHASE
INPUT TRANSITION
t PHL
3V
1.5V
0V
DISABLE
3V
CONTROL
INPUT
1.5V
OUTPUT
NORM ALLY
LOW
3V
1.5V
0V
SW ITCH
CLOSED
3.5V
1.5V
SW ITCH
OPEN
3.5V
0.3V
t PZH
OUTPUT
NORM ALLY
HIGH
0V
t PLZ
tPZL
V OH
1.5V
V OL
V OL
tPHZ
0.3V
V OH
1.5V
0V
0V
Propagation Delay
Enable and Disable Times
NOTES:
1. Diagram shown for input Control Enable-LOW and input Control Disable-HIGH.
2. Pulse Generator for All Pulses: Rate ≤ 1.0MHz; tF ≤ 2.5ns; tR ≤ 2.5ns.
7
IDT74FCT16260AT/CT/ET
FAST CMOS 12-BIT TRI-PORT BUS EXCHANGER
INDUSTRIAL TEMPERATURE RANGE
ORDERING INFORMATION
IDT
XX
Temp. Range
FCT
XXX
XXXX
XX
Family
Device Type
Package
PV
PA
Shrink Small Outline Package
Thin Shrink Small Outline Package
206AT
206CT
206ET
12-Bit Tri-Port Bus Exchanger
16
Double-Density, 5 Volt, Balanced Drive
74
– 40°C to +85°C
DATA SHEET DOCUMENT HISTORY
1/21/2002
Removed Military temp grade
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8
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