IDT74FCT162373AT/CT/ET FAST CMOS 16-BIT TRANSPARENT LATCH INDUSTRIAL TEMPERATURE RANGE FAST CMOS 16-BIT TRANSPARENT LATCH IDT74FCT162373AT/CT/ET FEATURES: DESCRIPTION: • • • • • • • • The FCT162373T 16-bit transparent D-type latch is built using advanced dual metal CMOS technology. This high-speed, low-power latch is ideal for temporary storage of data. It can be used for implementing memory address latches, I/O ports, and bus drivers. The Output Enable and Latch Enable controls are organized to operate each device as two 8-bit latches, or one 16-bit latch. Flow-through organization of signal pins simplifies layout. All inputs are designed with hysteresis for improved noise margin. The FCT162373T has balanced output drive with current limiting resistors. This offers low ground bounce, minimal undershoot, and controlled output fall times–reducing the need for external series terminating resistors. The FCT162373T is a plug-in replacement for the FCT16373T and ABT16373 for on-board interface applications. 0.5 MICRON CMOS Technology High-speed, low-power CMOS replacement for ABT functions Typical tSK(o) (Output Skew) < 250ps Low input and output leakage ≤1µA (max.) VCC = 5V ±10% Balanced Output Drivers: ±24mA Reduced system switching noise Typical VOLP (Output Ground Bounce) < 0.6V at VCC = 5V, TA = 25°C • Available in SSOP and TSSOP packages FUNCTIONAL BLOCK DIAGRAM 1 OE 2 OE 1 LE 2 LE 1D 1 D 2D 1 D 1O 1 2O 1 C C TO SEVEN OTHER CHANNELS TO SEVEN OTHER CHANNELS The IDT logo is a registered trademark of Integrated Device Technology, Inc. INDUSTRIAL TEMPERATURE RANGE JUNE 2006 1 © 2006 Integrated Device Technology, Inc. DSC-5455/5 IDT74FCT162373AT/CT/ET FAST CMOS 16-BIT TRANSPARENT LATCH INDUSTRIAL TEMPERATURE RANGE PIN CONFIGURATION ABSOLUTE MAXIMUM RATINGS(1) 1 48 1LE 1O1 2 47 1D 1 1O2 3 46 1D 2 1OE Symbol Description Max Unit VTERM(2) Terminal Voltage with Respect to GND –0.5 to +7 V VTERM(3) Terminal Voltage with Respect to GND –0.5 to VCC+0.5 V TSTG Storage Temperature –65 to +150 °C IOUT DC Output Current –60 to +120 mA NOTES: 1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. 2. All device terminals except FCT162XXX Output and I/O terminals. 3. Output and I/O terminals terminals for FCT162XXX. GND 4 45 GND 1O3 5 44 1D 3 1O4 6 43 1D 4 VCC 7 42 VCC 1O5 8 41 1D 5 1O6 9 40 1D 6 GND 10 39 GND 1O7 11 38 1D 7 1O8 12 37 1D 8 2O1 13 36 2D 1 2O2 14 35 2D 2 GND 15 34 GND xDx Data Inputs 2O3 16 33 2D 3 xLE Latch Enable Input (Active HIGH) 2O4 17 32 2D 4 xOE Outputs Enable Input (Active LOW) xOx 3-State Outputs VCC 18 31 VCC 2O5 19 30 2D 5 2O6 20 29 2D 6 GND 21 28 GND 2O7 22 27 2O8 23 2OE 24 CAPACITANCE (TA = +25°C, F = 1.0MHz) Parameter(1) Conditions Typ. Max. Unit CIN Input Capacitance VIN = 0V 3.5 6 pF COUT Output Capacitance VOUT = 0V 3.5 8 pF Symbol NOTE: 1. This parameter is measured at characterization but not tested. PIN DESCRIPTION Pin Names Description FUNCTION TABLE(1) Inputs Outputs xDx xLE xOE xOx 2D 7 H H L H 26 2D 8 L H L L 25 2LE X X H Z NOTE: 1. H = HIGH Voltage Level X = Don’t Care L = LOW Voltage Level Z = High-Impedance SSOP/ TSSOP TOP VIEW 2 IDT74FCT162373AT/CT/ET FAST CMOS 16-BIT TRANSPARENT LATCH INDUSTRIAL TEMPERATURE RANGE DC ELECTRICAL CHARACTERISTICS OVER OPERATING RANGE Following Conditions Apply Unless Otherwise Specified: Industrial: TA = –40°C to +85°C, VCC = 5.0V ±10% Symbol Test Conditions(1) Parameter Min. Typ.(2) Max. Unit VIH Input HIGH Level Guaranteed Logic HIGH Level 2 — — V VIL Input LOW Level Guaranteed Logic LOW Level — — 0.8 V IIH Input HIGH Current (Input pins)(5) VCC = Max. — — ±1 µA — — ±1 — — ±1 — — ±1 VO = 2.7V — — ±1 VO = 0.5V — — ±1 — –0.7 –1.2 V –80 –140 –250 mA — 100 — mV — 5 500 µA Typ.(2) VI = VCC Input HIGH Current (I/O pins)(5) IIL Input LOW Current (Input pins)(5) VCC = Max. VI = GND Input LOW Current (I/O pins)(5) IOZH High Impedance Output Current IOZL (3-State Output pins)(5) VIK Clamp Diode Voltage IOS Short Circuit Current VH Input Hysteresis ICCL ICCH ICCZ Quiescent Power Supply Current VCC = Max. VCC = Min., IIN = –18mA VCC = Max., VO = GND(3) — VCC = Max. VIN = GND or VCC µA µA OUTPUT DRIVE CHARACTERISTICS Symbol Test Conditions(1) Max. Unit Output LOW Current VCC = 5V, VIN = VIH or VIL, VO = 1.5V(3) 60 115 200 mA IODH VOH Output HIGH Current Output HIGH Voltage VCC = 5V, VIN = VIH or VIL, VO = 1.5V(3) IOH = –24mA –60 2.4 –115 3.3 –200 — mA V VOL Output LOW Voltage IOL = 24mA — 0.3 0.55 V IODL Parameter VCC = Min VIN = VIH or VIL VCC = Min VIN = VIH or VIL Min. NOTES: 1. For conditions shown as Min. or Max., use appropriate value specified under Electrical Characteristics for the applicable device type. 2. Typical values are at VCC = 5.0V, +25°C ambient. 3. Not more than one output should be tested at one time. Duration of the test should not exceed one second. 4. Duration of the condition can not exceed one second. 5. The test limit for this parameter is ±5µA at TA = –55°C. 3 IDT74FCT162373AT/CT/ET FAST CMOS 16-BIT TRANSPARENT LATCH INDUSTRIAL TEMPERATURE RANGE POWER SUPPLY CHARACTERISTICS Test Conditions(1) Min. Typ.(2) Max. Unit — 0.5 1.5 mA VIN = VCC VIN = GND — 60 100 µA/ MHz VCC = Max. Outputs Open fi = 10MHz VIN = VCC VIN = GND — 0.6 1.5 mA 50% Duty Cycle xOE = GND xLE = VCC One Bit Togging VIN = 3.4V VIN = GND — 0.9 2.3 VCC = Max. Outputs Open fi = 2.5MHz 50% Duty Cycle VIN = VCC VIN = GND — 2.4 4.5(5) xOE = GND xLE = VCC Sixteen Bits Togging VIN = 3.4V VIN = GND — 6.4 16.5(5) Symbol Parameter ΔICC Quiescent Power Supply Current TTL Inputs HIGH VCC = Max. VIN = 3.4V(3) ICCD Dynamic Power Supply Current(4) VCC = Max. Outputs Open xOE = GND One Input Togging 50% Duty Cycle Total Power Supply Current(6) IC NOTES: 1. For conditions shown as Min. or Max., use appropriate value specified under Electrical Characteristics for the applicable device type. 2. Typical values are at VCC = 5.0V, +25°C ambient. 3. Per TTL driven input (VIN = 3.4V). All other inputs at VCC or GND. 4. This parameter is not directly testable, but is derived for use in Total Power Supply Calculations. 5. Values for these conditions are examples of the ICC formula. These limits are guaranteed but not tested. 6. IC = IQUIESCENT + IINPUTS + IDYNAMIC IC = ICC + ΔICC DHNT + ICCD (fCPNCP/2 + fiNi) ICC = Quiescent Current (ICCL, ICCH and ICCZ) ΔICC = Power Supply Current for a TTL High Input (VIN = 3.4V) DH = Duty Cycle for TTL Inputs High NT = Number of TTL Inputs at DH ICCD = Dynamic Current caused by an Input Transition Pair (HLH or LHL) fCP = Clock Frequency for Register Devices (Zero for Non-Register Devices) NCP = Number of Clock Inputs at fCP fi = Input Frequency Ni = Number of Inputs at fi 4 IDT74FCT162373AT/CT/ET FAST CMOS 16-BIT TRANSPARENT LATCH INDUSTRIAL TEMPERATURE RANGE SWITCHING CHARACTERISTICS OVER OPERATING RANGE Symbol tPLH tPHL tPLH tPHL tPZL tPZH tPHZ tPLZ tSU tH tW tSK(o) Parameter Propagation Delay xDx to xOx Propagation Delay xLE to xOx Output Enable Time Condition(1) CL = 50pF RL = 500Ω 74FCT162373AT Min.(2) Max. 1.5 5.2 74FCT162373CT Min.(2) Max. 1.5 4.2 74FCT162373ET Min.(2) Max. 1.5 3.4 Unit ns 2 8.5 2 5.5 1.5 3.7 ns 1.5 6.5 1.5 5.5 1.5 4.4 ns Output Disable Time 1.5 5.5 1.5 5 1.5 3.6 ns Set-up Time HIGH or LOW, xDx to xLE Hold Time HIGH or LOW, xDx to xLE xLE Pulse Width HIGH Output Skew(3) 2 1.5 5 — — — — 0.5 2 1.5 5 — — — — 0.5 1 1 3(4) — — — — 0.5 ns ns ns ns NOTES: 1. See test circuit and waveforms. 2. Minimum limits are guaranteed but not tested on Propagation Delays. 3. Skew between any two outputs of the same package switching in the same direction. This parameter is guaranteed by design. 4. This limit is guaranteed but not tested. 5 IDT74FCT162373AT/CT/ET FAST CMOS 16-BIT TRANSPARENT LATCH INDUSTRIAL TEMPERATURE RANGE TEST CIRCUITS AND WAVEFORMS V CC SWITCH POSITION 7.0V 500Ω V OUT VIN Pulse Generator 50pF Switch Closed All Other Tests Open DEFINITIONS: CL = Load capacitance: includes jig and probe capacitance. RT = Termination resistance: should be equal to ZOUT of the Pulse Generator. D.U.T. RT Test Open Drain Disable Low Enable Low 500Ω CL Test Circuits for All Outputs DATA INPUT tH tSU TIMING INPUT ASYNCHRONOUS CONTROL PRESET CLEAR ETC. SYNCHRONOUS CONTROL PRESET CLEAR CLOCK ENABLE ETC. tREM tSU 3V 1.5V 0V 3V 1.5V 0V LOW-HIGH-LOW PULSE 1.5V tW 3V 1.5V 0V HIGH-LOW-HIGH PULSE 1.5V 3V 1.5V 0V tH Pulse Width Set-up, Hold, and Release Times ENABLE SAME PHASE INPUT TRANSITION tPLH tPHL OUTPUT tPLH OPPOSITE PHASE INPUT TRANSITION tPHL 3V 1.5V 0V DISABLE 3V 1.5V CONTROL INPUT tPZL VOH 1.5V VOL OUTPUT NORMALLY LOW 3V 1.5V 0V OUTPUT NORMALLY HIGH Propagation Delay SWITCH CLOSED tPZH SWITCH OPEN 0V tPLZ 3.5V 3.5V 1.5V 0.3V VOL tPHZ 0.3V VOH 1.5V 0V 0V Enable and Disable Times NOTES: 1. Diagram shown for input Control Enable-LOW and input Control Disable-HIGH. 2. Pulse Generator for All Pulses: Rate ≤ 1.0MHz; tF ≤ 2.5ns; tR ≤ 2.5ns. 6 IDT74FCT162373AT/CT/ET FAST CMOS 16-BIT TRANSPARENT LATCH INDUSTRIAL TEMPERATURE RANGE ORDERING INFORMATION IDT XX FCT Temp. Range XXX Family XXXX Device Type XX Package PV PVG PA PAG Shrink Small Outline Package SSOP - Green Thin Shrink Small Outline Package TSSOP - Green 373AT 16-Bit Transparent Latch 373CT 373ET CORPORATE HEADQUARTERS 6024 Silver Creek Valley Road San Jose, CA 95138 162 Double-Density, 5 Volt, Balanced Drive 74 – 40°C to +85°C for SALES: 800-345-7015 or 408-284-8200 fax: 408-284-2775 www.idt.com 7 for Tech Support: [email protected]