SMSC FDC37N972

FDC37N972
ADVANCE INFORMATION
Advanced Notebook I/O Controller with Enhanced
Keyboard Control and System Management
FEATURES
!" 3.3V Operation With 5V Tolerant Buffers
!" ACPI 1.0 and PC99 Compliant
!" Three Power Planes
!" ACPI Embedded Controller Interface
!" Low Standby Current in Sleep Mode
!" Configuration Register Set Compatible With
ISA Plug-and-Play Standard (Version 1.0a)
!" Serial IRQ Interface Compatible With
Serialized IRQ Support for PCI Systems
!" Floppy Disk Interface on Parallel Port
!" 8051 Controller uses Parallel Port to
Reprogram the Flash ROM
!" Advanced Infrared Communications
Controller (IrCC 2.0)
- IrDA V1.1 (4Mbps), HPSIR, ASKIR,
Consumer IR Support
- Two IR Ports
- Relocatable Base I/O Address
!" 512k Byte Flash ROM Interface
- 8051/Host CPU Multiplexed Interface
- Sixteen 32K Pages - 8051 Keyboard
BIOS
- Eight 64K Pages - Host System BIOS
- Embedded Controller uses Parallel Port
to Reprogram Flash ROM
!" ISA Host Interface With Clock Run Support
and ACPI SCI Interface
- 16 Bit Address Qualification
- 8 Bit Data Bus
- Zero Wait-State I/O Register Access
- Shadowed Write Only registers
- IOCHRDY for ECP, IRCC 2.0 and Flash
Cycles
- 15 Direct IRQs Including nSMI
- Four 8 Bit DMA Channels
- XNOR Test Chain
!"High-Performance Embedded 8051
Keyboard and System Controller
- Provides System Power Management
- System Watch Dog Timer (WDT)
- 8042 Style Host Interface
- Asynchronous Access to Two Data
Registers and One Status Register
- Supports Interrupt and Polling Access
- 2K Internal ROM, nEA Pin Select
- 32K Bank Switchable External Flash
ROM Interface
- 256 Bytes Data RAM
- On-Chip Control Registers Available via
MOVX External Data Access Commands
- Access to RTC and CMOS Registers
- Up to 16x8 Keyboard Scan Matrix
- Three 16 Bit Timer/Counters
- Integrated TX/RX Serial Interface
- Eleven 8051 Interrupt Sources
- Thirty-Two 8 Bit, Host/8051 Mailbox
Registers
- Thirty Maskable Hardware Wake-Up
Events Supported
- Fast GATEA20
- Fast CPU_RESET
- Multiple Clock Sources and Frequencies
- IDLE and SLEEP Modes
- Fail-Safe Ring Oscillator
!"Real Time Clock
- MC146818 and DS1287 Compatible
- 256 Bytes of Battery Backed CMOS in
Two 128-Byte Banks
- 128 Bytes of CMOS RAM Lockable in
4x32 Byte Blocks
- 12 and 24 Hour Time Format
- Binary and BCD Format
-
100% IBM Compatibility
Detects All Overrun and Underrun
Conditions
- 12 mA Drivers and Schmitt Trigger Inputs
- DMA Enable Logic
- Data Rate and Drive Control Registers
!" Enhanced Digital Data Separator
- Low Cost Implementation
- No Filter Components Required
- 2 Mbps, 1 Mbps, 500 Kbps, 300 Kbps,
250 Kbps Data Rates
- Programmable Precompensation Modes
!"Multi-Mode Parallel Port with ChiProtect
- Standard Mode IBM PC/XT, PC/AT, and
PS/2 Compatible Bi-directional Parallel
Port
- Enhanced Parallel Port EPP 1.7 and EPP
1.9 Compatible (IEEE 1284 Compliant)
IEEE 1284 Compliant Enhanced
Capabilities Port (ECP)
- ChiProtect Circuitry to Prevent Printer
Power-On Damage
- Relocatable to 480 Different Base I/O
Addresses
- 15 IRQ Options
- 4 DMA Options
- Microsoft and HP compatible High Speed
Mode
- 12 mA Output Drivers
!" Serial Port
- High-Speed NS16550A-Compatible
UART with 16-Byte Send/Receive FIFOs
- Programmable Baud Rate Generator
Modem Control Circuitry Including 230k
and 460k Baud
- Relocatable to 480 Different Base I/O
Addresses
- 15 IRQ Options
!" 208 Pin TQFP Package Options
!" 208 Pin FBGA Package Options
- <2!A Standby Current (typ)
!" Two 8584-Style ACCESS.bus Controllers
!" Four independent Hardware Driven PS/2
Ports
!" General Purpose I/O
- 22 I/O Pins
- 12 Out Pins
- Eight In Pins
!" Two Programmable Pulse-Width Modulator
Outputs
- Independent Clock Rates
- 6 Bit Duty Cycle Granularity
- VCC1 and VCC2 operation mode
!" Intelligent Auto Power Management
!" 2.88MB Super I/O Floppy Disk Controller
- Relocatable to 480 Different Base I/O
Addresses
- 15 IRQ Options
- Four DMA Options
- Open-Drain/Push-Pull Configurable
Output Drivers
- Licensed CMOS 765B Floppy Disk
Controller
- Advanced Digital Data Separator
- Software and Register Compatible With
SMSC's Proprietary 82077AA Compatible
Core
- Low Power CMOS Design with
Sophisticated Power Control Circuitry
(PCC) Including Multiple Powerdown
Modes for Reduced Power Consumption
- Supports Two Floppy Drives on the FDD
Interface and Two Floppy Drives on the
Parallel Port Interface
- 12 mA FDD Interface Cable Drivers With
Schmitt Trigger Inputs
!" Licensed CMOS 765B Floppy Disk Controller
Core
- Supports Vertical Recording Format
- 16-Byte Data FIFO
2
GENERAL DESCRIPTION
8051 controller can also take control of the
parallel port interface to provide remote
diagnostics or “Flashing” of the Flash memory.
The FDC37N972 is a 208-pin 3.3V ISA Host
ACPI 1.0 and PC98 (/PC99)-compliant Ultra I/O
Controller with Fast Infrared for mobile
applications.
The FDC37N972 has three separate power
planes to provide “instant on” and system power
management functions.
Additionally, the
FDC37N972 incorporates sophisticated power
control circuitry (PCC).
The PCC supports
multiple low power down modes. Wake-up
events and ACPI-related functions are supported
through the SCI Interface.
The
FDC37N972
incorporates
a
highperformance 8051-based keyboard controller; a
512k byte Flash ROM interface; four PS/2 ports;
a real-time clock; SMSC's true CMOS 765B
floppy disk controller with advanced digital data
separator and 16-byte data FIFO; an
NS16C550A-compatible
UART,
SMSC’s
advanced Infrared Communications Controller
(IrCC 2.0) with a UART and a Synchronous
Communications Engine to provide IrDA v1.1
(Fast IR) capabilities; one Multi-Mode parallel
port with ChiProtect circuitry plus EPP and ECP
support; two 8584-style Access Bus controllers;
a Serial IRQ peripheral agent interface; an ACPI
Embedded
Controller
Interface;
General
Purpose
I/O
pins;
two
independently
programmable pulse width modulators; twofloppy direct drive support; and maskable
hardware wake-up events.
The FDC37N972’s configuration register set is
compatible with the ISA Plug-and-Play Standard
(Version 1.0a) and provides the functionality to
support Windows '95. Through internal
configuration
registers,
each
of
the
FDC37N972's logical device's I/O address, DMA
channel and IRQ channel may be programmed.
There are 480 I/O address location options, 15
IRQ options, and four DMA channel options for
each logical device.
The FDC37N972 does not require any external
filter components and is, therefore, easy to use
and offers lower system cost and reduced board
area. The FDC37N972 is software and register
compatible with SMSC's proprietary 82077AA
core.
The true CMOS 765B core provides 100%
compatibility with IBM PC/XT and PC/AT
architectures in addition to providing data
overflow and underflow protection. The SMSC
advanced digital data separator incorporates
SMSC's patented data separator technology,
allowing for ease of testing and use.
The parallel port is compatible with IBM PC/AT
architecture, as well as EPP and ECP. The
3
TABLE OF CONTENTS
FEATURES ....................................................................................................................................... 1
GENERAL DESCRIPTION ................................................................................................................ 3
PIN CONFIGURATION...................................................................................................................... 9
DESCRIPTION OF PIN FUNCTIONS .............................................................................................. 11
FUNCTIONAL DESCRIPTION......................................................................................................... 28
FLOPPY DISK CONTROLLER........................................................................................................ 30
FDC INTERNAL REGISTERS ...................................................................................................... 30
STATUS REGISTER ENCODING ................................................................................................ 44
FDC RESET................................................................................................................................. 46
FDC MODES OF OPERATION .................................................................................................... 47
DMA TRANSFERS....................................................................................................................... 47
CONTROLLER PHASES................................................................................................................. 47
FDC INSTRUCTION SET............................................................................................................. 53
FDC DATA TRANSFER COMMANDS .......................................................................................... 64
ACPI EMBEDDED CONTROLLER.................................................................................................. 82
ECI CONFIGURATION REGISTERS............................................................................................ 83
SERIAL PORT (UART).................................................................................................................... 86
FIFO INTERRUPT MODE OPERATION ....................................................................................... 97
FIFO POLLED MODE OPERATION ............................................................................................. 97
INFRARED COMMUNICATIONS CONTROLLER (IRCC 2.0) .........................................................102
OVERVIEW ................................................................................................................................103
IRRX/IRTX PIN ENABLE.............................................................................................................104
IR REGISTERS - LOGICAL DEVICE 5 ........................................................................................104
IR DMA CHANNELS ...................................................................................................................105
IR IRQS.......................................................................................................................................105
IR HALF DUPLEX TIMEOUT.......................................................................................................106
IRTX OUTPUT PINS DEFAULT...................................................................................................106
PARALLEL PORT .......................................................................................................................106
THE PARALLEL PORT PHYSICAL INTERFACE (PPPI)..............................................................128
PARALLEL PORT FDC INTERFACE...........................................................................................129
AUTO POWER MANAGEMENT.....................................................................................................131
SYSTEM POWER MANAGEMENT .............................................................................................131
DSR FROM POWERDOWN .......................................................................................................132
WAKE UP FROM AUTO POWERDOWN ....................................................................................132
REGISTER BEHAVIOR...............................................................................................................132
PIN BEHAVIOR...........................................................................................................................132
SYSTEM INTERFACE PINS........................................................................................................133
4
FDD INTERFACE PINS...............................................................................................................134
UART POWER MANAGEMENT ..................................................................................................135
PARALLEL PORT POWER MANAGEMENT................................................................................135
8051 EMBEDDED CONTROLLER .................................................................................................136
8051 FUNCTIONAL OVERVIEW.................................................................................................136
POWERING UP OR RESETTING THE 8051...............................................................................137
CPU RESET SEQUENCE ...........................................................................................................140
8051 CLOCK CONTROLS ..........................................................................................................142
8051 RING OSCILLATOR FAIL-SAFE CONTROLS ....................................................................144
8051 MEMORY MAP...................................................................................................................145
FLASH ROM INTERFACE...........................................................................................................152
8051 CONTROL REGISTERS.....................................................................................................153
8051 CONFIGURATION/CONTROL MEMORY MAPPED REGISTERS .........................................162
8051 INTERRUPTS.....................................................................................................................165
WATCH DOG TIMER .....................................................................................................................183
WDT OPERATION......................................................................................................................183
WDT ACTION .............................................................................................................................183
WDT ACTIVATION .....................................................................................................................183
WDT RESET MECHANISM.........................................................................................................183
WDT MEMORY MAPPED REGISTERS ......................................................................................184
SHARED FLASH INTERFACE .......................................................................................................185
FLASH INTERFACE DIAGRAM...................................................................................................185
SYSTEM MEMORY MAP ............................................................................................................186
KEYBOARD BIOS (KMEM) .........................................................................................................187
SYSTEM BIOS (HMEM) ..............................................................................................................189
HOST FLASH ACCESS ..............................................................................................................189
IDLE MODE ................................................................................................................................195
SLEEP MODE.............................................................................................................................197
WAKE-UP EVENTS ....................................................................................................................201
8042 STYLE HOST INTERFACE.................................................................................................204
KEYBOARD DATA WRITE..........................................................................................................204
8051- TO- HOST KEYBOARD COMMUNICATION ......................................................................205
HOST-TO 8051 KEYBOARD COMMUNICATION ........................................................................206
GATEA20 HARDWARE SPEED-UP ............................................................................................208
SMSC PS/2 LOGIC OVERVIEW .................................................................................................217
SMSC PS/2 MEMORY MAPPED CONTROL REGISTERS ..........................................................218
DEVIL LOGIC OVERVIEW..........................................................................................................225
THE DEVIL PS/2 LOGIC COMMANDS........................................................................................225
DEVIL PS/2 MEMORY MAPPED CONTROL REGISTERS ..........................................................227
5
ACCESS.BUS ................................................................................................................................233
BACKGROUND ..........................................................................................................................233
REGISTER DESCRIPTION .........................................................................................................234
ACCESS.BUS INTERFACE DESCRIPTION ................................................................................238
MEMORY MAPPED CONTROL REGISTERS..............................................................................239
SECOND I2C BUS INTERFACE .....................................................................................................241
MEMORY MAPPED CONTROL REGISTERS..............................................................................241
I2C CLOCK DIVIDER BIT ............................................................................................................243
OVERVIEW ................................................................................................................................244
MAILBOX REGISTERS INTERFACE BASE ADDRESS ...............................................................246
MAILBOX REGISTERS ...............................................................................................................247
THE SYSTEM/8051 INTERFACE REGISTERS` ..........................................................................247
LED CONTROLS ........................................................................................................................249
PULSE WIDTH MODULATORS ..................................................................................................250
OPERATION REGISTERS ..........................................................................................................257
GENERAL PURPOSE I/O (GPIO) ..................................................................................................260
OVERVIEW ................................................................................................................................266
MULTIPLEXING_1 REGISTER ...................................................................................................266
MULTIPLEXING_2 REGISTER ...................................................................................................270
MULTIPLEXING_3 REGISTER ...................................................................................................272
ACPI PM1 BLOCK .........................................................................................................................276
ACPI PM1 BLOCK OVERVIEW...................................................................................................276
ACPI PM1 BLOCK SCI EVENT-GENERATING FUNCTIONS ......................................................276
ACPI PM1 BLOCK BASE ADDRESS...........................................................................................277
ACPI PM1 BLOCK ......................................................................................................................278
REGISTERS ...............................................................................................................................278
REAL TIME CLOCK.......................................................................................................................283
GENERAL DESCRIPTION ..........................................................................................................283
CONFIGURATION REGISTERS .................................................................................................283
ISA HOST I/O INTERFACE.........................................................................................................284
INTERNAL REGISTERS .............................................................................................................285
TIME CALENDAR AND ALARM ..................................................................................................286
UPDATE CYCLE.........................................................................................................................287
CONTROL AND STATUS REGISTERS.......................................................................................288
INTERRUPTS .............................................................................................................................292
FREQUENCY DIVIDER...............................................................................................................292
32KHZ CLOCK INPUT .................................................................................................................295
POWER MANAGEMENT ............................................................................................................295
6
PCI CLOCK RUN SUPPORT..........................................................................................................295
OVERVIEW ................................................................................................................................295
SERIAL INTERRUPTS ...................................................................................................................298
SERIRQ MODE BIT FUNCTION .................................................................................................299
FDC37N972 CONFIGURATION ....................................................................................................303
OVERVIEW ................................................................................................................................303
CONFIGURATION REGISTER ACCESS.....................................................................................303
CHIP LEVEL (GLOBAL) CONTROL/CONFIGURATION REGISTERS [0X00-0X2F] .....................308
LOGICAL DEVICE CONFIGURATION/CONTROL REGISTERS [0X30-0XFF] .............................311
I/O BASE ADDRESS CONFIGURATION REGISTER DESCRIPTION..........................................313
INTERRUPT SELECT CONFIGURATION REGISTER DESCRIPTION ........................................315
DMA CHANNEL SELECT CONFIGURATION REGISTER DESCRIPTION ...................................316
IRQ AND DMA ENABLE AND DISABLE ......................................................................................317
SMSC DEFINED LOGICAL DEVICE CONFIGURATION REGISTERS.........................................318
ELECTRICAL SPECIFICATIONS ...................................................................................................327
MAXIMUM GUARANTEED RATINGS* ........................................................................................327
DC SPECIFICATIONS ................................................................................................................328
AC SPECIFICATIONS.................................................................................................................332
TIMING DIAGRAMS ......................................................................................................................333
LOAD CAPACITANCE ................................................................................................................333
FAST GATEA20 IOW TIMING.....................................................................................................334
ISA IO WRITE ............................................................................................................................335
ISA IO READ CYCLE ..................................................................................................................336
DMA TIMING (BURST TRANSFER MODE).................................................................................340
FLOPPY DISK DRIVE TIMING (AT MODE) .................................................................................341
SERIAL PORT TIMING ...............................................................................................................342
PARALLEL PORT TIMING ..........................................................................................................343
EPP 1.9 DATA OR ADDRESS WRITE CYCLE ............................................................................344
EPP 1.9 DATA OR ADDRESS READ CYCLE..............................................................................346
EPP 1.7 DATA OR ADDRESS WRITE CYCLE ............................................................................348
EPP 1.7 DATA OR ADDRESS READ CYCLE..............................................................................350
ECP PARALLEL PORT TIMING ..................................................................................................351
ACCESS.BUS TIMING ................................................................................................................355
HOST FLASH READ TIMING ......................................................................................................356
HOST FLASH READ/WRITE.......................................................................................................358
ZERO WAIT STATE (NOWS) TIMING ........................................................................................360
FLASH PROGRAM FETCH TIMING............................................................................................361
8051 FLASH READ TIMING........................................................................................................362
8051 FLASH WRITE TIMING ......................................................................................................363
7
EPP 1.7 DATA OR ADDRESS READ CYCLE.............................................................................353
ECP PARALLEL PORT TIMING..................................................................................................354
ACCESS.BUS TIMING..................................................................................................................358
HOST FLASH READ TIMING......................................................................................................359
HOST FLASH READ/WRITE .......................................................................................................361
ZERO WAIT STATE (NOWS) TIMING.......................................................................................363
FLASH PROGRAM FETCH TIMING...........................................................................................364
8051 FLASH READ TIMING ........................................................................................................365
8051 FLASH WRITE TIMING ......................................................................................................366
PS/2 CHANNEL RECEIVE TIMING DIAGRAM ........................................................................367
PS/2 CHANNEL TRANSMIT TIMING DIAGRAM.....................................................................369
PS/2 CHANNEL “BIT-BANG” TIMING ......................................................................................371
IN CIRCUIT TEST (ICT)
................................................................................................................ 373
APPENDIX A................................................................................................................................... 377
HIGH-PERFORMANCE 8051 CYCLE TIMING AND INSTRUCTION SET.............................377
APPENDIX B................................................................................................................................... 382
HIGH PERFORMANCE 8051 EXTENDED INTERRUPT UNIT................................................382
8
PIN CONFIGURATION
24MHz_OUT
nEC_SCI
VSS
32kHz_OUT
VCC1_PWRGD
nPWR_LED
PWRGD
SLCT
PE
BUSY
nACK
PD7
PD6
PD5
PD4
VCC2
PD3
PD2
PD1
PD0
nSLCTIN
nINIT
nERROR
nALF
nSTROBE
RXD
TXD
VSS
nDSR
nRTS
nCTS
nDTR
nDCD
nRI
GPIO15
GPIO14
GPIO8
GPIO9
VCC1
FA18
GPIO10
GPIO11
GPIO12
IN0
IN1
IN2
IN3
IN4
IN5
IN6
IN7
VCC0
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
FDC37N972
208 PIN TQFP
104
103
102
101
100
99
98
97
96
95
94
93
92
91
90
89
88
87
86
85
84
83
82
81
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
VCC2
CLOCKI
nRESET_OUT
SER_IRQ
nCLKRUN
PCI_CLK
nMEMWR
nMEMRD
nROMCS
IOCHRDY
TC
DRQ1
nDACK1
DRQ0
nDACK0
VSS
SD7
SD6
SD5
SD4
SD3
VCC2
SD2
SD1
SD0
AEN
nIOW
nIOR
nNOWS
OUT4
OUT3
VSS
OUT2
nIRQ8
OUT0
SA15
SA14
SA13
SA12
SA11
SA10
SA9
SA8
SA7
SA6
SA5
SA4
SA3
SA2
SA1
SA0
EMDAT
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
181
182
183
184
185
186
187
188
189
190
191
192
193
194
195
196
197
198
199
200
201
202
203
204
205
206
207
208
VSS
OUT5
OUT6
DRVDEN0
DRVDEN1
nMTR0
VSS
nDS0
nDIR
nSTEP
nWDATA
nWGATE
nHDSEL
nINDEX
nTRK0
nWRTPRT
nRDATA
nDSKCHG
FPD
IRTX
IRRX
KSO13
KSO12
KSO11
KSO10
KSO9
KSO8
KSO7
VCC1
KSO6
KSO5
KSO4
KSO3
KSO2
KSO1
KSO0
KSI7
KSI6
KSI5
KSI4
KSI3
KSI2
KSI1
KSI0
GPIO20
GPIO21
IMCLK
IMDAT
VSS
KCLK
KDAT
EMCLK
XOSEL
XTAL1
XTAL2
AGND
FAD0
FAD1
FAD2
FAD3
FAD4
FAD5
VSS
FAD6
FAD7
FA8
FA9
FA10
FA11
FA12
FA13
VCC1
FA14
FA15
FA16
FA17
FALE
nFRD
nFWR
nFCS
GPIO1
GPIO2
GPIO3
GPIO4
GPIO5
GPIO6
GPIO7
VSS
nEA
MODE
AB1_DATA
AB1_CLK
nBAT_LED
nFDD_LED
OUT11
OUT10
OUT9
OUT8
OUT7
GPIO16
VCC2
GPIO17
GPIO18
GPIO19
FIGURE 1 - FDC37N972 PIN CONFIGURATION
For FBGA BALL PAD Configuration refer to FIGURE 81 on Page 372.
9
nIOR
nIOW
nMEMRD
nMEMWR
nROMCS
AEN
SA[0:15]
SD[0:7]
DRQ[0:1]
DRQ[2:3]*
nDACK[0:1]
TC
nDACK[2:3]*
nNOWS
IOCHRDY
nIRQ8*
nSMI*
SER_IRQ
nCLKRUN
PCI_CLK
MODE
nEA
VCC1_PWRGD
PWRGD
32KHz_OUT
24MHz_OUT
CLOCKI
(14.318 MHz)
HOST
CPU
INTERFACE
TXD, nRTS, nDTR
16C550
COMPATIBLE
SERIAL PORT 1
RXD, nCTS, nDSR, nDCD
nRI
nDSKCHG, nWRTPRT,
nTRK0, nINDEX, FPD, nTRK0
nWGATE, nHDSEL, nDIR,
nSTEP, nDS0, nDS1*, nMTR0,
nMTR1*, DRVDEN0, DRVDEN1*,
FPD
POWER
MANAGEMENT
CONFIGURATION REGISTERS
IRRX*
IRRX2
IRMODE / IRRX3A, IRMODE / IRRX3B
IRTX*
IRTX2
INFRARED
PD[0:7]
MULTI-MODE
PARALLEL
PORT / FDC
MUX
BUSY, SLCT, PE, nERROR, nACK
nSLCTIN, nINIT, nALF, nSTROBE
IN
GENERAL
OUT
PURPOSE I/O
I/O
INTERFACE
I/O
INTERRUPTS
CONTROL
INPUTS
PLL CLOCK
GENERATOR
XTAL2
2 x 128 BYTE
BANKS OF
CMOS RAM
BANK
1
LED
DRIVER
CONTROL, ADDRESS, DATA
nEC_SCI
XOSEL
AGND
nRDATA
SMSC
PROPRIETARY
82077 COMPATIBLE
VERTICAL FLOPPY DISK
CONTROLLER CORE
RTC
XTAL1
VCC0
MDATA
SYSTEM
RESET
RDATA
nRESET_OUT
nWDATA
RCLOCK
VCC1(3)
VCC2(4)
VSS(9)
MCLOCK
DIGITAL DATA
SEPARATOR
WITH WRITE
PRECOMPENSATION
8051
MAILBOX
REGISTERS
256B Direct
RAM
8051
SUB-BLOCK
EXTERNAL
CONTROL
REGISTERS
ACPI
EMBEDDED
CONTROLLER
PM1
BLOCK
256B
EXTERNAL
8051 RAM
Ring
Oscillator
w/ FAIL SAFE
16 x 8
KEYBOARD
INTERFACE
PS/2
PORTS
GPIO 0-15
nBAT_LED, nPWR_LED, nFDD_LED
KSI[0:7]
KS0[0:13], KS0[14:15]*
KCLK, EMCLK, IMCLK, PS2CLK
KDAT, EMDAT, IMDAT, PS2DAT
ACCESS
BUS2
AB2_DATA *, AB2_CLK *
VCC2 POWERED
* -- ALTERNATE FUNCITON
VCC1 POWERED
FIGURE 2 - FDC37N972 BLOCK DIAGRAM
10
GPIO 16-21
AB_DATA, AB_CLK
FLASH
INTERFACE
BANK
2
OUT0-11
ACCESS
BUS
PWM
WDT
IN0-7
PWM0*, PWM1*
FAD[0:7]
FA[8:18], nFRD, nFWR, FALE
nFCS
FDC37N97x
(TIKKI)
DESCRIPTION OF PIN FUNCTIONS
TABLE 1 - FDC37N972 PIN CONFIGURATION
TQFP
PIN#
FGBA
PIN#
TQFP
PIN#
FGBA
PIN#
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
A1
C2
D4
B1
C1
D2
D3
E4
D1
E2
E3
F4
E1
F2
F3
G4
F1
G2
VSS
OUT5
OUT6
DRVDEN0
DRVDEN1
nMTR0
VSS
nDS0
nDIR
nSTEP
nWDATA
nWGATE
nHDSEL
nINDEX
nTRK0
nWRTPRT
nRDATA
nDSKCHG
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
M3
N4
M1
N2
N3
N1
P1
P2
P3
R1
T1
R2
R3
T2
U1
T3
P4
U2
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
G3
H4
G1
H2
H3
J4
H1
J2
J3
K4
J1
K2
K3
L4
K1
FPD
IRTX
IRRX
KSO13
KSO12
KSO11
KSO10
KSO9
KSO8
KSO7
VCC1
KSO6
KSO5
KSO4
KSO3
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
34
35
36
37
L2
L3
M4
L1
KSO2
KSO1
KSO0
KSI7
38
M2
KSI6
NAME
TQFP
PIN#
FGBA
PIN#
KSI5
KSI4
KSI3
KSI2
KSI1
KSI0
GPIO20
GPIO21
IMCLK
IMDAT
VSS
KCLK
KDAT
EMCLK
EMDAT
SA0
SA1
SA2
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
U8
T9
R9
P10
U9
T10
R10
P11
U10
T11
R11
P12
U11
T12
R12
P13
U12
T13
nIOR
nIOW
AEN
SD0
SD1
SD2
VCC2
SD3
SD4
SD5
SD6
SD7
VSS
nDACK0
DRQ0
nDACK1
DRQ1
TC
U3
T4
R4
P5
U4
T5
R5
P6
U5
T6
R6
P7
U6
T7
R7
SA3
SA4
SA5
SA6
SA7
SA8
SA9
SA10
SA11
SA12
SA13
SA14
SA15
OUT0
OUT1
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
R13
U13
U14
T14
R14
U15
U16
T15
R15
T16
U17
R16
P14
T17
R17
72
73
74
75
P8
U7
T8
R8
OUT2
VSS
OUT3
OUT4
110
111
112
113
P16
P15
N14
P17
IOCHRDY
nROMCS
nMEMRD
nMEMWR
PCI_CLK
nCLKRUN
SER_IRQ
nRESET_OUT
CLOCKI
VCC2
24MHz_OUT
nEC_SCI
VSS
32kHz_OUT
VCC1_
PWRGD
nPWR_LED
PWRGD
SLCT
PE
76
P9
11
nNOWS
114
N16
BUSY
NAME
NAME
TQFP
PIN#
FGBA
PIN#
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
N15
M14
N17
M16
M15
L14
M17
L16
L15
K14
L17
K16
K15
J14
K17
J16
J15
H14
J17
H16
H15
G14
H17
G16
G15
F14
G17
F16
F15
E14
F17
E16
NAME
nACK
PD7
PD6
PD5
PD4
VCC2
PD3
PD2
PD1
PD0
NSLCTIN
nINIT
nERROR
nALF
nSTROBE
RXD
TXD
VSS
nDSR
nRTS
nCTS
nDTR
nDCD
nRI
GPIO15
GPIO14
GPIO8
GPIO9
VCC1
FA18
GPIO10
GPIO11
VCC2
TQFP
PIN#
FGBA
PIN#
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
E15
E17
D17
D16
D15
C17
B17
C16
C15
B16
A17
B15
D14
A16
A15
B14
C14
D13
A14
B13
C13
D12
A13
B12
C12
D11
A12
B11
C11
D10
A11
B10
VCC1
12
NAME
GPIO12
IN0
IN1
IN2
IN3
IN4
IN5
IN6
IN7
VCC0
XOSEL
XTAL1
XTAL2
AGND
FAD0
FAD1
FAD2
FAD3
FAD4
FAD5
VSS
FAD6
FAD7
FA8
FA9
FA10
FA11
FA12
FA13
VCC1
FA14
FA15
TQFP
PIN#
FGBA
PIN#
179
180
181
182
183
184
185
186
187
188
189
190
191
192
193
194
195
196
197
198
199
200
201
202
203
204
205
206
207
208
C10
D9
A10
B9
C9
D8
A9
B8
C8
D7
A8
B7
C7
D6
A7
B6
C6
D5
A6
B5
C5
A5
A4
B4
C4
A3
A2
B3
C3
B2
VCC0
NAME
FA16
FA17
FALE
nFRD
nFWR
nFCS
GPIO1
GPIO2
GPIO3
GPIO4
GPIO5
GPIO6
GPIO7
VSS
nEA
MODE
AB1_DATA
AB1_CLK
nBAT_LED
nFDD_LED
OUT11
OUT10
OUT9
OUT8
OUT7
GPIO16
VCC2
GPIO17
GPIO18
GPIO19
The pins and descriptions in Table 2 are
organized by primary pin function. For example,
the PS2 Serial Clock and PS2 Serial Data pins
are technically part of the KEYBOARD AND
MOUSE INTERFACE but are listed in the
GENERAL PURPOSE I/O INTERFACE because
the GPIO function of these pins is the default.
Device functions per pin are shown in TABLE 2.
Buffer Modes symbols in TABLE 2 are described
in Table 3. Multifunction pins are summarized
in Table 4, including a multiplex controls
reference.
TABLE 2 - PIN FUNCTION DESCRIPTION
TQFP
POWER
BUFFER
PIN#
NOTES
NAME
DESCRIPTION
PLANE
MODES2
FDD INTERFACE (15)
The following FDC output pins can be configured as either Open Drain outputs capable of sinking 12mA
(OD12) or as push-pull outputs capable of driving 6mA and sinking 12mA (O12). The FDC output pins
must tristate when the FDC is in powerdown mode (The board designer must provide external pull-up
resistors on these output pins).
4
DRVDEN0
Drive Density Select 0
VCC2
(O12/OD12)
5
DRVDEN1
Drive Density Select 1
VCC2
(O12/OD12)
6
nMTR0
Motor On 0
VCC2
(O12/OD12)
8
nDS0
Drive Select 0
VCC2
(O12/OD12)
9
nDIR
Step Direction
VCC2
(O12/OD12)
10
nSTEP
Step Pulse
VCC2
(O12/OD12)
11
nWDATA
Write Disk Data
VCC2
(O12/OD12)
12
nWGATE
Write Gate
VCC2
(O12/OD12)
13
nHDSEL
Head Select
VCC2
(O12/OD12)
14
nINDEX
Index Pulse Input
VCC2
IS
15
nTRK0
Track 0
VCC2
IS
16
nWRTPRT
Write Protected
VCC2
IS
17
nRDATA
Read Disk Data
VCC2
IS
18
nDSKCHG
Disk Change
VCC2
IS
19
FPD
Floppy Power Down Output Control
VCC2
O8
PCI POWER MANAGEMENT AND SIRQ INTERFACE (4)
106
7
nEC_SCI
Power Management Event
VCC1
PCI_OD
99
PCI_CLK
PCI Clock
VCC2
PCI_ICLK
101
SER_IRQ
Serial IRQ
VCC2
PCI_IO
100
nCLKRUN
PCI Clock Control
VCC2
PCI_OD
ISA HOST INTERFACE (37)
80: 82,
SD[7:0]
System Data Bus
VCC2
IO12
84: 88
54: 69
SA[15:0]
System Address Bus
VCC2
I
96
nROMCS
ROM Chip Select
VCC2
I
79
AEN
Address Enable
VCC2
I
95
IOCHRDY
I/O Channel Ready
VCC2
OD12
91, 93
DRQ[1:0]
DMA Requests
VCC2
O12
13
TQFP
PIN#
NOTES
NAME
DESCRIPTION
90, 92
NDACK[1:0]
DMA Acknowledge
94
TC
Terminal Count
77
nIOR
I/O Read
78
nIOW
I/O Write
97
nMEMRD
Memory Read
98
nMEMWR
Memory Write
76
nNOWS
No Wait State
FLASH ROM INTERFACE (23)
FAD[7:0]
Flash Address/Data[7:0] Bus
161:
166,
168,
169
FA[8:17]
Flash Address[17:8]
170:
175,
NOTE: Upper Address bit FA18 is
177:
multiplexed on GPIO13
180
Flash Address 18
144
5
FA18/
General Purpose I/O
GPIO13
(WK_SE17)
182
nFRD
Flash Memory Read
183
nFWR
Flash Memory Write
181
FALE
Flash Address Latch Enable
184
5
nFCS/
Flash ROM Chip Select
GPIO0
General Purpose I/O
(WK_SE02)
KEYBOARD AND MOUSE INTERFACE (29)
30: 36,
KSO[0:11]
Keyboard Scan Outputs (14 × 8).
24:
NOTE: GPIO4 and GPIO5 can be
28
configured as KSO14 and KSO15
(16 × 8).
23
3
KSO12/
Keyboard Scan Output
OUT8/
General Purpose Output
KBRST
CPU_RESET
22
11
KSO13/
Keyboard Scan Output
GPIO18
General Purpose I/O
37:44
KSI[0:7]
Keyboard Scan Inputs
193
nEA
External Access for 2k ROM
52
EMCLK
EM Serial Clock
53
EMDAT
EM Serial Data
47
IMCLK
IM Serial Clock
48
IMDAT
IM Serial Data
51
KDAT
Keyboard Data
14
POWER
PLANE
VCC2
VCC2
VCC2
VCC2
VCC2
VCC2
VCC2
BUFFER
MODES2
I
I
I
I
I
I
OD12
VCC1
IO8
VCC1
O8
VCC1
O8/IO8
VCC1
VCC1
VCC1
VCC1
O8
O8
O8
O8/IO8
VCC1
OD4
VCC1
OD4/OD4/
OD4
VCC1
OD4/IOD4
VCC1
VCC1
VCC2
VCC2
VCC2
VCC2
VCC2
ISP
I
IOD16
IOD16
IOD16
IOD16
IOD16
TQFP
PIN#
NOTES
NAME
DESCRIPTION
50
KCLK
Keyboard Clock
GENERAL PURPOSE I/O INTERFACE (40)
70
7,8
OUT0 (SCI)
General Purpose Output (SCI)
71
3
OUT1/
General Purpose Output/
nIRQ8
Active Low RTC IRQ
72
OUT2
General Purpose Output
74
OUT3/
General Purpose Output
FRW
Inverted Flash ROM Memory Write
75
OUT4
General Purpose Output
General Purpose Output
2
3
OUT5/
FDD Drive Select 13
nDS1/
KBRST
CPU_RESET3
3
3
OUT6/
General Purpose Output
nMTR1
FDD Motor On 1
203
3
OUT7/
General Purpose Output
nSMI
SMI Output
General Purpose Output
202
3
OUT8/
DMA Request
DRQ2/
CPU_RESET
KBRST
201
3
OUT9/
General Purpose Output
DRQ3
DMA Request
200
OUT10/
General Purpose Output
PWM0
Pulse Width Modulator Output
199
OUT11/
General Purpose Output
PWM1
Pulse Width Modulator Output
148
4
IN0
General Purpose Input
(WK_EE4)
149
4
IN1
General Purpose Input
(WK_EE2)
150
4
IN2
General Purpose Input
(WK_EE3)
151
IN3
General Purpose Input (General
(nGPWKUP)
Purpose Wake Up)
152
5
IN4
General Purpose Input
(WK_SE00)
153
5
IN5
General Purpose Input
(WK_SE01)
154
5
IN6
General Purpose Input
(WK_SE05)
155
4
IN7
General Purpose Input
(WK_EE1)
185
5
GPIO1
General Purpose I/O
(WK_SE03)
15
POWER
PLANE
VCC2
BUFFER
MODES2
IOD16
VCC1
VCC1
(O12/OD12)
O12/O12
VCC1
VCC1
O12
O12/O12
VCC1
VCC1
O12
O12/(O12/
OD12)/O12
VCC1
O12/(O12/
OD12)
O12/OD12
VCC1
VCC1
O12/O12/
O12
VCC1
O12/O12
VCC1
O12/O12
VCC1
O12/O12
VCC1
I
VCC1
I
VCC1
I
VCC1
I
VCC1
I
VCC1
I
VCC1
I
VCC1
I
VCC1
IO8
TQFP
PIN#
186
NOTES
5
187
6
188
5
189
5
190
5
191
5, 8
141
5
142
1,
5
145
5
146
5
147
5
140
5
139
5
204
5
206
3,
5
NAME
GPIO2
(WK_SE04)
GPIO3
(TRIGGER)
GPIO4
(WK_SE07)/
KSO14
GPIO5
(WK_SE10)/
KSO15
GPIO6
(WK_SE11)/
IRMODE/IRR
X3A
GPIO7
(WK_SE06)5
GPIO8
(WK_SE12)/
IRRX2
GPIO9
(WK_SE13)/
IRTX2
GPIO10
(WK_SE14)/
IRMODE/IRR
X3B
GPIO11
(WK_SE15)/
AB2_DATA
GPIO12
(WK_SE16)/
AB2_CLK
GPIO14
(WK_SE20)
GPIO15
(WK_SE21)
GPIO16
(WK_SE22)5
GPIO17
(WK_SE23)/
GATEA20
POWER
PLANE
VCC1
BUFFER
MODES2
IO8
General Purpose I/O (Interrupt 1
Event)
General Purpose I/O
Keyboard Scan Output
VCC1
IO8
VCC1
IO8/OD8
General Purpose I/O
Keyboard Scan Output
VCC1
IO8/OD8
General Purpose I/O
FIR Mode Output or 2nd Receive
Input
VCC1
IO8/(O8/I)
General Purpose I/O
VCC1
(IO8/IOD8)8
General Purpose I/O
IR Receive Input
VCC1
IO8/I
General Purpose I/O
IR Transmit Output
VCC1
IO12/O12
General Purpose I/O
FIR Mode Output or 2nd Receive
Input
VCC1
IO8/O8/
(O8/I)
General Purpose I/O
ACCESS.bus 2 Serial Data
VCC1
IO12/IOD12
General Purpose I/O
ACCESS.bus 2 Clock
VCC1
IO12/IOD12
General Purpose I/O
VCC1
IO8
General Purpose I/O
VCC1
IO8
General Purpose I/O
VCC1
IO8
General Purpose I/O
KBD GATEA20 Output
VCC1
IO8/O8
DESCRIPTION
General Purpose I/O
16
TQFP
PIN#
207
NOTES
5
NAME
GPIO18
(WK_SE27)/
nDACK2
208
5
GPIO19
(WK_SE24)/
nDACK3
45
3,
GPIO20
5
(WK_SE25)/
PS2CLK/
8051RX/
46
3,5
GPIO21
(WK_SE26)/
PS2DAT/
8051TX
INFRARED INTERFACE (2)
21
IRRX
20
1
IRTX
PARALLEL PORT INTERFACE (17)
126
nINIT/
nDIR
125
nSLCTIN/
nSTEP
124
PD0/
nINDEX
123
PD1/
nTRK0
122
PD2/
nWRTPRT
121
PD3/
nRDATA
119
PD4/
nDSKCHG
118
PD5
117
PD6/
nMTR0
116
PD7
112
SLCT/
nWGATE
113
PE/
nWDATA
114
BUSY/
nMTR1
POWER
PLANE
VCC1
BUFFER
MODES2
IO8/I
General Purpose I/O/
DMA Acknowledge
VCC1
IO8/I
General Purpose I/O
PS2 Serial Clock
8051 RX Input
VCC1
IOD16/
IOD16/I
General Purpose I/O
PS2 Serial Data
8051 TX Input
VCC1
IOD16/
IOD16/
OD16
IR Receive Input
IR Transmit Output
VCC1
VCC2
I
O12
Initiate Output
FDC Direction Control
Printer Select Input
FDC Step Pulse
Port Data 0
FDC Index
Port Data 1
FDC Track 0
Port Data 2
FDC Write Protected
Port Data 3
FDC Read Disk Data
Port Data 4
FDC Disk Change
Port Data 5
Port Data 6
FDC Motor On 0
Port Data 7
Printer Selected Status
FDC Write Gate
Paper End
FDC Write Data
Busy
FDC Motor On 1
VCC2
VCC2
(OD14/
OP14)/OD14
(OD14/
OP14)/OD14
IOP14/I
VCC2
IOP14/I
VCC2
IOP14/I
VCC2
IOP14/I
VCC2
IOP14/I
VCC2
VCC2
IOP14
IOP14/OD14
VCC2
VCC2
IOP14
I/OD12
VCC2
I/OD12
VCC2
I/OD12
DESCRIPTION
General Purpose I/O/
DMA Acknowledge
17
VCC2
TQFP
PIN#
115
NOTES
NAME
nACK/
nDS1
127
nERROR/
nHDSEL
128
nALF/
DRVDEN0
129
nSTROBE/
nDS0
SERIAL PORT INTERFACE (8)
130
RXD
131
TXD
133
nDSR
134
nRTS
135
nCTS
136
nDTR
138
nRI
137
nDCD
MISCELLANEOUS (11)
108
32kHz_OUT
105
24MHz_OUT
103
194
CLOCKI
MODE
157
10
XOSEL
DESCRIPTION
Acknowledge
FDC Drive Select 1
Error
FDC Head Select
Autofeed Output
FDC Density Select 0
Strobe Output
FDC Drive Select 0
POWER
PLANE
VCC2
BUFFER
MODES2
I/OD12
VCC2
I/OD12
VCC2
(OD14/OP14)/
OD14
(OD14/OP14)/
OD14
VCC2
Receive Data
Transmit Data
Data Set Ready
Request to Send
Clear to Send
Data Terminal Ready
Ring Indicator
Data Carrier Detect
VCC2
VCC2
VCC2
VCC2
VCC2
VCC2
VCC1
VCC2
I
O12
I
O8
I
O8
I
I
32.768kHz Output Clock --The 32
KHz output is enabled / disabled by
setting / clearing bit-0 of the Output
Enable 8051 memory mapped
register. When disabled the 32
KHz_OUT pin is driven low. The 32
KHz_OUT pin defaults to the
disabled state on VCC1 POR.
24MHz Clock Output
Programmable Clock Output.
1.8432 MHz (default = 24 MHz/13)
14.318 MHz
16 MHz
24 MHz
48 MHz
14.318MHz Clock Input
Configuration Ports Base Address
Select
External 32kHz Clock Enable Input
VCC1
O8
VCC2
O24
VCC2
VCC1
ICLK
I
VCC0
I
18
TQFP
PIN#
109
102
197
110
198
NOTES
9
NAME
VCC1_PWR
GD
nRESET_OUT
nBAT_LED
nPWR_LED
nFDD_LED
111
9
PWRGD
ACCESS BUS INTERFACE (2)
195
AB1_DATA
196
AB1_CLK
REAL TIME CLOCK INTERFACE (2)
158
XTAL1
159
10
XTAL2
POWER PLANES
156
VCC0
29,
VCC1
143,
176,
83,
VCC2
104,
120,
205
160
AGND
1,7,49,
VSS
73, 89,
107,
132,
167,
192
POWER
PLANE
VCC1
BUFFER
MODES2
IP
VCC2
VCC1
VCC1
VCC1
O8
OD12
OD12
OD12
VCC1
I
ACCESS.bus 1 Serial Data
ACCESS.bus 1 Clock
VCC1
VCC1
IOD12
IOD12
32.768kHz Crystal Input
32.768kHz Crystal Output
VCC0
VCC0
ICLK2
(OCLK2/I)
DESCRIPTION
VCC1 Power Good Input. The
trailing edge of VCC1 POR is
released 20ms from the assertion of
this pin. If this pin is pulled low
while VCC1 is valid, then VCC1
POR will be asserted and held until
20ms from re-assertion of this pin.
This pin has an internal weak
(90µA) pull-up to VCC1.
System Reset
Battery LED (0 = ON)
Power LED (0 = ON)
Floppy LED (0 = ON). This pin is
asserted whenever either DRVSEL1
or DRVSEL0 is asserted or
controlled by the 8051.
VCC2 Power Good Input
RTC (VBAT) Supply Voltage
+3.3V ± 5% Main Battery Supply
+3.3V ± 5% Switched AC/Main
Battery Supply
Analog Ground
Digital Ground
19
NOTE 1:
NOTE 2:
NOTE 3:
NOTE 4:
NOTE 5:
NOTE 6:
NOTE 7:
NOTE 8:
NOTE 9:
NOTE 10:
These pins default to “output”, “low” to prevent infrared transceiver damage (see
Section IRTX Output Pins DEFAULT).
Buffer Modes per function on multiplexed pins are separated by a slash “/”; e.g., a
pin with two multiplexed functions where the primary function is an input and the
secondary function is an 8mA bidirectional driver is represented as “I/IO8”. Buffer
Modes in parenthesis represent multiple buffer modes for a single pin function.
This pin is tristated when PWRGD is inactive and the pin is configured as a VCC2powered alternate function.
These devices can generate wake-up events on either edge of the signal that is
applied when the pin is configured as an input. The interrupts are masked by the
Wake-up Mask Register bits.
These devices can generate wake-up events on selectable edges of the signal that is
applied when the pin is configured as an input. The interrupts are masked by the
Wake-up Mask Registers and selected edges are programmed via the Edge Select
registers (see section 8051 Internal PARALLEL on page 170).
This interrupt is masked by INT1 Mask Register bit 3. GPIO3 is the only GPIO pin
which does not generate a wakeup event.
The nEC_SCI pin can be controlled by hardware and 8051 software. The nEC_SCI
pin can drive either the ACPI Run-time GPE Chipset input or the Wake GPE Chipset
input (FIGURE 7). Depending how the nEC_SCI pin is used, other ACPI-related SCI
functions may be best supplied by FDC37N972 general purpose output OUT0.
OUT0 and GPIO7 are suitable as an SCI output pin because the buffer type can be
configured as a push-pull or open-drain output (see a description of the MISC21 and
MISC23 bits in Multiplexing_3 Register on page 278).
Input levels for the PWRGD and VCC1_PWRGD pins are rail-to-rail ±400mV; e.g.,
PWRGD VIL = .4V max, PWRGD VIH = 2.7V min. @ VCC1 min.
The function of these pins are described in Section 32kHz Clock Input
The FDC37N972 uses the XOSEL pin to select either a 32.768kHz input clock or a
32.768kHz crystal to drive the Real Time Clock Interface (Table 2 - PIN FUNCTION
DESCRIPTION).
When XOSEL = ‘0’, the RTC uses a 32.768kHz crystal connected between the
XTAL1 and XTAL2 pins. When XOSEL = ‘1’, the RTC is driven by a 32.768kHz
single-ended clock source connected to THE XTAL2 PIN.
NOTE 11:
NOTE: ICC0 ≥ 10µA for time-keeping operations under VCC0 using a single-ended
clock source. ICC1 = 30µA under VCC1 using a single-ended clock source.
The GPIO18 alternate function of the KS013 pin has no wake-up capability (see note
following).
20
BUFFER SYMBOL
I
IO12
IO8
IOD16
IOD8
IOP14
IP
IS
ISP
O12
O8
OD12
OD14
OD16
OD4
OD8
OP14
PCI_ICLK
PCI_IO
PCI_OD
ICLK
ICLK2
OCLK2
O24
TABLE 3 - BUFFER MODE LEGEND
DESCRIPTION
Input
Bidirectional – 12mA sink, 6mA source
Bidirectional – 8mA, 4mA source
Input, open drain output – 16mA sink
Input, open drain output – 8mA sink
Bidirectional – 14mA sink, 14mA source, backdrive
protected
Input with pullup
Schmitt trigger input
Schmitt trigger input with pullup
Output – 12mA, 6mA source
Output – 8mA, 4mA source
Open drain – 12mA sink
Open drain – 14mA sink
Open drain – 16mA sink
Open drain – 4mA sink
Open drain – 8mA sink
Output – 14mA sink, 14mA source, backdrive protected
PCI clock input
PCI bidirectional
PCI open drain
Clock input
Clock input 2
Clock output 2
Output – 12mA, 6mA source
21
DEFAULT
FUNCTION2
OUT1
VCC1
OUT3
VCC1
TABLE 4 - ALTERNATE FUNCTION PINS
ALTERNATE
ALTERNATE
FUNCTION #1
FUNCTION #2
nIRQ83
VCC2
FWR
VCC1
-
OUT5
OUT6
OUT7
OUT8
VCC1
VCC1
VCC1
VCC1
nDS13
nMTR13
nSMI3
DRQ23
VCC2
VCC2
VCC2
VCC2
KBRST3
KBRST3
OUT9
OUT10
OUT11
nFCS
GPIO4
GPIO5
GPIO6
VCC1
VCC1
VCC1
VCC1
VCC1
VCC1
VCC1
VCC2
VCC1
VCC1
VCC1
VCC1
VCC1
VCC2
-
GPIO8
GPIO9
GPIO10
VCC1
VCC1
VCC1
VCC1
VCC2
VCC2
-
GPIO11
GPIO12
FA18
GPIO17
GPIO18
GPIO19
GPIO20
GPIO21
KSO12
VCC1
VCC1
VCC1
VCC1
VCC1
VCC1
VCC1
VCC1
VCC1
DRQ33
PWM0
PWM1
GPIO0
KSO14
KSO15
IRMODE/IR
RX3A3
IRRX
IRTX4
IRMODE/IR
RX3B3
AB2_DATA
AB2_CLK
GPIO13
GATEA203
nDACK2
nDACK3
PS2CLK3
PS2DAT3
OUT8
VCC1
VCC1
VCC1
VCC1
VCC1
VCC1
VCC2
VCC2
VCC1
8051RX
8051TX
KBRST3
KSO13
VCC1
GPIO18
VCC1
-
22
VCC2
VCC2
MULTIPLEX
CONTROLS
MISC0
ALT WRITE
SELECT6
MISC[5, 22]5
MISC5
MISC181
MISC[17,10,
6]
MISC11
MISC4
MISC121
MISC191
MISC9
MISC[14:13]
MISC[2,7]
MISC[16:15]
MISC20
VCC1
VCC1
VCC2
MISC81
MISC6
MISC17
MISC11
MISC[3, 1]
MISC[17, 10,
6]
MISC17
DEFAULT
FUNCTION2
nINIT
VCC2
nSLCTIN
VCC2
PD0
VCC2
PD1
VCC2
PD2
VCC2
PD3
VCC2
PD4
VCC2
PD6
VCC2
SLCT
VCC2
PE
VCC2
BUSY
VCC2
nACK
VCC2
nERROR
VCC2
nALF
VCC2
nSTROBE VCC2
NOTE 1:
NOTE 2:
NOTE 3:
NOTE 4:
NOTE 5:
NOTE 6:
ALTERNATE
FUNCTION #1
nDIR
VCC2
nSTEP
VCC2
nINDEX
VCC2
nTRK0
VCC2
nWRTPRT
VCC2
nRDATA
VCC2
nDSKCHG
VCC2
nMTR0
VCC2
nWGATE
VCC2
nWDATA
VCC2
nMTR1
VCC2
NDS1
VCC2
NHDSEL
VCC2
DRVDEN0
VCC2
NDS0
VCC2
ALTERNATE
FUNCTION #2
-
MULTIPLEX
CONTROLS
CR25[4:3]
See a description in Section MULTIFUNCTION PIN on page 271.
The FDC37N972 pins are identified by primary pin function (see
DESCRIPTION OF PIN FUNCTIONS on page 11). Note that some functions are
available on more than one pin; e.g., OUT8, GPIO18 and KBRST.
When this pin is configured as an alternate function output and PWRGD is inactive,
i.e. VCC2 is 0v, the pin will tri-state to prevent back-biasing of external circuitry (see
Section General Purpose I/O (GPIO) on page 265).
This pin defaults to “output”, “low” for both the default (GPIO) function and the
alternate (IRTX) function, regardless of the state of PWRGD (see Section General
Purpose I/O (GPIO) on page 265).
MISC5 must be inactive for MISC22 to enable KBRST.
The ALT WRITE SELECT bit is in the Flash Configuration Register (see Section
ALT WRITE SELECT Bit, D3 on page 197).
23
TYPE 1 devices do not require a VCC0 battery
connection. Power supply requirements for
TYPE 1 devices are as follows: VCC0 is tied to
VSS, VCC1 is connected to the main battery
supply, and VCC2 is switched from either the
main battery or AC power if available. In this
configuration all internal components which
utilize VCC0 power plane are switched internally
to the VCC1 upon POR according to
VCC1_PWRGD.
There are three power planes in the FDC37N972
VCC0, VCC1, and VCC2 with the following power
sequencing requirement:
1. VCC2
shall
have
power
applied
simultaneously with or after VCC1.
2. VCC1
shall
have
power
applied
simultaneously with or after VCC0.
All internal components which utilize VCC0 power
plane are switched internally between the VCC1
and VCC0 pins according to VCC1_PWRGD
TYPE 2 devices require a VCC0 battery
connection. Power supply requirements for
TYPE 2 devices are as follows: VCC0 is
connected to a backup battery (VBAT), VCC1 is
connected to the main battery supply, and VCC2
is switched from either the main battery or AC
power if available. In this configuration all
internal components which utilize VCC0 power
plane only when VCC1 is absent. Normally (when
VCC1_PWRGD is asserted) they are switched
internally to the VCC1 power plane.
See Table 5 for power consumption in various
states.
Two FDC37N972 power supply configurations
can be utilized.
These power supply
configuration types fundamentally differ upon
the need for a backup battery (VBAT) connection
to VCC0.
24
VCC2
(VDC)
3.3
3.3
3.3
3.3
0
0
0
0
0
0
Note:
TABLE 5 - POWER COMSUMPTION IN VARIOUS STATES
8051
CLOCK
STATE
STATE
SYM
TYP
MAX
COMMENTS
Run
24 MHz
ICC2
15 ma
20 ma
FLOPPY @ 1 Meg Data Rate
ICC1
24 ma
30 ma
I2C @ 24 MHz
3.3
Run
12 MHz
ICC2
13 ma
15 ma
Floppy @ 500K Data Rate
ICC1
12 ma
18 ma
I2C @ 12 MHz
3.3
Run
Ring
ICC2
>1ma
2 ma
PLL On
OSC
ICC1
8 ma
10 ma
I2C Off
3.3
Idle
Ring
ICC2
>1ma
2 ma
PLL Off
OSC
ICC1
5 ma
7 ma
3.3
Run
Ring
ICC2
PLL Off
OSC
ICC1
8 ma
10 ma
I2C Off
3.3
Idle
Ring
ICC2
PLL Off
OSC
ICC1
6 ma
8 ma
I2C Off
3.3
Sleep
Stop
ICC1
160 µa
XOSEL=1
3.3
Sleep
Stop
ICC1
5 µa
10 µa
XOSEL=0
0
ICC0
40 µa
60 µa
2.4 < Vcc0 < 4 VDC,
XOSEL=1,
0
ICC0
0.4 µa
1.5 µa
2.4 < Vcc0 < 4 VDC,
XOSEL = 0
When a single-ended 32.768kHz clock source is selected (see Section 32kHz Clock Input).
The FDC37N972 uses the XOSEL pin to select either a 32.768kHz input clock or a
32.768kHz crystal to drive the Real Time Clock Interface (Table 2 - PIN FUNCTION
DESCRIPTION). When XOSEL = ‘0’, The RTC uses a 32.768kHz crystal connected between
the XTAL1 and XTAL2 pins. When XOSEL = ‘1’, the RTC is driven by a 32.768kHz singleended clock source connected to the XTAL2 pin.
VCC1
(VDC)
3.3
25
TABLE 7 - POWER PIN LIST
BIAS PINS
156
29, 143, 176
VCC0
VCC1
83, 104, 120, 205
VCC2
160
1, 7, 49, 73, 89,
107, 132, 167, 192
AGND
VSS
Note:
AB
CI
WDT
MR
CR
PM
AB2
FI
RTC (VBAT)Supply Voltage 2.7-3.3V ibat<2ma
8051 + AB + CI + RTC+ ACPI + PM1 + WDT + MR + CR
+ PM + AB2 + FI + PWM + KI + GPIO + LED + IR + 3.3V
+/-5% Supply Voltage (Note)
SR + PCG + FDC + DDS + UART + PP + PS/2 + Core
+3.3V +/-5%Supply Voltage
Analog Ground for VCC0.
Digital Ground
KI
GPIO
IR
SR
PCG
FDC
DDS
PP
= ACCESS.bus
= Control Inputs
= Watch Dog Timer
= Mailbox Registers
= Control Registers
= Power Management
= ACCESS.BUS2
= Flash Interface
= Keyboard Interface
= General Purpose I/O Interface
= Infrared
= System Reset
= PLL Clock Generator
= Floppy Disk Controller
= Digital Data Seperator
= Multi-Mode Parallel Port
PWRGD and VCC1_PWRGD timing is illustrated in FIGURE 3 through FIGURE 5.
26
10µ s
min.
PWRGD
3V
VCC2
CLOCKI
FIGURE 3 – POWER-FAIL EVENT
10µs
min.
PWRGD
3V
VCC2
CLOCKI
FIGURE 4 - VCC2 POWER-UP TIMING
1µs
min.
1µs
min.
VCC1_PWRGD
VCC1
3V
3V
FIGURE 5 - VCC1_PWRGD TIMING
These figures also appear in the “Timing Diagrams” section of this spec.
27
FUNCTIONAL DESCRIPTION
FDC37N972 OPERATING REGISTERS
HOST PROCESSOR INTERFACE
The address map, shown below in TABLE 8,
shows the set of operating registers and
addresses for each of the logical blocks of the
FDC37N972 Ultra I/O controller. The base
addresses of the FDC, Parallel, Serial 1 and
Infrared ports can be moved via the
configuration registers.
The host processor communicates with the
FDC37N972 through a series of read/write
registers. The range of base I/O port addresses
for these registers is shown in TABLE 8.
Register access is accomplished through
programmed I/O or DMA transfers. All registers
are 8 bits. Most of the registers support zero
wait-state access (NOWS). All host interface
output buffers are capable of sinking a minimum
of 6 mA.
LOGICAL
DEVICE
NUMBER
0x00
0x03
TABLE 8 - FDC37N972 OPERATING REGISTER ADDRESSES
BASE I/O
RANGE
FIXED
LOGICAL
(NOTE3)
BASE OFFSETS
DEVICE
FDC
[0x100:0x0FF8]
+0 : SRA
+1 : SRB
+2 : DOR
ON 8 BYTE
+3 : TSR
BOUNDARIES
+4 : MSR/DSR
+5 : FIFO
+7 : DIR/CCR
Parallel
[0x100:0x0FFC]
+0 : Data / ecpAfifo
Port
ON 4 BYTE
+1 : Status
BOUNDARIES
+2 : Control
(EPP Not supported) +400h : cfifo / ecpDfifo
or
tfifo / cnfgA
[0x100:0x0FF8]
+401h : cnfgB
ON 8 BYTE
+402h : ecr
BOUNDARIES
(all modes
supported,
EPP is only available
when the base
address is on an 8byte boundary)
28
ISA
CYCLE
TYPE
NOWS
Std. ISA I/O
LOGICAL
DEVICE
NUMBER
0x04
LOGICAL
DEVICE
Serial
Port 1
BASE I/O
RANGE
(NOTE3)
[0x100:0x0FF8]
FIXED
BASE OFFSETS
+0 : RB/TB  LSB div
+1 : IER  MSB div
+2 : IIR/FCR
+3 : LCR
+4 : MCR
+5 : LSR
+6 : MSR
+7 : SCR
+0 : RB/TB  LSB div
+1 : IER  MSB div
+2 : IIR/FCR
+3 : LCR
+4 : MCR
+5 : LSR
+6 : MSR
+7 : SCR
ON 8 BYTE
BOUNDARIES
0x05
Infrared
Port
[0x100:0x0FF8]
ON 8 BYTE
BOUNDARIES
0x62,
0x63
[0x100:0x0FF8]
ON 8 BYTE
BOUNDARIES
0x06
RTC
Not Relocatable
Fixed Base Address
0x07
KYBD
Not Relocatable
Fixed Base
Address
+0 : Register Block N,
address 0
+1 : Register Block N,
address 1
+2 : Register Block N,
address 2
+3 : Register Block N,
address 3
+4 : Register Block N,
address 4
+5 : Register Block N,
address 5
+6 : Register Block N,
address 6
+7 : SCE Master Control
Reg.
0x70, 0x74 : Address
Register
0x71, 0x76 : Data Register
0x60 : Data Register
0x64 : Command/Status
Reg.
ISA
CYCLE
TYPE
NOWS
NOWS
NOWS
Std. ISA I/O
NOWS
Note 1: Refer to the configuration register descriptions for setting the base address
Note 2: This chip uses all ISA address bits to decode the base address of each of its logical devices.
29
FLOPPY DISK CONTROLLER
The FDC is compatible to the 82077AA using
SMSC's proprietary FDC core.
The Floppy Disk Controller (FDC) provides the
interface between a host microprocessor and
the Floppy Disk Drives (FDD).
The FDC
integrates
the
functions
of
the
formatter/controller, Digital Data Separator,
Write Precompensation and data rate Selection
logic for an IBM XT/AT compatible FDC. The
true CMOS 765B core guarantees 100% IBM
PC XT/AT compatibility in addition to providing
data overflow and underflow protection.
FDC INTERNAL REGISTERS
The FDC contains eight internal registers, which
facilitate the interfacing between the host
microprocessor and the disk drive TABLE 9
shows the addresses required toaccess these
registers. Registers other than the ones shown
are not supported.
TABLE 9 - STATUS, DATA AND CONTROL REGISTERS
FDC PRIMARY BASE I/O
ADDRESS OFFSET
R/W
REGISTER
0
R
Status Register A (SRA)
1
R
Status Register B (SRB)
2
R/W
Digital Output Register (DOR)
3
R/W
Tape Drive Register (TDR)
4
R
Main Status Register (MSR)
4
W
Data Rate Select Register (DSR)
5
R/W
Data (FIFO)
6
Reserved
7
R
Digital Input Register (DIR)
7
W
Configuration Control Register (CCR)
STATUS REGISTER A (SRA)
FDC I/O BASE ADDRESS + 0x00
(READ ONLY)
This register is read-only and monitors the state of the FDC Interrupt pin and several disk
interface pins in PS/2 and Model 30 modes. The SRA can be accessed at any time when in PS/2
mode. In the PC/AT mode the data bus pins D0 - D7 are held in a high impedance state for a read of
SRA.
30
RESET
COND.
TABLE 10 - SRB - PS/2 MODEL 30 MODE
7
6
5
4
3
2
INT
nDRV2 STEP nTRK0 HDSEL nINDX
PENDING
0
N/A
0
N/A
0
N/A
1
nWP
0
DIR
N/A
0
BIT 0 DIRECTION
Active high status indicating the direction of head movement. A logic "1" indicates inward direction; a
logic "0" indicates outward direction.
BIT 1 nWRITE PROTECT
Active low status of the WRITE PROTECT disk interface input. A logic "0" indicates that the disk is
write protected.
BIT 2 nINDEX
Active low status of the INDEX disk interface input.
BIT 3 HEAD SELECT
Active high status of the HDSEL disk interface input. A logic "1" selects side 1 and a logic "0" selects
side 0.
BIT 4 nTRACK 0
Active low status of the TRK0 disk interface input.
BIT 5 STEP
Active high status of the STEP output disk interface output pin.
BIT 6 nDRV2
Active low status of the DRV2 disk interface input pin, indicating that a second drive has been
installed.
BIT 7 INTERRUPT PENDING
Active high bit indicating the state of the Floppy Disk Interrupt output.
31
RESET
COND.
TABLE 11 - SRA - PS/2 MODEL 30 MODE
7
6
5
4
3
2
INT
DRQ STEP TRK0 NHDSE INDX
PENDING
F/F
L
0
0
0
N/A
1
N/A
1
WP
0
nDIR
N/A
1
BIT 0 nDIRECTION
Active low status indicating the direction of head movement. A logic "0" indicates inward direction; a
logic "1" indicates outward direction.
BIT 1 WRITE PROTECT
Active high status of the WRITE PROTECT disk interface input. A logic "1" indicates that the disk is
write protected.
BIT 2 INDEX
Active high status of the INDEX disk interface input.
BIT 3 nHEAD SELECT
Active low status of the HDSEL disk interface input. A logic "0" selects side 1 and a logic "1" selects
side 0.
BIT 4 TRACK 0
Active high status of the TRK0 disk interface input.
BIT 5 STEP
Active high status of the latched STEP disk interface output pin. This bit is latched with the STEP
output going active, and is cleared with a read from the DIR register, or with a hardware or software
reset.
BIT 6 DMA REQUEST
Active high status of the FDC’s DRQ output pin.
BIT 7 INTERRUPT PENDING
Active high bit indicating the state of the Floppy Disk Interrupt output.
32
DIGITAL OUTPUT REGISTER (DOR)
FDC I/O BASE ADDRESS + 0X02 (READ/WRITE)
The DOR controls the drive select and motor enables of the disk interface outputs. It also contains
the enable for the DMA logic and a software reset bit. The contents of the DOR are unaffected by a
software reset. The DOR can be written to at any time.
7
MOT
EN3
0
6
MOT
EN2
0
TABLE 12 - FDC DOR
5
4
3
2
MOT
MOT DMAEN nRESE
EN1
EN0
T
0
0
0
0
1
0
DRIVE DRIVE
SEL1 SEL0
0
0
RESET
COND.
BIT 0 and 1 DRIVE SELECT
These two bits are binary encoded for the two drive selects output pins nds0 and nds1, thereby
allowing only one drive to be selected at one time.
BIT 2 nreset
A logic “0” written to this bit resets the FDC. This reset will remain active until a logic “1” is written to
this bit. This software reset does not affect the DSR and CCR registers, nor does it affect the other
bits of the DOR register. The minimum reset duration required is 100ns, therefore toggling this bit by
consecutive writes to this register is a valid method of issuing a software reset.
BIT 3 DMAEN
PC/AT and Model 30 Mode: Writing this bit to logic “1” will enable the FDC’s ndack and TC inputs and
enable the FDC’s DRQ and Interrupt outputs. This bit being a logic “0” will disable the FDC’s ndack
and TC inputs, and hold the FDC’s DRQ and Interrupt outputs in a high impedance state. This bit is a
logic “0” after a reset.
PS/2 Mode: In this mode the TC and the FDC’s DRQ, ndack, and Interrupt pins are always enabled.
During a reset, the DRQ, ndack, TC, and Interrupt pins will remain enabled, but this bit will be cleared
to a logic “0”.
BIT 4 MOTOR ENABLE 0
This bit controls the nmtr0 disk interface output. A logic “1” in this bit will cause the output pin to
assert.
BIT 5 MOTOR ENABLE 1
This bit controls the nmtr1 disk interface output. A logic “1” in this bit will cause the output pin to
assert.
BIT 6 MOTOR ENABLE 2
This bit controls the nmtr2 disk interface output. A logic “1” in this bit will cause the output pin to
assert.
BIT 7 MOTOR ENABLE 3
This bit controls the nmtr3 disk interface output. A logic “1” in this bit will cause the output pin to
assert.
33
RESET
COND.
RESET
COND.
TABLE 13 – FDC SRB – PS/2 MODEL 30 MODE
7
6
5
4
3
2
1
0
nDRV2 nDS1 nDS0 WDATA RDATA WGATE nDS3 nDS2
F/F
F/F
F/F
N/A
1
1
0
0
0
1
1
7
MOT
EN3
0
6
MOT
EN2
0
TABLE 14 - FDC DOR
5
4
3
2
MOT
MOT
DMAEN nRESET
EN1
EN0
0
0
0
0
1
DRIVE
SEL1
0
0
DRIVE
SEL0
0
BIT 0 and 1 DRIVE SELECT
These two bits are binary encoded for the two drive selects output pins nds0 and nds1, thereby
allowing only one drive to be selected at one time.
BIT 2 nRESET
A logic “0” written to this bit resets the FDC. This reset will remain active until a logic “1” is written to
this bit. This software reset does not affect the DSR and CCR registers, nor does it affect the other
bits of the DOR register. The minimum reset duration required is 100ns, therefore toggling this bit by
consecutive writes to this register is a valid method of issuing a software reset.
BIT 3 DMAEN
PC/AT and Model 30 Mode:
Writing this bit to logic “1” will enable the FDC’s nDACK and TC inputs and enable the FDC’s DRQ
and Interrupt outputs. This bit being a logic “0” will disable the FDC’s nDACK and TC inputs, and hold
the FDC’s DRQ and Interrupt outputs in a high impedance state. This bit is a logic “0” after a reset.
PS/2 Mode: In this mode the TC and the FDC’s DRQ, and Interrupt pins are always enabled. During
a reset, the DRQ, TC, and Interrupt pins will remain enabled, but this bit will be cleared to a logic “0”.
BIT 4 MOTOR ENABLE 0
This bit controls the disk interface output. A logic “1” in this bit will cause the output pin to assert.
BIT 5 MOTOR ENABLE 1
This bit controls the nMTR1 disk interface output. A logic “1” in this bit will cause the output pin to
assert.
BIT 6 MOTOR ENABLE 2
This bit controls the nMTR2 disk interface output. A logic “1” in this bit will cause the output pin to
assert.
BIT 7 MOTOR ENABLE 3
This bit controls the nMTR3 disk interface output. A logic “1” in this bit will cause the output pin to
assert.
34
TABLE 13 – FDC INTERNAL 2 DRIVE DECODE – DRIVES 0 AND 1 SWAPPED
MOTOR ON OUTPUTS
DRIVE SELECT
DIGITAL OUTPUT REGISTER
(ACTIVE LOW)
OUTPUTS (ACTIVE
LOW)
Bit 7 Bit 6 Bit 5 Bit 4 Bit1 Bit 0
Nds1
Nds0
Nmtr1
Nmtr0
X
X
X
1
0
0
0
1
Nbit 4
Nbit 5
X
X
1
X
0
1
1
0
Nbit 4
Nbit 5
X
1
X
X
1
0
1
1
Nbit 4
Nbit 5
1
X
X
X
1
1
1
1
Nbit 4
Nbit 5
0
0
0
0
X
X
1
1
Nbit 4
Nbit 5
TAPE DRIVE REGISTER (TDR)
NORMAL FLOPPY MODE
FDC I/O BASE ADDRESS + 0x03
(READ/WRITE)
Normal mode. The TDR allows the user to
assign tape support to a particular drive during
initialization. Any future references to that drive
number automatically invokes tape support.
The Tape Select bits are TDR[1:0]. The TDR
Register contains only bits 0 and 1. When this
register is read, bits 2 – 7 are a high impedance.
This register is included for 82077 software
compatability. The TDR is unaffected by a
software reset. The improved data separator
incorporates tape drive support and requires the
Tape Select bits in the FDC Tape Drive register
to identify which drive has been assigned to
receive this support (see the following section).
DB7
REG 3F3 Tri-state
TABLE 14 - FDC TDR NORMAL FLOPPY MODE
DB6
DB5
DB4
DB3
DB2
Tri-state Tri-state Tri-state Tri-state Tri-state
TAPE SEL1
(TDR.1)
0
0
1
1
TAPE SEL2
(TDR.0)
0
1
0
1
35
DRIVE
SELECTED
None
1
2
3
DB1
tape sel 1
DB0
tape sel 0
ENHANCED FLOPPY MODE 2 (OS2)
The TDR Register for Enhanced Floppy Mode 2 operation.
REG 3F3
DB7
1
TABLE 15 - FDC TDR ENHANCED FLOPPY MODE 2 (OS2)
DB6
DB5
DB4
DB3
DB2
DB1
DB0
1
Drive Type ID
Floppy Boot Drive
tape sel1 tape sel0
BIT 7 This bit is always set active high
BIT 6 This bit is always set active high
BITS 5 and 4 Drive Type ID
These bits reflect two of the bits of L0-CRF1 (Logical Device 0 – Configuration Register 0xF1).
Which two bits these are depends on the last drive selected in the Digital Output Register. (See
TABLE 20)
BITS 3 and 2 Floppy Boot Drive
These bits reflect two of the bits of L0-CRF1. Bit 3 = L0-CRF1-B7. Bit 2 = L0-CRF1-B6.
BIT 1 and 0 – Tape Drive Select (READ/WRITE)
Same as in Normal and Enhanced Floppy Mode 2.
TABLE 16 – DRIVE TYPE ID
DIGITAL OUTPUT REGISTER
TDR REGISTER – DRIVE TYPE ID
Bit 1
Bit 0
Bit 5
Bit 4
0
0
L0-CRF2 – B1
L0-CRF2 – B0
0
1
L0-CRF2 – B3
L0-CRF2 – B2
1
0
L0-CRF2 – B5
L0-CRF2 – B4
1
1
L0-CRF2 – B7
L0-CRF2 – B6
Note:
L0-CRF2-Bx = Logical Device 0, Configuration Register F2, Bit x.
MID[1:0] FDD INTERFACE PINS
The FDC Media ID pins are not supported in the FDC37N972. The MID[1:0] inputs to the FDC core
are strapped so that the Media ID bits the TDR are always “high”.
36
DATA RATE SELECT REGISTER (DSR)
Microchannel applications. Other applications
can set the data rate in the DSR. The data rate
of the floppy controller is the most recent write
of either the DSR or CCR.
The DSR is
unaffected by a software reset. A hardware
reset will set the DSR to 02H, which
corresponds to the default precompensation
setting and 250 Kbps.
FDC I/O BASE ADDRESS + 0x04 (WRITE
ONLY)
This register is write only. It is used to program
the data rate, amount of write precompensation,
power down status, and software reset. The
data
rate
is
programmed
using
the
Configuration Control Register (CCR) not the
DSR, for PC/AT and PS/2 Model 30 and
RESET
COND.
7
6
S/W POWER
RESET DOWN
0
0
TABLE 17 - FDC DSR
5
4
3
0
PREPRECOMP2 COMP1
0
0
0
2
1
0
PRE- DRATE DRATE
COMP0 SEL1
SEL0
0
1
0
BITS 0 - 1 DATA RATE SELECT
These bits control the data rate of the floppy controller. See TABLE 19 for the settings corresponding
to the individual data rates. The data rate select bits are unaffected by a software reset and are set to
250 Kbps after a hardware reset.
BITS 2 - 4 PRECOMPENSATION SELECT
These three bits select the value of write precompensation that will be applied to the WDATA output
signal. TABLE 18 shows the precompensation values for the combination of these bits settings.
Track 0 is the default starting track number to start precompensation. This starting track number can
be changed by the configure command.
BIT 5 UNDEFINED
Should be written as a logic "0".
BIT 6 LOW POWER
A logic "1" written to this bit will put the floppy controller into manual low power mode. The floppy
controller clock and data separator circuits will be turned off. The controller will come out of manual
low power mode after a software reset or access to the Data Register or Main Status Register.
BIT 7 SOFTWARE RESET
This active high bit has the same function as the DOR RESET (DOR bit 2) except that this bit is self
clearing.
37
TABLE 18 - FDC PRECOMPENSATION DELAYS
PRECOMPENSATION
PRECOMP 432
DELAY (nsec)
<2Mbps
2Mbps
0
0.00
111
20.8
41.67
001
41.7
83.34
010
62.5
125.00
011
83.3
166.67
100
104.2
208.33
101
125
250.00
110
Default
Default
000
Default: See TABLE 16
DRIVE RATE
DRT1
DRT0
0
0
0
0
0
0
0
0
0
1
0
1
0
1
0
1
1
0
1
0
1
0
1
0
TABLE 19 – FDC DATA RATES
DATA RATE
DATA RATE
SEL1
SEL0
MFM
FM
1
1
1Meg
--0
0
500
250
0
1
300
150
1
0
250
125
1
1
1Meg
--0
0
500
250
0
1
500
250
1
0
250
125
1
1
1Meg
--0
0
500
250
0
1
2Meg
--1
0
250
125
DENSEL
1
1
0
0
1
1
0
0
1
1
0
0
DRATE(1)
1
0
1
1
0
0
0
1
1
0
1
1
0
0
0
1
1
0
1
1
0
0
0
1
1
0
Drive Rate Table (Recommended) 00 = 360K, 1.2M, 720K, 1.44M and 2.88M Vertical Format
01 = 3-Mode Drive
10 = 2 Meg Tape
Note 1: The DRATE and DENSEL values are mapped onto the DRIVEDEN pins.
38
DT1
0
DT0
0
1
0
1
0
1
1
TABLE 20 - FDC DRVDEN MAPPING
DRVDEN1 (1)
DRVDEN0 (1)
DRIVE TYPE
DRATE0
DENSEL
4/2/1 MB 3.5"
2/1 MB 5.25" FDDS
2/1.6/1 MB 3.5" (3-MODE)
DRATE0
DRATE1
DRATE0
nDENSEL
PS/2
DRATE1
DRATE0
TABLE 21 - FDC DEFAULT PRECOMPENSATION DELAYS
PRECOMPENSATION
DATA RATE
DELAYS
20.8 ns
2 Mbps
41.67 ns
1 Mbps
125 ns
500 Kbps
125 ns
300 Kbps
125 ns
250 Kbps
39
MAIN STATUS REGISTER
time.
The MSR indicates when the disk
controller is ready to receive data via the Data
Register. It should be read before each byte
transferring to or from the data register except in
DMA mode. No delay is required when reading
the MSR after a data transfer.
FDC I/O BASE ADDRESS + 0x04
(READ ONLY)
The Main Status Register is a read-only register
and indicates the status of the disk controller.
The Main Status Register can be read at any
7
RQM
6
DIO
5
NON
DMA
TABLE 22 - FDC MSR
4
3
2
CMD
DRV3
DRV2
BUSY
BUSY
BUSY
1
DRV1
BUSY
0
DRV0
BUSY
BIT 0 - 3 DRVx BUSY
These bits are set to 1s when a drive is in the seek portion of a command, including implied and
overlapped seeks and recalibrates.
BIT 4 COMMAND BUSY
This bit is set to a “1” when a command is in progress. This bit will go active after the command byte
has been accepted and goes inactive at the end of the results phase. If there is no result phase (Seek,
Recalibrate commands), this bit is returned to a “0” after the last command byte.
BIT 5 NON-DMA
This mode is selected in the SPECIFY command and will be set to a “1” during the execution phase of
a command. This is for polled data transfers and helps differentiate between the data transfer phase
and the reading of result bytes.
BIT 6 DIO
Indicates the direction of a data transfer once a RQM is set. A “1” indicates a read and a “0” indicates
a write is required.
BIT 7 RQM
Indicates that the host can transfer data if set to a “1”. No access is permitted if set to a “0”.
40
DATA REGISTER (FIFO)
FDC
I/O
BASE
(READ/WRITE)
ADDRESS
+
TABLE 31 gives several examples of the delays
with a FIFO. The data is based upon the
following formula:
0x05
All command parameter information, disk data
and result status are transferred between the
host processor and the FDC through the Data
Register. Data transfers are governed by the
RQM and DIO bits in the Main Status Register.
Threshold # x [8/DATA RATE] - 1.5ms = Delay
At the start of a command, the FIFO action is
always disabled and command parameters
must be sent based upon the RQM and DIO bit
settings. As the command execution phase is
entered, the FIFO is cleared of any data to
ensure that invalid data is not transferred.
The Data Register defaults to FIFO disabled
mode after any form of reset. This maintains
PC/AT hardware compatibility.
The default
values can be changed through the Configure
command (enable full FIFO operation with
threshold control). The advantage of the FIFO
is that it allows the system a larger DMA latency
without causing a disk error.
An overrun or underrun will terminate the
current command and the transfer of data. Disk
writes will complete the current sector by
generating a 00 pattern and valid CRC. Reads
require the host to remove the remaining data
so that the result phase may be entered.
TABLE 23
FIFO THRESHOLD
EXAMPLES
1 byte
2 bytes
8 bytes
15 bytes
- FIFO SERVICE DELAY
MAXIMUM DELAY TO SERVICING
AT 2 Mbps* DATA RATE
1 x 4 ms - 1.5 ms = 2.5 ms
2 x 4 ms - 1.5 ms = 6.5 ms
8 x 4 ms - 1.5 ms = 30.5 ms
15 x 4 ms - 1.5 ms = 58.5 ms
FIFO THRESHOLD
EXAMPLES
1 byte
2 bytes
8 bytes
15 bytes
MAXIMUM DELAY TO SERVICING
AT 1 Mbps DATA RATE
1 x 8 ms - 1.5 ms = 6.5 ms
2 x 8 ms - 1.5 ms = 14.5 ms
8 x 8 ms - 1.5 ms = 62.5 ms
15 x 8 ms - 1.5 ms = 118.5 ms
FIFO THRESHOLD
EXAMPLES
1 byte
2 bytes
8 bytes
15 bytes
MAXIMUM DELAY TO SERVICING
AT 500 Kbps DATA RATE
1 x 16 ms - 1.5 ms = 14.5 ms
2 x 16 ms - 1.5 ms = 30.5 ms
8 x 16 ms - 1.5 ms = 126.5 ms
15 x 16 ms - 1.5 ms = 238.5 ms
41
DIGITAL INPUT REGISTER (DIR)
FDC I/O BASE ADDRESS + 0X07 (READ ONLY)
This register is read-only in all modes.
DIR - PC-AT Mode
RESET
COND.
7
DSK
CHG
N/A
TABLE 24 - FDC DIR ALL MODES
6
5
4
3
2
N/A
N/A
N/A
N/A
N/A
1
0
N/A
N/A
BIT 0 – 6 UNDEFINED
The data bus outputs D0 – 6 will remain in a high impedance state during a read of this register.
BIT 7 DSKCHG
This bit monitors the pin of the same name and reflects the opposite value seen on the disk cable.
DIR – PS/2 MODE
RESET
COND.
7
DSK CHG
N/A
6
1
N/A
TABLE 25 - FDC DIR PS/2 MODE
5
4
3
2
1
0
1
1
1 DRATE SEL1 DRATE SEL0 nHIGH DENS
N/A N/A N/A
N/A
N/A
1
BIT 0 nhigh DENS
This bit is low whenever the 500 Kbps or 1 Mbps data rates are selected, and high when 250 Kbps and
300 Kbps are selected.
BITS 1 – 2 DATA RATE SELECT
These bits control the data rate of the floppy controller. See TABLE 19for the settings corresponding
to the individual data rates. The data rate select bits are unaffected by a software reset, and are set to
250 Kbps after a hardware reset.
BITS 3 – 6 UNDEFINED
Always read as a logic “1”
BIT 7 DSKCHG
This bit monitors the pin of the same name and reflects the opposite value seen on the disk cable.
42
DIR – MODEL 30 MODE
RESET
COND.
7
DSK
CHG
N/A
TABLE 26 - FDC DIR MODEL 30 MODE
6
5
4
3
2
1
0
0
0
0
DMAEN nOPREC DRATE DRATE
SEL1
SEL0
0
0
0
0
0
1
0
BITS 0 and 1 DATA RATE SELECT
These bits control the data rate of the floppy controller. See TABLE 19 for the settings corresponding
to the individual data rates. The data rate select bits are unaffected by a software reset and are set to
250 Kbps after a hardware reset.
BIT 2 nOPREC
This bit reflects the value of nOPREC bit set in the CCR register.
BIT 3 DMAEN
This bit reflects the value of DMAEN bit set in the DOR register bit 3.
BITS 4 - 6 UNDEFINED
Always read as a logic "0"
BIT 7 DSKCHG
This bit monitors the pin of the same name and reflects the opposite value seen on the pin.
CONFIGURATION CONTROL REGISTER (CCR)
FDC I/O BASE ADDRESS + 0x07
(WRITE ONLY)
TABLE 27 - FDC CCR PC/AT AND PS/2 MODE
6
5
4
3
2
1
0
DRATE DRATE
SEL1
SEL0
N/A
N/A
N/A
N/A
N/A
N/A
1
0
7
RESET
COND.
BIT 0 and 1 DATA RATE SELECT 0 and 1
These bits determine the data rate of the floppy controller. See TABLE 19 for the appropriate values.
BIT 2 - 7 RESERVED
Should be set to a logical "0"
43
TABLE 28 - FDC CCR - PS/2 MODEL 30 MODE
6
5
4
3
2
1
0
NOPREC DRATE DRATE
SEL1
SEL0
N/A
N/A
N/A
N/A
N/A
N/A
1
0
7
RESET
COND.
BIT 0 and 1 DATA RATE SELECT 0 and 1
These bits determine the data rate of the floppy controller. See TABLE 19 for the appropriate values.
BIT 2 NO PRECOMPENSATION
This bit can be set by software, but it has no functionality. It can be read by bit 2 of the DSR when in
Model 30 register mode. Unaffected by software reset.
BIT 3 - 7 RESERVED
Should be set to a logical "0". TABLE 19 shows the state of the DENSEL pin. The DENSEL pin is set
high after a hardware reset and is unaffected by the DOR and the DSR resets.
STATUS REGISTER ENCODING
During the Result Phase of certain commands, the Data Register contains data bytes that give the
status of the command just executed.
BIT NO.
7,6
SYMBOL
IC
5
SE
4
EC
3
2
1,0
H
DS1,0
TABLE 29 - FDC STATUS REGISTER 0
NAME
DESCRIPTION
Interrupt Code 00 - Normal termination of command. The specified
command was properly executed and completed
without error.
01 - Abnormal termination of command. Command
execution was started, but was not successfully
completed.
10 - Invalid command. The requested command could
not be executed.
11 - Abnormal termination caused by Polling.
Seek End
The FDC completed a Seek, Relative Seek or
Recalibrate command (used during a Sense Interrupt
Command).
Equipment
The TRK0 pin failed to become a "1" after:
Check
Step pulses in the Recalibrate command.
The Relative Seek command caused the FDC to step
outward beyond Track 0.
Unused. This bit is always "0".
Head Address The current head address.
Drive Select
The current selected drive.
44
TABLE 30 - FDC STATUS REGISTER 1
BIT NO. SYMBOL
NAME
DESCRIPTION
7
EN
End of Cylinder The FDC tried to access a sector beyond the final sector of
the track (255D). Will be set if TC is not issued after Read
or Write Data command.
6
Unused. This bit is always "0".
5
DE
Data Error
The FDC detected a CRC error in either the ID field or the
data field of a sector.
4
OR
Overrun/
Becomes set if the FDC does not receive CPU or DMA
Underrun
service within the required time interval, resulting in data
overrun or underrun.
3
Unused. This bit is always "0".
2
ND
No Data
Any one of the following:
Read Data, Read Deleted Data command - the FDC did not
find the specified sector.
Read ID command - the FDC cannot read the ID field
without an error.
Read A Track command - the FDC cannot find the proper
sector sequence.
1
NW
Not Writable
WP pin became a "1" while the FDC is executing a Write
Data, Write Deleted Data, or Format A Track command.
0
MA
Missing Address Any one of the following:
Mark
The FDC did not detect an ID address mark at the specified
track after encountering the index pulse from the IDX pin
twice.
The FDC cannot detect a data address mark or a deleted
data address mark on the specified track.
45
TABLE 31 - FDC STATUS REGISTER 2
NAME
DESCRIPTION
Unused. This bit is always "0".
Control Mark
Any one of the following:
Read Data command - the FDC encountered a deleted
data address mark.
Read Deleted Data command - the FDC encountered a
data address mark.
Data Error in
The FDC detected a CRC error in the data field.
Data Field
Wrong
The track address from the sector ID field is different
Cylinder
from the track address maintained inside the FDC.
Unused. This bit is always "0".
Unused. This bit is always "0".
Bad Cylinder
The track address from the sector ID field is different
from the track address maintained inside the FDC and
is equal to FF hex, which indicates a bad track with a
hard error according to the IBM soft-sectored format.
Missing Data
The FDC cannot detect a data address mark or a
Address Mark
deleted data address mark.
BIT NO.
7
6
SYMBOL
5
DD
4
WC
3
2
1
BC
0
MD
BIT NO.
7
6
5
4
3
2
1,0
SYMBOL
CM
WP
T0
HD
DS1,0
TABLE 32 - FDC STATUS REGISTER 3
NAME
DESCRIPTION
UNUSED. THIS BIT IS ALWAYS "0".
Write Protected Indicates the status of the WP pin.
Unused. This bit is always "1".
Track 0
Indicates the status of the TRK0 pin.
Unused. This bit is always "1".
Head Address
Indicates the status of the HDSEL pin.
Drive Select
Indicates the status of the nDS1, nDS0 pins.
All operations are terminated upon a RESET,
and the Floppy Disk Controller enters an idle
state. A reset while a disk write is in progress
will corrupt the data and CRC.
FDC RESET
There are three sources of system reset on the
FDC: the nRESET_OUT bit of the 8051’s Output
enable
Register
(which
controls
the
nRESET_OUT pin of the FDC37N972); a reset
generated via a bit in the DOR; and a reset
generated via a bit in the DSR. At VCC2 power
on, a VCC2 Power On Reset initializes the FDC.
All resets take the FDC out of the power down
state.
On exiting the reset state, various internal
registers are cleared, including the Configure
command information, and the Floppy Disk
Controller waits for a new command. Drive
polling will start unless disabled by a new
Configure command.
46
and DRQ can be hi-Z), TC is active high and
DENSEL is active low.
DMA TRANSFERS
nRESET_OUT PIN (HARDWARE RESET)
The nRESET_OUT pin is a global reset and
clears all registers except those programmed by
the Specify command. The DOR reset bit is
enabled and must be cleared by the host to exit
the reset state.
DMA transfers are enabled with the Specify
command and are initiated by the FDC by
activating its DRQ pin during a data transfer
command. The FIFO is enabled directly by
asserting nDACK and addresses need not be
valid.
DOR RESET VS. DSR RESET (SOFTWARE
RESET)
These two resets are functionally the same.
Both will reset the FDC core, which affects drive
status information and the FIFO circuits. The
DSR reset clears itself automatically while the
DOR reset requires the host to manually clear it.
DOR reset has precedence over the DSR reset.
The DOR reset is set automatically upon a
nRESET_OUT pin reset.
The user must
manually clear this reset bit in the DOR to exit
the reset state.
Note that if the DMA controller (i.e. 8237A) is
programmed to function in verify mode, a
pseudo read is performed by the FDC based
only on nDACK. This mode is only available
when the FDC has been configured into byte
mode (FIFO disabled) and is programmed to do
a read. With the FIFO enabled, the FDC can
perform the above operation by using the Verify
command; no DMA operation is needed.
FDC MODES OF OPERATION
CONTROLLER PHASES
The FDC has three modes of operation, PC/AT
mode, PS/2 mode and Model 30 mode. These
are determined by the state of IDENT and MFM,
bits[3] and [2] respectively of L0-CRF0.
For simplicity, command handling in the FDC
can be divided into three phases: Command,
Execution, and Result. Each phase is described
in the following sections.
PC/AT MODE - (IDENT high, MFM a "don't
care")
The PC/AT register set is enabled, the DMA
enable bit of the DOR becomes valid (The
FDC’s IRQ and DRQ can be hi-Z), and TC and
DENSEL become active high signals.
COMMAND PHASE
After a reset, the FDC enters the command
phase and is ready to accept a command from
the host. For each of the commands, a defined
set of command code bytes and parameter
bytes has to be written to the FDC before the
command phase is complete. (Please refer to
TABLE 33 for the command set descriptions).
These bytes of data must be transferred in the
order prescribed.
PS/2 MODE - (IDENT low, MFM high)
This mode supports the PS/2 models 50/60/80
configuration and register set. The DMA bit of
the DOR becomes a "don't care", (the FDC’s
IRQ and DRQ are always valid), TC and
DENSEL become active low.
Before writing to the FDC, the host must
examine the RQM and DIO bits of the Main
Status Register. RQM and DIO must be equal
to "1" and "0" respectively before command
bytes may be written. RQM is set false by the
FDC after each write cycle until the received
MODEL 30 MODE - (IDENT low, MFM low)
This mode supports PS/2 Model 30
configuration and register set. The DMA enable
bit of the DOR becomes valid (The FDC’s IRQ
47
Non-DMA Mode - Transfers from the FIFO to
the Host
byte is processed. The FDC asserts RQM again
to request each parameter byte of the command
unless an illegal command condition is
detected.
After the last parameter byte is
received, RQM remains "0" and the FDC
automatically enters the next phase as defined
by the command definition.
The FDC’s IRQ pin and RQM bits in the Main
Status Register are activated when the FIFO
contains (16-<threshold>) bytes or the last bytes
of a full sector have been placed in the FIFO.
The FDC’s IRQ pin can be used for interruptdriven systems, and RQM can be used for
polled systems. The host must respond to the
request by reading data from the FIFO. This
process is repeated until the last byte is
transferred out of the FIFO. The FDC will
deactivate the FDC’s IRQ pin and RQM bit when
the FIFO becomes empty.
The FIFO is disabled during the command
phase to provide for the proper handling of the
"Invalid Command" condition.
EXECUTION PHASE
All data transfers to or from the FDC occur
during the execution phase, which can proceed
in DMA or non-DMA mode as indicated in the
Specify command.
Non-DMA Mode - Transfers from the Host to the
FIFO
The FDC’s IRQ pin and RQM bit in the Main
Status Register are activated upon entering the
execution phase of data transfer commands.
The host must respond to the request by writing
data into the FIFO. The FDC’s IRQ pin and
RQM bit remain true until the FIFO becomes
full. They are set true again when the FIFO has
<threshold> bytes remaining in the FIFO. The
FDC’s IRQ pin will also be deactivated if TC and
nDACK both go inactive. The FDC enters the
result phase after the last byte is taken by the
FDC from the FIFO (i.e. FIFO empty condition).
After a reset, the FIFO is disabled. Each data
byte is transferred by an FDC IRQ or DRQ
depending on the DMA mode. The Configure
command can enable the FIFO and set the
FIFO threshold value.
The following paragraphs detail the operation of
the FIFO flow control. In these descriptions,
<threshold> is defined as the number of bytes
available to the FDC when service is requested
from the host and ranges from 1 to 16. The
parameter FIFOTHR, which the user programs,
is one less and ranges from 0 to 15.
DMA Mode - Transfers from the FIFO to the
Host
A low threshold value (i.e. 2) results in longer
periods of time between service requests, but
requires faster servicing of the request for both
read and write cases. The host reads (writes)
from (to) the FIFO until empty (full), then the
transfer request goes inactive. The host must
be very responsive to the service request. This
is the desired case for use with a "fast" system.
The FDC activates the FDC’s DRQ pin when the
FIFO contains (16 - <threshold>) bytes, or the
last byte of a full sector transfer has been
placed in the FIFO. The DMA controller must
respond to the request by reading data from the
FIFO. The FDC will deactivate the FDC’s DRQ
pin when the FIFO becomes empty. FDC’s
DRQ goes inactive after nDACK goes active for
the last byte of a data transfer (or on the active
edge of nIOR, on the last byte, if no edge is
present on nDACK). A data underrun may
A high value of threshold (i.e. 12) is used with a
"sluggish" system by affording a long latency
period after a service request, but results in
more frequent service requests.
48
Note that when the host is sending data to the
FIFO of the FDC, the internal sector count will
be complete when the FDC reads the last byte
from its side of the FIFO. There may be a delay
in the removal of the transfer request signal of
up to the time taken for the FDC to read the last
16 bytes from the FIFO. The host must tolerate
this delay.
occur if the FDC’s DRQ is not removed in time
to prevent an unwanted cycle.
DMA Mode - Transfers from the Host to the
FIFO
The FDC activates the FDC’s DRQ pin when
entering the execution phase of the data transfer
commands. The DMA controller must respond
by activating the nDACK and nIOW pins placing
data in the FIFO.
The FDC’s DRQ remains
active until the FIFO becomes full. The FDC’s
DRQ is again set true when the FIFO has
<threshold> bytes remaining in the FIFO. The
FDC will also deactivate the FDC’s DRQ pin
when TC becomes true (qualified by nDACK),
indicating that no more data is required. The
FDC’s DRQ goes inactive after nDACK goes
active for the last byte of a data transfer (or on
the active edge of nIOW of the last byte, if no
edge is present on nDACK). A data overrun
may occur if the FDC’s DRQ is not removed in
time to prevent an unwanted cycle.
Data Transfer Termination
RESULT PHASE
The generation of the FDC’s IRQ determines the
beginning of the result phase. For each of the
commands, a defined set of result bytes has to
be read from the FDC before the result phase is
complete. These bytes of data must be read out
for another command to start.
RQM and DIO must both equal "1" before the
result bytes may be read. After all the result
bytes have been read, the RQM and DIO bits
switch to "1" and "0" respectively, and the CB bit
is cleared, indicating that the FDC is ready to
accept the next command.
The FDC supports terminal count explicitly
through the TC pin and implicitly through the
underrun/overrun and end-of-track (EOT)
functions. For full sector transfers, the EOT
parameter can define the last sector to be
transferred in a single or multi-sector transfer.
COMMAND SET/DESCRIPTIONS
Commands can be written whenever the FDC is
in the command phase. Each command has a
unique set of needed parameters and status
results. The FDC checks to see that the first
byte is a valid command and, if valid, proceeds
withthe command. If it is invalid, an interrupt is
issued. The user sends a Sense Interrupt
Status command which returns an invalid
command error.
Refer to Table 33 for
explanations of the various symbols used.
TABLE 34 lists the required parameters and the
results associated with each command that the
FDC is capable of performing.
If the last sector to be transferred is a partial
sector, the host can stop transferring the data in
mid-sector, and the FDC will continue to
complete the sector as if a hardware TC was
received. The only difference between these
implicit functions and TC is that they return
"abnormal termination" result status.
Such
status indications can be ignored if they were
expected.
49
TABLE 33 - DESCRIPTION OF THE FDC COMMAND SYMBOLS
NAME
DESCRIPTION
Cylinder Address The currently selected address; 0 to 255.
Data Pattern
The pattern to be written in each sector data field during
formatting.
D0, D1, D2, Drive Select 0-3
Designates which drives are perpendicular drives on the
D3
Perpendicular Mode Command. A "1" indicates a perpendicular
drive.
DIR
Direction Control If this bit is 0, then the head will step out from the spindle during a
relative seek. If set to a 1, the head will step in toward the spindle.
DS0, DS1 Disk Drive Select
DS1
DS0
DRIVE
SYMBOL
C
D
0
1
0
1
0
0
1
1
DTL
Special Sector
Size
EC
Enable Count
EFIFO
Enable FIFO
EIS
Enable Implied
Seek
EOT
GAP
GPL
End of Track
H/HDS
Head Address
HLT
Gap Length
Head Load Time
drive 0
drive 1
drive 2
drive 3
By setting N to zero (00), DTL may be used to control the number
of bytes transferred in disk read/write commands. The sector size
(N = 0) is set to 128. If the actual sector (on the diskette) is larger
than DTL, the remainder of the actual sector is read but is not
passed to the host during read commands; during write
commands, the remainder of the actual sector is written with all
zero bytes. The CRC check code is calculated with the actual
sector. When N is not zero, DTL has no meaning and should be
set to FF HEX.
When this bit is "1" the "DTL" parameter of the Verify command
becomes SC (number of sectors per track).
This active low bit when a 0, enables the FIFO. A "1" disables the
FIFO (default).
When set, a seek operation will be performed before executing any
read or write command that requires the C parameter in the
command phase. A "0" disables the implied seek.
The final sector number of the current track.
Alters Gap 2 length when using Perpendicular Mode.
The Gap 3 size. (Gap 3 is the space between sectors excluding
the VCO synchronization field).
Selected head: 0 or 1 (disk side 0 or 1) as encoded in the sector
ID field.
The time interval that the FDC waits after loading the head and
before initializing a read or write operation. Refer to the Specify
command for actual delays.
50
SYMBOL
HUT
NAME
Head Unload
Time
LOCK
MFM
MT
N
NCN
ND
MFM/FM Mode
Selector
Multi-Track
Selector
Sector Size Code
New Cylinder
Number
Non-DMA Mode
Flag
OW
Overwrite
PCN
Present Cylinder
Number
Polling Disable
POLL
DESCRIPTION
The time interval from the end of the execution phase (of a read or
write command) until the head is unloaded. Refer to the Specify
command for actual delays.
Lock defines whether EFIFO, FIFOTHR, and PRETRK parameters
of the CONFIGURE COMMAND can be reset to their default
values by a "software Reset". (A reset caused by writing to the
appropriate bits of either tha DSR or DOR)
A one selects the double density (MFM) mode. A zero selects
single density (FM) mode.
When set, this flag selects the multi-track operating mode. In this
mode, the FDC treats a complete cylinder under head 0 and 1 as
a single track. The FDC operates as this expanded track started
at the first sector under head 0 and ended at the last sector under
head 1. With this flag set, a multitrack read or write operation will
automatically continue to the first sector under head 1 when the
FDC finishes operating on the last sector under head 0.
This specifies the number of bytes in a sector. If this parameter is
"00", then the sector size is 128 bytes. The number of bytes
transferred is determined by the DTL parameter. Otherwise the
sector size is (2 raised to the "N'th" power) times 128. All values
up to "07" hex are allowable. "07"h would equal a sector size of
16k. It is the user's responsibility to not select combinations that
are not possible with the drive.
N
SECTOR SIZE
128 bytes
256 bytes
512 bytes
1024 bytes
...
...
07
16 Kbytes
The desired cylinder number.
When set to 1, indicates that the FDC is to operate in the nonDMA mode. In this mode, the host is interrupted for each data
transfer. When set to 0, the FDC operates in DMA mode,
interfacing to a DMA controller by means of the DRQ and nDACK
signals.
The bits D0-D3 of the Perpendicular Mode Command can only be
modified if OW is set to 1. OW id defined in the Lock command.
The current position of the head at the completion of Sense
Interrupt Status command.
When set, the internal polling routine is disabled. When clear,
polling is enabled.
51
SYMBOL
PRETRK
R
RCN
SC
SK
SRT
ST0
ST1
ST2
ST3
WGATE
NAME
Precompensation
Start Track
Number
Sector Address
DESCRIPTION
Programmable from track 00 to FFH.
The sector number to be read or written. In multi-sector transfers,
this parameter specifies the sector number of the first sector to be
read or written.
Relative Cylinder Relative cylinder offset from present cylinder as used by the
Number
Relative Seek command.
Number of
The number of sectors per track to be initialized by the Format
Sectors Per Track command. The number of sectors per track to be verified during a
Verify command when EC is set.
Skip Flag
When set to 1, sectors containing a deleted data address mark will
automatically be skipped during the execution of Read Data. If
Read Deleted is executed, only sectors with a deleted address
mark will be accessed. When set to "0", the sector is read or
written the same as the read and write commands.
Step Rate Interval The time interval between step pulses issued by the FDC.
Programmable from 0.5 to 8 milliseconds in increments of 0.5 ms
at the 1 Mbit data rate. Refer to the SPECIFY command for actual
delays.
Status 0
Registers within the FDC which store status information after a
Status 1
command has been executed. This status information is available
Status 2
to the host during the result phase after command execution.
Status 3
Write Gate
Alters timing of WE to allow for pre-erase loads in perpendicular
drives.
52
FDC INSTRUCTION SET
PHASE
Command
R/W
W
W
W
W
W
W
W
W
W
Execution
Result
R
R
R
R
R
R
R
TABLE 34 - FDC INSTRUCTION SET
READ DATA
DATA BUS
D7
D6
D5 D4 D3 D2 D1 D0
REMARKS
MT MFM SK
0
0
1
1
0 Command Codes
0
0
0
0
0 HDS DS1 DS0
-------- C -------Sector ID information prior
to Command execution.
-------- H --------------- R --------------- N -------------- EOT ------------- GPL ------------- DTL ------Data transfer between the
FDD and system.
------- ST0 ------Status information after
Command execution.
------- ST1 ------------- ST2 -------------- C -------Sector ID information after
Command execution.
-------- H --------------- R --------------- N --------
53
PHASE
Command
R/W
W
W
W
D7
MT
0
W
W
W
W
W
W
Execution
PHASE
R/W
R
R
R
R
R
D7
READ DELETED DATA
DATA BUS
D6
D5 D4 D3 D2 D1 D0
REMARKS
MFM SK
0
1
1
0
0 Command Codes
0
0
0
0 HDS DS1 DS0
-------- C -------Sector ID information prior to
Command execution.
-------- H --------------- R --------------- N -------------- EOT ------------- GPL ------------- DTL ------Data transfer between the
FDD and system.
DATA BUS
D6 D5 D4 D3 D2 D1 D0 REMARKS
------- ST2 -------------- C -------Sector ID information after
Command execution.
-------- H --------------- R --------------- N --------
54
PHASE
Command
R/W
W
W
W
W
W
W
W
W
W
Execution
Result
R
R
R
R
R
R
R
D7
MT
0
D6
MFM
0
WRITE DATA
DATA BUS
D5 D4 D3 D2 D1 D0
REMARKS
0
0
0
1
0
1 Command Codes
0
0
0 HDS DS1 DS0
-------- C -------Sector ID information prior to
Command execution.
-------- H --------------- R --------------- N -------------- EOT ------------- GPL ------------- DTL ------Data transfer between the
FDD and system.
------- ST0 ------Status information after
Command execution.
------- ST1 ------------- ST2 -------------- C -------Sector ID information after
Command execution.
-------- H --------------- R --------------- N --------
55
PHASE
Command
R/W
W
W
W
W
W
W
W
W
W
WRITE DELETED DATA
DATA BUS
D7
D6
D5 D4 D3
D2
D1
MT MFM 0
0
1
0
0
0
0
0
0
0
HDS DS1
-------- C --------
REMARKS
Command Codes
Sector ID information
prior to Command
execution.
-------- H --------------- R --------------- N -------------- EOT ------------- GPL ------------- DTL -------
Execution
Result
D0
1
DS0
R
------- ST0 -------
R
R
R
------- ST1 ------------- ST2 -------------- C --------
R
R
R
-------- H --------------- R --------------- N --------
56
Data transfer between
the FDD and system.
Status information after
Command execution.
Sector ID information
after Command
execution.
PHASE
Command
R/W
W
W
W
D7
0
0
D6
MFM
0
W
W
W
W
W
W
PHASE
R/W
R
R
R
R
R
R
D7
D6
READ A TRACK
DATA BUS
D5 D4 D3
D2
0
0
0
0
0
0
0
HDS
-------- C --------
-------- H --------------- R --------------- N -------------- EOT ------------- GPL ------------- DTL ------DATA BUS
D5
D4
D3
D2
------- ST1 ------------- ST2 -------------- C --------
-------- H --------------- R --------------- N --------
57
D1
1
DS1
D0
0
DS0
REMARKS
Command Codes
Sector ID information
prior to Command
execution.
D1
D0
REMARKS
Sector ID information
after Command
execution.
PHASE
Command
R/W
W
W
W
W
W
W
W
W
W
D7
D6
MT MFM
EC
0
VERIFY
DATA BUS
D5 D4 D3
D2
SK
1
0
1
0
0
0
HDS
-------- C --------
D0
0
DS0
REMARKS
Command Codes
Sector ID information
prior to Command
execution.
-------- H --------------- R --------------- N -------------- EOT ------------- GPL ------------ DTL/SC ------
Execution
Result
D1
1
DS1
R
------- ST0 -------
R
R
R
------- ST1 ------------- ST2 -------------- C --------
R
R
R
-------- H --------------- R --------------- N --------
58
No data transfer takes
place.
Status information after
Command execution.
Sector ID information
after Command
execution.
PHASE
Command
Result
R/W
W
R
D7
0
1
D6
0
0
PHASE
Command
R/W
W
W
W
W
W
W
D7
0
0
D6
MFM
0
Execution for
Each Sector
Repeat:
Result
VERSION
DATA BUS
D5 D4 D3
D2
D1
0
1
0
0
0
0
1
0
0
0
FORMAT A TRACK
DATA BUS
D5 D4 D3
D2
D1
0
0
1
1
0
0
0
0
HDS DS1
-------- N --------------- SC -------------- GPL -------------- D --------
W
-------- C --------
W
W
W
-------- H --------------- R --------------- N --------
R
------- ST0 -------
R
R
R
R
R
R
------- ST1 ------------- ST2 ------------ Undefined ----------- Undefined ----------- Undefined ----------- Undefined ------
59
D0
0
0
D0
1
DS0
REMARKS
Command Code
Enhanced Controller
REMARKS
Command Codes
Bytes/Sector
Sectors/Cylinder
Gap 3
Filler Byte
Input Sector
Parameters
FDC formats an entire
cylinder
Status information after
Command execution
PHASE
Command
R/W
W
W
D7
0
0
D6
0
0
D5
0
0
RECALIBRATE
DATA BUS
D4 D3 D2
D1
0
0
1
1
0
0
0
DS1
D0
1
DS0
Execution
PHASE
Command
Result
Head retracted to Track 0
Interrupt.
R/W
W
R
D7
0
SENSE INTERRUPT STATUS
DATA BUS
D6 D5 D4 D3 D2 D1 D0
0
0
0
1
0
0
0
------- ST0 -------
R
PHASE
Command
PHASE
Command
Result
PHASE
Command
REMARKS
Command Codes
R/W
W
W
W
R/W
W
W
R
R/W
W
W
W
REMARKS
Command Codes
Status information at the end
of each seek operation.
------- PCN ------SPECIFY
DATA BUS
D7 D6 D5 D4 D3 D2 D1 D0
REMARKS
0
0
0
0
0
0
1
1 Command Codes
--- SRT ----- HUT -------- HLT -----ND
D7
0
0
D7
0
0
D6
0
0
D6
0
0
SENSE DRIVE STATUS
DATA BUS
D5 D4 D3
D2
D1
0
0
0
1
0
0
0
0
HDS DS1
------- ST3 -------
SEEK
DATA BUS
D5 D4 D3
D2
0
0
1
1
0
0
0
HDS
------- NCN -------
Execution
D1
1
DS1
D0
0
DS0
REMARKS
Command Codes
Status information about
FDD
D0
1
DS0
REMARKS
Command Codes
Head positioned over
proper cylinder on
diskette.
60
PHASE
Command
R/W
W
D7
0
0
0
Execution
W
W
W
PHASE
Command
PHASE
Command
Execution
Result
R/W
W
W
W
R/W
W
R
R
R
R
R
R
R
R
R
R
D7
1
0
D6
0
D5
0
CONFIGURE
DATA BUS
D4
D3
1
0
D2
0
D1
1
D0
1
REMARKS
Configure
Information
0
0
0
0
0
0
0
EIS EFIFO POLL
--- FIFOTHR ----------- PRETRK ---------
D6
DIR
0
D7
0
LOCK
0
RELATIVE SEEK
DATA BUS
D5 D4 D3
D2
D1
0
0
1
1
1
0
0
0
HDS DS1
------- RCN -------
D6
0
DUMPREG
DATA BUS
D5
D4
D3 D2
0
0
1
1
D0
1
DS0
D1
1
REMARKS
D0
0
------ PCN-Drive 0 ------------ PCN-Drive 1 ------------ PCN-Drive 2 ------------ PCN-Drive 3 ---------- SRT ------ HUT --------- HLT ------ND
------- SC/EOT ------0
D3
D2
D1 D0
GAP WGATE
EIS EFIFO POLL
-- FIFOTHR --------- PRETRK --------
61
REMARKS
*Note:
Registers
placed in
FIFO
PHASE
Command
R/W
W
W
D7
0
0
D6
MFM
0
D5
0
0
READ ID
DATA BUS
D4 D3
D2
0
1
0
0
0
HDS
D1
1
DS1
Execution
Result
R
-------- ST0 --------
D0
0
DS0
REMARKS
Commands
The first correct ID
information on the
Cylinder is stored in
Data Register
Status information after
Command execution.
Disk status after the
Command has
completed
R
R
R
R
R
R
PHASE
Command
R/W
W
-------- ST1 --------------- ST2 --------------- C --------------- H --------------- R --------------- N --------
D7
0
OW
PERPENDICULAR MODE
DATA BUS
D6 D5 D4 D3 D2
D1
0
0
1
0
0
1
0
D3 D2 D1 D0
GAP
62
D0
0
WGATE
REMARKS
Command Codes
PHASE
Command
R/W
W
Result
R
PHASE
Command
Result
R/W
W
R
D7
INVALID CODES
DATA BUS
D6 D5 D4 D3 D2 D1
----- Invalid Codes -----
D0
REMARKS
Invalid Command Codes
(NoOp - FDC goes into
Standby State)
ST0 = 80H
------- ST0 -------
D7
LOCK
0
D6
0
0
LOCK
DATA BUS
D5
D4
D3
0
1
0
0
LOCK
0
D2
1
0
D1
0
0
D0
0
0
REMARKS
Command Codes
SC is returned if the last command that was issued was the Format command. EOT is returned if the
last command was a Read or Write.
Note: These bits are used internally only. They are not reflected in the Drive Select pins. It is the
user's responsibility to maintain correspondence between these bits and the Drive Select pins (DOR).
63
FDC DATA TRANSFER COMMANDS
Drive Busy bit for the drive will go active in the
Main Status Register during the seek portion of
the command. If the seek portion fails, it will be
reflected in the results status normally returned
for a Read/Write Data command.
Status
Register 0 (ST0) would contain the error code
and C would contain the cylinder on which the
seek failed.
All of the Read Data, Write Data and Verify type
commands use the same parameter bytes and
return the same results information, the only
difference being the coding of bits 0-4 in the first
byte.
An implied seek will be executed if the feature
was enabled by the Configure command. This
seek is completely transparent to the user. The
TABLE 35 - FDC SECTOR SIZES
N
SECTOR SIZE
128 bytes
00
256 bytes
01
512 bytes
02
1024 bytes
03
...
..
16 Kbytes
07
READ DATA
A set of nine (9) bytes is required to place the
FDC in the Read Data Mode. After the Read
Data command has been issued, the FDC loads
the head (if it is in the unloaded state), waits the
specified head settling time (defined in the
Specify command), and begins reading ID
Address Marks and ID fields. When the sector
address read off the diskette matches with the
sector address specified in the command, the
FDC reads the sector's data field and transfers
the data to the FIFO.
N determines the number of bytes per sector
(see TABLE 35 above). If N is set to zero, the
sector size is set to 128. The DTL value
determines the number of bytes to be
transferred. If DTL is less than 128, the FDC
transfers the specified number of bytes to the
host. For reads, it continues to read the entire
128-byte sector and checks for CRC errors. For
writes, it completes the 128-byte sector by filling
in zeros. If N is not set to 00 Hex, DTL should
be set to FF Hex and has no impact on the
number of bytes transferred.
After completion of the read operation from the
current sector, the sector address is
incremented by one and the data from the next
logical sector is read and output via the FIFO.
This continuous read function is called "MultiSector Read Operation". Upon receipt of TC, or
an implied TC (FIFO overrun/underrun), the
FDC stops sending data but will continue to
read data from the current sector, check the
CRC bytes, and at the end of the sector,
terminate the Read Data Command.
The amount of data which can be handled with
a single command to the FDC depends upon
MT (multi-track) and N (number of bytes/sector).
The Multi-Track function (MT) allows the FDC to
read data from both sides of the diskette. For a
particular cylinder, data will be transferred
starting at Sector 1, Side 0 and completing the
last sector of the same track at Side 1.
64
ND bit in Status Register 1 to "1" indicating a
sector not found, and terminates the Read Data
Command. After reading the ID and Data Fields
in each sector, the FDC checks the CRC bytes.
Ifa CRC error occurs in the ID or data field, the
FDC sets the IC code in Status Register 0 to
"01" indicating abnormal termination, sets the
DE bit flag in Status Register 1 to "1", sets the
DD bit in Status Register 2 to "1" if CRC is
incorrect in the ID field, and terminates the Read
Data Command.
If the host terminates a read or write operation
in the FDC, the ID information in the result
phase is dependent upon the state of the MT bit
and EOT byte.
At the completion of the Read Data command,
the head is not unloaded until after the Head
Unload Time Interval (specified in the Specify
command) has elapsed. If the host issues
another command before the head unloads,
then the head settling time may be saved
between subsequent reads.
TABLE 40 - VERIFY COMMAND RESULT
PHASE TABLE describes the effect of the SK
bit on the Read Data command execution and
results. Except where noted in TABLE 36, the C
or R value of the sector address is automatically
incremented (see TABLE 42).
If the FDC detects a pulse on the nINDEX pin
twice without finding the specified sector
(meaning that the diskette's index hole passes
through index detect logic in the drive twice), the
FDC sets the IC code in Status Register 0 to
"01" indicating abnormal termination, sets the
MT
0
1
0
1
0
1
SK BIT
VALUE
0
1
N
1
1
2
2
3
3
TABLE 36 - EFFECTS OF MT AND N BITS
MAXIMUM TRANSFER
FINAL SECTOR READ
CAPACITY
FROM DISK
256 x 26 = 6,656
26 at side 0 or 1
256 x 52 = 13,312
26 at side 1
512 x 15 = 7,680
15 at side 0 or 1
512 x 30 = 15,360
15 at side 1
1024 x 8 = 8,192
8 at side 0 or 1
1024 x 16 = 16,384
16 at side 1
TABLE 37 - SKIP BIT VS READ DATA COMMAND
DATA ADDRESS
MARK TYPE
ENCOUNTERED
RESULTS
SECTOR CM BIT OF
DESCRIPTION OF
READ?
ST2 SET?
RESULTS
Normal Data
Yes
No
Normal termination
Deleted Data
No
Yes
Normal termination.
Sector not read
("skipped")
65
READ DELETED DATA
This command is the same as the Read Data
command, only it operates on sectors that
contain a Deleted Data Address Mark at the
beginning of a Data Field.
TABLE 41 describes the effect of the SK bit on
the Read Deleted Data command execution and
results. Except where noted in TABLE 41, the C
or R value of the sector address is automatically
incremented (seeTABLE 42).
TABLE 38 - SKIP BIT VS. READ DELETED DATA COMMAND
DATA ADDRESS
SK BIT
MARK TYPE
VALUE
ENCOUNTERED
RESULTS
SECTOR CM BIT OF
DESCRIPTION
READ?
ST2 SET?
OF RESULTS
0
Normal Data
Yes
Yes
Address not
incremented.
Next sector not
searched for
0
Deleted Data
Yes
No
Normal
termination
1
Normal Data
No
Yes
Normal
termination.
Sector not read
("skipped")
1
Deleted Data
Yes
No
Normal
termination
66
READ A TRACK
no comparison. Multi-track or skip operations
are not allowed with this command. The MT
and SK bits (bits D7 and D5 of the first
command byte respectively) should always be
set to "0".
This command is similar to the Read Data
command except that the entire data field is
read continuously from each of the sectors of a
track. Immediately after encountering a pulse
on the nINDEX pin, the FDC starts to read all
data fields on the track as continuous blocks of
data without regard to logical sector numbers. If
the FDC finds an error in the ID or DATA CRC
check bytes, it continues to read data from the
track and sets the appropriate error bits at the
end of the command. The FDC compares the
ID information read from each sector with the
specified value in the command and sets the
ND flag of Status Register 1 to a "1" if there is
MT
HEAD
This command terminates when the EOT
specified number of sectors has not been read.
If the FDC does not find an ID Address Mark on
the diskette after the second occurrence of a
pulse on the IDX pin, then it sets the IC code in
Status Register 0 to "01" (abnormal
termination), sets the MA bit in Status Register
1 to "1", and terminates the command.
TABLE 39 - RESULT PHASE TABLE
FINAL SECTOR
TRANSFERRED TO
HOST
ID INFORMATION AT RESULT PHASE
C
H
R
N
Less than EOT
NC
NC
R+1
NC
0
0
Equal to EOT
Less than EOT
C+1
NC
NC
NC
01
R+1
NC
NC
Equal to EOT
Less than EOT
C+1
NC
NC
NC
01
R+1
NC
NC
Equal to EOT
Less than EOT
NC
NC
LSB
NC
01
R+1
NC
NC
C+1
LSB
01
NC
1
0
1
1
Equal to EOT
NC: No Change, the same value as the one at the beginning of command execution.
LSB: Least Significant Bit, the LSB of H is complemented.
67
WRITE DATA
Transfer Capacity
After the Write Data command has been
issued, the FDC loads the head (if it is in the
unloaded state), waits the specified head load
time if unloaded (defined in the Specify
command), and begins reading ID fields.
When the sector address read from the
diskette matches the sector address specified
in the command, the FDC reads the data from
the host via the FIFO and writes it to the
sector's data field.
EN (End of Cylinder) bit
ND (No Data) bit
Head Load, Unload Time Interval
ID information when the host terminates the
command
Definition of DTL when N = 0 and when N does
not = 0.
After writing data into the current sector, the
FDC computes the CRC value and writes it
into the CRC field at the end of the sector
transfer. The Sector Number stored in "R" is
incremented by one, and the FDC continues
writing to the next data field. The FDC
continues this "Multi-Sector Write Operation".
Upon receipt of a terminal count signal or if a
FIFO over/under run occurs while a data field
is being written, then the remainder of the data
field is filled with zeros.
The FDC reads the ID field of each sector and
checks the CRC bytes. If it detects a CRC
error in one of the ID fields, it sets the IC code
in Status Register 0 to "01" (abnormal
termination), sets the DE bit of Status Register
1 to "1", and terminates the Write Data
command.
The Write Data command operates in much
the same manner as the Read Data
command. The following items are the same.
Please refer to the Read Data Command for
details:
WRITE DELETED DATA
This command is almost the same as the Write
Data command except that a Deleted Data
Address Mark is written at the beginning of the
Data Field instead of the normal Data Address
Mark. This command is typically used to mark a
bad sector containing an error on the floppy disk.
VERIFY
The Verify command is used to verify the data
stored on a disk. This command acts exactly like
a Read Data command except that no data is
transferred to the host. Data is read from the disk
and CRC is computed and checked against the
previously-stored value.
Because data is not transferred to the host, TC
(pin 94) cannot be used to terminate this
command. By setting the EC bit to "1", an implicit
TC will be issued to the FDC. This implicit TC
will occur when the SC value has decremented
to 0 (an SC value of 0 will verify 256 sectors).
This command can also be terminated by setting
the EC bit to "0" and the EOT value equal to the
final sector to be checked. If EC is set to "0",
DTL/SC should be programmed to 0FFH. Refer
to TABLE 42 and TABLE 43 for information
concerning the values of MT and EC versus SC
and EOT value.
68
Definitions:
# Sectors Per Side = Number of formatted sectors per each side of the disk.
# Sectors Remaining = Number of formatted sectors left which can be read, including side 1 of the
disk if MT is set to "1".
MT
0
0
0
0
1
1
1
1
TABLE 40 - VERIFY COMMAND RESULT PHASE TABLE
EC
SC/EOT VALUE
TERMINATION RESULT
0
SC = DTL
Success Termination
Result Phase Valid
EOT ≤ # Sectors Per Side
0
SC = DTL
Unsuccessful Termination
EOT > # Sectors Per Side
Result Phase Invalid
1
Successful Termination
SC ≤ # Sectors Remaining AND
Result Phase Valid
EOT ≤ # Sectors Per Side
1
SC > # Sectors Remaining OR
Unsuccessful Termination
EOT > # Sectors Per Side
Result Phase Invalid
0
SC = DTL
Successful Termination
Result Phase Valid
EOT ≤ # Sectors Per Side
0
SC = DTL
Unsuccessful Termination
EOT > # Sectors Per Side
Result Phase Invalid
1
Successful Termination
SC ≤ # Sectors Remaining AND
Result Phase Valid
EOT ≤ # Sectors Per Side
1
SC > # Sectors Remaining OR
Unsuccessful Termination
EOT > # Sectors Per Side
Result Phase Invalid
NOTE: If MT is set to "1" and the SC value is greater than the number of remaining formatted sectors
on Side 0, verifying will continue on Side 1 of the disk.
FORMAT A TRACK
The Format command allows an entire track to
be formatted. After a pulse from the IDX pin is
detected, the FDC starts writing data on the disk
including gaps, address marks, ID fields, and
data fields per the IBM System 34 or 3740
format (MFM or FM respectively). The particular
values that will be written to the gap and data
field are controlled by the values programmed
into N, SC, GPL, and D which are specified by
the host during the command phase. The data
field of the sector is filled with the data byte
specified by D. The ID field for each sector is
supplied by the host; that is, four data bytes per
sector are needed by the FDC for C, H, R, and
N (cylinder, head, sector number and sector size
respectively).
After formatting each sector, the host must send
new values for C, H, R and N to the FDC for the
next sector on the track. The R value (sector
number) is the only value that must be changed
by the host after each sector is formatted. This
allows the disk to be formatted with
nonsequential sector addresses (interleaving).
This incrementing and formatting continues for
the whole track until the FDC encounters a pulse
on the IDX pin again and it terminates the
command.
69
and the number of sectors on each track.
Actual values can vary due to drive electronics.
TABLE 45 contains typical values for gap fields
which are dependent upon the size of the sector
TABLE 41 - DISKETTE FORMAT FIELDS
SYSTEM 34 (DOUBLE DENSITY) FORMAT
GAP4a
80x
4E
SYNC
12x
00
IAM
GAP1 SYNC
12x
50x
00
4E
3x FC
C2
IDAM
C
Y
L
H
D
S
E
C
N
O
C
R
C
GAP2 SYNC
12x
22x
00
4E
3x FE
A1
DATA
AM
DATA
C
R
C
GAP3 GAP 4b
DATA
C
R
C
GAP3 GAP 4b
DATA
C
R
C
GAP3 GAP 4b
3x FB
A1 F8
SYSTEM 3740 (SINGLE DENSITY) FORMAT
GAP4a
40x
FF
SYNC
6x
00
IAM
GAP1 SYNC
6x
26x
00
FF
FC
IDAM
C
Y
L
H
D
S
E
C
N
O
C
R
C
GAP2 SYNC
6x
11x
00
FF
FE
DATA
AM
FB or
F8
PERPENDICULAR FORMAT
GAP4a
80x
4E
SYNC
12x
00
IAM
3x FC
C2
GAP1 SYNC
12x
50x
00
4E
IDAM
C
Y
L
H
D
S
E
C
3x FE
A1
N
O
C
R
C
GAP2 SYNC
12x
41x
00
4E
DATA
AM
3x FB
A1 F8
70
5.25"
Drives
3.5"
Drives
TABLE 42 - TYPICAL VALUES FOR FORMATTING
FORMAT SECTOR SIZE
N
SC
GPL1
07
12
00
128
10
10
00
128
18
08
02
512
46
04
03
1024
FM
C8
02
04
2048
C8
01
05
4096
0A
12
01
256
20
10
01
256
2A
09
02
512*
80
04
03
1024
MFM
C8
02
04
2048
C8
01
05
4096
07
0F
0
128
0F
09
1
FM
256
1B
05
2
512
0E
0F
1
256
1B
09
2
MFM
512**
35
05
3
1024
GPL2
09
19
30
87
FF
FF
0C
32
50
F0
FF
FF
1B
2A
3A
36
54
74
GPL1 = suggested GPL values in Read and Write commands to avoid splice point
between data field and ID field of contiguous sections.
GPL2 = suggested GPL value in Format A Track command.
*PC/AT values (typical)
**PS/2 values (typical). Applies with 1.0 MB and 2.0 MB drives.
NOTE: All values except sector size are in hex.
nINDEX pin, it then sets the IC code in Status
Register 0 to "01" (abnormal termination), sets
the MA bit in Status Register 1 to "1", and
terminates the command.
FDC CONTROL COMMANDS
Control commands differ from the other
commands in that no data transfer takes place.
Three commands generate an interrupt when
complete: Read ID, Recalibrate, and Seek. The
other control commands do not generate an
interrupt.
The following commands will generate an
interrupt upon completion. They do not return
any result bytes. It is highly recommended that
control commands be followed by the Sense
Interrupt Status command. Otherwise, valuable
interrupt status information will be lost.
READ ID
The Read ID command is used to find the
present position of the recording heads. The
FDC stores the values from the first ID field it is
able to read into its registers. If the FDC does
not find an ID address mark on the diskette after
the second occurrence of a pulse on the
RECALIBRATE
This command causes the read/write head
within the FDC to retract to the track 0 position.
The FDC clears the contents of the PCN counter
71
PCN < NCN:
Direction signal to drive set to
"1" (step in) and issues step pulses.
PCN > NCN:
Direction signal to drive set to
"0" (step out) and issues step pulses.
and checks the status of the nTR0 pin from the
FDD. As long as the nTR0 pin is low, the DIR
pin remains 0 and step pulses are issued.
When the nTR0 pin goes high, the SE bit in
Status Register 0 is set to "1" and the command
is terminated. If the nTR0 pin is still low after 79
step pulses have been issued, the FDC sets the
SE and the EC bits of Status Register 0 to "1"
and terminates the command. Disks capable of
handling more than 80 tracks per side may
require more than one Recalibrate command to
return the head back to physical Track 0.
The rate at which step pulses are issued is
controlled by SRT (Stepping Rate Time) in the
Specify command. After each step pulse is
issued, NCN is compared against PCN, and
when NCN = PCN the SE bit in Status Register
0 is set to "1" and the command is terminated.
During the command phase of the seek or
recalibrate operation, the FDC is in the BUSY
state, but during the execution phase it is in the
NON-BUSY state. At this time, another Seek or
Recalibrate command may be issued, and in
this manner, parallel seek operations may be
done on up to four drives at once. Note that if
implied seek is not enabled, the read and write
commands should be preceded by:
The Recalibrate command does not have a
result phase. The Sense Interrupt Status
command must be issued after the Recalibrate
command to effectively terminate it and to
provide verification of the head position (PCN).
During the command phase of the recalibrate
operation, the FDC is in the BUSY state, but
during the execution phase it is in a NON-BUSY
state.
At this time, another Recalibrate
command may be issued, and in this manner
parallel Recalibrate operations may be done on
up to four drives at once.
Seek command - Step to the proper track
Sense Interrupt Status command - Terminate
the Seek command
Read ID - Verify head is on proper track
Issue Read/Write command.
Upon power up, the software must issue a
Recalibrate command to properly initialize all
drives and the controller.
The Seek command does not have a result
phase. Therefore, it is highly recommended that
the Sense Interrupt Status command be issued
after the Seek command to terminate it and to
provide verification of the head position (PCN).
The H bit (Head Address) in ST0 will always
return to a "0". When exiting POWERDOWN
mode, the FDC clears the PCN value and the
status information to zero. Prior to issuing the
POWERDOWN command, it is highly
recommended that the user service all pending
interrupts through the Sense Interrupt Status
command.
SEEK
The read/write head within the drive is moved
from track to track under the control of the Seek
command. The FDC compares the PCN, which
is the current head position, with the NCN and
performs the following operation if there is a
difference:
72
Interrupt Status command must be issued
immediately after these commands to terminate
them and to provide verification of the head
position (PCN). The H (Head Address) bit in
ST0 will always return a "0". If a Sense Interrupt
Status is not issued, the drive will continue to be
BUSY and may affect the operation of the next
command.
SENSE INTERRUPT STATUS
An interrupt signal on the FDC’s IRQ pin is
generated by the FDC for one of the following
reasons:
Upon entering the Result Phase of:
Read Data command
Read A Track command
Read ID command
Read Deleted Data command
Write Data command
Format A Track command
Write Deleted Data command
Verify command
End of Seek, Relative Seek, or Recalibrate
command
SENSE DRIVE STATUS
Sense Drive Status obtains drive status
information. It has no execution phase and
goes directly to the result phase from the
command phase. Status Register 3 contains
the drive status information.
FDC requires a data transfer during the
execution phase in the non-DMA mode The
Sense Interrupt Status command resets the
interrupt signal and, via the IC code and SE bit
of Status Register 0, identifies the cause of the
interrupt.
TABLE 43
SE
0
1
1
SPECIFY
The Specify command sets the initial values for
each of the three internal times. The HUT
(Head Unload Time) defines the time from the
end of the execution phase of one of the
read/write commands to the head unload state.
The SRT (Step Rate Time) defines the time
interval between adjacent step pulses. Note that
the spacing between the first and second step
pulses may be shorter than the remaining step
pulses. The HLT (Head Load Time) defines the
time between when the Head Load signal goes
high and the read/write operation starts. The
values change with the data rate speed
selection and are documented in TABLE 44 Drive Control Delays (ms). The values are the
same for MFM and FM.
- INTERRUPT IDENTIFICATION
IC
INTERRUPT DUE TO
11
Polling
00
Normal termination of
Seek or Recalibrate
01
command
Abnormal termination of
Seek or Recalibrate
command
The Seek, Relative Seek, and Recalibrate
commands have no result phase. The Sense
73
0
1
..
E
F
2M
64
4
..
56
60
TABLE 44 - DRIVE CONTROL DELAYS(MS)
HUT
SRT
1M
500K 300K 250K
2M
1M
500K 300K
26.7
16
8
4
512
426
256
128
25
15
7.5
3.75
32
26.7
16
8
..
..
..
..
..
..
..
..
3.33
2
1
0.5
448
373
224
112
1.67
1
0.5
0.25
480
400
240
120
250K
32
30
..
4
2
HLT
00
01
02
..
7F
7F
2M
64
0.5
1
..
63
63.5
1M
128
1
2
..
126
127
500K
256
2
4
..
252
254
300K
426
3.3
6.7
..
420
423
250K
512
4
8
.
504
508
FDC will perform a Seek operation before
executing a read or write command. Defaults to
no implied seek.
The choice of DMA or non-DMA operations is
made by the ND bit. When this bit is "1", the
non-DMA mode is selected, and when ND is "0",
the DMA mode is selected. In DMA mode, data
transfers are signalled by the FDC’s DRQ pin.
Non-DMA mode uses the RQM bit and the
FDC’s IRQ pin to signal data transfers.
EFIFO - A "1" disables the FIFO (default). This
means data transfers are asked for on a byteby-byte basis. Defaults to "1", FIFO disabled.
The threshold defaults to "1".
CONFIGURE
POLL - Disable polling of the drives. Defaults to
"0", polling enabled. When enabled, a single
interrupt is generated after a reset. No polling is
performed while the drive head is loaded and
the head unload delay has not expired.
The Configure command is issued to select the
special features of the FDC. A Configure
command need not be issued if the default
values of the FDC meet the system
requirements.
FIFOTHR - The FIFO threshold in the execution
phase of read or write commands. This is
programmable from 1 to 16 bytes. Defaults to
one byte. A "00" selects one byte; "0F" selects
16 bytes.
Configure Default Values:
EIS - No Implied Seeks
EFIFO - FIFO Disabled
POLL - Polling Enabled
FIFOTHR - FIFO Threshold Set to 1 Byte
PRETRK - Pre-Compensation Set to Track 0
PRETRK - Pre-Compensation Start Track
Number. Programmable from track 0 to 255.
Defaults to track 0. A "00" selects track 0; "FF"
selects track 255.
EIS - Enable Implied Seek. When set to "1", the
74
that the FDC could position the head on using
Relative Seek will be 295 (D), the initial track +
255 (D). The maximum count that the head can
be moved with a single Relative Seek command
is 255 (D).
VERSION
The Version command checks to see if the
controller is an enhanced type or the older type
(765A). A value of 90 H is returned as the result
byte.
The internal register, PCN, will overflow as the
cylinder number crosses track 255 and will
contain 39 (D). The resulting PCN value is thus
(RCN + PCN) mod 256. Functionally, the FDC
starts counting from 0 again as the track
number goes above 255 (D). It is the user's
responsibility to compensate FDC functions
(precompensation
track
number)
when
accessing tracks greater than 255. The FDC
does not keep track that it is working in an
"extended track area" (greater than 255). Any
command issued will use the current PCN value
except for the Recalibrate command, which only
looks for the TRACK0 signal. Recalibrate will
return an error if the head is farther than 79 due
to its limitation of issuing a maximum of 80 step
pulses. The user simply needs to issue a
second Recalibrate command.
The Seek
command and implied seeks will function
correctly within the 44 (D) track (299-255) area
of the "extended track area". It is the user's
responsibility not to issue a new track position
that will exceed the maximum track that is
present in the extended area.
RELATIVE SEEK
The command is coded the same as for Seek,
except for the MSB of the first byte and the DIR
bit.
DIR
0
1
DIR
ACTION
Step Head Out
Step Head In
Head Step Direction Control
RCN
Relative
Cylinder
Number
that
determines how many tracks to step the head in
or out from the current track number. The
Relative Seek command differs from the Seek
command in that it steps the head the absolute
number of tracks specified in the command
instead of making a comparison against an
internal register. The Seek command is good
for drives that support a maximum of 256
tracks. Relative Seeks cannot be overlapped
with other Relative Seeks. Only one Relative
Seek can be active at a time. Relative Seeks
may be overlapped with Seeks and
Recalibrates. Bit 4 of Status Register 0 (EC)
will be set if Relative Seek attempts to step
outward beyond Track 0.
To return to the standard floppy range (0-255) of
tracks, a Relative Seek should be issued to
cross the track 255 boundary.
A Relative Seek can be used instead of the
normal Seek, but the host is required to
calculate the difference between the current
head location and the new (target) head
location. This may require the host to issue a
Read ID command to ensure that the head is
physically on the track that software assumes it
to be. Different FDC commands will return
different cylinder results which may be difficult
to keep track of with software without the Read
ID command.
As an example, assume that a floppy drive has
300 useable tracks. The host needs to read
track 300 and the head is on any track (0-255).
If a Seek command is issued, the head will stop
at track 255. If a Relative Seek command is
issued, the FDC
will move the head the
specified number of tracks, regardless of the
internal cylinder position register (but will
increment the register). If the head was on track
40
(d),
the
maximum
track
75
GAP = 1), VCOEN goes active after 43 bytes to
accommodate the increased Gap2 field size.
For both cases, and approximate two-byte
cushion is maintained from the beginning of the
sync field for the purposes of avoiding write
splices in the presence of motor speed variation.
PERPENDICULAR MODE
The Perpendicular Mode command should be
issued prior to executing Read/Write/Format
commands that access a disk drive with
perpendicular recording capability. With this
command, the length of the Gap2 field and VCO
enable timing can be altered to accommodate
the unique requirements of these drives. TABLE
54 describes the effects of the WGATE and
GAP bits for the Perpendicular Mode command.
Upon a reset, the FDC will default to the
conventional mode (WGATE = 0, GAP = 0).
For the Write Data case, the FDC activates
Write Gate at the beginning of the sync field
under the conventional mode. The controller
then writes a new sync field, data address mark,
data field, and CRC. With the pre-erase head of
the perpendicular drive, the write head must be
activated in the Gap2 field to insure a proper
write of the new sync field. For the 1 Mbps
perpendicular mode (WGATE = 1, GAP = 1), 38
bytes will be written in the Gap2 space. Since
the bit density is proportional to the data rate, 19
bytes will be written in the Gap2 field for the 500
Kbps perpendicular mode (WGATE = 1, GAP
=0).
It should be noted that none of the
alterations in Gap2 size, VCO timing, or Write
Gate timing affect normal program flow. The
information provided here is just for background
purposes and is not needed for normal
operation.
Once the Perpendicular Mode
command is invoked, FDC software behavior
from the user standpoint is unchanged.
Selection of the 500 Kbps and 1 Mbps
perpendicular modes is independent of the
actual data rate selected in the Data Rate Select
Register. The user must ensure that these two
data rates remain consistent.
The Gap2 and VCO timing requirements for
perpendicular recording type drives are dictated
by the design of the read/write head. In the
design of this head, a pre-erase head precedes
the normal read/write head by a distance of 200
micrometers. This works out to about 38 bytes
at a 1 Mbps recording density. Whenever the
write head is enabled by the Write Gate signal,
the pre-erase head is also activated at the same
time. Thus, when the write head is initially
turned on, flux transitions recorded on the media
for the first 38 bytes will not be preconditioned
with the pre-erase head since it has not yet been
activated. To accommodate this head activation
and deactivation time, the Gap2 field is
expanded to a length of 41 bytes. The format
field illustrates the change in the Gap2 field size
for the perpendicular format.
The perpendicular mode command is enhanced
to allow specific drives to be designated
Perpendicular
recording
drives.
This
enhancement allows data transfers between
Conventional and Perpendicular drives without
having to issue Perpendicular mode commands
between the accesses of the different drive
types, nor having to change write precompensation values.
When both GAP and WGATE bits of the
PERPENDICULAR MODE COMMAND are both
programmed to "0" (Conventional mode), then
D0, D1, D2, D3, and D4 can be programmed
independently to "1" for that drive to be set
automatically to Perpendicular mode. In this
mode the following set of conditions also apply:
On the read back by the FDC, the controller
must begin synchronization at the beginning of
the sync field. For the conventional mode, the
internal PLL VCO is enabled (VCOEN)
approximately 24 bytes from the start of the
Gap2 field. But, when the controller operates in
the 1 Mbps perpendicular mode (WGATE = 1,
76
1.
2.
3.
The GAP2 written to a perpendicular drive
during a write operation will depend upon
the programmed data rate.
The write pre-compensation given to a
perpendicular mode drive will be 0ns.
For D0-D3 programmed to "0" for
conventional mode drives any data written
will be at the currently programmed write
pre-compensation.
Software and hardware
following effect on the
MODE COMMAND:
1.
2.
Note:
Bits D0-D3 can only be overwritten
when OW is programmed as a "1". If either
GAP or WGATE is a "1" then D0-D3 are
ignored.
WGATE
0
0
1
1
resets have the
PERPENDICULAR
"Software" resets (via the DOR or DSR
registers) will only clear GAP and WGATE
bits to "0". D0-D3 are unaffected and retain
their previous value.
"Hardware" resets will clear all bits (GAP,
WGATE and D0-D3) to "0", i.e all
conventional mode.
TABLE 45 - EFFECTS OF WGATE AND GAP BITS
LENGTH OF GAP2
PORTION OF GAP 2 WRITTEN
GAP
MODE
FORMAT FIELD
BY WRITE DATA OPERATION
22 Bytes
0 Bytes
0
Conventional
22 Bytes
19 Bytes
1
Perpendicular
(500 Kbps)
22 Bytes
0 Bytes
Reserved
0
(Conventional)
41 Bytes
38 Bytes
Perpendicular
1
(1 Mbps)
77
LOCK
COMPATIBILITY
In order to protect systems with long DMA
latencies against older application software that
can disable the FIFO the LOCK Command has
been added. This command should only be
used by the FDC routines, and application
software should refrain from using it. If an
application calls for the FIFO to be disabled
then the CONFIGURE command should be
used. The LOCK command defines whether the
EFIFO, FIFOTHR, and PRETRK parameters of
the CONFIGURE command can be RESET by
the DOR and DSR registers. When the LOCK
bit is set to logic "1" all subsequent "software
RESETS by the DOR and DSR registers will not
change the previously set parameters to their
default values. All "hardware" RESET from the
RESET pin will set the LOCK bit to logic "0" and
return the EFIFO, FIFOTHR, and PRETRK to
their default values. A status byte is returned
immediately after issuing a a LOCK command.
This byte reflects the value of the LOCK bit set
by the command byte.
The FDC37N972 was designed with software
compatibility in mind. It is a fully backwardscompatible solution with the older generation
765A/B disk controllers.
The FDC also
implements on-board registers for compatibility
with the PS/2, as well as PC/AT and PC/XT,
FDC subsystems. After a hardware reset of the
FDC, all registers, functions and enhancements
default to a PC/AT, PS/2 or PS/2 Model 30
compatible operating mode, depending on how
the IDENT and MFM bits are configured by the
system BIOS.
PARALLEL PORT FDC
Refer to the Parallel Port Section for details.
HOT SWAPPABLE FDD CAPABILITY
The FDC output pins will tri-state whenever the
FDC Logical Device is powered-down or not
activated. In addition setting bit 7 of the FDD
Mode Configuration register (LD0_CRF0) will tristate the FDC output pins. Bit 7 only affects the
standard FDC interface, it has no effect on the
Parallel Port Floppy Interface.
ENHANCED DUMPREG
The DUMPREG command is designed to
support system run-time diagnostics and
application software development and debug.
To accommodate the LOCK command and the
enhanced
PERPENDICULAR
MODE
command the
eighth
byte
of the
DUMPREG command contains the data from
these two commands.
The following table illustrates the state of the
FDC and Parallel Port FDC pins for
combinations of 1) the FDC Output Control bit;
2) the Activate bit; and 3) the FDC powerdown
state.
TABLE - 46 FDC HOT SWAPPING STATE OF THE FDC AND PARALLEL PORT FDC PINS
FDD MODE
ACTIVATE
FDC IN POWER
PARALLEL PORT
REGISTER, BIT[7]
BIT
DOWN
FDC PINS
FDC PINS
X
0
X
Hi-Z
Hi-Z
X
1
Y
Hi-Z
Hi-Z
0
1
N
Active
Active
1
1
N
Hi-Z
Active
78
When the FDC is disabled, powered down or inactive the FDC output pins will tri-state allowing ‘hotswapping’ of the Floppy Disk Drive. The following table lists the five control/configuration
mechanisms that power down or deactivate the FDC logical device.
TABLE 47 - FDC HOT SWAPPING MECHANISMS
MECHANISM
FDC OUTPUT PINS STATE
TriTri-State
State
Tri-State
Tri-State
(Note 1)
0
X
1
1
FDC Logical Dev Activate bit
=0: FDC LD deactivated
=1: FDC LD activated
Refer to the description of the
FDC Logical Device
Configuration register 0x30 in
the Configuration section of the
FDC37N972 Specification.
VALID
VALID
INVALID
FDC Logical Dev Base Address X
BASE
BASE
BASE
0x100 < Base < 0x0FF8:
ADDRESS
ADDRESS ADDRESS
FDC LD Base Address Valid.
0xFFF < Base < 0x100:
FDC LD Base Address Invalid.
Refer to the description of the
FDC Base I/O Address
registers in the Configuration
section of the FDC37N972
Specification.
GCR 0x22 bit-0 (FDC Power)
=0: Power Off
=1: Power On
Refer to the description of the
Global Config Register 0x22 in
the Configuration section of the
FDC37N972 Specification.
DSR, bit-6 (pwr down)
=0: Normal Run
=1: Manual Pwr down
Refer to the description of the
DSR in the FDC section of any
SMSC Super or Ultra I/O data
sheet.
Tri-State
(Note 2)
1
VALID
BASE
ADDRESS
X
X
0
1
1
X
X
X
1
0
79
MECHANISM
GCR 0x23 bit-0 (FDC auto
power management)
=1: Pwr Mngnt on
=0: Pwr Mngnt off
Refer to the description of the
Global Config Register 0x23 in
the Configuration section of the
FDC37N972 Specification.
X
FDC OUTPUT PINS STATE
X
X
X
Note:
1
FDC Output pins = nWDATA, DRVDEN0, nHDSELm nWGATE, nDIR, nSTEP, nDS1, nDS0,
nMTR0, nMTR1.
Note1: DSR pwr down overrides auto pwr down.
Note 2: Outputs tri-state only if all of the required auto power down conditions are met, otherwise
outputs are active. See Auto Power Management Section of the FDC37C93x Data Sheet.
80
FDC FORCE WRITE PROTECT
The FDC37N972 includes a Force Write Protect
function for the floppy disk controller. Force
Write Protect asserts the internal nWRTPRT
input to the controller (TABLE 48 and FIGURE
6).
nWRTPRT
nWRTPRT
FDC
nDS0
nDS0
nDS1
nDS1
FORCE
WRTPRT
FIGURE 6 - FORCE WRITE PROTECT FUNCTION
NOTE: This figure is for illustration purposes only and is not intended to suggest specific
implementation details.
The FORCE WRTPRT bit is D0 in the Disable
register (see Section Disable REGISTER on
page 166). The FORCE WRTPRT bit is activehigh and set to “0” by default. The Force Write
nWRTPRT
(FDD PIN)
0
FORCE
WRTPRT
X
1
1
1
1
1
0
1
1
Protect function applies to the nWRTPRT input
from the FDD Interface as well as the
nWRTPRT input from the Parallel Port FDC.
TABLE 48 - FORCE WRTPRT FUNCTION
nWRTPRT
DESCRIPTION
nDS0 nDS1
(FDC)
X
X
0
Active nWRTPRT pin function is
always enabled.
1
1
1
nWRTPRT function inactive.
1
1
1
0
1
0
Enabled FORCE WRTPRT function
overrides an inactive nWRTPRT pin.
1
0
0
81
ACPI EMBEDDED CONTROLLER
Overview
ACPI defines a standard hardware and software
communications interface between the OS and
an embedded controller. This interface allows
the OS to support a standard driver that can
directly communicate with the embedded
controller, allowing other drivers within the
system to communicate with and use the EC
resources; for example, Smart Battery and AML
code.
(wake)
(run-time)
(run-time)
(wake & run-time)
Ring
Thermal
Dock
Battery
The FDC37N972 contains an Embedded
Controller Interface (ECI) to handle SCI Wake
and Run-time event processing (FIGURE 8).
The ECI is configured in Logical Device Number
8 in the FDC37N972 configuration register map
and presents an 8042-style interface to the ISA
host.
Run-Time
EC
(Arbitrates Wake and
Run-time SCI Events)
GPEx
Wake
GPEy
CHIPSET
FIGURE 7 – EMBEDDED CONTROL (EC) ILLUSTRATION
EC Input
Buffer
Data Read
EC Output
Buffer
Status Read
EC Status
Register
SCI
Interface
Code
Main
Firmware
(8051)
I/O
Wake
Data Write
Run-Time
ACPI Interface
Command Write
SCI Interface
FIGURE 8 – GENERIC ACPI EC BLOCK DIAGRAM
82
ECI CONFIGURATION REGISTERS
Register 0x60 is the ECI Primary Base Address
High Byte, register 0x61 is the ECI Primary
Base Address Low Byte.
The three device configuration registers in LDN8
provide ECI activation control and the base
address for the ECI run-time registers (TABLE
49). Register 0x30 is the Activate register. The
Activate register qualifies address decoding for
the ECI; e.g., if the Activate bit D0 in the
Activate register is “0”, ECI addresses will not
be decoded; if the Activate bit is “1”, ECI
addresses will be decoded depending on the
values programmed in the ECI Primary Base
Address registers. Registers 0x60 and 0x61 are
the ECI Primary Base Address registers.
NOTE: Bits D0 and D2 in the ECI Primary Base
Address Low Byte must be “0”. For example,
0x62 is a valid ECI Base Address, while 0x66 is
not a valid ECI Base Address. The valid ECI
Primary Base Address range is 0x0000 –
0x0FFA.
TABLE 49 - ECI CONFIGURATION REGISTERS (LDN8)
INDEX
TYPE
HARD
RESET
SOFT
RESET
VCC2
POR
VCC1&
VCC0
POR
D7
0x30
R/W
0x00
0x00
0x00
-
0x60
R/W
0x00
0x00
0x00
-
0x61
R/W
0x62
0x62
0x62
-
D6
D5
DESCRIPTION
D4
D3
D2
D1
D0
ACTIVATE
Activate
Reserved
ECI PRIMARY BASE ADDRESS HIGH
BYTE
ECI PRIMARY BASE ADDRESS LOW
BYTE1
A7
A6
A5
A4
A3
“0”
A1
“0”
NOTE1 Bits D0 and D2 of the ECI Base Address Low Byte must be “0”.
An ACPI-compliant ECI contains three registers:
EC_COMMAND, EC_STATUS, and EC_DATA.
The ECI registers occupy two addresses in the
Host I/O space (TABLE 50).
8051. The CMD bit in the EC_STATUS register
is used by the 8051 to discriminate commands
from data written by the host to the ECI. CMD
is controlled by hardware: host writes to the
EC_DATA register set CMD = “0”; host writes to
the EC_COMMAND register set CMD = “1”.
The EC_DATA and EC_COMMAND registers
appear as a single 8-bit data register in the
Descriptions of these registers follow in the
sections below.
ECI RUNTIME REGISTERS
83
TABLE 50 - ECI RUN-TIME REGISTERS
ISA HOST
INTERFACE
REGISTER
NAME
EC_DATA
EC_COMMAND
EC_STATUS
HOST INDEX
ECI Base
Address
ECI Base
Address + 4
ECI Base
Address + 4
HOST
TYPE
R/W
8051 INTERFACE
8051
INDEX
8051
1
CMD
(7F00+)
TYPE
0
0x53
R/W
POWER
PLANE
VCC1
VCC1
POR
-
VCC2
POR
-
W
1
0x53
R
VCC1
-
-
R
-
0x54
R/W
VCC1
0x00
-
NOTE1 CMD is bit D3 in the EC_STATUS register.
the EC_STATUS register is read-only. To the
8051, some bits in the EC_STATUS register are
read-only (TABLE 51). These bits are controlled
by hardware. The 8051 software controlled bits
in the EC_STATUS register are read/write.
EC_STATUS REGISTER
The EC_STATUS register indicates the state of
the Embedded Controller Interface. To the host,
HOST TYPE
8051 TYPE
NAME
D7
R
R/W
UD1
TABLE 51 – EC_STATUS REGISTER
D6
D5
D4
D3
R
R
R
R
R/W
R/W
R/W
R
SMI_EVT SCI_EVT BURST
CMD
D2
R
R/W
UD1
D1
R
R
IBF
D0
R
R
OBF
NOTE1 The UD bits are User-Defined. UD bits are maintained by 8051 software, only.
The EC_OBF interrupt is routed to bit 3 in the
INT0 SRC register (FIGURE 19). The EC_OBF
interrupt mask is bit 4 in the INT1 Mask register.
OBF Bit – D0
The Output Buffer Full (OBF) flag is set when
the 8051 writes a byte of data into the data port
(EC_DATA), but the host has not yet read it.
Once the host reads the status byte and sees
the OBF flag set, the host reads the data port to
get the byte of data that the 8051 has written.
IBF Bit – D1
The Input Buffer Full (IBF) flag is set when the
host has written a byte of data to the command
or data port, but the 8051 has not yet read it.
Once the host reads the data, the OBF flag is
automatically cleared by hardware. An EC_OBF
interrupt signals the 8051 that the data has been
read by the host and the 8051 is free to write
more data to the EC_DATA register.
An EC_IBF interrupt signals the 8051 that there
is data available. Once the 8051 reads the
status byte and sees the IBF flag set, the 8051
reads the data port to get the byte of data that
the host has written.
The EC_OBF interrupt is generated whenever
the OBF bit in the EC_STATUS register is reset.
Once the 8051 reads the data, the IBF flag is
automatically cleared by hardware. The 8051
must then generate a software interrupt (SCI) to
84
The SCI_EVT bit is an 8051-maintained
software flag that is set when the embedded
controller has detected an internal event that
requires operating system attention. The EC
sets SCI_EVT before generating an SCI to the
OS.
alert the host that the data has been read and
that the host is free to write more data to the
ECI as needed.
An EC_IBF interrupt is generated whenever the
IBF bit in the EC_STATUS register is set. The
EC_IBF interrupt is routed to bit 4 in the INT0
SRC register. The EC_IBF interrupt mask is bit
5 in the INT1 Mask register.
CMD Bit – D3
The CMD bit is “1” when the EC_DATA register
contains a command byte; the CMD bit is “0”
when the EC_DATA register contains a data
byte.
SMI_EVT Bit – D6
The SMI Event flag SMI_EVT is “1” when an
SMI event is pending; i.e., the 8051 is
requesting an SMI query; SMI_EVT is “0” when
no SMI events are pending.
The SMI_EVT bit is an 8051-maintained
software flag that is set when the embedded
controller has detected an internal event that
requires system management interrupt handler
attention.
The EC sets SMI_EVT before
generating an SMI.
The CMD bit is controlled by hardware: host
writes to the EC_DATA register set CMD = “0”;
host writes to the EC_COMMAND register set
CMD = “1”.
The CMD bit allows the embedded controller to
differentiate the start of a command sequence
from a data byte write operation.
BURST Bit – D4
The BURST bit is “1” when the EC is in Burst
Mode for polled command processing; the
BURST bit is “0” when the EC is in Normal
Mode for interrupt-driven command processing.
EC_COMMAND Register
The EC_COMMAND register is a write-only
register that allows the host to issue commands
to the embedded controller.
Writes to the EC_COMMAND register are
latched in the 8051 data register and the input
buffer full flag is set in the EC_STATUS register.
Writes to the EC_COMMAND register also
cause the CMD bit to be set to “1” in the
EC_STATUS register.
The BURST bit is an 8051-maintained software
flag that indicates the embedded controller has
received the Burst Enable command from the
host, has halted normal processing, and is
waiting for a series of commands to be sent
from the host. Burst Mode allows the OS or
system management handler to quickly read
and write several bytes of data at a time without
the overhead of SCIs between commands.
EC_DATA Register
The EC_DATA register is a read/write register
that allows the host to issue command
arguments to the embedded controller and
allows the OS to read data returned by the
embedded controller.
SCI_EVT Bit – D5
The SCI Event flag SCI_EVT is “1” when an SCI
event is pending; i.e., the 8051 is requesting an
SCI query; SCI_EVT is “0” when no SCI events
are pending.
Host writes to the EC_DATA register are latched
in the 8051 data register and the input buffer full
flag is set in the EC_STATUS register. Host
writes to the EC_DATA register also cause the
85
generator that is capable of dividing the input
clock or crystal by a number from 1 to 65535.
The UART is also capable of supporting the
MIDI data rate. Refer to the Configuration
Registers for information on disabling, power
down and changing the base address of the
UART. The interrupt from a UART is enabled by
programming OUT2 of the UART to a logic "1".
OUT2 being a logic "0" disables that UART's
interrupt.
CMD bit to be reset to “0” in the EC_STATUS
register.
Host reads from the EC_DATA register return
data from the 8051 data register and clear the
output buffer full flag in the EC_STATUS
register.
SERIAL PORT (UART)
The FDC37N972 incorporates one full function
UART.
The UART is compatible with the
NS16450, the 16450 ACE registers and the
NSC16550A. The UART performs serial-toparallel conversion on received characters and
parallel-to-serial
conversion
on
transmit
characters. The data rates are independently
programmable from 460.8K baud down to 50
baud. The character options are programmable
for 1 start; 1, 1.5 or 2 stop bits; even, odd, sticky
or no parity; and prioritized interrupts. The
UART contains a programmable baud rate
REGISTER DESCRIPTION
Addressing of the accessible registers of the
Serial Port is shown below.
The base
addresses of the serial ports are defined by the
configuration registers (see Configuration
section). The Serial Port registers are located at
sequentially increasing addresses above these
base addresses. The FDC37N972 contains a
serial port, which contains a register set as
described below.
86
DLAB*
0
0
0
X
X
X
X
X
X
X
1
1
TABLE 52 - ADDRESSING THE SERIAL PORT
A2
A1
A0
REGISTER NAME
0
0
0
Receive Buffer (read)
0
0
0
Transmit Buffer (write)
0
0
1
Interrupt Enable (read/write)
0
1
0
Interrupt Identification (read)
0
1
0
FIFO Control (write)
0
1
1
Line Control (read/write)
1
0
0
Modem Control (read/write)
1
0
1
Line Status (read/write)
1
1
0
Modem Status (read/write)
1
1
1
Scratchpad (read/write)
0
0
0
Divisor LSB (read/write)
0
0
1
Divisor MSB (read/write)
Note: DLAB is Bit 7 of the Line Control Register
The following section describes the operation of the registers.
the Transmit Buffer when the transmission of
the previous byte is complete.
RECEIVE BUFFER REGISTER (RB)
Address Offset = 0H, DLAB = 0, READ ONLY
INTERRUPT ENABLE REGISTER (IER)
This register holds the received incoming data
byte. Bit 0 is the least significant bit, which is
transmitted and received first. Received data is
double buffered; this uses an additional shift
register to receive the serial data stream and
convert it to a parallel 8 bit word which is
transferred to the Receive Buffer register. The
shift register is not accessible.
Address Offset = 1H, DLAB = 0, READ/WRITE
The lower four bits of this register control the
enables of the five interrupt sources of the Serial
Port interrupt. It is possible to totally disable the
interrupt system by resetting bits 0 through 3 of
this register. Similarly, setting the appropriate
bits of this register to a high, selected interrupts
can be enabled. Disabling the interrupt system
inhibits the Interrupt Identification Register and
disables any Serial Port interrupt out of the
FDC37N972 .
All other system functions
operate in their normal manner, including the
Line Status and MODEM Status Registers. The
contents of the Interrupt Enable Register are
described below.
TRANSMIT BUFFER REGISTER (TB)
Address Offset = 0H, DLAB = 0, WRITE ONLY
This register contains the data byte to be
transmitted.
The transmit buffer is double
buffered, utilizing an additional shift register (not
accessible) to convert the 8 bit data word to a
serial format. This shift register is loaded from
87
BIT 0
This bit enables the Received Data Available Interrupt (and timeout interrupts in the FIFO mode) when
set to logic "1".
BIT 1
This bit enables the Transmitter Holding Register Empty Interrupt when set to logic "1".
BIT 2
This bit enables the Received Line Status Interrupt when set to logic "1". The error sources causing
the interrupt are Overrun, Parity, Framing and Break. The Line Status Register must be read to
determine the source.
BIT 3
This bit enables the MODEM Status Interrupt when set to logic "1". This is caused when one of the
Modem Status Register bits changes state.
BITS 4 - 7
These bits are always logic "0".
FIFO CONTROL REGISTER (FCR)
Address Offset = 2H, DLAB = X, WRITE
This is a write only register at the same location as the IIR. This register is used to enable and clear
the FIFOs, set the RCVR FIFO trigger level. Note: DMA is not supported.
BIT 0
Setting this bit to a logic "1" enables both the XMIT and RCVR FIFOs. Clearing this bit to a logic "0"
disables both the XMIT and RCVR FIFOs and clears all bytes from both FIFOs. When changing from
FIFO Mode to non-FIFO (16450) mode, data is automatically cleared from the FIFOs. This bit must
be a 1 when other bits in this register are written to or they will not be properly programmed.
BIT 1
Setting this bit to a logic "1" clears all bytes in the RCVR FIFO and resets its counter logic to “0”. The
shift register is not cleared. This bit is self-clearing.
BIT 2
Setting this bit to a logic "1" clears all bytes in the XMIT FIFO and resets its counter logic to “0”. The
shift register is not cleared. This bit is self-clearing.
BIT 3
Writing to this bit has no effect on the operation of the UART. The RXRDY and TXRDY pins are not
available on this chip.
88
BITS 4 and 5
Reserved
BITS 6 and 7
These bits are used to set the trigger level for the RCVR FIFO interrupt.
BIT 7
0
0
1
1
BIT 6
0
1
0
1
RCVR FIFO
TRIGGER LEVEL (BYTES)
1
4
8
14
INTERRUPT IDENTIFICATION REGISTER (IIR)
Address Offset = 2H, DLAB = X, READ
By accessing this register, the host CPU can determine the highest priority interrupt and its source.
Four levels of priority interrupt exist.
They are in descending order of priority:
1. Receiver Line Status (highest priority)
2. Received Data Ready
3. Transmitter Holding Register Empty
4. MODEM Status (lowest priority)
Information indicating that a prioritized interrupt is pending and the source of that interrupt is stored in
the Interrupt Identification Register (refer to Interrupt Control Table). When the CPU accesses the IIR,
the Serial Port freezes all interrupts and indicates the highest priority pending interrupt to the CPU.
During this CPU access, even if the Serial Port records new interrupts, the current indication does not
change until access is completed. The contents of the IIR are described below.
BIT 0
This bit can be used in either a hardwired prioritized or polled environment to indicate whether an
interrupt is pending. When bit 0 is a logic "0", an interrupt is pending and the contents of the IIR may
be used as a pointer to the appropriate internal service routine. When bit 0 is a logic "1", no interrupt
is pending.
BITS 1 and 2
These two bits of the IIR are used to identify the highest priority interrupt pending as indicated by the
Interrupt Control Table.
BIT 3
In non-FIFO mode, this bit is a logic "0". In FIFO mode this bit is set along with bit 2 when a timeout
interrupt is pending.
89
BITS 4 and 5
These bits of the IIR are always logic "0".
BITS 6 and 7
These two bits are set when the FIFO CONTROL Register bit 0 equals 1.
FIFO
MODE
ONLY
BIT 3
0
0
0
1
0
0
TABLE 53 - INTERRUPT CONTROL TABLE
INTERRUPT
IDENTIFICATION
REGISTER
INTERRUPT SET AND RESET FUNCTIONS
PRIORITY
INTERRUPT
INTERRUPT
INTERRUPT
BIT 2 BIT 1 BIT 0
LEVEL
TYPE
SOURCE
RESET CONTROL
0
0
1
None
None
Reading the Line
1
1
0
Highest
Receiver Line
Overrun Error,
Status Register
Status
Parity Error,
Framing Error
or Break
Interrupt
1
0
0
Second
Received Data
Receiver Data
Read Receiver
Available
Available
Buffer or the FIFO
drops below the
trigger level.
1
0
0
Second
Character
No Characters
Reading the
Timeout
Have Been
Receiver Buffer
Indication
Removed From Register
or Input to the
RCVR FIFO
during the last 4
Char times and
there is at least
1 char in it
during this time
0
1
0
Third
Transmitter
Transmitter
Reading the IIR
Holding Register Holding Register Register (if Source
Empty
Empty
of Interrupt) or
Writing the
Transmitter
Holding Register
0
0
0
Fourth
MODEM Status Clear to Send or Reading the
Data Set Ready MODEM Status
or Ring Indicator Register
or Data Carrier
Detect
90
LINE CONTROL REGISTER (LCR)
Address Offset = 3H, DLAB = 0, READ/WRITE
This register contains the format information of
the serial line. The bit definitions are:
BITS 0 and 1
These two bits specify the number of bits in each transmitted or received serial character.
encoding of bits 0 and 1 is as follows:
BIT 1
0
0
1
1
BIT 0
0
1
0
1
The
WORD LENGTH
5 Bits
6 Bits
7 Bits
8 Bits
The Start, Stop and Parity bits are not included in the word length.
BIT 2
This bit specifies the number of stop bits in each transmitted or received serial character.
following table summarizes the information.
BIT 2
0
1
1
1
1
WORD LENGTH
-5 bits
6 bits
7 bits
8 bits
The
NUMBER OF
STOP BITS
1
1.5
2
2
2
Note: The receiver will ignore all stop bits beyond the first, regardless of the number used in
transmitting.
BIT 3
Parity Enable bit. When bit 3 is a logic "1", a parity bit is generated (transmit data) or checked
(receive data) between the last data word bit and the first stop bit of the serial data. (The parity bit is
used to generate an even or odd number of 1s when the data word bits and the parity bit are
summed).
BIT 4
Even Parity Select bit. When bit 3 is a logic "1" and bit 4 is a logic "0", an odd number of logic "1"'s is
transmitted or checked in the data word bits and the parity bit. When bit 3 is a logic "1" and bit 4 is a
logic "1" an even number of bits is transmitted and checked.
BIT 5
Stick Parity bit. When bit 3 is a logic "1" and bit 5 is a logic "1", the parity bit is transmitted and then
detected by the receiver in the opposite state indicated by bit 4.
91
BIT 6
Set Break Control bit. When bit 6 is a logic "1", the transmit data output (TXD) is forced to the
Spacing or logic "0" state and remains there (until reset by a low level bit 6) regardless of other
transmitter activity. This feature enables the Serial Port to alert a terminal in a communications
system.
BIT 7
Divisor Latch Access bit (DLAB). It must be set high (logic "1") to access the Divisor Latches of the
Baud Rate Generator during read or write operations. It must be set low (logic "0") to access the
Receiver Buffer Register, the Transmitter Holding Register, or the Interrupt Enable Register.
MODEM CONTROL REGISTER (MCR)
Address Offset = 4H, DLAB = X, READ/WRITE
This 8 bit register controls the interface with the MODEM or data set (or device emulating a MODEM).
The contents of the MODEM control register are described below.
BIT 0
This bit controls the Data Terminal Ready (nDTR) output. When bit 0 is set to a logic "1", the nDTR
output is forced to a logic "0". When bit 0 is a logic "0", the nDTR output is forced to a logic "1".
BIT 1
This bit controls the Request To Send (nRTS) output. Bit 1 affects the nRTS output in a manner
identical to that described above for bit 0.
BIT 2
This bit controls the Output 1 (OUT1) bit. This bit does not have an output pin and can only be read
or written by the CPU.
BIT 3
Output 2 (OUT2). This bit is used to enable an UART interrupt. When OUT2 is a logic "0", the serial
port interrupt output is forced to a high impedance state - disabled. When OUT2 is a logic "1", the
serial port interrupt outputs are enabled.
BIT 4
This bit provides the loopback feature for diagnostic testing of the Serial Port. When bit 4 is set to
logic "1", the following occur:
1. The TXD is set to the Marking State(logic "1").
2. The receiver Serial Input (RXD) is disconnected.
3. The output of the Transmitter Shift Register is "looped back" into the Receiver Shift Register
input.
4. All MODEM Control inputs (nCTS, nDSR, nRI and nDCD) are disconnected.
5. The four MODEM Control outputs (nDTR, nRTS, OUT1 and OUT2) are internally connected to the
four MODEM Control inputs (nDSR, nCTS, RI, DCD).
6. The Modem Control output pins are forced inactive high.
7. Data that is transmitted is immediately received.
92
This feature allows the processor to verify the transmit and receive data paths of the Serial Port. In
the diagnostic mode, the receiver and the transmitter interrupts are fully operational. The MODEM
Control Interrupts are also operational but the interrupts' sources are now the lower four bits of the
MODEM Control Register instead of the MODEM Control inputs. The interrupts are still controlled by
the Interrupt Enable Register.
BITS 5 - 7
These bits are permanently set to logic zero.
LINE STATUS REGISTER (LSR)
Address Offset = 5H, DLAB = X, READ/WRITE
BIT 0
Data Ready (DR). It is set to a logic "1" whenever a complete incoming character has been received
and transferred into the Receiver Buffer Register or the FIFO. Bit 0 is reset to a logic "0" by reading all
of the data in the Receive Buffer Register or the FIFO.
BIT 1
Overrun Error (OE). Bit 1 indicates that data in the Receiver Buffer Register was not read before the
next character was transferred into the register, thereby destroying the previous character. In FIFO
mode, an overrun error will occur only when the FIFO is full and the next character has been
completely received in the shift register, the character in the shift register is overwritten but not
transferred to the FIFO. The OE indicator is set to a logic "1" immediately upon detection of an
overrun condition, and reset whenever the Line Status Register is read.
BIT 2
Parity Error (PE). Bit 2 indicates that the received data character does not have the correct even or
odd parity, as selected by the even parity select bit. The PE is set to a logic "1" upon detection of a
parity error and is reset to a logic "0" whenever the Line Status Register is read. In the FIFO mode this
error is associated with the particular character in the FIFO it applies to. This error is indicated when
the associated character is at the top of the FIFO.
BIT 3
Framing Error (FE). Bit 3 indicates that the received character did not have a valid stop bit. Bit 3 is
set to a logic "1" whenever the stop bit following the last data bit or parity bit is detected as a zero bit
(Spacing level). The FE is reset to a logic "0" whenever the Line Status Register is read. In the FIFO
mode this error is associated with the particular character in the FIFO it applies to. This error is
indicated when the associated character is at the top of the FIFO. The Serial Port will try to
resynchronize after a framing error. To do this, it assumes that the framing error was due to the next
start bit, so it samples this 'start' bit twice and then takes in the 'data'.
BIT 4
Break Interrupt (BI). Bit 4 is set to a logic "1" whenever the received data input is held in the Spacing
state (logic "0") for longer than a full word transmission time (that is, the total time of the start bit +
data bits + parity bits + stop bits). The BI is reset after the CPU reads the contents of the Line Status
93
Register. In the FIFO mode this error is associated with the particular character in the FIFO it applies
to. This error is indicated when the associated character is at the top of the FIFO. When break
occurs only one zero character is loaded into the FIFO. Restarting after a break is received, requires
the serial data (RXD) to be logic "1" for at least 1/2 bit time. Note: Bits 1 through 4 are the error
conditions that produce a Receiver Line Status Interrupt whenever any of the corresponding conditions
are detected and the interrupt is enabled.
BIT 5
Transmitter Holding Register Empty (THRE). Bit 5 indicates that the Serial Port is ready to accept a
new character for transmission. In addition, this bit causes the Serial Port to issue an interrupt when
the Transmitter Holding Register interrupt enable is set high. The THRE bit is set to a logic "1" when a
character is transferred from the Transmitter Holding Register into the Transmitter Shift Register. The
bit is reset to logic "0" whenever the CPU loads the Transmitter Holding Register. In the FIFO mode
this bit is set when the XMIT FIFO is empty, it is cleared when at least 1 byte is written to the XMIT
FIFO. Bit 5 is a read only bit.
BIT 6
Transmitter Empty (TEMT). Bit 6 is set to a logic "1" whenever the Transmitter Holding Register
(THR) and Transmitter Shift Register (TSR) are both empty. It is reset to logic "0" whenever either
the THR or TSR contains a data character. Bit 6 is a read only bit. In the FIFO mode this bit is set
whenever the THR and TSR are both empty,
BIT 7
This bit is permanently set to logic "0" in the 450 mode. In the FIFO mode, this bit is set to a logic "1"
when there is at least one parity error, framing error or break indication in the FIFO. This bit is cleared
when the LSR is read if there are no subsequent errors in the FIFO.
MODEM STATUS REGISTER (MSR)
Address Offset = 6H, DLAB = X, READ/WRITE This 8 bit register provides the current state of the
control lines from the MODEM (or peripheral device). In addition to this current state information, four
bits of the MODEM Status Register (MSR) provide change information.
These bits are set to logic "1" whenever a control input from the MODEM changes state. They
are reset to logic "0" whenever the MODEM Status Register is read.
BIT 0
Delta Clear To Send (DCTS). Bit 0 indicates that the nCTS input to the chip has changed state since
the last time the MSR was read.
BIT 1
Delta Data Set Ready (DDSR). Bit 1 indicates that the nDSR input has changed state since the last
time the MSR was read.
94
BIT 2
Trailing Edge of Ring Indicator (TERI). Bit 2 indicates that the nRI input has changed from logic "0" to
logic "1".
BIT 3
Delta Data Carrier Detect (DDCD). Bit 3 indicates that the nDCD input to the chip has changed state.
NOTE: Whenever bit 0, 1, 2, or 3 is set to a logic "1", a MODEM Status Interrupt is generated.
BIT 4
This bit is the complement of the Clear To Send (nCTS) input. If bit 4 of the MCR is set to logic "1",
this bit is equivalent to nRTS in the MCR.
BIT 5
This bit is the complement of the Data Set Ready (nDSR) input. If bit 4 of the MCR is set to logic "1",
this bit is equivalent to DTR in the MCR.
BIT 6
This bit is the complement of the Ring Indicator (nRI) input. If bit 4 of the MCR is set to logic "1", this
bit is equivalent to OUT1 in the MCR.
BIT 7
This bit is the complement of the Data Carrier Detect (nDCD) input. If bit 4 of the MCR is set to logic
"1", this bit is equivalent to OUT2 in the MCR.
SCRATCHPAD REGISTER (SCR)
Address Offset =7H, DLAB =X, READ/WRITE
This 8 bit read/write register has no effect on the operation of the Serial Port. It is intended as a
scratchpad register to be used by the programmer to hold data temporarily.
95
PROGRAMMABLE BAUD RATE GENERATOR
(AND DIVISOR LATCHES DLH, DLL)
prevents long counts on initial load. If a 0 is
loaded into the BRG registers the output divides
the clock by the number 3. If a 1 is loaded the
output is the inverse of the input oscillator. If a
two is loaded the output is a divide by 2 signal
with a 50% duty cycle. If a 3 or greater is
loaded the output is low for 2 bits and high for
the remainder of the count. The input clock to
the BRG is the 24 MHz crystal divided by 13,
giving a 1.8462 MHz clock.
The Serial Port contains a programmable Baud
Rate Generator that is capable of taking any
clock input (DC to 3 MHz) and dividing it by any
divisor from 1 to 65535. This output frequency
of the Baud Rate Generator is 16x the Baud
rate. Two 8 bit latches store the divisor in 16 bit
binary format. These Divisor Latches must be
loaded during initialization in order to insure
desired operation of the Baud Rate Generator.
Upon loading either of the Divisor Latches, a 16
bit Baud counter is immediately loaded. This
TABLE 54 shows the baud rates possible with a 1.8462 MHz crystal.
TABLE 54 - UART BAUD RATES
DESIRED
BAUD RATE
50
75
110
134.5
150
300
600
1200
1800
2000
2400
3600
4800
7200
9600
19200
38400
57600
115200
230400
460800
DIVISOR USED TO
GENERATE 16X CLOCK
2304
1536
1047
857
768
384
192
96
64
58
48
32
24
16
12
6
3
2
1
32770
32769
PERCENT ERROR DIFFERENCE BETWEEN
1
DESIRED AND ACTUAL
0.001
0.004
0.005
0.030
0.16
0.16
0.16
0.16
HIGH SPEED
2
BIT
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
1
1
Note1: The percentage error for all baud rates, except where indicated otherwise, is 0.2%.
Note2: The High Speed bit is located in the Device Configuration Space.
Using 1.8462 MHz Clock for <=38.4;
Using 1.843 MHz Clock for 115.2k;
Using 3.6864 MHz Clock for 230.4k;
Using 7.3728 MHz Clock for 460.8k
96
C. When a timeout interrupt has occurred it is
cleared and the timer reset when the CPU reads
one character from the RCVR FIFO.
D. When a timeout interrupt has not occurred
the timeout timer is reset after a new character
is received or after the CPU reads the RCVR
FIFO.
FIFO INTERRUPT MODE OPERATION
When the RCVR FIFO and receiver interrupts
are enabled (FCR bit 0 = "1", IER bit 0 = "1"),
RCVR interrupts occur as follows:
A. The receive data available interrupt will be
issued when the FIFO has reached its
programmed trigger level; it is cleared as soon
as the FIFO drops below its programmed trigger
level.
B. The IIR receive data available indication also
occurs when the FIFO trigger level is reached.
It is cleared when the FIFO drops below the
trigger level.
C. The receiver line status interrupt (IIR=06H),
has higher priority than the received data
available (IIR=04H) interrupt.
D. The data ready bit (LSR bit 0) is set as soon
as a character is transferred from the shift
register to the RCVR FIFO. It is reset when the
FIFO is empty.
When the XMIT FIFO and transmitter interrupts
are enabled (FCR bit 0 = "1", IER bit 1 = "1"),
XMIT interrupts occur as follows:
A. The transmitter holding register interrupt
(02H) occurs when the XMIT FIFO is empty; it is
cleared as soon as the transmitter holding
register is written to (1 of 16 characters may be
written to the XMIT FIFO while servicing this
interrupt) or the IIR is read.
B. The transmitter FIFO empty indications will
be delayed 1 character time minus the last stop
bit time whenever the following occurs: THRE=1
and there have not been at least two bytes at
the same time in the transmitter FIFO since the
last THRE=1. The transmitter interrupt after
changing FCR0 will be immediate, if it is
enabled.
When RCVR FIFO and receiver interrupts are
enabled, RCVR FIFO timeout interrupts occur
as follows:
Character timeout and RCVR FIFO trigger level
interrupts have the same priority as the current
received data available interrupt; XMIT FIFO
empty has the same priority as the current
transmitter holding register empty interrupt.
A. A FIFO timeout interrupt occurs if all the
following conditions exist:
At least one character is in the FIFO
The most recent serial character
received was longer than 4 continuous
character times ago. (If 2 stop bits are
programmed, the second one is
included in this time delay.)
The most recent CPU read of the FIFO
was longer than 4 continuous character
times ago.
FIFO POLLED MODE OPERATION
With FCR bit 0 = "1" resetting IER bits 0, 1, 2 or
3 or all to zero puts the UART in the FIFO
Polled Mode of operation. Since the RCVR and
XMITTER are controlled separately, either one
or both can be in the polled mode of operation.
In this mode, the user's program will check
RCVR and XMITTER status via the LSR. LSR
definitions for the FIFO Polled Mode are as
follows:
Bit 0=1 as long as there is one byte in the RCVR
FIFO.
This will cause a maximum character received
to interrupt issued delay of 160 msec at 300
BAUD with a 12 bit character.
B. Character times are calculated by using the
RCLK input for a clock signal (this makes the
delay proportional to the baudrate).
97
There is no trigger level reached or timeout
condition indicated in the FIFO Polled Mode,
however, the RCVR and XMIT FIFOs are still
fully capable of holding characters.
Bits 1 to 4 specify which error(s) have occurred.
Character error status is handled the same
way as when in the interrupt mode, the IIR is
not affected since EIR bit 2=0.
Bit 5 indicates when the XMIT FIFO is empty.
Bit 6 indicates that both the XMIT FIFO and shift
register are empty.
Bit 7 indicates whether there are any errors in
the RCVR FIFO.
EFFECT OF THE RESET ON REGISTER FILE
The Reset Function Table (TABLE 55) details
the effect of Vcc2 POR or nRESET_OUT on
each of the registers of the Serial Port.
TABLE 55 - RESET FUNCTION TABLE
REGISTER/SIGNAL
RESET CONTROL
RESET STATE
Interrupt Enable Register
RESET
All bits low
Interrupt Identification Reg.
RESET
Bit 0 is high; Bits 1 - 7 low
FIFO Control
RESET
All bits low
Line Control Reg.
RESET
All bits low
MODEM Control Reg.
RESET
All bits low
Line Status Reg.
RESET
All bits low except 5, 6 high
MODEM Status Reg.
RESET
Bits 0 - 3 low; Bits 4 - 7 input
TXD1, TXD2
RESET
High
INTRPT (RCVR errs)
RESET/Read LSR
Low
INTRPT (RCVR Data Ready) RESET/Read RBR
Low
INTRPT (THRE)
RESET/ReadIIR/Write THR
Low
OUT2B
RESET
High
RTSB
RESET
High
DTRB
RESET
High
OUT1B
RESET
High
RCVR FIFO
RESET/
All Bits Low
FCR1*FCR0/_FCR0
XMIT FIFO
RESET/
All Bits Low
FCR1*FCR0/_FCR0
98
TABLE 56 - REGISTER SUMMARY FOR AN INDIVIDUAL UART CHANNEL
REGISTER
REGISTER
ADDRESS*
REGISTER NAME
SYMBOL
BIT 0
BIT 1
ADDR = 0
Receive Buffer Register (Read RBR
Data Bit 0 (Note 1) Data Bit 1
DLAB = 0
Only)
ADDR = 0
Transmitter Holding Register
THR
Data Bit 0
Data Bit 1
DLAB = 0
(Write Only)
Enable
ADDR = 1
Interrupt Enable Register
IER
Enable Received
Transmitter
DLAB = 0
Data Available
Interrupt (ERDAI) Holding
Register
Empty
Interrupt
(ETHREI)
ADDR = 2
Interrupt Ident. Register (Read IIR
"0" if Interrupt
Interrupt ID
Only)
Pending
Bit
ADDR = 2
FIFO Control Register (Write
FCR
FIFO Enable
RCVR
Only)
FIFO Reset
ADDR = 3
Line Control Register
LCR
Word Length
Word
Select Bit 0
Length
(WLS0)
Select Bit 1
(WLS1)
ADDR = 4
MODEM Control Register
MCR
Data Terminal
Request to
Ready (DTR)
Send
(RTS)
ADDR = 5
Line Status Register
LSR
Data Ready (DR)
Overrun
Error (OE)
ADDR = 6
MODEM Status Register
MSR
Delta Clear to
Delta Data
Send (DCTS)
Set Ready
(DDSR)
ADDR = 7
Scratch Register (Note 4)
SCR
Bit 0
Bit 1
ADDR = 0
Divisor Latch (LS)
DDL
Bit 0
Bit 1
DLAB = 1
ADDR = 1
Divisor Latch (MS)
DLM
Bit 8
Bit 9
DLAB = 1
*DLAB is Bit 7 of the Line Control Register (ADDR = 3).
Note 1: Bit 0 is the least significant bit. It is the first bit serially transmitted or received.
Note 2: When operating in the XT mode, this bit will be set any time that the transmitter shift register
is empty.
99
TABLE 56 - REGISTER SUMMARY FOR AN INDIVIDUAL UART CHANNEL (CONTINUED)
BIT 2
BIT 3
BIT 4
BIT 5
BIT 6
BIT 7
Data Bit 2
Data Bit 3
Data Bit 4
Data Bit 5
Data Bit 6
Data Bit 7
Data Bit 2
Data Bit 3
Data Bit 4
Data Bit 5
Data Bit 6
Data Bit 7
0
0
0
0
Enable
Enable
MODEM
Receiver
Line Status Status
Interrupt
Interrupt
(EMSI)
(ELSI)
FIFOs
Interrupt ID Interrupt ID 0
0
FIFOs
Enabled
Bit
Bit (Note 5)
Enabled
(Note 5)
(Note 5)
Reserved
RCVR
RCVR
XMIT FIFO DMA Mode Reserved
Trigger LSB Trigger MSB
Reset
Select
(Note 6)
Divisor
Even Parity Stick Parity Set Break
Parity
Number of
Latch
Select
Enable
Stop Bits
Access Bit
(EPS)
(PEN)
(STB)
(DLAB)
OUT1
OUT2
Loop
0
0
0
(Note 3)
(Note 3)
Parity Error Framing
Break
Transmitter Transmitter Error in
(PE)
Error (FE)
Interrupt
Holding
Empty
RCVR FIFO
(BI)
Register
(TEMT)
(Note 5)
(THRE)
(Note 2)
Trailing
Delta Data Clear to
Data Set
Ring
Data Carrier
Edge Ring
Carrier
Send (CTS) Ready
Indicator
Detect
Indicator
Detect
(DSR)
(RI)
(DCD)
(TERI)
(DDCD)
Bit 2
Bit 3
Bit 4
Bit 5
Bit 6
Bit 7
Bit 2
Bit 3
Bit 4
Bit 5
Bit 6
Bit 7
Bit 10
Bit 11
Bit 12
Bit 13
Bit 14
Bit 15
Note 3:
Note 4:
Note 5:
Note 6:
This bit no longer has a pin associated with it.
When operating in the XT mode, this register is not available.
These bits are always zero in the non-FIFO mode.
Writing a one to this bit has no effect. DMA modes are not supported in this chip.
100
UART REGISTER SUMMARY NOTES:
*DLAB is Bit 7 of the Line Control Register (ADDR = 3).
Note 1:
Note 2:
empty.
Note 3:
Note 4:
Note 5:
Note 6:
Bit 0 is the least significant bit. It is the first bit serially transmitted or received.
When operating in the XT mode, this bit will be set any time that the transmitter shift register is
This bit no longer has a pin associated with it.
When operating in the XT mode, this register is not available.
These bits are always zero in the non-FIFO mode.
Writing a one to this bit has no effect. DMA modes are not supported in this chip.
NOTES ON SERIAL PORT FIFO MODE OPERATION
GENERAL
The RCVR FIFO will hold up to 16 bytes regardless of which trigger level is selected.
TX AND RX FIFO OPERATION
The Tx portion of the UART transmits data through TXD as soon as the CPU loads a byte into the Tx
FIFO. The UART will prevent loads to the Tx FIFO if it currently holds 16 characters. Loading to the
Tx FIFO will again be enabled as soon as the next character is transferred to the Tx shift register.
These capabilities account for the largely autonomous operation of the Tx.
The UART starts the above operations typically with a Tx interrupt. The chip issues a Tx interrupt
whenever the Tx FIFO is empty and the Tx interrupt is enabled, except in the following instance.
Assume that the Tx FIFO is empty and the CPU starts to load it. When the first byte enters the FIFO
the Tx FIFO empty interrupt will transition from active to inactive. Depending on the execution speed
of the service routine software, the UART may be able to transfer this byte from the FIFO to the shift
register before the CPU loads another byte. If this happens, the Tx FIFO will be empty again and
typically the UART's interrupt line would transition to the active state. This could cause a system with
an interrupt control unit to record a Tx FIFO empty condition, even though the CPU is currently
servicing that interrupt. Therefore, after the first byte has been loaded into the FIFO the UART will
wait one serial character transmission time before issuing a new Tx FIFO empty interrupt. This one
character Tx interrupt delay will remain active until at least two bytes have been loaded into the FIFO,
concurrently. When the Tx FIFO empties after this condition, the Tx interrupt will be activated without
a one character delay.
Rx support functions and operation are quite different from those described for the transmitter. The
Rx FIFO receives data until the number of bytes in the FIFO equals the selected interrupt trigger level.
At that time if Rx interrupts are enabled, the UART will issue an interrupt to the CPU. The Rx FIFO
will continue to store bytes until it holds 16 of them. It will not accept any more data when it is full.
Any more data entering the Rx shift register will set the Overrun Error flag. Normally, the FIFO depth
and the programmable trigger levels will give the CPU ample time to empty the Rx FIFO before an
overrun occurs.
101
One side-effect of having a Rx FIFO is that the selected interrupt trigger level may be above the data
level in the FIFO. This could occur when data at the end of the block contains fewer bytes than the
trigger level. No interrupt would be issued to the CPU and the data would remain in the UART. To
prevent the software from having to check for this situation the chip incorporates a timeout interrupt.
The timeout interrupt is activated when there is a least one byte in the Rx FIFO, and neither the CPU
nor the Rx shift register has accessed the Rx FIFO within 4 character times of the last byte. The
timeout interrupt is cleared or reset when the CPU reads the Rx FIFO or another character enters it.
These FIFO related features allow optimization of CPU/UART transactions and are especially useful
given the higher baud rate capability (256 kbaud).
INFRARED COMMUNICATIONS CONTROLLER (IRCC 2.0)
The Infrared Communications Controller is fully compliant to the IrDA Specification Version 1.1 which
includes data rates up to 4 Mbps to support IrDA-SIRA, IrDA-SIRB, IrDA-HDLC and IrDA-FIR modes.
In addition the IRCC 2.0 provides support for ASK-IR, Consumer (TV remote) IR, and RAW-IR (Host
controller has direct access to the IR bit stream from/to the transceiver module). It is important to
note that the IRCC 2.0 block is a superset of a 16C550A UART. The IRCC 2.0 includes an
Asynchronous Communications Engine (ACE) and a separate Synchronous Communications Engine
(SCE) to provide the full set of IR modes as well as the standard UART Com mode. The IRCC 2.0
block details are fully described in SMSC’s specification titled “Infrared Communications Controller”.
The information in this section of the specification will provide details on the integration of the FIR
logic block into the FDC37N972 .
The infrared interface provides a two-way wireless communications port using infrared as a
transmission medium. The IR transmission can use the standard IRTX and IRRX pins or optional
IRTX2 and IRRX2 pins. These can be selected through the configuration registers. The IRTX2 and
IRRX2 pins are alternate function pins.
IrDA-SIR allows serial communication at baud rates up to 115K Baud. Each word is sent serially
beginning with a “0” value start bit. A “0” is signaled by sending a single IR pulse at the beginning of
the serial bit time. A “1” is signaled by sending no IR pulse during the bit time. Please refer to the AC
timing for the parameters of these pulses and the IrDA waveform. The Amplitude Shift Keyed IR
allows serial communication at baud rates up to 19.2K Baud. Each word is sent serially beginning
with a “0” value start bit. A “0” is signaled by sending a 500 kHz waveform for the duration of the
serial bit time. A “1” is signaled by sending no transmission the bit time. Please refer to the AC
timing for the parameters of the ASK-IR waveform.
If the Half Duplex option is chosen, there is a time-out when the direction of the transmission is
changed. This time-out starts at the last bit transferred during a transmission and blocks the receiver
input until the time-out expires. If the transmit buffer is loaded with more data before the time-out
expires, the timer is restarted after the new byte is transmitted. If data is loaded into the transmit
buffer while a character is being received, the transmission will not start until the time-out expires after
the last receive bit has been received. If the start bit of another character is received during this timeout, the timer is restarted after the new character is received. The time-out is four character times. A
character time is defined as 10 bit times regardless of the actual word length being used.
102
IrCC 2.0 Block
RAW
TV
GPIO9_IN
GPIO9_OUT
IRTX2
COM IRRX2
ASK OUT IR
MUX
IrDA
1
0
GPIO8_OUT
1
MISC7
IRTX
IRRX
“FRx”
COM
G.P. Data
FAST_BIT
IR Data Reg bit-0
0
IRTX
1
0
IR Data Reg bit-1
1
0
GPIO8
MISC2
0
1
TX
AUX RX
FIR
GPIO9
0
1
GPIO6_OUT
0
IRRX
GPIO6
1
FRX_SEL
GPIO10_OUT
00
“IR_MODE”
GPIO10
01
11
FAST
HP_MODE
MISC[14:13]
MISC[16:15]
FIGURE 9 - INTEGRATION OF IRCC 2.0 LOGIC INTO THE FDC37N972
HP_MODE = (MISC[14:13] == [1:0]) | (MISC[16:15] == [1:0])
FRX_SEL = (MISC[14:13] == [1:0])
OVERVIEW
1.
2.
The FDC37N972 requires additional configuration register support to accommodate the IrCC 2.0
core.
NOTE: The IrCC 2.0 is configured in Logical Device Number 5. LD5 is still technically considered
the Serial Port 2 block, even though UART2 is not included in the FDC37N97.
103
IRRX/IRTX PIN ENABLE
When MISC2=0 the IRRX and IRTX pins are enabled as when IrCC 2.0 (LD5) is activated or enabled
and the IRCC 2.0 Output Mux is set to use the IR Port, otherwise the IRTX pin is tri-stated. When
MISC2=1, the IRRX and IRTX pins are always enabled as they can be bit banged through the IR Data
Register, bits 1 and 0 respectively.
Therefore, if the IR interface is on IRRX (pin 21) and IRTX (pin 20), then MISC2 allows the IR interface
to be switched between the IRCC 2.0 block and the IR Data Register. The IR Data Register is only
available from the host, and is located at index register 98. This register is available through the
Mailbox Register Interface.
IR REGISTERS - LOGICAL DEVICE 5
CONFIGURATION REGISTERS OVERVIEW
In order to support the Infrared Communications Controller ten configuration registers are included in
Logical Device 5. Refer to the Configuration section of this specification for details.
BASE I/O ADDRESSES
550 UART
TABLE 57 - ASYNCHRONOUS COMMUNICATIONS ENGINE (UART) REGISTER
REGISTER
FIXED REGISTER BASE
INDEX
BASE I/O RANGE
OFFSETS
0x60, 0x61
[0x100:0x0FF8]
+0 : RB/TB  LSB div
+1 : IER  MSB div
ON 8 BYTE BOUNDARIES
+2 : IIR/FCR
+3 : LCR
+4 : MCR
+5 : LSR
+6 : MSR
+7 : SCR
Register 0x60 stores the MSB and 0x61 the LSB of the 550-UART’s 16 bit Base Address.
104
FAST IR/SCE
TABLE 58 - SYNCHRONOUS COMMUNICATIONS ENGINE (SCE) REGISTERS
REGISTER
FIXED REGISTER BASE
INDEX
BASE I/O RANGE
OFFSETS
0x62, 0x63
[0x100:0x0FF8]
+0 : Register Block, address 0
+1 : Register Block, address 1
+2 : Register Block, address 2
ON 8 BYTE BOUNDARIES
+3 : Register Block, address 3
+4 : Register Block, address 4
+5 : Register Block, address 5
+6 : Register Block, address 6
+7 : SCE Master Control Register
Register 0x60 stores the MSB and 0x61 the LSB of the 550-UART’s 16 bit Base Address.
Note:
Refer to the Infrared Communications Controller (IRCC 2.0) Specification for register details.
Note:
If Base I/O Address is set below 0x100 then no decode will occur.
Select A & B registers in SCE Register Block
Three.
IR DMA CHANNELS
DMA channel 0, 1, 2 or 3 may be selected for
use with the IRCC 2.0 logic through the
configuration registers of Logical Device 5.
Refer to the Configuration section of this
specification for further details on setting the
DMA channel and to the IRCC 2.0 specification
for details on IR DMA transfers.
The FDC37N972 Software Select A register is
LD5:CRF7, the FDC37N972 Software Select B
register is LD5:CRF8. These registers are R/W.
Writing to LD5:CRF7 is the only way to revise
the contents of the Software Select A register in
the IrCC 2.0. Writing the contents of the
Software Select A register can only be done in
the configuration state and only after the LDN
has been set to “5” and the CSR has been
initialized to “F7H”. The default value of this
register after power up is 00H (TABLE 59).
IR IRQs
The interrupt (IRQ) for the IRCC 2.0 logic is
selectable through the configuration registers for
logical device 5. Refer to the Configuration
section of this specification for further details on
setting the IRQ and to the IRCC 2.0
specification for details on IR IRQ events.
Software Select Registers A and B
Writing to LD5:CRF8 is the only way to revise
the contents of the Software Select B register in
the IrCC 2.0. Writing the contents of the
Software Select B register can only be done in
the configuration state and only after the LDN
has been set to “5” and the CSR has been
initialized to “F8H”. The default value of this
register after power up is 00H (TABLE 59).
The Software Select A and Software Select B
registers in the FDC37N972 configuration space
in Logical Device Number 5 are directly
connected to the read-only IrCC 2.0 Software
105
LD5:CRF7
LD5:CRF8
TABLE 59 - FDC37N972 SOFTWARE SELECT A&B REGISTERS
D7
D6
D5
D4
D3
D2
D1
D0
R/W
Software Select A
R/W
Software Select B
DEFAULT
0x00
0x00
IR HALF DUPLEX TIMEOUT
changes in the IrCC 2.0. The IR Half Duplex
Time-Out is started as each IR message data
bit is transferred and prevents direction mode
changes until the time-out expires. The timer is
restarted whenever new data is transferred in
the current direction mode.
LD5:CRF2 is the FDC37N972 IR Half Duplex
Time-Out register (TABLE 60).
In the
FDC37N972, this register is linked to the IrCC
2.0 IR Half Duplex Time-Out register.
In the FDC37N972, these two registers must
behave like the other IrCC 2.0 legacy controls
where either source uniformly updates the value
of both registers registers when either register is
explicitly written using IOW or following a
device-level POR. IrCC 2.0 software resets do
not affect these registers.
The IR Half Duplex Time-Out is programmable
from 0 to 25.5ms in 100µs increments, as
follows:
IR HALF DUPLEX TIME-OUT = (CRF2) x
100µ
µs
The IR Half Duplex Time-Out constrains the
timing of transmit/receive direction mode
LD5:CRF2
TABLE 60 - IR HALF DUPLEX TIME-OUT REGISTER
D7
D6
D5
D4
D3
D2
D1
R/W
IR HALF DUPLEX TIME-OUT
D0
Default
0x03
Registers for information on disabling, power
down, changing the base address of the parallel
port, and selecting the mode of operation.
IRTX OUTPUT PINS DEFAULT
The IRCC 2.0 IRTX pins default at power-up to
“output”, “low” to prevent infrared transceiver
damage. This default behavior applies to both
the dedicated IRTX2 pin and to GPIO9 (see
General Purpose I/O (GPIO) on page 265).
The parallel port also incorporates SMSC's
ChiProtect circuitry, which prevents possible
damage to the parallel port due to printer powerup. The functionality of the parallel port is
achieved through
the
use
of
eight
addressable
ports,
with their associated
registers and control gating. The control and
data port are read/write by the CPU, the status
port is read/write in the EPP mode.
The
address map of the Parallel Port is shown
below:
PARALLEL PORT
The FDC37N972 incorporates an IBM XT/AT
compatible parallel port. This supports the
optional PS/2 type bi-directional parallel port
(SPP), the Enhanced Parallel Port (EPP) and
the Extended Capabilities Port (ECP) parallel
port modes.
Refer to the Configuration
106
TABLE 61 - ADDRESS MAP FOR PARALLEL PORT
REGISTER NAME
ADDRESS
DATA PORT
BASE ADDRESS + 00H
STATUS PORT
BASE ADDRESS + 01H
CONTROL PORT
BASE ADDRESS + 02H
EPP ADDR PORT
BASE ADDRESS + 03H
EPP DATA PORT 0
BASE ADDRESS + 04H
EPP DATA PORT 1
BASE ADDRESS + 05H
EPP DATA PORT 2
BASE ADDRESS + 06H
EPP DATA PORT 3
BASE ADDRESS + 07H
TABLE 62 - THE BIT MAP OF THESE REGISTERS IS:
D0
D1
D2
D3
D4
D5
D6
D7
NOTE
PD0
PD1
PD2
PD3
PD4
PD5 PD6
PD7
1
TMOUT
0
0
nERR
SLCT
PE nACK nBUSY
1
DATA PORT
STATUS
PORT
CONTROL
STROBE
PORT
EPP ADDR
PD0
PORT
EPP DATA
PD0
PORT 0
EPP DATA
PD0
PORT 1
EPP DATA
PD0
PORT 2
EPP DATA
PD0
PORT 3
ALF
nINIT
SLC
IRQE
PCD
0
0
1
PD1
PD2
PD3
PD4
PD5
PD6
AD7
2,3
PD1
PD2
PD3
PD4
PD5
PD6
PD7
2,3
PD1
PD2
PD3
PD4
PD5
PD6
PD7
2,3
PD1
PD2
PD3
PD4
PD5
PD6
PD7
2,3
PD1
PD2
PD3
PD4
PD5
PD6
PD7
2,3
Note 1: These registers are available in all modes.
Note 2: These registers are only available in EPP mode.
Note 3 : For EPP mode, IOCHRDY must be connected to the ISA bus.
107
TABLE 63 - PARALLEL PORT CONNECTOR PIN MAP
HOST
CONNECTOR PIN NUMBER STANDARD
EPP
ECP
1
129
nSTROBE
nWrite
nSTROBE
2-9
124-121,
PData<0:7> PData<0:7>
PData<0:7>
119-116
10
115
nAck
Intr
nAck
11
114
Busy
nWait
Busy, PeriphAck(3)
12
113
PE
(NU)
PError,
nAckReverse(3)
13
112
Select
(NU)
Select
14
128
Nalf
nDatastb
nALF,
HostAck(3)
15
127
NError
(NU)
nFault(1)
nPeriphRequest(3)
16
126
NInit
(NU)
nInit(1)
nReverseRqst(3)
17
125
NSelectin
nAddrstrb
nSelectIn(1,3)
(1)= Compatible Mode
(3)= High Speed Mode
Note:
For the cable interconnection required for ECP support and the Slave Connector pin
numbers, refer to the IEEE P1284 D2.0 Standard, “Standard Signaling Method for a Bi-directional
Parallel Peripheral Interface for Personal Computers”, September 10, 1993. This document is
available from the IEEE.
IBM XT/AT COMPATIBLE, BI-DIRECTIONAL
AND EPP MODES
STATUS PORT
ADDRESS OFFSET = 01H
DATA PORT
ADDRESS OFFSET = 00H
The Status Port is located at an offset of '01H'
from the base address. The contents of this
register are latched for the duration of an nIOR
read cycle. The bits of the Status Port are
defined as follows:
The Data Port is located at an offset of '00H'
from the base address. The data register is
cleared at initialization by RESET. During a
WRITE operation, the Data Register latches the
contents of the data bus with the rising edge of
the nIOW input. The contents of this register
are buffered (non inverting) and output onto the
PD0-PD7 ports. During a READ operation in
SPP mode, PD0-PD7 ports are buffered (not
latched) and output to the host CPU.
BIT 0 TMOUT - TIME OUT
This bit is valid in EPP mode only and indicates
that a 10 µsec time out has occured on the EPP
bus. A logic “0” means that no time out error
has occured; a logic “1” means that a time out
error has been detected. This bit is cleared by a
RESET. Writing a one to this bit clears the time
out status bit. On a write, this bit is self clearing
and does not require a write of a “0”. Writing a
“0” to this bit has no effect.
108
initialized by the RESET input, bits 0 to 5 only
being affected; bits 6 and 7 are hard wired low.
BITS 1, 2 - are not implemented as register bits,
during a read of the Printer Status Register
these bits are a low level.
BIT 0 STROBE - STROBE
This bit is inverted and output onto the
nSTROBE output.
BIT 3 nERR - nERROR
The level on the nERROR input is read by the
CPU as bit 3 of the Printer Status Register. A
logic 0 means an error has been detected; a
logic “1” means no error has been detected.
BIT 1 ALF - AUTOFEED
This bit is inverted and output onto the nALF
output.
A logic “1” causes the printer to
generate a line feed after each line is printed. A
logic “0” means no autofeed.
BIT 4 SLCT - PRINTER SELECTED STATUS
The level on the SLCT input is read by the CPU
as bit 4 of the Printer Status Register. A logic
“1” means the printer is on line; a logic 0 means
it is not selected.
BIT 2 nINIT - nINITIATE OUTPUT
This bit is output onto the nINIT output without
inversion.
BIT 5 PE - PAPER END
The level on the PE input is read by the CPU as
bit 5 of the Printer Status Register. A logic “1”
indicates a paper end; a logic 0 indicates the
presence of paper.
BIT 3 SLCTIN - PRINTER SELECT INPUT
This bit is inverted and output onto the nSLCTIN
output. A logic “1” on this bit selects the printer;
a logic “0” means the printer is not selected.
BIT 6 nACK - nACKNOWLEDGE
The level on the nACK input is read by the CPU
as bit 6 of the Printer Status Register. A logic
“0” means that the printer has received a
character and can now accept another. A logic
“1” means that it is still processing the last
character or has not received the data.
BIT 4 IRQE - INTERRUPT REQUEST ENABLE
The interrupt request enable bit when set to a
high level may be used to enable interrupt
requests from the Parallel Port to the CPU. An
interrupt request is generated on the IRQ port by
a positive going nACK input. When the IRQE
bit is programmed low the IRQ is disabled.
BIT 7 nBUSY - nBUSY
The complement of the level on the BUSY input
is read by the CPU as bit 7 of the Printer Status
Register. A logic “0” in this bit means that the
printer is busy and cannot accept a new
character. A logic “1” means that it is ready to
accept the next character.
BIT 5 PCD - PARALLEL CONTROL
DIRECTION
Parallel Control Direction is not valid in printer
mode. In printer mode, the direction is always
out regardless of the state of this bit. In bidirectional, EPP or ECP mode, a logic 0 means
that the printer port is in output mode (write); a
logic “1” means that the printer port is in input
mode (read).
CONTROL PORT
ADDRESS OFFSET = 02H
Bits 6 and 7 during a read are a low level, and
cannot be written
The Control Port is located at an offset of '02H'
from the base address. The Control Register is
109
EPP ADDRESS PORT
ADDRESS OFFSET = 03H
EPP DATA PORT 1
ADDRESS OFFSET = 05H
The EPP Address Port is located at an offset of
'03H' from the base address. The address
register is cleared at initialization by RESET.
During a WRITE operation, the contents of DB0DB7 are buffered (non inverting) and output onto
the PD0 - PD7 ports, the leading edge of nIOW
causes an EPP ADDRESS WRITE cycle to be
performed, the trailing edge of IOW latches the
data for the duration of the EPP write cycle.
During a READ operation, PD0-PD7 ports are
read, the leading edge of IOR causes an EPP
ADDRESS READ cycle to be performed and the
data output to the host CPU, the deassertion of
ADDRSTB latches the PData for the duration of
the IOR cycle. This register is only available in
EPP mode.
The EPP Data Port 1 is located at an offset of
'05H' from the base address. Refer to EPP
DATA PORT 0 for a description of operation.
This register is only available in EPP mode.
EPP DATA PORT 2
ADDRESS OFFSET = 06H
The EPP Data Port 2 is located at an offset of
'06H' from the base address. Refer to EPP
DATA PORT 0 for a description of operation.
This register is only available in EPP mode.
EPP DATA PORT 3
ADDRESS OFFSET = 07H
The EPP Data Port 3 is located at an offset of
'07H' from the base address. Refer to EPP
DATA PORT 0 for a description of operation.
This register is only available in EPP mode.
EPP DATA PORT 0
ADDRESS OFFSET = 04H
The EPP Data Port 0 is located at an offset of
'04H' from the base address. The data register
is cleared at initialization by RESET. During a
WRITE operation, the contents of DB0-DB7 are
buffered (non inverting) and output onto the
PD0-PD7 ports, the leading edge of nIOW
causes an EPP DATA WRITE cycle to be
performed, the trailing edge of IOW latches the
data for the duration of the EPP write cycle.
During a READ operation, PD0 - PD7 ports are
read, the leading edge of IOR causes an EPP
READ cycle to be performed and the data
output to the host CPU, the deassertion of
DATASTB latches the PData for the duration of
the IOR cycle. This register is only available in
EPP mode.
EPP 1.9 OPERATION
When the EPP mode is selected in the
configuration register, the standard and bidirectional modes are also available. If no EPP
Read, Write or Address cycle is currently
executing, then the PDx bus is in the standard or
bi-directional mode, and all output signals
(STROBE, ALF, INIT) are as set by the SPP
Control Port and direction is controlled by PCD
of the Control port.
In EPP mode, the system timing is closely
coupled to the EPP timing. For this reason, a
watchdog timer is required to prevent system
lockup. The timer indicates if more than 10µsec
have elapsed from the start of the EPP cycle
(nIOR or nIOW asserted) to nWAIT being
deasserted (after command). If a time-out
occurs, the current EPP cycle is aborted and the
time-out condition is indicated in Status bit 0.
110
During an EPP cycle, if STROBE is active, it
overrides the EPP write signal forcing the PDx
bus to always be in a write mode and the
nWRITE signal to always be asserted.
4.
SOFTWARE CONSTRAINTS
6.
5.
Before an EPP cycle is executed, the software
must ensure that the control register bit PCD is
a logic "0" (i.e. a 04H or 05H should be written
to the Control port). If the user leaves PCD as
a logic "1", and attempts to perform an EPP
write, the chip is unable to perform the write
(because PCD is a logic "1") and will appear to
perform an EPP read on the parallel bus, no
error is indicated.
7.
EPP 1.9 WRITE
8.
The timing for a write operation (address or
data) is shown in timing diagram EPP Write
Data or Address cycle. IOCHRDY is driven
active low at the start of each EPP write and is
released when it has been determined that the
write cycle can complete. The write cycle can
complete under the following circumstances:
9.
The chip places address or data on PData
bus, clears PDIR, and asserts nWRITE.
Chip asserts nDATASTB or nADDRSTRB
indicating that PData bus contains valid
information, and the WRITE signal is valid.
Peripheral deasserts nWAIT, indicating that
any setup requirements have been satisfied
and the chip may begin the termination
phase of the cycle.
a)The chip deasserts nDATASTB or
nADDRSTRB, this marks the beginning of
the termination phase. If it has not already
done so, the peripheral should latch the
information byte now.
b)The chip latches the data from the SData
bus for the PData bus and asserts
(releases) IOCHRDY allowing the host to
complete the write cycle.
Peripheral asserts nWAIT, indicating to the
host that any hold time requirements have
been satisfied and acknowledging the
termination of the cycle.
Chip may modify nWRITE and nPDATA in
preparation for the next cycle.
EPP 1.9 READ
The timing for a read operation (data) is shown
in timing diagram EPP Read Data cycle.
IOCHRDY is driven active low at the start of
each EPP read and is released when it has been
determined that the read cycle can complete.
The read cycle can complete under the following
circumstances:
1.If the EPP bus is not ready (nWAIT is active
low) when nDATASTB or nADDRSTB goes
active then the write can complete when nWAIT
goes inactive high.
2.If the EPP bus is ready (nWAIT is inactive
high) then the chip must wait for it to go active
low before changing the state of nDATASTB,
nWRITE or nADDRSTB.
The write can
complete once nWAIT is determined inactive.
1.If the EPP bus is not ready (nWAIT is active
low) when nDATASTB goes active then the
read can complete when nWAIT goes inactive
high.
Write Sequence of operation
1. The host selects an EPP register, places
data on the SData bus and drives nIOW
active.
2. The chip drives IOCHRDY inactive (low).
3. If WAIT is not asserted, the chip must wait
until WAIT is asserted.
2.If the EPP bus is ready (nWAIT is inactive
high) then the chip must wait for it to go active
low before changing the state of WRITE or
before nDATASTB goes active. The read can
complete once nWAIT is determined inactive.
111
In EPP mode, the system timing is closely
coupled to the EPP timing. For this reason, a
watchdog timer is required to prevent system
lockup. The timer indicates if more than 10µsec
have elapsed from the start of the EPP cycle
(nIOR or nIOW asserted) to the end of the cycle
nIOR or nIOW deasserted).
If a time-out
occurs, the current EPP cycle is aborted and the
time-out condition is indicated in Status bit 0.
Read Sequence of Operation
1.
The host selects an EPP register and drives
nIOR active.
2. The chip drives IOCHRDY inactive (low).
3. If WAIT is not asserted, the chip must wait
until WAIT is asserted.
4. The chip tri-states the PData bus and
deasserts nWRITE.
5. Chip asserts nDATASTB or nADDRSTRB
indicating that PData bus is tri-stated, PDIR
is set and the nWRITE signal is valid.
6. Peripheral drives PData bus valid.
7. Peripheral deasserts nWAIT, indicating that
PData is valid and the chip may begin the
termination phase of the cycle.
8. a)The chip latches the data from the PData
bus for the SData bus and deasserts
nDATASTB or nADDRSTRB. This marks
the beginning of the termination phase.
b)The chip drives the valid data onto the
SData bus and asserts (releases)
IOCHRDY allowing the host to complete the
read cycle.
9. Peripheral tri-states the PData bus and
asserts nWAIT, indicating to the host that
the PData bus is tri-stated.
10. Chip may modify nWRITE, PDIR and
nPDATA in preparation for the next
cycle.Peripheral
deasserts
nWAIT,
indicating that PData is valid and the chip
may begin the termination phase of the
cycle.
SOFTWARE CONSTRAINTS
Before an EPP cycle is executed, the software
must ensure that the control register bits D0, D1
and D3 are set to zero. Also, bit D5 (PCD) is a
logic "0" for an EPP write or a logic "1" for and
EPP read.
EPP 1.7 Write
The timing for a write operation (address or
data) is shown in timing diagram EPP 1.7 Write
Data or Address cycle. IOCHRDY is driven
active low when nWAIT is active low during the
EPP cycle. This can be used to extend the cycle
time.
The write cycle can complete when
nWAIT is inactive high.
Write Sequence of Operation
The host sets PDIR bit in the control register to
a logic "0". This asserts nWRITE.
The host selects an EPP register, places data
on the SData bus and drives nIOW active.
The chip places address or data on PData bus.
Chip asserts nDATASTB or nADDRSTRB
indicating that PData bus contains valid
information, and the WRITE signal is valid.
If nWAIT is asserted, IOCHRDY is deasserted
until the peripheral deasserts nWAIT or a timeout occurs.
EPP 1.7 OPERATION
When the EPP 1.7 mode is selected in the
configuration register, the standard and bidirectional modes are also available. If no EPP
Read, Write or Address cycle is currently
executing, then the PDx bus is in the standard or
bi-directional mode, and all output signals
(STROBE, ALF, INIT) are as set by the SPP
Control Port and direction is controlled by PCD
of the Control port.
When the host deasserts nIOW the chip
deasserts nDATASTB or nADDRSTRB and
latches the data from the SData bus for the
PData bus.
112
3.
Chip may modify nWRITE, PDIR and nPDATA
in preparation of the next cycle.
EPP 1.7 READ
4.
The timing for a read operation (data) is shown
in timing diagram EPP 1.7 Read Data cycle.
IOCHRDY is driven active low when nWAIT is
active low during the EPP cycle. This can be
used to extend the cycle time. The read cycle
can complete when nWAIT is inactive high.
5.
6.
7.
Read Sequence of Operation
1.
The host sets PDIR bit in the control
register to a logic "1". This deasserts
nWRITE and tri-states the PData bus.
2.
The host selects an EPP register and
drives nIOR active.
8.
9.
Chip
asserts
nDATASTB
or
nADDRSTRB indicating that PData bus
is tri-stated, PDIR is set and the
nWRITE signal is valid.
If nWAIT is asserted, IOCHRDY is
deasserted
until
the
peripheral
deasserts nWAIT or a time-out occurs.
The Peripheral drives PData bus valid.
The Peripheral deasserts nWAIT,
indicating that PData is valid and the
chip may begin the termination phase
of the cycle.
When the host deasserts nIOR the chip
deasserts nDATASTB or nADDRSTRB.
Peripheral tri-states the PData bus.
Chip may modify nWRITE, PDIR and
nPDATA reparation of the next cycle.
TABLE 64 - EPP PIN DESCRIPTIONS
EPP
SIGNAL
nWRITE
PD<0:7>
INTR
WAIT
DATASTB
RESET
ADDRSTB
PE
SLCT
nERR
EPP NAME
nWrite
Address/Data
Interrupt
TYPE
O
I/O
I
I
I
EPP DESCRIPTION
This signal is active low. It denotes a write operation.
Bi-directional EPP byte wide address and data bus.
This signal is active high and positive edge triggered. (Pass
through with no inversion, Same as SPP).
This signal is active low. It is driven inactive as a positive
acknowledgement from the device that the transfer of data is
completed. It is driven active as an indication that the device
is ready for the next transfer.
This signal is active low. It is used to denote data read or
write operation.
This signal is active low. When driven active, the EPP
device is reset to its initial operational mode.
This signal is active low. It is used to denote address read
or write operation.
Same as SPP mode.
Same as SPP mode.
nWait
I
nData Strobe
O
nReset
O
nAddress
Strobe
Paper End
Printer
Selected Status
Error
O
I
Same as SPP mode.
113
EPP
SIGNAL
PDIR
EPP NAME
Parallel Port
Direction
TYPE
O
EPP DESCRIPTION
This output shows the direction of the data transfer on the
parallel port bus. A low means an output/write condition and
a high means an input/read condition. This signal is normally
a low (output/write) unless PCD of the control register is set
or if an EPP read cycle is in progress.
Note 1: SPP and EPP can use 1 common register.
Note 2: nWrite is the only EPP output that can be over-ridden by SPP control port during an EPP
cycle. For correct EPP read cycles, PCD is required to be a low.
EXTENDED CAPABILITIES PARALLEL PORT
ECP provides a number of advantages, some of which are listed below. The individual features are
explained in greater detail in the remainder of this section.
High performance half-duplex forward and reverse channel
Interlocked handshake, for fast reliable transfer
Optional single byte RLE compression for improved throughput (64:1)
Channel addressing for low-cost peripherals
Maintains link and data layer separation
Permits the use of active output drivers
Permits the use of adaptive signal timing
Peer-to-peer capability
VOCABULARY
The following terms are used in this document:
assert: When a signal asserts it transitions to a "true" state, when a signal deasserts it transitions to
a "false" state.
forward: Host to Peripheral communication.
reverse: Peripheral to Host communication.
PWord: A port word; equal in size to the width of the ISA interface. For this implementation, PWord is
always 8 bits.
1:
A high level.
0:
A low level.
These terms may be considered synonymous:
PeriphClk, nAck
HostAck, nALF
PeriphAck, Busy
nPeriphRequest, nFault
nReverseRequest, nInit
114
nAckReverse, PError
Xflag, Select
ECPMode, nSelectln
HostClk, nSTROBE
Reference Document
IEEE 1284 Extended Capabilities Port Protocol and ISA Interface Standard, Rev 1.14, July 14, 1993.
This document is available from Microsoft.
TABLE 65 - BIT MAP OF THE EXTENDED PARALLEL PORT REGISTERS
D7
D6
D5
D4
D3
D2
D1
D0
data
PD7
PD6
PD5
PD4
PD3
PD2
PD1 PD0
ecpAFifo Addr/RL
Address or RLE field
E
dsr
nBusy
nAck
PError
Select
nFault
0
0
0
dcr
0
0
Direction ackIntEn SelectIn
nInit
alf
strobe
cFifo
Parallel Port Data FIFO
ecpDFifo
ECP Data FIFO
tFifo
Test FIFO
cnfgA
0
0
0
1
0
0
0
0
cnfgB
compres intrValue
0
0
0
0
0
0
s
nErrIntrEn dmaEn serviceIntr full
ecr
MODE
empty
Note 1: These registers are available in all modes.
Note 2: All FIFOs use one common 16 byte FIFO.
115
NOTE
2
1
1
2
2
2
it provides an automatic high burst-bandwidth
channel that supports DMA for ECP in both the
forward and reverse directions.
ISA IMPLEMENTATION STANDARD
This specification describes the standard ISA
interface to the Extended Capabilities Port
(ECP). All ISA devices supporting ECP must
meet the requirements contained in this section
or the port will not be supported by Microsoft.
For a description of the ECP Protocol, please
refer to the IEEE 1284 Extended Capabilities
Port Protocol and ISA Interface Standard, Rev.
1.14, July 14, 1993. This document is available
from Microsoft.
Small FIFOs are employed in both forward and
reverse directions to smooth data flow and
improve the maximum bandwidth requirement.
The size of the FIFO is 16 bytes deep. The port
supports an automatic handshake for the
standard parallel port to improve compatibility
mode transfer speed.
The port also supports run length encoded
(RLE) decompression (required) in hardware.
Compression is accomplished by counting
identical bytes and transmitting an RLE byte
that indicates how many times the next byte is
to be repeated. Decompression simply
intercepts the RLE byte and repeats the
following byte the specified number of times.
Hardware support for compression is optional.
DESCRIPTION
The port is software and hardware compatible
with existing parallel ports so that it may be
used as a standard LPT port if ECP is not
required. The port is designed to be simple and
requires a small number of gates to implement.
It does not do any "protocol" negotiation, rather
NAME
nSTROBE
PData 7:0
nAck
PeriphAck (Busy)
PError
(nAckReverse)
Select
TABLE 66 - ECP PIN DESCRIPTIONS
TYPE
DESCRIPTION
O
During write operations nSTROBE registers data or address into the
slave on the asserting edge (handshakes with Busy).
I/O
Contains address or data or RLE data.
I
Indicates valid data driven by the peripheral when asserted. This signal
handshakes with nALF in reverse.
I
This signal deasserts to indicate that the peripheral can accept data.
This signal handshakes with nSTROBE in the forward direction. In the
reverse direction this signal indicates whether the data lines contain
ECP command information or data. The peripheral uses this signal to
flow control in the forward direction. It is an "interlocked" handshake
with nSTROBE. PeriphAck also provides command information in the
reverse direction.
I
Used to acknowledge a change in the direction the transfer (asserted =
forward). The peripheral drives this signal low to acknowledge
nReverseRequest. It is an "interlocked" handshake with
nReverseRequest. The host relies upon nAckReverse to determine
when it is permitted to drive the data bus.
I
Indicates printer on line.
116
NAME
nALF
(HostAck)
nFault
(nPeriphRequest)
nInit
nSelectIn
TYPE
DESCRIPTION
O
Requests a byte of data from the peripheral when asserted,
handshaking with nAck in the reverse direction. In the forward direction
this signal indicates whether the data lines contain ECP address or
data. The host drives this signal to flow control in the reverse direction.
It is an "interlocked" handshake with nAck. HostAck also provides
command information in the forward phase.
I
Generates an error interrupt when asserted. This signal provides a
mechanism for peer-to-peer communication. This signal is valid only in
the forward direction. During ECP Mode the peripheral is permitted
(but not required) to drive this pin low to request a reverse transfer. The
request is merely a "hint" to the host; the host has ultimate control over
the transfer direction. This signal would be typically used to generate
an interrupt to the host CPU.
O
Sets the transfer direction (asserted = reverse, deasserted = forward).
This pin is driven low to place the channel in the reverse direction. The
peripheral is only allowed to drive the bi-directional data bus while in
ECP Mode and HostAck is low and nSelectIn is high.
O
Always deasserted in ECP mode.
port is equivalent to a generic parallel port
interface and may be operated in that mode.
The port registers vary depending on the mode
field in the ecr. The table below lists these
dependencies. Operation of the devices in
modes other that those specified is undefined.
REGISTER DEFINITIONS
The register definitions are based on the
standard IBM addresses for LPT. All of the
standard printer ports are supported.
The
additional registers attach to an upper bit
decode of the standard LPT port definition to
avoid conflict with standard ISA devices. The
NAME
data
ecpAFifo
dsr
dcr
cFifo
ecpDFifo
tFifo
cnfgA
cnfgB
ecr
TABLE 67 - ECP REGISTER DEFINITIONS
ADDRESS (Note 1) ECP MODES FUNCTION
+000h R/W
000-001
Data Register
+000h R/W
011
ECP FIFO (Address)
+001h R/W
All
Status Register
+002h R/W
All
Control Register
+400h R/W
010
Parallel Port Data FIFO
+400h R/W
011
ECP FIFO (DATA)
+400h R/W
110
Test FIFO
+400h R
111
Configuration Register A
+401h R/W
111
Configuration Register B
+402h R/W
All
Extended Control Register
Note 1: These addresses are added to the parallel port base address as selected by configuration
register or jumpers.
Note 2: All addresses are qualified with AEN. Refer to the AEN pin definition.
117
TABLE 68 - EXTENDED CONTROL REGISTER MODE DESCRIPTIONS
MODE
DESCRIPTION*
000
SPP mode
001
PS/2 Parallel Port mde
010
Parallel Port Data FIFO mode
011
ECP Parallel Port mode
100
EPP mode (If this option is enabled in the configuration registers)
101
(Reserved)
110
Test mode
111
Configuration mode
*Refer to ECR Register Description
DATA AND ECPAFIFO PORT
ADDRESS OFFSET = 00H
Modes 000 and 001 (Data Port)
The Data Port is located at an offset of '00H' from the base address. The data register is cleared at
initialization by RESET. During a WRITE operation, the Data Register latches the contents of the data
bus on the rising edge of the nIOW input. The contents of this register are buffered (non inverting)
and output onto the PD0 - PD7 ports. During a READ operation, PD0 - PD7 ports are read and output
to the host CPU.
Mode 011 (ECP FIFO - Address/RLE)
A data byte written to this address is placed in the FIFO and tagged as an ECP Address/RLE. The
hardware at the ECP port transmitts this byte to the peripheral automatically. The operation of this
register is ony defined for the forward direction (direction is 0). Refer to the ECP Parallel Port Forward
Timing Diagram, located in the Timing Diagrams section of this data sheet .
DEVICE STATUS REGISTER (DSR)
ADDRESS OFFSET = 01H
The Status Port is located at an offset of '01H' from the base address. Bits 0-2 are not implemented
as register bits, during a read of the Printer Status Register these bits are a low level. The bits of the
Status Port are defined as follows:
BIT 3 nFault
The level on the nFault input is read by the CPU as bit 3 of the Device Status Register.
BIT 4 Select
The level on the Select input is read by the CPU as bit 4 of the Device Status Register.
118
BIT 5 PError
The level on the PError input is read by the CPU as bit 5 of the Device Status Register. Printer Status
Register.
BIT 6 nAck
The level on the nAck input is read by the CPU as bit 6 of the Device Status Register.
BIT 7 nBusy
The complement of the level on the BUSY input is read by the CPU as bit 7 of the Device Status
Register.
DEVICE CONTROL REGISTER (DCR)
ADDRESS OFFSET = 02H
The Control Register is located at an offset of '02H' from the base address. The Control Register is
initialized to zero by the RESET input, bits 0 to 5 only being affected; bits 6 and 7 are hard wired low.
BIT 0 STROBE - STROBE
This bit is inverted and output onto the nSTROBE output.
BIT 1 ALF - AUTOFEED
This bit is inverted and output onto the nALF output. A logic “1” causes the printer to generate a line
feed after each line is printed. A logic “0” means no autofeed.
BIT 2 nINIT - nINITIATE OUTPUT
This bit is output onto the nINIT output without inversion.
BIT 3 SELECTIN
This bit is inverted and output onto the nSLCTIN output. A logic “1” on this bit selects the printer; a
logic “0” means the printer is not selected.
BIT 4 ackIntEn - INTERRUPT REQUEST ENABLE
The interrupt request enable bit when set to a high level may be used to enable interrupt requests
from the Parallel Port to the CPU due to a low to high transition on the nACK input. Refer to the
description of the interrupt under Operation, Interrupts.
BIT 5 DIRECTION
If mode=000 or mode=010, this bit has no effect and the direction is always out regardless of the state
of this bit. In all other modes, Direction is valid and a logic 0 means that the printer port is in output
mode (write); a logic “1” means that the printer port is in input mode (read).
BITS 6 and 7 during a read are a low level, and cannot be written.
119
the tFIFO. If an attempt is made to read data
from an empty tFIFO, the last data byte is reread again. The full and empty bits must
always keep track of the correct FIFO state.
The tFIFO will transfer data at the maximum
ISA rate so that software may generate
performance metrics.
The FIFO size and
interrupt threshold can be determined by writing
bytes to the FIFO and checking the full and
serviceIntr bits.
CFIFO (PARALLEL PORT DATA FIFO)
ADDRESS OFFSET = 400H
Mode = 010
Bytes written or DMAed from the system to this
FIFO are transmitted by a hardware handshake
to the peripheral using the standard parallel port
protocol.
Transfers to the FIFO are byte
aligned. This mode is only defined for the
forward direction.
The writeIntrThreshold can be derermined by
starting with a full tFIFO, setting the direction bit
to “0” and emptying it a byte at a time until
serviceIntr is set. This may generate a spurious
interrupt, but will indicate that the threshold has
been reached.
ECPDFIFO (ECP DATA FIFO)
ADDRESS OFFSET = 400H
Mode = 011
Bytes written or DMAed from the system to this
FIFO, when the direction bit is “0”, are
transmitted by a hardware handshake to the
peripheral using the ECP parallel port protocol.
Transfers to the FIFO are byte aligned.
The readIntrThreshold can be derermined by
setting the direction bit to “1” and filling the
empty tFIFO a byte at a time until serviceIntr is
set. This may generate a spurious interrupt, but
will indicate that the threshold has been
reached.
Data bytes from the peripheral are read under
automatic hardware handshake from ECP into
this FIFO when the direction bit is “1”. Reads or
DMAs from the FIFO will return bytes of ECP
data to the system.
Data bytes are always read from the head of
tFIFO regardless of the value of the direction bit.
For example if 44h, 33h, 22h is written to the
FIFO, then reading the tFIFO will return 44h,
33h, 22h in the same order as was written.
TFIFO (TEST FIFO MODE)
ADDRESS OFFSET = 400H
CNFGA (CONFIGURATION REGISTER A)
ADDRESS OFFSET = 400H
Mode = 110
Mode = 111
Data bytes may be read, written or DMAed to or
from the system to this FIFO in any direction.
Data in the tFIFO will not be transmitted to the
to the parallel port lines using a hardware
protocol handshake.
However, data in the
tFIFO may be displayed on the parallel port data
lines.
This register is a read only register. When read,
10H is returned. This indicates to the system
that this is an 8-bit implementation. (PWord = 1
byte)
cnfgB (Configuration Register B)
ADDRESS OFFSET = 401H
The tFIFO will not stall when overwritten or
underrun. If an attempt is made to write data to
a full tFIFO, the new data is not accepted into
Mode = 111
120
BIT 7 compress
This bit is read only. During a read it is a low
level. This means that this chip does not
support hardware RLE compression. It does
support hardware de-compression!
BIT 3 dmaEn
Read/Write
1:
Enables DMA (DMA starts
serviceIntr is 0).
0:
Disables DMA unconditionally.
BIT 6 intrvalue
Returns the value on the ISA iRq line to
determine possible conflicts.
BIT 2 serviceIntr
Read/Write
1:
Disables DMA and all of the service
interrupts.
0:
Enables one of the following 3 cases of
interrupts. Once one of the 3 service interrupts
has occurred serviceIntr bit shall be set to a 1 by
hardware. It must be reset to 0 to re-enable the
interrupts. Writing this bit to a 1 will not cause
an interrupt.
case dmaEn=1:
During DMA (this bit is set to a “1” when
terminal count is reached).
case dmaEn=0 direction=0:
BITS 5:0 Reserved
During a read are a low level. These bits cannot
be written.
ecr (Extended Control Register)
ADDRESS OFFSET = 402H
Mode = all
This register controls the extended ECP parallel
port functions.
BITS 7 - 5
These bits are Read/Write and select the Mode.
when
This bit shall be set to 1 whenever there are
writeIntrThreshold or more bytes free in the
FIFO.
case dmaEn=0 direction=1:
This bit shall be set to 1 whenever there are
readIntrThreshold or more valid bytes to be read
from the FIFO.
BIT 4 nErrIntrEn
Read/Write (Valid only in ECP Mode)
1:
Disables the interrupt generated on the
asserting edge of nFault.
0:
Enables an interrupt pulse on the high
to low edge of nFault. Note that an interrupt will
be generated if nFault is asserted (interrupting)
and this bit is written from a 1 to a 0. This
prevents interrupts from being lost in the time
between the read of the ecr and the write of the
ecr.
BIT 1 full
Read only
1:
The FIFO cannot accept another byte
or the FIFO is completely full.
0:
The FIFO has at least 1 free byte.
BIT 0 empty
Read only
1:
The FIFO is completely empty.
0:
The FIFO contains at least 1 byte of
data.
121
R/W
000:
001:
010:
011:
100:
101:
R/W
110:
111:
TABLE 69 - EXTENDED CONTROL REGISTER
MODE
Standard Parallel Port Mode . In this mode the FIFO is reset and common collector drivers
are used on the control lines (nSTROBE, nALF, nInit and nSelectIn). Setting the direction bit
will not tri-state the output drivers in this mode.
PS/2 Parallel Port Mode. Same as above except that direction may be used to tri-state the
data lines and reading the data register returns the value on the data lines and not the value
in the data register. All drivers have active pull-ups (push-pull).
Parallel Port FIFO Mode. This is the same as 000 except that bytes are written or DMAed to
the FIFO. FIFO data is automatically transmitted using the standard parallel port protocol.
Note that this mode is only useful when direction is 0. All drivers have active pull-ups
(push-pull).
ECP Parallel Port Mode. In the forward direction (direction is 0) bytes placed into the
ecpDFifo and bytes written to the ecpAFifo are placed in a single FIFO and transmitted
automatically to the peripheral using ECP Protocol. In the reverse direction (direction is 1)
bytes are moved from the ECP parallel port and packed into bytes in the ecpDFifo. All
drivers have active pull-ups (push-pull).
Selects EPP Mode: In this mode, EPP is selected if the EPP supported option is selected in
configuration register L3-CRF0. All drivers have active pull-ups (push-pull).
Reserved
MODE
Test Mode. In this mode the FIFO may be written and read, but the data will not be
transmitted on the parallel port. All drivers have active pull-ups (push-pull).
Configuration Mode. In this mode the confgA, confgB registers are accessible at 0x400 and
0x401. All drivers have active pull-ups (push-pull).
122
OPERATION
After negotiation, it is necessary to initialize
some of the port bits. The following are required:
MODE SWITCHING/SOFTWARE CONTROL
Software will execute P1284 negotiation and all
operation prior to a data transfer phase under
programmed I/O control (mode 000 or 001).
Hardware provides an automatic control line
handshake, moving data between the FIFO and
the ECP port only in the data transfer phase
(modes 011 or 010).
Set Direction = 0, enabling the drivers.
Set strobe = 0, causing the nSTROBE signal to
default to the deasserted state.
Set alf= 0, causing the nALF signal to default to
the deasserted state.
Set mode = 011 (ECP Mode)
ECP address/RLE bytes or data bytes may be
sent automatically by writing the ecpAFifo or
ecpDFifo respectively.
Setting the mode to 011 or 010 will cause the
hardware to initiate data transfer.
If the port is in mode 000 or 001 it may switch to
any other mode. If the port is not in mode 000
or 001 it can only be switched into mode 000 or
001. The direction can only be changed in
mode 001.
Note that all FIFO data transfers are byte wide
and byte aligned. Address/RLE transfers are
byte-wide and only allowed in the forward
direction.
The host may switch directions by first switching
to mode = 001, negotiating for the forward or
reverse channel, setting direction to “1” or “0”,
then setting mode = 011. When direction is 1
the hardware shall handshake for each ECP
read data byte and attempt to fill the FIFO.
Bytes may then be read from the ecpDFifo as
long as it is not empty.
Once in an extended forward mode the software
should wait for the FIFO to be empty before
switching back to mode 000 or 001. In this case
all control signals will be deasserted before the
mode switch. In an ecp reverse mode the
software waits for all the data to be read from
the FIFO before changing back to mode 000 or
001.
Since the automatic hardware
ecp
reverse handshake only cares about the state of
the FIFO it may have acquired extra data which
will be discarded. It may in fact be in the middle
of a transfer when the mode is changed back to
000 or 001. In this case the port will deassert
nALF independent of the state of the transfer.
The design shall not cause glitches on the
handshake signals if the software meets the
constraints above.
ECP transfers may also be accomplished (albeit
slowly) by handshaking individual bytes under
program control in mode = 001, or 000.
TERMINATION FROM ECP MODE
Termination from ECP Mode is similar to the
termination from Nibble/Byte Modes. The host is
permitted to terminate from ECP Mode only in
specific well-defined states. The termination can
only be executed while the bus is in the forward
direction. To terminate while the channel is in
the reverse direction, it must first be transitioned
into the forward direction.
ECP OPERATION
Prior to ECP operation the Host must negotiate
on the parallel port to determine if the peripheral
supports the ECP protocol. This is a somewhat
complex negotiation carried out under program
control in mode 000.
123
The most significant bit of the command
indicates whether it is a run-length count (for
compression) or a channel address.
COMMAND/DATA
ECP Mode supports two advanced features to
improve the effectiveness of the protocol for
some
applications.
The
features
are
implemented by allowing the transfer of normal
8 bit data or 8 bit commands.
When in the reverse direction, normal data is
transferred when PeriphAck is high and an 8 bit
command is transferred when PeriphAck is low.
The most significant bit of the command is
always “0”. Reverse channel addresses are
seldom used and may not be supported in
hardware.
When in the forward direction, normal data is
transferred when HostAck is high and an 8 bit
command is transferred when HostAck is low.
TABLE 70 - FORWARD CHANNEL COMMANDS (HOSTACK LOW) &
REVERSE CHANNEL COMMANDS (PERIPACK LOW)
D7
D[6:0]
0
Run-Length Count (0-127)
(mode 0011 0X00 only)
1
Channel Address (0-127)
DATA COMPRESSION
PIN DEFINITION
The ECP port supports run length encoded
(RLE) decompression in hardware and can
transfer compressed data to a peripheral. Run
length encoded (RLE) compression in hardware
is not supported. To transfer compressed data
in ECP mode, the compression count is written
to the ecpAFifo and the data byte is written to
the ecpDFifo.
The drivers for nSTROBE, nALF, nInit and
nSelectIn are open-collector in mode 000 and
are push-pull in all other modes.
ISA CONNECTIONS
The interface can never stall causing the host to
hang. The width of data transfers is strictly
controlled on an I/O address basis per this
specification. All FIFO-DMA transfers are byte
wide, byte aligned and end on a byte boundary.
(The PWord value can be obtained by reading
Configuration Register A, cnfgA, described in
the next section.) Single byte wide transfers
are always possible with standard or PS/2
mode using program control of the control
signals.
Compression is accomplished by counting
identical bytes and transmitting an RLE byte
that indicates how many times the next byte is
to be repeated.
Decompression simply
intercepts the RLE byte and repeats the
following byte the specified number of times.
When a run-length count is received from a
peripheral, the subsequent data byte is
replicated the specified number of times. A
run-length count of zero specifies that only one
byte of data is represented by the next data
byte, whereas a
run-length count of 127
indicates that the next byte should be expanded
to 128 bytes. To prevent data expansion,
however, run-length counts of zero should be
avoided.
INTERRUPTS
The interrupts are enabled by serviceIntr in the
ecr register.
serviceIntr = 1
Disables the DMA and all of
the service interrupts.
124
Programmed I/O cycle or PDRQ depending on
the selection of DMA or Programmed I/O mode.
serviceIntr = 0
Enables the selected interrupt
condition. If the interrupting condition is valid,
then the interrupt is generated immediately
when this bit is changed from a 1 to a 0. This
can occur during Programmed I/O if the number
of bytes removed or added from/to the FIFO
does not cross the threshold.
The following paragraphs detail the operation of
the FIFO flow control. In these descriptions,
<threshold> ranges from 1 to 16.
The
parameter FIFOTHR, which the user programs,
is one less and ranges from 0 to 15.
The interrupt generated is ISA friendly in that it
must pulse the interrupt line low, allowing for
interrupt sharing.
After a brief pulse low
following the interrupt event, the interrupt line is
tri-stated so that other interrupts may assert.
An interrupt is generated when:
1. For DMA transfers: When serviceIntr is “0”,
dmaEn is 1 and the DMA TC is received.
2. For Programmed I/O:
a.
When serviceIntr is 0, dmaEn is 0,
direction is “0” and there are writeIntrThreshold
or more free bytes in the FIFO. Also, an
interrupt is generated when serviceIntr is cleared
to 0 whenever there are writeIntrThreshold or
more free bytes in the FIFO.
b.
(1) When serviceIntr is “0”, dmaEn is 0,
direction is “1” and there are readIntrThreshold
or more bytes in the FIFO. (2) An interrupt is
also generated when serviceIntr is cleared to “0”
whenever there are readIntrThreshold or more
bytes in the FIFO.
3.
When nErrIntrEn is 0 and nFault
transitions from high to low or when nErrIntrEn
is set from “1” to “0” and nFault is asserted.
4.
When ackIntEn is “1” and the nAck
signal transitions from a low to a high.
A low threshold value (i.e. 2) results in longer
periods of time between service requests, but
requires faster servicing of the request for both
read and write cases. The host must be very
responsive to the service request. This is the
desired case for use with a "fast" system.
A high value of threshold (i.e. 12) is used with a
"sluggish" system by affording a long latency
period after a service request, but results in
more frequent service requests.
DMA TRANSFERS
DMA transfers are always to or from the
ecpDFifo, tFifo or CFifo. DMA utilizes the
standard PC DMA services. To use the DMA
transfers, the host first sets up the direction and
state as in the programmed I/O case. Then it
programs the DMA controller in the host with the
desired count and memory address. Lastly it
sets dmaEn to “1” and serviceIntr to 0. The
ECP requests DMA transfers from the host by
activating the PDRQ pin. The DMA will empty
or fill the FIFO using the appropriate direction
and mode. When the terminal count in the DMA
controller is reached, an interrupt is generated
and serviceIntr is asserted, disabling DMA. In
order to prevent possible blocking of refresh
requests dReq shall not be asserted for more
than 32 DMA cycles in a row. The FIFO is
enabled directly by asserting nPDACK and
addresses need not be valid.
PINTR is
generated when a TC is received. PDRQ must
not be asserted for more than 32 DMA cycles in
a row. After the 32nd cycle, PDRQ must be
kept unasserted until nPDACK is deasserted for
FIFO OPERATION
The FIFO threshold is set in the chip
configuration registers. All data transfers to or
from the parallel port can proceed in DMA or
Programmed I/O (non-DMA) mode as indicated
by the selected mode. The FIFO is used by
selecting the Parallel Port FIFO mode or ECP
Parallel Port Mode. (FIFO test mode will be
addressed separately.) After a reset, the FIFO
is disabled. Each data byte is transferred by a
125
a minimum of 350nsec. (Note: The only way to
properly terminate DMA transfers is with a TC.)
PROGRAMMED I/O MODE OR NON-DMA
MODE
DMA may be disabled in the middle of a transfer
by first disabling the host DMA controller. Then
setting serviceIntr to 1, followed by setting
dmaEn to “0”, and waiting for the FIFO to
become empty or full. Restarting the DMA is
accomplished by enabling DMA in the host,
setting dmaEn to “1”, followed by setting
serviceIntr to 0.
The ECP or parallel port FIFOs may also be
operated using interrupt driven programmed I/O.
Software can determine the writeIntrThreshold,
readIntrThreshold, and FIFO depth by accessing
the FIFO in Test Mode. Programmed I/O
transfers are to the ecpDFifo at 400H and
ecpAFifo at 000H or from the ecpDFifo located
at 400H, or to/from the tFifo at 400H. To use
the programmed I/O transfers, the host first sets
up the direction and state, sets dmaEn to 0 and
serviceIntr to 0. The ECP requests programmed
I/O transfers from the host by activating the
PINTR pin. The programmed I/O will empty or
fill the FIFO using the appropriate direction and
mode.
DMA MODE - TRANSFERS FROM THE FIFO
TO THE HOST
(Note: In the reverse mode, the peripheral may
not continue to fill the FIFO if it runs out of data
to transfer, even if the chip continues to request
more data from the peripheral.)
Note: A threshold of 16 is equivalent to a
threshold of 15. These two cases are treated
the same.
The ECP activates the PDRQ pin whenever
there is data in the FIFO. The DMA controller
must respond to the request by reading data
from the FIFO. The ECP will deactivate the
PDRQ pin when the FIFO becomes empty or
when the TC becomes true (qualified by
nPDACK), indicating that no more data is
required. PDRQ goes inactive after nPDACK
goes active for the last byte of a data transfer
(or on the active edge of nIOR, on the last byte,
if no edge is present on nPDACK). If PDRQ
goes inactive due to the FIFO going empty, then
PDRQ is active again as soon as there is one
byte in the FIFO. If PDRQ goes inactive due to
the TC, then PDRQ is active again when there
is one byte in the FIFO, and serviceIntr has
been re-enabled. (Note: A data underrun may
occur if PDRQ is not removed in time to prevent
an unwanted cycle).
PROGRAMMED I/O - TRANSFERS FROM
THE FIFO TO THE HOST
In the reverse direction an interrupt occurs when
serviceIntr is 0 and readIntrThreshold bytes are
available in the FIFO. If at this time the FIFO is
full it can be emptied completely in a single
burst, otherwise readIntrThreshold bytes may
be read from the FIFO in a single burst.
readIntrThreshold = (16-<threshold>) data bytes
in FIFO
An interrupt is generated when serviceIntr is 0
and the number of bytes in the FIFO is greater
than or equal to (16-<threshold>). (If the
threshold = 12, then the interrupt is set
whenever there are 4-16 bytes in the FIFO.)
The PINT pin can be used for interrupt-driven
systems. The host must respond to the request
by reading data from the FIFO. This process is
repeated until the last byte is transferred out of
the FIFO. If at this time the FIFO is full, it can
126
writeIntrThreshold = (16-<threshold>) free bytes
in FIFO
be completely emptied in a single burst,
otherwise a minimum of (16-<threshold>) bytes
may be read from the FIFO in a single burst.
An interrupt is generated when serviceIntr is 0
and the number of bytes in the FIFO is less than
or equal to <threshold>. (If the threshold = 12,
then the interrupt is set whenever there are 12 or
less bytes of data in the FIFO.) The PINT pin
can be used for interrupt-driven systems. The
host must respond to the request by writing data
to the FIFO. If at this time the FIFO is empty, it
can be completely filled in a single burst,
otherwise a minimum of (16-<threshold>) bytes
may be written to the FIFO in a single burst.
This process is repeated until the last byte is
transferred into theFIFO.
PROGRAMMED I/O - TRANSFERS FROM
THE HOST TO THE FIFO
In the forward direction an interrupt occurs when
serviceIntr is 0 and there are writeIntrThreshold
or more bytes free in the FIFO. At this time if
the FIFO is empty it can be filled with a single
burst before the empty bit needs to be re-read.
Otherwise
it
may
be
filled
with
writeIntrThreshold bytes.
127
PARALLEL PORT INTERFACE MULTIPLEXOR
THE PARALLEL PORT PHYSICAL INTERFACE (PPPI)
The Parallel Port Physical Interface (PPPI) may be owned and controlled by any of threesources. The
sources are detailed as follows:
PPPI
CONTROLLING
SOURCE
DEVICE
8051
FDC
Host
TABLE 71 - PARALLEL PORT MULTIPLEXING OPTIONS
CONFIG
REGISTER
0X25
BITS[4:3]
DESCRIPTION
[X:X]
The parallel port physical interface is configured
as a SPP mode bi-directional parallel port
controlled directly by the 8051 through a set of
memory mapped external RAM registers.
[1:0]
The parallel port physical interface is configured
or
as a standard Floppy Disk Drive interface. All
[0:1]
configuration and control bits pertaining to the
FDC logical device apply to the PPPI in this
mode
The parallel port physical interface is configured
[0:0]
as the legacy parallel port which supports
or
Compatible, SPP, EPP and ECP modes of
[1:1]
operation. All configuration and control bits
pertaining to the parallel port logical device apply
to the PPPI in this mode.
When the Host (Parallel Port logical device)
owns/controls the parallel port interface, its state
(i.e., pwrdown) determines the states of the
pins. When the FDC (FDC logical device)
owns/controls the Parallel Port interface, its
state (i.e., powerdown) determines the state of
the pins. When the 8051 controls/owns the
parallel port interface, it has direct control of the
Parallel Port Physical Interface pins. Under
8051 control the Parallel Port Output pins are
always enabled or driven and only tri-state when
VCC2 is removed (powergood=0).
PP_HA
0
1
1
activate the DRQ and IRQ of the Parallel Port
Logical Device by either setting its DMA
Channel Select Configuration Register to 0x04
and its Interrupt Select Configuration Regsiter to
0x00 or by clearing the Parallel Port Logical
Device’s Activate bit. Also, if the Host does not
have control of the PPPI, then the following
parallel port logical device registers are read as
follows.
Data Register (read) = last Data Register
(write).
Control Register (read): read as “cable not
connected” [STROBE, LF, and SLC = 0 and
nINIT = 1.
Status Register (read): nBUSY, PE, SLCT = 0,
nACK, nERR = 1.
If the Host does not have control of the Parallel
Port Physical Interface (PPPI), then it is left as a
function of the software driver or BIOS to de128
Note: Bit D7 of the 8051 memory mapped
DISABLE register (parallel port enable bit) has
no effect on the parallel port physical interface
pins when the port is owned by any source other
than the the Host (parallel port logical device).
PARALLEL PORT FDC INTERFACE
In this mode, the floppy disk control signals are
available on the parallel port pins. When this
mode is selected, the parallel port is not
available to the Host.
HOST (LEGACY) PARALLEL PORT
INTERFACE (FDC37N972 STANDARD)
PARALLEL PORT FDC PIN OUT
The FDC signals are muxed onto the ‘Parallel
Port pins as shown in the following table.
Outputs are OD14, Open Drain which sink
14ma.
In this mode, the parallel port pins are controlled
by the host through the parallel port logical
device. Refer to the Configuration section and
the Parallel Port section for information on the
configuration and control registers respectively.
TABLE 72 - PARALLEL PORT FLOPPY PIN OUT
CONNECTOR
PIN #
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
PARALLEL PORT SPP MODE
PIN
SIGNAL NAME
DIRECTION
nSTROBE
I/O
PD0
I/O
PD1
I/O
PD2
I/O
PD3
I/O
PD4
I/O
PD5
I/O
PD6
I/O
PD7
I/O
NACK
I
BUSY
I
PE
I
SLCT
I
nALF
I/O
nERR
I
nINIT
I/O
nSLCTIN
I/O
FDC MODE
SIGNAL
PIN
NAME
DIRECTION
nDS0
(O)*
nINDEX
I
nTRK0
I
nWP
I
nRDATA
I
nDSKCHG
I
nMTR0
(O)*
nDS1
(O)*
nMTR1
(O)*
nWDATA
O
nWGATE
O
DRVDEN0
O
nHDSEL
O
nDIR
O
nSTEP
O
*These pins are outputs in mode PPFD2; in mode PPFD1 only one pair, depending on Drive Swap bit,
is active and should be connected to the FDD, the inactive pair should not be connected to the FDD.
129
PARALLEL PORT FDC CONTROL
There are two modes of operation, PPFD1 and
PPFD2. These modes can be selected in
Global Configuration Register 0x25 (Device
Mode), bits 3 and 4. PPFD1 mode has only
drive 1 on the parallel port pins; PPFD2 mode
has drive 0 and 1 on the parallel port pins. Note:
The Drive Swap bit, FDD Mode Configuration
Register bit-4 (LD0_CRF0), can be used to swap
the motor and drive select outputs on of the
Parallel Port FDC.
TABLE 73 - PARALLEL PORT FDC MODES OF OPERATION
PPFD1: Drive 0 is on the FDC pins.
Drive Swap bit = 0
Drive 1 is on the parallel port pins.
Drive 1 is on the FDC pins.
Drive Swap bit = 1
Drive 0 is on the parallel port pins.
PPFD2: Drive 0 is on the parallel port pins.
Drive 1 is on the parallel port pins.
The following FDC output pins are Open Drain 14mA outputs when the Parallel Port FDC is selected
by the drive select register. Reminder, it is up to the designer to provide pull-up resistors on these
FDC output pins.
nWDATA, DRVDEN0, nHDSELm nWGATE, nDIR, nSTEP, nDS1, nDS0, nMTR0,
nMTR1.
130
the PAR PORT CONTROL, and the PAR PORT
DATA registers. In this mode, the parallel port
pins are not controlled by the parallel port
logical device. Refer to the 8051 section of this
specification for information on these control
registers.
PARALLEL PORT - 8051 CONTROL
In this mode, the parallel port pins are controlled
by the 8051 through a set of three on-chip
memory mapped registers. The memory
mapped registers are the PAR PORT STATUS,
FDC Parallel
Port Mode
CR25 Bits
[4:3]
01 or 10
01 or 10
01 or 10
00 or 11
00
00
00
TABLE 74 - FDC ON PARALLEL PORT ACTIVATION CONTROL
FDC in Parallel Parallel
Port In
Port
Power
Power
Parallel Port Pins
Active
Down
FDC Active Bit
Down
PP_ HA
(Mode) State
Bit
L0-CR30-Bit0
0
x
x
x
1
(FDC) Inactive
1
N
x
x
1
(FDC) Active
1
Y
x
x
1
(FDC) Inactive
X
x
0
x
1
(Parallel Port) Inactive
X
x
1
N
1
(Parallel Port) Active
X
x
1
Y
1
(Parallel Port) Inactive
X
x
x
x
0
(8051 Mode) Active
INACTIVE = HI-Z ON PINS
Active = OD14/O14 as per selected mode.
The FDD pins that are multiplexed onto the
Parallel Port function independently of the state
of the Parallel Port logical device. This affects
the pins when CR25 bits [4:3] are 01 or 10.
(Note: FDC Mode Bits L0-CRF0-B[7:6] have no
effect on the parallel port Pins).
FDC POWER MANAGEMENT
Direct power management is controlled through
Global Configuration Register 22 (CR22). Refer
to CR22 in the Configuration section for more
information.
Auto Power Management is enabled through bit0 of CR23. When set, this bit allows the FDC to
enter powerdown when all of the following
conditions have been met:
AUTO POWER MANAGEMENT
Auto Power Management (APM) capabilities are
provided for the following logical devices: Floppy
Disk, UART, Infrared and the Parallel Port. For
each logical device, two types of power
management are provided; direct powerdown
and auto powerdown.
1.The motor enable pins of the FDC’s DOR
register are inactive (zero).
2.The FDC37N972 must be idle; the MSR
register = 80h and the FDC’s INTerrupt = 0 (INT
may be high even if MSR = 80H due to polling
interrupts).
3.The head unload timer must have expired.
4.The Auto powerdown timer (10msec) must
have timed out.
SYSTEM POWER MANAGEMENT
See the “8051 System Power Management”
section for details.
An internal timer is initiated as soon as the auto
powerdown command is enabled. The
131
FDC37N972 is then powered down when all the
conditions are met.
REGISTER BEHAVIOR
TABLE 75 shows the AT and PS/2 (including
Model 30) configuration registers available. It
also shows the type of access permitted. In
order to maintain software transparency, access
to all the registers is maintained. As TABLE 75
shows, two sets of registers are distinguished
based on whether their access results in the
FDC37N972 remaining in powerdown state or
exiting it.
Disabling the auto powerdown mode cancels the
timer and holds the FDC block out of auto
powerdown.
DSR FROM POWERDOWN
Bit 6 of the FDC’s DSR register is another FDC
powerdown bit. If DSR powerdown is used
when the FDC37N972 is in auto powerdown, the
DSR powerdown will override the auto
powerdown. However, when the FDC37N972 is
awakened from DSR powerdown, the auto
powerdown will once again become effective.
Access to all other registers is possible without
awakening the FDC37N972. These registers
can be accessed during powerdown without
changing the status of the FDC37N972. A read
from these registers will reflect the true status as
shown in the register description in the FDC
section. Writes to these registers will result in
the FDC37N972 retaining the data and
subsequently reflecting it when the FDC37N972
awakens. Accessing the FDC37N972 during
powerdown may cause an increase in the power
consumption by the FDC37N972.
The
FDC37N972 will revert back to its low power
mode when the access has been completed.
WAKE UP FROM AUTO POWERDOWN
If the FDC37N972 enters the Powerdown State
through the auto powerdown mode, then the
FDC37N972 can be awakened by reset or by
appropriate access to certain registers.
If a hardware or software reset is used then the
FDC37N972 will go through the normal reset
sequence. If the access is through the selected
registers, then the FDC resumes operation as
though it was never in powerdown. Besides
activating the nRESET_OUT pin or one of the
software reset bits in the DOR or DSR registers,
the following register accesses will wake up the
FDC37N972:
1.
2.
3.
PIN BEHAVIOR
The FDC37N972 is specifically designed for
portable PC systems in which power
conservation is a primary concern. This makes
the behavior of the pins during powerdown very
important.
Seting any one of the motor enable bits in
the DOR register (reading the DOR does
not awaken the FDC37N972).
A read from the MSR register.
A read from or a write to the Data register.
The pins which interface to the floppy disk drive
are disabled so that no power will be drawn
through the FDC37N972 as a result of any
voltage applied to the pin within the VCC2
power supply range. Most of the pins that
interface to the system are left active to monitor
system accesses that may wake up the
FDC37N972.
Once awake, the FDC will reinitiate the auto
powerdown timer for 10 ms. The FDC37N972
will powerdown again when all the powerdown
conditions are satisfied.
132
the powerdown are labeled "Unchanged". Input
pins are "Disabled" to prevent them from
causing currents internal to the FDC37N972
when they have indeterminate input values.
SYSTEM INTERFACE PINS
Table 76 gives the state of the system interface
pins in the powerdown state. Pins unaffected by
TABLE 75 - PC/AT AND PS/2 AVAILABLE REGISTERS
BASE + ADDRESS
AVAILABLE REGISTERS
ACCESS PERMITTED
PC/AT
PS/2 (Model 30)
Access to these registers DOES NOT wake up the FDC37N972
00H
---SRA
R
01H
---SRB
R
02H
DOR (1)
DOR (1)
R/W
03H
------04H
DSR (1)
DSR (1)
W
06H
------07H
DIR
DIR
R
07H
CCR
CCR
W
Access to these registers wakes up the FDC37N972
04H
MSR
MSR
R
05H
Data
Data
R/W
Note 1: Writing to the DOR or DSR does not wake up the FDC37N972, however, writing any of the
motor enable bits or doing a software reset (via DOR or DSR reset bits) will wake up the FDC37N972.
TABLE 76 - STATE OF SYSTEM PINS IN FDC AUTO POWERDOWN
SYSTEM PINS
STATE IN AUTO POWERDOWN
Input Pins
nIOR
Unchanged
nIOW
Unchanged
AEN
Unchanged
nMEMRD
Unchanged
nMEMWR
Unchanged
SA[15:0]
Unchanged
SD[7:0]
Unchanged
nNOWS
Unchanged(hi-Z)
nDACKx
Unchanged
TC
Unchanged
nROMCS
Unchanged
Output Pins
nRESET_OUT
Unchanged
IRQx
Unchanged(low)
DB[0:7]
Unchanged
DRQx
Unchanged(low)
IOCHRDY
Unchange(n/a)
133
FDC. Whenever the FDC Shutdown bit is set
(see FDD Mode Register, bit-5 in the
Configuration Register Section) the FPD pin
goes high. If the FDC Shutdown bit is not set
then the FPD pin will go high whenever the FDC
bit (see bit 0 of the Power Mgmt Register in the
Configuration Section) is set and the FDC has
entered an auto powerdown state as described
above. If neither the FDC Shutdown bit nor the
FDC bit are set then the FPD pin goes active
“high” when the Power- down bit is set (see bit 6
of the Data Rate Select Register [DSR]) and
“low” when the Powerdown bit is cleared. Refer
to Table 78 - FDD POWER DOWN PIN
BEHAVIOR.
FDD INTERFACE PINS
All pins in the FDD interface, which can be
connected directly to the floppy disk drive itself,
are either DISABLED or TRISTATED. Pins
used for local logic control or part programming
are unaffected. Table 77 depicts the state of the
floppy disk drive interface pins in the
Powerdown State.
FDD POWER DOWN PIN (FPD) BEHAVIOR
The FPD pin can be used to automatically shut
off power to the floppy disk drive when it is not
required. The FPD pin is an active high output
signal that is driven based on the states of the
TABLE 77 - STATE OF FLOPPY DISK DRIVE INTERFACE PINS IN FDC POWERDOWN
STATE IN FDC AUTO
FDD PINS
POWERDOWN
Input Pins
nRDATA
Input
nWPROT
Input
nTRK0
Input
nINDEX
Input
nDSKCHG
Input
Output Pins
nMTR[1:0]
Tristated
nDS[1:0]
Tristated
nDIR
Active
nSTEP
Active
nWDATA
Tristated
WGATE
Tristated
nHDSEL
Active
DRVDEN[1:0]
Active
FPD
Active
134
Table 78 - FDD POWER DOWN PIN BEHAVIOR
POWER DOWN BIT, FDC BIT, GCR23 BIT-0
FDC SHUTDOWN BIT,
DSR, BIT-6
AUTO POWER DOWN
FDD MODE REGISTER
0
0
0
POWER DOWN BIT, FDC BIT, GCR23 BIT-0
FDC SHUTDOWN BIT,
DSR, BIT-6
AUTO POWER DOWN
FDD MODE REGISTER
1
0
0
X
1
0
X
X
1
Note:
FPD PIN
STATE
0
FPD PIN
STATE
1
1 (Note)
1
The FPD pin will go active when the FDC auto powers down. Refer to the
FDC auto power management section for more details.
UART POWER MANAGEMENT
PARALLEL PORT POWER MANAGEMENT
Direct power management is controlled by
CR22. Refer to CR22 in the Configuration
Section for more information.
Direct power management is controlled by
CR22. Refer to CR22 in the Configuration
Section for more information.
Auto power management is enabled by CR23 bit
4 and bit 5. When set, these bits allow the
following auto power management operations:
1.The transmitter enters auto powerdown when
the transmit buffer and shift register are empty.
2.The receiver enters powerdown when the
following conditions are all met:
A. Receive FIFO is empty
B. The receiver is waiting for a start bit
Auto power management is enabled by CR23 bit
3. When set, this bit allows the ECP or EPP
logical parallel port blocks to be placed into
powerdown when not being used.
The EPP logic is in powerdown under any of the
following conditions:
EPP is not enabled in the configuration
registers.
EPP is not selected through ecr while in ECP
mode.
Note:
While in powerdown the Ring Indicator
interrupt is still valid.
The ECP logic is in powerdown under any of the
following conditions:
EXIT AUTO POWERDOWN
ECP is not enabled in the configuration
registers.
SPP, PS/2 Parallel port or EPP mode is
selected through ecr while in ECP mode.
The transmitter exits powerdown on a write to
the transmit buffer. The receiver exits auto
powerdown when RXD changes state.
XIT AUTO POWERDOWN
The parallel port logic can change powerdown
modes when the ECP mode is changed through
the ecr register or when the parallel port mode is
changed through the configuration registers.
135
8051 EMBEDDED CONTROLLER
the Hardware Description of the 8051, 8052,
and 80C51 and the 80C51BH-1/80C51BH-2
CHMOS Single-Chip 8 Bit Microcomputer data
sheets in the 8 Bit Embedded Controller
Handbook.
8051 FUNCTIONAL OVERVIEW
The
High-Performance
8051
embedded
controller is a fully static CMOS core compatible
with
the
industrystandard
80C51
microcontroller. The high-performance 8051
features include:
FEATURES
2.5X average instruction execution speed
improvement over the entire instruction set; i.e.,
typical 4-clock instruction cycle in highperformance 8051 vs. 12-clock instruction cycle
in standard 8051.
Faster clock speed: 24MHz or higher vs. 16MHz
in standard 8051.
Dual Data Pointers
More Interrupts: Power-Fail, External Interrupt 2,
External Interrupt 3, etc.
16x32K External ROM
256 Byte Internal Scratch ROM
256 Bytes Internal RAM
256 Bytes of External RAM
256 Byte External Memory/Mapped Control
Register Area
128 Byte Special Function Register Area
Access to 256 Byte RTC CMOS RAM
8042 style Keyboard Controller Host Interface
Eleven Interrupt Sources
Watch Dog Timer (WDT)
Ring Oscillator with Fail Safe Control
A set of External Memory/Mapped Control
Registers provides the 80C51 core with the
ability to directly control many functional blocks
of the FDC37N972.
High-Performance
Features
This section concentrates on the FDC37N972
enhancements to the 80C51. For Non-Standard
Special Function Registers, interrupt processing
and Timer 2 functions see Appendix B. For
general information about the 80C51, refer to
8051
Implemented
There are five significant features implemented
in the high-performance 8051 core. These
features, summarized in TABLE 79, are
described more fully in the sub-sections that
follow.
TABLE 79 - HIGH-PERFORMANCE 8051 IMPLEMENTED FEATURES
FEATURE
VALUE
DESCRIPTION
Internal RAM Size
256 (bytes)
The internal RAM size is 256 bytes to maintain
compatibility with existing implementations.
Internal Timers (Note)
3
There are three internal Timers (T0, T1 & T2).
Internal ROM Size
2048 (bytes) The internal ROM size is 2048 bytes to maintain
compatibility with existing implementations.
Serial Ports
1
There is one Serial Port.
Interrupts
11
The high-performance 8051 interrupt unit provides
11 interrupt sources (see TABLE 92).
Note:
The external inputs for Timer/Counter T0, T1, and T2, as well as the Timer/Counter 2
capture/reload trigger T2EX are not supported in the FDC37N972.
136
INSTRUCTION SET on page 380 for number of
cycles on individaul instruction requries.
FUNCTIONAL BLOCKS
Below are the functional blocks that the 8051
core has control of through its on-chip
memory/mapped external registers.
POWERING UP OR RESETTING THE 8051
DEFAULT RESET CONDITIONS
8042 Style Keyboard Controller Interface
Extended Interrupts
Power Management Functions
Direct Keyboard Scan Matrix (up to 128 keys)
Four channel PS/2 Interface
Dual Access Bus Interface
LED controls
Two Pulse Width Modulators
RTC CMOS RAM Access
8051 Control of the Parallel Port Interface
42 General Purpose I/O (GPIO) pins
ACPI Embedded Controller
PM1 Block
The FDC37N972 has two sources of reset: a
VCC1 Power On Reset (VCC1 POR) or a VCC2
POR. An FDC37N972 reset from any of these
sources will cause the hardware response
shown in TABLE 86, 8051 On-Chip External
Memory Mapped Registers.
Note that the
values shown are those prior to any resident
firmware control. Refer to TABLE 86 for the
effect of each type of reset on each of the onchip registers.
POWER-UP SEQUENCE
HIGH-PERFORMANCE 8051 CYCLE TIMING
AND INSTRUCTION SET
When the 8051 first powers up by VCC1, the
ring oscillator is started, once this has
stabilized, the 8051 starts executing from
program address 00. Once running, the 8051
can access all of the registers that are on VCC1
and if VCC2 is at 3.3V it can access all of the
registers on VCC2. For on-chip registers
powered by VCC1 which are reset upon VCC2
Power On Reset (VCC2 POR), it is important
that 8051 firmware not initialize or write to any
of these registers until 1ms following VCC2 =
3.3V AND PWRGD = 1 (See TABLE 86.)
The high-performance 8051 processor offers
increased performance by executing instructions
in a 4-clock cycle, as opposed to the standard
8051. The shortened bus timing improves the
instruction execution rate for most instructions
by a factor of three over the standard 8051
architectutres.
Some instructions require a different number of
instruction cycles on the high-performance
8051than they do on the standard 8051. In the
standard 8051, all instructions except for MUL
and DIV take one or two instruction cycles to
complete.
In the high-performance 8051
architecture, instructions can take between one
and five instructions to complete. The average
speed improvement for the entire instruction set
is approximately 2.5X. See TABLE 253 - 8051
Note: In order to guarantee that the external
Flash device has powered up and is ready to
operate before the 8051 attempts to access it,
the internal VCC1 POR pulse has been
extended to 20ms. The internal VCC1 POR
signal is asserted upon VCC1 reaching a valid
level and will remain asserted for a period of
20ms
following
the
assertion
of
the
VCC1_PWRGD pin.
137
No power to system
(VCC0, VCC1, VCC2 off)
VCC0, VCC1 on; VCC2 off
VCC1 powered registers
are reset to their VCC1
POR values. IRESET_OUT
bit forced high and latched
by the FDC37N972
hardware
Ring oscillator is started
Once the ring oscillator has
stabilized, the 8051 is held in
reset for the required number
of clock cycles and then
released.
N
The 8051 begins executing
from program address 00h.
nEA = 0 ?
Y
The 8051 begins executing
code at address 8000h.
FIGURE 10 - SYSTEM POWER UP SEQUENCE
138
SYSTEM RESET SEQUENCE
System is running
(VCC2 on, VCC1 on)
8051 executing
keyboard firmware.
Somehow a reset event is
conveyed to the 8051.
Note1: IRESET_OUT being reset to 0
(Toggling from 1 to 0)
1) sets 8051STP_CLK[0]=1
command from host and/or directly
2) sets HMEM[7:0]=03h
from a GPI/O type pin transition?
and
3) causes the StopClock Counter to start counting down
Note 2: In order to leave idle mode the 8051 must receive
an interrupt; typically a software timer interrupt will be used.
8051 asserts iRESET_OUT
nRESET_OUT pin
8051 programs the
Stop Clock Counter
STP_CNT[3:0] <- X
nRESET_OUT de-asserted
nRESET_OUT pin
8051 releases the system
reset (iRESET_OUT
register bit is reset)
(Note 1)
nRESET_OUT = high &
8051STP_CLK = 1 cause
8051 clock to stop
8051 goes into idle mode
Host now owns Flash
Interface,
shadows Flash to RAM
Y
N
Stop-clock cnt
=0?
Host resets
8051STP_CLK bit
N
8051 Timer
IRQ ?
Y
(Note 2)
8051 wakes up from idle
mode and starts executing
from where it left off
FIGURE 11 - TYPICAL SYSTEM RESET SEQUENCE
139
CPU RESET SEQUENCE
emulated CPU instructions that cause the CPU
to jump to its shadowed Boot vector address at
(1MB - 16B).
Often the Host CPU (x486 or Pentium) is reset
by the hardware signal, CPU_RESET, which is
issued by software to switch the Processor from
Protected, or “Virtual 86”, mode back to Real
mode. CPU_RESET can be generated from the
FDC37N972 8051 core or it may be generated
from other logic on the PC motherboard.
CPU_RESET is meant only to reset the CPU;
the rest of the system continues to run normally,
including the keyboard BIOS in the 8051.
If the host does not have control of the Flash
when
nROMCS
and
nMEMRD
are
simultaneously asserted, the FDC37N972
decodes the lower three System Address bits,
SA[2:0] and presents the Host with 0xEA on the
System Data Bus SD[7:0] when SA[2:0] = 0, or
0xF0 otherwise (FIGURE 12). This results in an
opcode that instructs the Host CPU to perform
an absolute jump to address 0xFFFF0, where
the BIOS is shadowed.
Reacting to the CPU_RESET, the CPU performs
a code fetch to a reset vector address that is
located 16 bytes below the top address of
memory (4GB - 16B). This generates an active
nROMCS to the FDC37N972 along with
memory RD strobes, but since the 8051 has not
passed control of the Flash interface to the Host
CPU the FDC37N972 must supply a set of
NOTE: The FDC37N972 CPU reset sequence
described above is independent of the Bonding
Option.
140
System Vcc
SD7
SD6
SD5
SD4
A2
SD3
A1
A0
SD2
SD1
SD0
System Data Bus SD[7:0]
nROMCS
nMEMRD
HSTFL
FIGURE 12 - SYSTEM RESET BOOT VECTOR
141
8051 CLOCK CONTROLS
CLOCK SOURCES
Frequency Controls
EXTERNAL CLOCK SIGNAL
The 8051 system clock frequencies are selected
by the KBDCLK[1:0] control bits in the KSTP_CLK
register.
The KSTP_CLK register is MMCR
0x7F27.
The external clock source is from a
14.318MHz TTL compatible clock.
VCC2
must be powered in order for this to occur.
In the KSTP_CLK register, the STP_CNT[3:0] bits
are moved from the KSTP_CLK register to the
STOP_COUNT register, the KBDCLK ENABLE bit
and a RESERVED bit (possibly to control the
14.318 MHz PLL Power-Down function) are added
to the KSTP_CLK register.
INTERNAL CLOCK SIGNAL
The 8051 may program it self to run off of an
internal ring oscillator having a frequency
range between 4 and 12MHz. This is not a
precise clock, but is meant to provide the 8051
with a clock source when VCC2 is shut down
in the system.
To “stop” the 8051 clock, use the KBDCLK
ENABLE bit D0 in the KSTP_CLK register (TABLE
81).
TABLE 80 - STOP_COUNT REGISTER
HOST ADDRESS
-
HOST TYPE
8051 TYPE
BIT NAME
D7
R
8051 ADDRESS
0x7F2F
D6
D5
R
R
RESERVED
D4
R
POWER
PLANE
VCC1
DEFAULT
0x00
D3
D2
D1
R/W
R/W
R/W
STP_CNT[3:0]
D0
R/W
until the external nRESET_OUT pin goes
inactive high (deasserts). The STP_CNT[3:0]
bits are D0 – D3 in the FDC37N972 KSTP_CLK
Register.
STP_CNT[X]
This defines the number of machine cycles from
when the internal IRESET_OUT bit is cleared
142
HOST ADDRESS
-
HOST
TYPE
8051
TYPE
BIT
NAME
TABLE 81 - KSTP_CLK REGISTER
POWER
8051 ADDRESS
PLANE
0x7F27
VCC1
DEFAULT
0x10
D7
-
D6
-
D5
-
D4
-
D3
-
D2
-
D1
-
D0
-
R/W
R/W
R/W
R/W
R
R
R/W
R/W
KBCLK/ROSC
ROSCEN
PLL_STOP
KBDCLK
ENABLE
1
KBDCLK[1:0]
RESERVED
KBDCLK/ENABLE
ROSCEN
When the KBDCLK ENABLE bit is “0”, the 8051
PLL clock is stopped, like when the
KBDCLK[1:0] = 0,0 in the FDC37C95X. When
KBDCLK ENABLE is “1”, the 8051 PLL clock is
running.
This bit reflects the state of the ring oscillator
clock at all times. The 8051 can write this bit to
start or stop the ring oscillator. Other hardware
events can also start or stop this clock.
= 1 turn on ring oscillator
= 0 turn off ring oscillator
This bit is reset when the 8051 goes into
“SLEEP” mode and is set when the 8051 first
wakes up from “SLEEP” mode.
PLL_STOP
The PLL_STOP bit D1 is used to control the
power state of the 14.318MHz PLL. When the
PLL_STOP bit is “1” the PLL and all of the
internal clocks except for the RTC and Ring
Oscillator are stopped. When the PLL_STOP
bit is “0” the PLL and all of the internal clocks
are running. When VCC2 is active and the
PLL_STOP bit changes from “1” to “0”, there is
a delay of 100µs max. before the PLL clocks are
stable.
KBCLK/ROSC
This bit is used to control the clock source for
the 8051.
1 = 8051 clock source is KBCLK
0 = 8051 clock source is ring oscillator.
This bit is reset when the 8051 just wakes up
from the “SLEEP” mode
KBDCLK[1:0]
These 2 bits control the 8051 system clock
frequencies.
143
TABLE 82 - KBDCLK CONTROL BIT ENCODING
KBDCLK[1:0] CONTROL BITS
KSTP_CLK REGISTER
KBD CLOCK FREQUENCIES
D7
D6
FDC37N972
0
0
12MHz
0
1
16MHz
1
0
24MHz
1
1
RESERVED
8051 RING OSCILLATOR FAIL-SAFE CONTROLS
A fail-safe control for the 8051 ring oscillator is
in the FDC37N972 as protection against
unpredicted VCC2 power failures.
3.
The 8051 system clock is switched to the ring
oscillator.
NOTE: following a power fail
event, VCC2 must be ≥ 3V and the
14.318MHz input clock CLOCKI must remain
stable for 10µs min. (FIGURE 4 - VCC2
POWER-UP TIMING).
4.
An 8051power-fail interrupt (pfi) is generated
to inform the 8051 of the power fail event.
The fail-safe ring oscillator sequence occurs
as follows:
1.
A VCC2 power-fail event is detected when
the PWRGD pin changes from “1” to “0”
(FIGURE 3 – POWER-FAIL EVENT).
2.
The power-fail event sequence starts the
8051 Ring Oscillator. The Ring Oscillator
frequency range is the same as the
FDC37C95X; i.e., 4MHz to 12MHz.
There are four functional power-fail event
scenarios.
The actions taken for each are
described in TABLE 83.
144
1
2
3
4
8051 STATE
SLEEPING
ON RING
OSC.
RUNNING ON
RING OSC.
RUNNING ON
PLL
STOPPED ON
PLL
NOTE 1:
NOTE 2:
TABLE 83 - POWER-FAIL EVENT ACTIONS
ACTIONS
ASSERT
ASSERT
8051
ASSERT
RING
FLASH
DESCRIPTION
PGI1
OSC.2
ACCESS
3
NO FAIL-SAFE ACTIONS TAKEN
3
-
-
3
3
-
3
3
3
NO FAIL-SAFE ACTIONS TAKEN;
8051 CAN RESPOND TO PFI IF
NEEDED.
INTERNAL PWRGD IS DELAYED
UNTIL RING OSC. IS ASSERTED.
INTERNAL PWRGD IS DELAYED
UNTIL RING OSC. IS ASSERTED
AND THE 8051 CONTROLS THE
FLASH.
PGI is the Powergood Interrupt bit D0 in the PWRGD_INT register (see Power Fail
IRQ on page 184).
The 8051 is switched to the Ring Oscillator after a delay.
(See PWRGD and VCC1_PWRGD timing is illustrated in FIGURE 3 – POWER-FAIL EVENT through
FIGURE 5 - VCC1_PWRGD TIMING)
FFFFh by the 8051. This 32K can be mapped
to any of the sixteen 32K memory block in the
512K external ROM by the KMEM register.
8051 MEMORY MAP
The FDC37N972 has two modes of ROM
support based on the Bondout Option.
Under SMSC Bondout, the 8051 can address
256B of internal Scratch ROM and 32K of
external ROM. The nEA pin is used to enable
access to the 256B of internal Scratch ROM or
External program ROM. The FDC37N972 also
contains 256 bytes of internal on-chip RAM.
Under ALT Bondout, the 8051 can address 2KB
of internal ROM, 256B of internal Scratch ROM,
and up to 32K of external ROM. When high, the
nEA pin is used to enable fetches to the 2K +
256B of internal ROM and when low the nEA pin
diables fetches to internal ROM access by
routing them to external ROM. The FDC37N972
also contains 256 bytes of internal on-chip RAM.
Under SMSC Bondout with nEA=0, all the ROM
is addressed as the external ROM. It can
support up to 32K bytes of external code
memory addressed as 00h to 7FFFh (the
addresses from 8000h to FFFFh wrap to the
same addresses as 00h to 7FFFh). This 32K
can be mapped to any of the sixteen 32K
memory blocks in the 512K external ROM by the
For ALT Bondout with nEA=1, the internal ROM
is addressed from 0-7FF, all ROM access from
800h-7FFFh are invalid address locations. It
can support up to 32K bytes of additional
external code memory addressed as 8000h to
145
Memory Map Configuration Control Bit
KMEM register. At initial power-up (VCC1 POR)
the chip will execute from the block selected by
the default value of the KMEM register.
The Configuration Register 0, an 8051 memory
mapped register at address 7FF4h includes a bit
called the Memory Map Control bit (MMC). The
MMC bit is bit-3 of this register and defaults to
zero on VCC1 POR. When MMC=0 the 8051
memory map will contain an additional 256
bytes of external scratch RAM in the address
range 7D00h through 7DFFh. When MMC=1
the scratch ram at 7D00h-7DFFh becomes
scratch ROM at 00h-0FFh (for an SMSC Bond
Out device) or scratch ROM at 800h-8FFh (for
an ALT Bond Out device).
The 8051 can access up to 32K bytes of
external RAM addressed from 0-7FFFh. Refer to
TABLE 86 for a list of the implemented on-chip
memory mapped registers. External memory
addressed from 8000h-FFFFh will access the
32K bytes of program memory (8000-FFFFh)
selected by the KMEM register.
The 256 bytes of RAM from 7E00h-7EFFh as
well as the 256 bytes of Scratch RAM from
7D00h-7DFFh are powered by VCC1. These
are general purpose Read/Write registers
available to the 8051. The Scratch RAM may be
converted into scratch ROM by setting the MMC
bit.
The Configuration Register 0 register is
described in the 8051 Control Register Section
of this specification.
SMSC/ALT Bond Option [nEA=0]
Regardless of the bonding option, if nEA is held
low the 8051 memory map for both options is
the same as shown in the figure below.
146
FFFFh
Same
0000h External
8000h
7FFFh
7F00h
7 E0 0 h
7D00h
M/M
RAM
Scratch
Indirect
FFh
SFR (Direct
FFh
80h
80h
00h
Direct and
External
Program
Internal
Data
S M S C / A L T Bondout, n EA = 0 , M M C
FIGURE 13 - 8051 MEMORY MAP FOR ANY BOND OPTION WITH NEA LOW
Instructions to access memory
MOV
: Internal RAM/Registers.
MOVC : Program ROM from 0000h through FFFFh
MOVX : External RAM from 7D00h through 7FFFh -ANDExternal ROM from 8000h through FFFFh. (allows flashing of ROM).
SMSC Bond Option [nEA=1]
147
This section describes the 8051 memory map for an SMSC bonded part where the nEA pin is high.
The MMC bit determines the configuration of the 8051’s memory map. When nEA=1 an additional
256 of re-writable ROM space can be added to the 8051’s internal ROM space to allow patch code
upgrades. In order to take advantage of this extra 256 bytes of scratch RAM/ROM certain design
considerations must be met as outlined in the following Programmers notes.
MMC bit = 0
When the MMC bit is low (VCC1 POR default) a hard coded long jump LJMP to 8000h is encoded at
addresses 00h through 02h and a 256 byte scratch RAM is located at external addresses 7D00-7DFF.
The encoding for the hard coded Long Jump is shown in the following table.
HARD CODED LJMP TO 8000H.
8051 Address
Encoding
00h
02h
01h
80h
02h
00h
FFFFh
32K
External
8000h
7FFFh
7F00h
7E00h
7D00h
M/M Registers
RAM
Scratch RAM
FFh
Indirect Only
SFR (Direct Only)
FFh
80h
80h
02h
00h
Hard Coded Internal
00h
Direct and Indirect
External
Program Memory
Internal
Data Memory
SMC Bondout, nEA = 1, Reg MMC bit = 0
FIGURE 14 - 8051 MEMORY MAP FOR SMC BOND OPTION WITH NEA=1, MMC=0
148
Instructions to access memory
MOV
: Internal RAM/Registers.
MOVC : Program ROM from 8000h through FFFFh
MOVX : External RAM from 7D00h through 7FFFh -ANDExternal ROM from 8000h through FFFFh. (allows flashing of ROM).
MMC bit = 1
When the MMC bit is high the scratch RAM at 7D00h-7DFFh is disabled and now becomes the
executable internal scratch ROM at address locations 00h-0FFh. The hard coded LJMP to 8000h is
overrided by the scratch ROM.
FFFFh
32K
External
8000h
7FFFh
7F00h
7 E0 0 h
M/M
RAM
7D00h
Indirect
FFh
FFh
00h
SFR (Direct
FFh
80h
80h
Scratch
Internal
00h
Direct and
External
Program
Internal
Data
S M S C B o n d o u t , nEA = 1 , M M C b i t = 1
FIGURE 15 - 8051 MEMORY MAP FOR SMC BOND OPTION WITH nEA=1, MMC=1
Instructions to access memory
MOV
: Internal RAM/Registers.
MOVC : Program ROM from 8000h through FFFFh called from 00h-0FFh or from 8000h-0FFFFh.
Program ROM from 00h through 0FFh called from 00h-0FFh only.
MOVX : External RAM from 7E00h through 7FFFh -ANDExternal ROM from 8000h through FFFFh. (allows flashing of ROM).
149
ALT Bond Option [nEA=1]
This section describes the 8051 memory map for an ALT bonded part where the nEA pin is high. The
MMC bit determines the configuration of the 8051’s memory map.
MMC bit = 0
When the MMC bit is low (VCC1 POR default) an additional 256 bytes of Scratch RAM are added to
the 8051’s memory map at addresses 7D00h though 7DFFh.
FFFFh
32K
External
8000h
7FFFh
7F00h
7E00h
7D00h
M/M Registers
RAM
Scratch RAM
FFh
7FFh
2K
Internal Mask ROM
Indirect Only
SFR (Direct Only)
FFh
80h
80h
00h
00h
Direct and Indirect
External
Program Memory
Internal
Data Memory
ALT Bondout, nEA = 1, MMC bit = 0
FIGURE 16 - 8051 MEMORY MAP FOR ALT BOND OPTION WITH NEA=1, MMC=0
Instructions to access memory
MOV
: Internal RAM/Registers.
MOVC : Program ROM from 8000h through FFFFh called from 00h-7FFh or from 8000h-0FFFFh.
Program ROM from 00h through 7FFh called from 00h-7FFh only.
MOVX : External RAM from 7D00h through 7FFFh -ANDExternal ROM from 8000h through FFFFh. (allows flashing of ROM).
150
MMC bit = 1
When the MMC bit is high an additional 256 bytes of executable ROM space between address 800h
and 8FFh is added to the 8051’s internal ROM space to allow patch code upgrades.
FFFFh
32K
External
8000h
7FFFh
1000h
8FFh
800h
7FFh
RESERVED
Scratch ROM
Internal
7F00h
M/M Registers
7E00h
RAM
7D00h
FFh
2K
Internal Mask ROM
Indirect Only
SFR (Direct Only)
FFh
80h
80h
00h
00h
Direct and Indirect
External
Program Memory
Internal
Data Memory
ALT Bondout, nEA = 1, MMC bit = 1
FIGURE 17 - 8051 MEMORY MAP FOR ALT BOND OPTION WITH nEA=1, MMC=1
Instructions to access memory
MOV
: Internal RAM/Registers.
MOVC : Program ROM from 8000h through FFFFh called from 00h-8FFh or from 8000h-0FFFFh.
Program ROM from 00h through 8FFh called from 00h-8FFh only.
MOVX : External RAM from 7E00h through 7FFFh -ANDExternal ROM from 8000h through FFFFh. (allows flashing of ROM).
151
A chip enable output nFCS for the Flash ROM
interface is ‘1’ when the 8051 is sleeping with
control of the Flash or can optionally be
configured
to
follow
nFRD
(see
PROGRAMMABLE FLASH CHIP SELECT on
page 196). The external Flash ROM interface
timing for the high-performance 8051 core is
shown below in FIGURE 18. The preliminary
Flash ROM Address read-access times are
shown in TABLE 84.
(NOTE: THESE
SPECIFICATIONS
ARE
SUBJECT
TO
CHANGE)
FLASH ROM INTERFACE
OVERVIEW
The FDC37N972 supports a 512k Byte Flash
ROM interface (see HOST BOOT BLOCK
SELECT on page 195.) A high-order address
bit FA18 is added to the FDC37N972 on
GPIO13 (see TABLE 4 for a description of the
Alternate Function pins and MULTIFUNCTION
PIN on page 271).
TABLE 84 - FLASH ADDRESS ACCESS TIMES
8051 CLOCK
FLASH ADDRESS
(MHz)
ACCESS TIME (ns)
24
65
16
115
12
165
cycle
c1
c2
c3
c4
clock
FALE
Taddress access
nFRD
FAD[7:0]
FA[8:18]
ADDRESS
A0 – A7 OUT
INSTRUCTION IN
ADDRESS A8 – A18 OUT
FIGURE 18 - 8051 PROGRAM READ FLASH ROM INTERFACE TIMING
152
8051 CONTROL REGISTERS
SPECIAL FUNCTION REGISTERS (SFRS)
The high-performance 8051 includes SFRs to support the extended interrupt unit and timer 2 (TABLE
85). The high-performance 8051 does not support the MISZ register.
TABLE 85 - 8051 CONTROL REGISTERS
REGISTER
NAME
STARTING
ADDRESS
D7
SP
DPLO
DPHO
DPL1(1)
DPH1(1)
DPS(1)
PCON
81H
82H
83H
84H
85H
86H
87H
TCON
TMOD
TL0
TL1
TH0
TH1
SCON*
88H
89H
8AH
8BH
8CH
8DH
8EH
91H
92H
98H
SBUF
IE
IP*
T2CON
99H
A8H
B8H
C8H
RCAP2L
RCAP2H
TL2
TH2
PSW
EICON(1)
CAH
CBH
CCH
CDH
D0H
D8H
ACC
E0H
CKCON(1,3)
EXIF(1)
MPAGE(1,2)
REGISTER
RESET
VALUE
FIX BIT REGISTERS
D6
D5
D4
D3
D2
D1
D0
7H
0
SMO
D0
TF1
GATE
0
-
0
1
0
1
0
GF1
0
GF0
0
STO
P
IE0
M1
SEL
IDLE
TR1
C/T
TF0
M1
TR0
M0
IE1
GATE
IT1
C/T
IE5
IE4
T2M
IE3
T1M
IE2
T0M
1
MD2
MD1
0
MD0
0
SM0_
0
SM1
_0
SM2
_0
REN
_0
TB8_
0
RB8
_0
TI_0
RI_0
EA
1
TF2
ES1
PS1
ET2
PT2
ES0
PS0
ET1
PT1
EX1
PX1
TCLK
EXEN2
TR2
ET0
PT0
C/T2
EX0
PX0
CP/
RL2
EXF2
RCLK
CY
SMO
D1
AC
1
F0
EPFI
RS1
PFI
RS0
WDTI
OV
0
F1
0
P
0
153
0
30H
IT0
M0
1H
8H
00H
40H
REGISTER
NAME
STARTING
ADDRESS
D7
REGISTER
RESET
VALUE
FIX BIT REGISTERS
EIE(1)
E8H
1
D6
1
B
EIP(1)
F0H
F8H
1
1
D5
1
D4
EW
DI
D3
EX5
D2
EX4
D1
EX3
D0
EX2
E0H
1
PW
DI
PX5
PX4
PX3
PX2
E0H
(1) Not part of standard 8051 architecture. See Appendix B.
(2) The MPAGE special function register provides a means of 16-bit addressing without using the
data pointer. During MOVX A, @Ri and MOVX @Ri, A instructions, the 8051 places the contents
of the MPAGE register on the upper 8 address bits. The MPAGE register default is ‘00H’.
(3) The TM2 bit in the CKCON register is available, but not used, when Timer 2 is not implemented
(timer =0).
*=Bit-addressable register
MEMORY MAPPED CONTROL REGISTERS (MMCRS)
PM1 Block Interface (PM1). These addresses
are described in Column #2 (SYSTEM
ADDRESS) in TABLE 86.
MMCR SUMMARY
The Memory Mapped Control Registers are onchip memory-mapped registers that can be
accessed by the 8051 but are external to the
8051 core (TABLE 86). The 8051 can access
all of the Memory Mapped Control Registers.
The 8051 MMCR addresses are described in
Column #4 (8051 ADDR) in TABLE 86.
These Memory Mapped Control Registers can
be accessed by the following types of 8051
instructions.
movx
A,@DPTR
movx
@DPTR,A
mov
MPAGE,#7FH
movx
A,@Rx (R0 or R1 only)
mov
MPAGE,#7FH
movx
@Rx,A (R0 or R1 only)
Some MMCRs can also be accessed through
the ISA Host interface (ISAxxh), the Mailbox
Registers interface (MBXxxh), the Embedded
Controller Interface (ECI BASE), and the ACPI
154
TABLE 86 - 8051 ON-CHIP EXTERNAL MEMORY MAPPED REGISTERS
Y
REF.
PAGE#
205
N
O
T
E
S
7
1,7
-
Y
205
7
VCC1
00h
Y
205
2,7
-
VCC1
00h
-
13
-
-
VCC1
VCC1
00h
-
13
13
R/W
R
F3h
F4h
F5h
F6h
F7h
F8h
F9h
FAh
R/W
R/W
R/W
R/W
R/W
R/W
R/W
W
VCC1
VCC1
VCC1
VCC1
VCC1
VCC1
VCC1
VCC1
VCC1
00h
00h
80h
00h
00
00h
00h
-
13
Y
177
163
293
294
294
294
294
205
3,7
-
-
FBh
FCh
R/W
R/W
VCC1
VCC1
01h
00h
-
210
193
17
-
-
FDh
FEh
FFh
00h
R/W
W
W
R/WC
VCC1
VCC1
VCC1
VCC1
00h
00h
206
210
210
168
-
-
01h
R/W
VCC1
00h
170
SYSTEM
REGISTER
NAME
Reserved
Host I/F Data
Reg
[KBD
Data/Command
Write Reg.]
Host I/F Data
Reg
[KBD Data
Read Reg.]
Host I/F Status
Reg
[KBD Status
Reg.]
RTC Address
1
RTC Data 1
RTC Address
2
RTC Data 2
HTIMER
Config Reg 0
RTCCNTRL
RTCADDRL
RTCDATAL
RTCADDRH
RTCDATAH
Aux Host Data
Reg
[KBD Data
Read Reg.]
GATEA20
FLASH
CONFIG.
PCOBF
SETGA20L
RSTGA20L
Interrupt 0
source register
Interrupt 0
mask register
W
8051
ADDR.
(7F00+)
F0h
F1h
8051
TYPE
W
R
POWER
PLANE
VCC1
VCC1
VCC1
POR
-
ISA 60h
R
F1h
W
VCC1
ISA 64h
R
F2h
R/W
R/W
-
R/W
R/W
ISA 60h
SYSTEM
ADDRESS
ISA 60h
ISA 64h
ADDR.
TYPE
155
VCC2
POR
-
ZERO
WAIT
STATE
(8)
6
SYSTEM
REGISTER
NAME
Interrupt 1
source register
Interrupt 1
mask register
Keyboard Scan
out
Keyboard Scan
in
Device Rev
register
Device ID
register
(SMSC
BONDOUT)
Device ID
register
(ALT
BONDOUT)
System-to8051
Mailbox
register 0
8051-tosystem
Mailbox
register 1
Mailbox
register [2-F]
GPIO
Direction
register A
GPIO Output
register A
GPIO Input
register A
GPIO
Direction
register B
GPIO Output
register B
GPIO Input
register B
SYSTEM
ADDRESS
-
ADDR.
TYPE
8051
ADDR.
(7F00+)
8051
TYPE
-
02h
-
-
-
N
O
T
E
S
VCC1
POR
R/WC
POWER
PLANE
VCC1
00h
REF.
PAGE#
170
03h
R/W
VCC1
00h
171
-
04h
W
VCC1
20h
215
-
-
04h
R
VCC1
-
215
-
-
05h
06h
R
VCC1
00h
-
-
07h
R
VCC1
0Bh
163
-
-
07h
R
VCC1
0Ah
163
MBX 82h
R/W
08h
RC
VCC1
00
Y
248
4
MBX 83h
RC
09h
R/W
VCC1
00
Y
249
5
MBX
84h-91h
-
R/W
0A-17h
R/W
VCC1
00h
Y
244
-
18h
R/W
VCC1
00h
262
-
-
19h
R/W
VCC1
00h
262
-
-
1Ah
R
VCC1
-
262
-
-
1Bh
R/W
VCC1
02h
263
-
-
1Ch
R/W
VCC1
00h
263
-
-
1Dh
R
VCC1
-
263
156
VCC2
POR
ZERO
WAIT
STATE
(8)
-
-
162
-
SYSTEM
REGISTER
NAME
GPIO
Direction
register C
GPIO Output
register C
GPIO Input
register C
LED register
OUT register
D
OUT register E
IN register F
PWM0 register
PWM1 register
KSTP_CLK
Fan Control
Register
KMEM
WAKEUP
Source 1
WAKEUP
Source 2
WAKEUP
mask 1
WAKEUP
mask 2
KSTP_CLK_2
Multiplexing 3
register
ACCESS.BUS
Control reg
ACCESS.BUS
Status reg
ACCESS.BUS
Own Address
reg
ACCESS.BUS
Data reg
ACCESS.BUS
Clock
-
SYSTEM
ADDRESS
-
ADDR.
TYPE
8051
ADDR.
(7F00+)
8051
TYPE
-
1Eh
-
-
-
VCC1
POR
R/W
POWER
PLANE
VCC1
00h
REF.
PAGE#
264
1Fh
R/W
VCC1
00h
264
-
20h
R
VCC1
-
264
-
-
21h
22h
R/W
R/W
VCC1
VCC1
00h
00h
249
265
MBX 92h
MBX 93h
MBX 9D
R/W
R/W
R/W
23h
24h
25h
26h
27h
28h
R/W
R
R/W
R/W
R/W
R/W
VCC1
VCC1
VCC1
VCC1
VCC1
VCC1
00h
00h
00h
10h
30h
265
265
252
252
143
253
-
-
29h
2Ah
R/W
R/WC
VCC1
VCC1
00h
00h
188
172
-
-
2Bh
R/WC
VCC1
00h
173
-
-
2Ch
R/W
VCC1
00h
175
-
-
2Dh
R/W
VCC1
00h
175
-
-
2Eh
2Fh
30h
R/W
R/W
VCC1
VCC1
00h
00h
-
-
31h
W
VCC1
00h
239
-
-
31h
R
VCC1
81h
239
-
-
32h
R/W
VCC1
00h
239
-
-
33h
R/W
VCC1
00h
240
-
-
34h
R/W
VCC1
00h
240
-
-
35h
-
-
-
-
157
VCC2
POR
ZERO
WAIT
STATE
(8)
Y
Y
Y
-
-
142
272
N
O
T
E
S
-
SYSTEM
REGISTER
NAME
WDT
Control/Status
WDT Timer
PP Status Reg
PP Control
Reg
PP Data Reg
Multiplexing 1
register
Output Enable
register
DISABLE
register
Multiplexing 2
register
PS/2 Port1
Control/
PS/2 Chan A
Tx/Rx
PS/2 Port1
Status/
PS/2 Chan A
Control
PS/2 Port1
Error/
PS/2 Chan A
Status
PS/2 Port1
Transmit
PS/2 Port1
Receive/
PS/2 Chan B
Tx/Rx
PS/2 Chan B
Control
PS/2 Chan B
Status
PS/2_
STATUS_2
SYSTEM
ADDRESS
-
ADDR.
TYPE
8051
ADDR.
(7F00+)
8051
TYPE
-
36h
37h
-
-
-
-
VCC1
POR
R/W
POWER
PLANE
VCC1
38h
39h
3Ah
3Bh
R/W
R/W
R/W
VCC1
VCC2
VCC2
FFh
-
3Ch
3Dh
R/W
R/W
VCC2
VCC1
3Eh
R/W
VCC1
VCC2
POR
ZERO
WAIT
STATE
(8)
00h
00h
00h
-
REF.
PAGE#
184
184
257
258
00h
258
266
see
note
164
00h
N
O
T
E
S
9
-
-
3Fh
R/W
VCC1
see
note
00h
-
-
40h
R/W
VCC1
00h
-
-
41h
R/W
VCC2
-
00h
227
7
-
-
42h
R
R/W
VCC2
-
40h
229
7
-
-
43h
R
VCC2
-
00h
231
7
-
-
44h
W
VCC2
-
00h
232
-
-
45h
R
R/W
VCC2
-
00h
232
-
-
46h
R/W
VCC2
-
40h
220
-
-
47h
R
VCC2
-
00h
222
-
-
48h
R
VCC2
-
00h
158
11
162
270
-
224
7
SYSTEM
REGISTER
NAME
PS/2 Port2
Control/
PS/2 Chan C
Tx/Rx
PS/2 Port2
Status/
PS/2 Chan C
Control
PS/2 Port2
Error/
PS/2 Chan C
Status
PS/2 Port2
Transmit
PS/2 Port2
Receive/
PS/2 Chan D
Tx/Rx
PS/2 Chan D
Control
PS/2 Chan D
Status
8051_SIRQ
EC_DATA
EC_
COMMAND
EC_STATUS
Edge Select
4A
Edge Select
4B
Wake up SRC
4
Wake Up
Mask 4
-
00h
REF.
PAGE#
227
N
O
T
E
S
7
-
40h
229
7
VCC2
-
00h
231
7
W
VCC2
-
00h
232
4Dh
R
R/W
VCC2
-
00h
232
4Eh
R/W
VCC2
-
40h
4Fh
R
VCC2
-
00h
-
-
-
-
-
-
R/W
R/W
R/W
VCC1
VCC1
VCC1
00h
00h
00h
-
Y
Y
181
84
84
12
12
Y
84
12
-
178
-
SYSTEM
ADDRESS
-
ADDR.
TYPE
8051
ADDR.
(7F00+)
8051
TYPE
-
49h
R/W
-
-
4Ah
-
-
-
POWER
PLANE
VCC2
VCC1
POR
VCC2
POR
-
R
R/W
VCC2
4Bh
R
-
4Ch
-
-
-
-
ZERO
WAIT
STATE
(8)
-
220
222
-
-
ECI BASE
ECI
BASE+4
R/W
W
50h51h
52h
53h
53h
ECI
BASE+4
-
R
54h
R/W
VCC1
00h
-
55h
56h
57h
R/W
VCC1
00h
58h
R/W
VCC1
00h
178
59h
R/WC
VCC1
00h
173
5Ah
R/W
VCC1
00h
176
5Bh
-
-
-
-
-
159
-
-
7
-
-
-
SYSTEM
REGISTER
NAME
Edge Select
5A
Edge Select
5B
Wake up SRC
5
Wake Up
Mask 5
Edge Select
6A
Edge Select
6B
Wake up SRC
6
Wake Up
Mask 6
ACCESS.BUS
2 Control reg
ACCESS.BUS
2 Status reg
ACCESS.BUS
2 Own
Address reg
ACCESS.BUS
2 Data reg
ACCESS.BUS
2 Clock
Mailbox
registers[101F]
PM1_STS2
PM1_EN2
PM1_CNTRL2
8051_PM_
STS
PWRGD_INT
SYSTEM
ADDRESS
-
-
ADDR.
TYPE
-
-
8051
ADDR.
(7F00+)
8051
TYPE
5Ch
VCC2
POR
ZERO
WAIT
STATE
(8)
VCC1
POR
R/W
POWER
PLANE
VCC1
00h
REF.
PAGE#
178
5Dh
R/W
VCC1
00h
179
5Eh
R/WC
VCC1
00h
174
5Fh
R/W
VCC1
00h
176
60h
61h
R/W
VCC1
00h
62h
R/W
VCC1
00h
180
63h
R/WC
VCC1
00h
174
64h65h
66h
-
-
-
-
R/W
VCC1
00h
177
-
-
179
-
-
67h
W
VCC1
00h
241
-
-
67h
R
VCC1
81h
241
-
-
68h
R/W
VCC1
00h
242
-
-
69h
R/W
VCC1
00h
242
-
-
6Ah
R/W
VCC1
00h
242
-
-
-
-
-
MBX
A0-AF
R/W
6Bh –
6Fh
70h7Fh
R/W
VCC1
PM1+1
PM1+3
PM1+5
-
R/WC
R/W
R/W
-
80h
81h
82h
83h
R/W
R
R
R/W
-
-
84h
R/WC
160
-
N
O
T
E
S
-
-
-
-
00
Y
244
VCC1
VCC1
VCC1
VCC1
00
00
00
00
-
Y
Y
Y
-
279
280
281
282
-
VCC1
00
-
-
180
15
SYSTEM
SYSTEM
ADDRESS
-
ADDR.
TYPE
Test Register
-
-
-
-
-
256 bytes of
RAM
-
-
REGISTER
NAME
-
-
8051
ADDR.
(7F00+)
85h8Dh
8Eh8Fh
90hEFh
7E007EFFh
-
REF.
PAGE#
-
N
O
T
E
S
-
-
-
-
-
-
-
-
-
VCC1
POR
VCC2
POR
-
POWER
PLANE
-
ZERO
WAIT
STATE
(8)
-
-
-
-
-
-
-
-
R/W
VCC1
8051
TYPE
146
Notes:
1. Although the Input and Output Data registers are physically separate, they share address 7FF1.
2. The 8051 CPU cannot write to some bits of the Status register.
3. Writing to the Auxiliary Output Data Register, loads the Output data register and can set the
AUXOBF1 output if enabled. This does not set the PCOBF output.
4. Interrupt is cleared when read by the 8051.
5. Interrupt is cleared when read by the host.
6. See RTC control Register Definition.
7. These addresses are shared between the PS/2 Devil Logic and the SMSC PS/2 Hardware
Channels A – D (see PS/2 DEVICE INTERFACE section on page 221).
8. When accessed for a read or write by the System the registers marked with a “Y” will drive the
Zero wait state pin active.
9. Bit 0 is the only writable or resetable bit in this register.
10. When IRESET_OUT is cleared (written from “1” to”0”) 8051STP_CLK bit D0 as well as HMEM
bits D1 and D0 are all set to “1”.
11. VCC1 POR = 00000X10b, VCC2 POR = 00000X1Xb where X is not affected by VCC2 POR, but
is left at the current value.
12. These registers have the same structure as the keyboard interface registers.
13. The ISA RTC registers are relocatoable and accessed by the 8051 through MMCRs 0x7FF5 –
0x7FF9.
14. See Section General Purpose I/O (GPIO) on page 265.
15. See Power Fail IRQ on page 184.
16. See FLASH CONFIGURATION REGISTER on page 197.
17. SMSC PS/2 Status_2 REGISTERS section on page 229.
161
8051 CONFIGURATION/CONTROL MEMORY MAPPED REGISTERS
DISABLE REGISTER
TABLE 87 - DISABLE REGISTER
HOST
ADDRESS
-
HOST
TYPE
8051
TYPE
BIT
NAME
8051 ADDRESS
0x7F3F
POWER PLANE
VCC1
DEFAULT
0x00
D7
D6
D5
D4
D3
D2
D1
D0
-
-
-
-
-
-
-
-
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
SYSTEM
FLASH
Interface
1=Enable
0= DISABLE
Reserved
FORCE
2
WRTPRT
Parallel
Port 1 =
Enable
0=
Disable
Serial
Port
1=
Enable
0=
Disable
IR Port
1=
Enable
0=
Disable
Floppy
Port 1 =
Enable
0=
Disable
UD
1
NOTE1 The UD bits are User-Defined. UD bits are maintained by 8051 software, only.
NOTE2 See Section FDC FORCE WRITE PROTECTION page 84 for a description of the FORCE
WRTPRT Bit function.
DEVICE REV REGISTER
By reading this register, 8051 firmware can confirm the device revision that it is running on.
TABLE 88 - DEVICE REV REGISTER
Host
N/A
8051
0x7F06 (R)
Power
VCC1
Default
0x00
8051 R
Bit Description
D7
R
D6
R
D5
D4
D3
R
R
R
Current Revision
This register is hardwired.
162
D2
R
D1
R
D0
R
1
DEVICE ID REGISTER
By reading this register, 8051 firmware can determine which device it is running on.
TABLE 89 - DEVICE ID REGISTER
Host
N/A
8051
0x7F07 (R)
Power
VCC1
Default
0x0A
8051 R
Bit description
D7
R
0
D6
R
0
D5
R
0
D4
R
0
D3
R
0
D2
R
1
D1
R
1
D0
R
1
CONFIGURATION REGISTER
TABLE 90 - CONFIGURATION REGISTER 0
Host
N/A
8051
0x7FF4
Power
VCC1
Default
0x00
D7
AUXH
D6
0
D5
OBFEN
D4
PS2_SEL
D3
MMC
D2
PCOBFEN
D1
SAEN
D0
SLEEPFLAG
AUXH
Aux in Hardware; When high, AUXOBF of the status register is set in hardware by a write to 7FFAh.
When low, AUXOBF of the status register is a user defined bit (UD) and R/W.
OBFEN
When set PCOBF is gated onto KIRQ and AUXOBF1 is gated onto MIRQ. When low, KIRQ and
MIRQ are driven low. Software should not change this bit when OBF of the status register is equal to
1.
MMC
Memory Map Control Bit : When MMC=0, a 256 Byte Scratch RAM area at 7D00h is available to the
8051. When MMC=1 the Scratch RAM at 7D00h-7DFFh becomes scratch ROM at 00h--FFh.
PCOBFEN
When high, PCOBF reflects whatever value was written to the PCOBF firmware latch assigned to
7FFDH. When low, PCOBF reflects the status of writes to 7FF1H (the output data register).
163
PS2_SEL
If PS2_SEL=0 (default) then the PS2 Device Interface Logic (DEVIL) is enabled and if PS2_SEL=1
then the SMSC PS2 Interface (SPS2) is enabled. The following table illustrates this:
PS2_SEL
0
1
Internal active PS/2 Logic Block
PS2 Device Interface Logic (DEVIL)
SMSC PS2 Interface Logic (SPS2)
SAEN
Software-assist enable. When set to “1” SAEN allows control of the GATEA20 signal via firmware. If
SAEN is reset to ‘0’, GATEA20 corresponds to either the last host-initiated control of GATEA20 or the
firmware write to 7FFEh or 7FFFh.
SLEEPFLAG
If SLEEPFLAG=“0” when PCON bit-0 is set, the 8051 enters “IDLE” mode, whereas if
SLEEPFLAG=“1” when PCON bit 0 is set the 8051enters “SLEEP” mode. This bit is cleared by the
occurrence of any wake-up events and on VCC1 POR.
OUTPUT ENABLE REGISTER
Table 91 - Output Enable Register
Host
N/A
8051
0x7F3E
Power
VCC1
Default
00000X10b on VCC1 POR
00000X1Xb on VCC2 POR
Output Enable Register VCC1 POR = 0x00000X10, VCC2 POR = 00000X1Xb where X means the bit
holds its setting preceding VCC2 POR.
D7-D4
R/W
Reserved
0
AR= Access Rights
8051 AR
D3
R/W
iRESET_
OVRD
D2
R
Power_Good
iRESET_OUT
D0
R/W
32kHz Output
When POWERGOOD=0, iRESET_OUT is
forced high (within 100nsec) and latched. The
nRESET_OUT pin is not driven until VCC2 is
applied. iRESET_OUT cannot be cleared by the
8051 until POWERGOOD=1.
iRESET_OUT
When POWERGOOD=1,
controlled by the 8051.
D1
R/W
iRESET_OUT
is
164
The above sequence provides a means for the
8051 to directly control the state of the Super
I/O block’s internal reset. The FDC37N972
provides a means for the 8051 to drive low or
toggle the chip’s internal reset without stopping
the 8051 clock or giving the Flash interface to
the host.
POWER_GOOD
The Power_Good bit D2 reflects the state of the
FDC37N972 VCC2 Power Good pin PWRGD.
The Power_Good bit is read-only.
iRESET_OVRD
iRESET Override - when cleared the
iRESET_OUT bit functions as described above.
When set, iRESET_OUT is given direct control
over the internal reset and nRESET_OUT pins
without requiring the STOP_CLK counter or
affecting the 8051STP_CLK bit or the HMEM
register.
In the override mode, setting
iRESET_OUT drives nRESET_OUT low and
clearing iRESET_OUT drives nRESET_OUT
high.
32kHz OUTPUT
The RESET_OUT Override function allows the
8051 to take the rest of the FDC37N972 chip
(SIO) out of reset without giving up control (i.e.,
without stopping its clock and giving the flash
interface to the Host).
8051 INTERRUPTS
The 32kHz Output bit D0 controls the
FDC37N972
32kHz
Output
Clock
pin
32kHz_OUT. When 32kHz Output is ‘0’, the
32kHz Output Clock is disabled and the
32kHz_OUT pin is driven low. When 32kHz
Output is ‘1’, the 32kHz Output Clock is
enabled. The 32kHz Output bit is R/W and
disabled by default following VCC1 POR.
8051
INTERRUPT
FEATURES
ARCHITECHTURE
The eleven 8051 core interrupts are shown
described in TABLE 92 - 8051 INTERRUPTS.
The 8051 has the following run time sources:
int0, int1, int2, int3 and int4.
On the current FDC37N972, nRESET_OUT is
driven high by this sequence of events.
Sets STP_CNT to a non-zero value
Clears iRESET_OUT bit, causing
8051STP_CLK bit 0 to get set
HMEM[7:0] to get set to 0x07
and STOP Counter to start decrementing
The Interrupt sources of Int5_n create 8051
Wakeup Events which are used to monitor and
altar the power management state. There are
three type of source triggers for wakeup event:
Nonprogrammable (fixed edge), Selectable
Edge (SE), Either Edge (EE).
When STP_CNT reaches 0 the nRESET_OUT
pin deasserts (goes high) at which point the
8051’s clock stops and the Host owns the Flash
Interface.
The 8051 core has three interrupt priority levels:
PFI, high and low. The PFI interrupt, if enabled,
has priority over all other interrupts.
165
8051 INTERNAL PARALLEL INTERRUPTS
INT2
INT3
INT4
GRP2
0
1
2
3
GRP1
0
1
2
3
4
5
6
7
IN2
IN1
IN0
WK_EE3 STAT
WK_EE2 STAT
WK_EE4 STAT
ACCBUS2 STAT
PS2_A/PS2 P1 STAT
PS2_B/PS2 P2 STAT
PS2_C STAT
PS2_D STAT
0
1
2
3
4
5
6
7
IN7
RTC_ALRM STA
WK_EE1 STAT
IR_RX STAT
AB_DAT2 STA
AB_DAT 1 STA
PM1_STS_2 STA
PM1_EN 2 STA
PM1_CTL 2 STA
Wake Up Src 1 (0x7F2A)
0
1
2
3
4
5
6
7
IN3
IN2
IN1
IN0
nGPWKUP STAT
WK_ANYKEY ST
HTIMER STAT
WK_EE3 STAT
WK_EE2 STAT
WK_EE4 STAT
UART_RI1 STAT
RESERVED
Wake Up Src 2 (0x7F2B)
0
1
2
3
4
5
6
7
External Interrupt
Enable SFR
WK_EE3 MSK
WK_EE2 MSK
WK_EE4 MSK
ACCBUS2 MSK
PS2_A/PS2 P1 MSK
PS2_B/PS2 P2 MSK
PS2_C MSK
PS2_D MSK
POWER-FAIL EVENT
0
RTC_ALRM MK
WK_EE1 MK
IR_RX MK
AB_DAT 2 MK
AB_DAT 1 MK
PM1_STS_2 MK
PM1_EN 2 MK
PM1_CTL 2 MK
0
1
2
3
4
5
6
7
GRP1
nGPWKUP MK
WKANYKEY MK
HTIMER_MK
WK_EE3_MK
WK_EE2_MK
WK_EE4_MK
UART_RI1_MK
RESERVED
Wake Up MSK 2 (0x7F2D)
0
1
2
3
4
5
6
7
ANY WUP STAT
SYS-MBOX STA
ACCBUS1 STA
GPIO3 STAT
EC_OBF STAT
EC_IBF STAT
KBD SCAN STAT
IBF STAT
INT1 SRC (0x7F02)
0
1
2
3
4
5
6
7
ANY WUP_MK
SYS-MBOX_MK
ACCBUS1_MK
GPIO3_MK
EC_OBF_MK
EC_IBF_MK
KBD SCAN_MK
IBF_MK
INT1 MASK (0x7F03)
Note : WK_EE[2:4] are found at Wake Up register 2 and INT0 register.
5/20/98
INT0_EN
TF0_EN
INT1_EN
TF1_EN
RI + TI_EN
TF2_EN
RESERVED
RESERVED
Interrupt Enable
SFR
Wake Up MSK 1 (0x7F2C)
0
1
2
3
4
5
6
7
PGI
PWRGD_INT
(0x7F84)
INT0 MASK (0x7F01)
INT0 SRC (0x7F00)
0
1
2
3
4
5
6
7
INT2
INT3_n
INT4
INT5_n
8051 INTERRUPTS
FIGURE 19 - 8051 INTERRUPTS
166
PFI
EICON SFR
0
1
2
3
4
5
6
7
INT0 POL
TF0 POL
INT1 POL
TF1 POL
RI + TI POL
TF2 POL
RESERVED
RESERVED
Interrupt Polarity
SFR
IN4
IN5
GPIO0
GPIO1
GPIO2
IN6
GPIO7
GPIO4
0,1
WK_SE00_SEL
0
WK_SE00_SRC
0
WK_SE00_MK
2,3
WK_SE01_SEL
1
WK_SE01_SRC
1
WK_SE01_MK
4,5
WK_SE02_SEL
2
WK_SE02_SRC
2
WK_SE02_MK
6,7
WK_SE03_SEL
3
WK_SE03_SRC
3
WK_SE03_MK
0,1
WK_SE04_SEL
4
WK_SE04_SRC
4
WK_SE04_MK
2,3
WK_SE05_SEL
5
WK_SE05_SRC
5
WK_SE05_MK
4,5
WK_SE06_SEL
6
WK_SE06_SRC
6
WK_SE06_MK
6,7
WK_SE07_SEL
7
WK_SE07_SRC
7
WK_SE07_MK
Edge Select 4 (0x____)
GPIO5
GPIO6
GPIO8
GPIO9
GPIO10
GPIO11
GPIO12
GPIO13
Wake Up MSK 4 (0x____)
0,1
WK_SE10_SEL
0
WK_SE10_SRC
0
WK_SE10_MK
2,3
WK_SE11_SEL
1
WK_SE11_SRC
1
WK_SE11_MK
4,5
WK_SE12_SEL
2
WK_SE12_SRC
2
WK_SE12_MK
6,7
WK_SE13_SEL
3
WK_SE13_SRC
3
WK_SE13_MK
0,1
WK_SE14_SEL
4
WK_SE14_SRC
4
WK_SE14_MK
2,3
WK_SE15_SEL
5
WK_SE15_SRC
5
WK_SE15_MK
4,5
WK_SE16_SEL
6
WK_SE16_SRC
6
WK_SE16_MK
6,7
WK_SE17_SEL
7
WK_SE17_SRC
7
WK_SE17_MK
Edge Select 5 (0x____)
GPIO14
GPIO15
GPIO16
GPIO17
GPIO19
GPIO20
GPIO21
GPIO18
Wake Up SRC 4 (0x____)
Wake Up SRC 5 (0x____)
Wake Up MSK 5 (0x____)
0,1
WK_SE20_SEL
0
WK_SE20_SRC
0
WK_SE20_MK
2,3
WK_SE21_SEL
1
WK_SE21_SRC
1
WK_SE21_MK
4,5
WK_SE22_SEL
2
WK_SE22_SRC
2
WK_SE22_MK
6,7
WK_SE23_SEL
3
WK_SE23_SRC
3
WK_SE23_MK
0,1
WK_SE24_SEL
4
WK_SE24_SRC
4
WK_SE24_MK
2,3
WK_SE25_SEL
5
WK_SE25_SRC
5
WK_SE25_MK
4,5
WK_SE26_SEL
6
WK_SE26_SRC
6
WK_SE26_MK
6,7
WK_SE27_SEL
7
WK_SE27_SRC
7
WK_SE27_MK
Edge Select 6 (0x____)
Wake Up SRC 6 (0x____)
INT2
GRP2
INT3
INT4
Wake Up MSK 6 (0x____)
FIGURE 20 - EXTENDED INTERRUPTS & WAKE EVENTS
the WK_SE12 event can be used for IR wakeup.
See Section 8051 System Power
MANAGEMENT on page 198.
NOTE: Wake events apply per pin and are
available to all functions of that pin.
For
example, if the IRRX function is selected as an
alternate function of the GPIO8 pin (MISC7 = 1),
167
TABLE 92 - 8051 INTERRUPTS
INTERRUPT
pfi
int0_n
TF0
int1_n
TF1
TI_0 or
RI_0
TF2 or
EXF2
int2
int3_n
(1)
int4
int5_n
NATURAL
PRIORITY
0
1
2
3
4
5
INTERRUPT
VECTOR
0x33
0x03
0x0B
0x13
0x1B
0x23
6
0x2B
RESERVED
External Interrupt 2
External Interrupt 3
7
8
9
External Interrupt 4
External Interrupt 5
RESERVED
10
11
12
DESCRIPTION
Power Fail Interrupt
External Interrupt 0
Timer 0 Interrupt
External Interrupt 1
Timer 1 Interrupt
Serial Port 0 Transmit
or Receive
Timer 2 Interrupt
ENABLE
EICON.5
IE.0
IE.1
IE.2
IE.3
IE.4
PRIORITY
CONTROL
n/a
IP.0
IP.1
IP.2
IP.3
IP.4
IE.5
IP.5
0x3B
0x43
0x4B
FLAG
EICON.4
TCON.1
TCON.5
TCON.3
TCON.7
SCON0.0 (RI_0),
SCON0.1 (RI_0)
T2CON.7 (TF2),
T2CON.6 (EXF2)
RESERVED
EXIF.4
EXIF.5
IE.6
EIE.0
EIE.1
IP.6
EIP.0
EIP.1
0x53
0x5B
0x63
EXIF.6
EXIF.7
EICON.3
EIE.2
EIE.3
EIE.4
EIP.2
EIP.3
EIP.4
NOTE: The int5_n interrupt is used to restart the 8051 from sleep mode. This interrupt includes the
interrupt WAKE UP sources from GRP1 and GRP2 on FIGURE 19 and FIGURE 20.
8051 INT0 SOURCE REGISTER
The eight interrupts in the INT0 Source register (TABLE 93) are logically ‘OR’ed to drive the 8051
external interrupt 0 input, int0_n (FIGURE 19). When any bit in the INT0 Source register is ‘1’, an
interrupt has occurred and, assuming the interrupt is enabled, the 8051 int0_n input is asserted.
The bits in the INT0 Source register are cleared by a writing a “1” to the bit.
TABLE 93 - 8051 INT0 SOURCE REGISTER
n/a
HOST ADDRESS
0x7F00
8051 ADDRESS
VCC1
POWER
0x00
DEFAULT
HOST
TYPE
8051
TYPE
BIT
NAME
D7
-
D6
-
D5
-
D4
-
D3
-
D2
-
D1
-
D0
-
R/WC
R/WC
R/WC
R/WC
R/WC
R/WC
R/WC
R/WC
PS2_D
PS2_C
PS2_B/
PS2 P2
PS2_A/
PS2 P1
ACCESS
BUS 2
WK_EE4
WK_EE2
WK_EE3
168
SMSC PS/2 C & D Interrupts – D[7:6]
Access Bus 2 Interrupt – D3
INT0 Source register bit D7 is the SMSC PS/2
Channel D interrupt; INT0 Source register bit D6
is the SMSC PS/2 Channel C interrupt. These
interrupts are active when the PS2_SEL Control
bit D4 in Configuration Register 0 (0x7FF4) is
‘1.’
“1” Indicates an ACCESS.bus 2 interrupt is
active.
WK_EE[4:2]
ACCESS Bus 2 wake events can be generated.
AB_DAT ACCESS BUS 2 bit in Wake Sources
(Register 1.)
8051 INT0 Mask Register
When the SMSC PS/2 channels are active the
PS2_D interrupt is associated with the PS2CLK
and PS2DAT alternate functions of the GPIO20
and GPIO21 pins; PS2_C is associated with the
IMCLK and IMDATA pins.
Dual-Mode SMSC/DEVIL Interrupts – D[5:4]
The eight interrupts in the INT0 Source register
(TABLE 93) are enabled by bits of the same
name in the INT0 Mask register (TABLE 94).
INT0 Source register bits D5 and D4 are
multiplexed between the SMSC PS/2 Channels
A and B and the Devil Logic Ports P1 and P2.
When any bit in the INT0 Mask register is ‘0’,
the interrupt is enabled. When any bit in the
INT0 Mask register is ‘1, the interrupt is masked.
When masked interrupts are asserted, the
interrupt will be visible in the interrupt source
register but will not assert an interrupt to the
8051.
When the PS2_SEL Control bit D4 in
Configuration Register 0 (0x7FF4) is ‘1,’ the
SMSC PS/2 Interrupt Channels A and B are
selected; when PS2_SEL = ‘0,’ the Devil Logic
Ports P1 and P2 are selected.
The bits in the INT0 Mask register are
read/write. The INT0 interrupts are enabled by
default.
When the SMSC PS/2 channels are active the
PS2_B interrupt is associated with the KCLK
and KDAT pins; PS2_A is associated with the
EMCLK and EMDATA pins.
169
8051 INT0 MASK REGISTER
TABLE 94 - 8051 INT0 MASK REGISTER
n/a
HOST ADDRESS
0x7F01
8051 ADDRESS
VCC1
POWER
0x00
DEFAULT
HOST
TYPE
8051
TYPE
BIT
NAME
D7
-
D6
-
D5
-
D4
-
D3
-
D2
-
D1
-
D0
-
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
PS2_D
PS2_C
PS2_B/
PS2 P2
PS2_A/
PS2 P1
ACCESS
BUS 2
WK_EE4
WK_EE2
WK_EE3
8051 INT1 Source Register
The eight interrupts in the INT1 Source register (TABLE 95) are logically ‘OR’ed to drive the 8051
external interrupt 1 input, int1_n (FIGURE 19).
When any bit in the INT1 Source register is ‘1’, an interrupt has occurred and, assuming the interrupt
is enabled, the 8051 int1_n input is asserted.
Bits D0 and D2 – D6 in the INT1 Source register are cleared by a writing a “1” to the bit.
TABLE 95 - 8051 INT1 SOURCE REGISTER
N/a
HOST ADDRESS
0x7F02
8051 ADDRESS
VCC1
POWER
0x00
DEFAULT
HOST
TYPE
8051
TYPE
BIT
NAME
D7
-
D6
-
D5
-
D4
-
D3
-
D2
-
D1
-
D0
-
R
R/WC
R/WC
R/WC
R/WC
R/WC
R
R/WC
IBF1
KBD
SCAN
EC_IBF2
EC_OBF3
GPIO3
ACCESS
BUS 1
SYS-MBOX4
ANY
WUP
170
ACCESS BUS 1 [D2]
When ACCESS BUS 1 bit is equal to 1 an Access Bus IRQ is active.
IBF [D7]
IBF interrupt bit D7 is set when the host writes to the KBD Data/Command Write register and is
cleared when the 8051 reads from that register.
EC_IBF [D5]
EC_IBF interrupt bit D5 is set when the host writes to the EC Command or Data port (see IBF Bit – D1
on page 88).
EC_OBF [D4]
EC_OBF interrupt bit D4 is asserted when the OBF bit in the EC Status register has been cleared (see
OBF Bit – D0 on page 88).
SYS-MBOX [D1]
SYS-MBOX interrupt bit D1 is set when the host writes to mailbox register 0. The bit is cleared when
mailbox register 0 is read (see The SYSTEM/8051 Interface Registers on page 252).
8051 INT1 Mask Register
The eight interrupts in the INT1 Source register (TABLE 95) are enabled by bits of the same name in
the INT1 Mask register (TABLE 96).
When any bit in the INT1 Mask register is ‘0’, the interrupt is enabled. When any bit in the INT1 Mask
register is ‘1’, the interrupt is masked. When masked interrupts are asserted, the interrupt will be
visible in the interrupt source register but will not assert an interrupt to the 8051.
The bits in the INT1 Mask register are read/write. The INT1 interrupts are enabled by default.
8051 INT1 MASK REGISTER
TABLE 96 - 8051 INT1 MASK REGISTER
n/a
HOST ADDRESS
0x7F03
8051 ADDRESS
VCC1
POWER
0x00
DEFAULT
HOST
TYPE
8051
TYPE
BIT
NAME
D7
-
D6
-
D5
-
D4
-
D3
-
D2
-
D1
-
D0
-
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
IBF
KBD SCAN
EC_IBF
EC_OBF
GPIO3
ACCESS
BUS 1
SYS-MBOX
ANY
WUP
171
8051 WAKEUP SOURCE REGISTERS
TABLE 97 - WAKEUP SOURCE REGISTER 1
N/A
HOST ADDRESS
0x7F2A
8051 ADDRESS
VCC1
POWER
0x00
DEFAULT
HOST
TYPE
8051 R/W
BIT NAME
AND
DESCRIPTION
D7
-
D6
-
D5
-
D4
-
D3
-
D2
-
D1
-
R/WC
R/WC
R/WC
R/WC
1=
PM1
CTL 2
1=
PM1
EN 2
1=
PM1
STS 2
1=
AB_DAT
ACCESS.
BUS
interrupt
asserted
D0
-
R/WC
R/WC
R/WC
R/WC
1=
AB_DAT
ACCESS.
BUS 2
interrupt
asserted
1 = IRRX
(Note 3)
1=
WK_
EE1
change
d
(Note
1)
1 = RTC_
ALRM
asserted
(Note 2)
Res = Reserved. Read returns 0, writes are ignored.
Note 1: Input is going from low to high or from high to low (read the GPIO register to find out the
value of pin)
AB_DAT1 and AB_DAT2 -- When ACCESS.BUS=1, a start condition or other event was detected on
the ACCESS.BUS bus. When ACCESS.BUS 2=1, a start condition or other event was detected on the
ACCESS.BUS 2 bus
PM1_STS2, PM1 EN2, PM1CTL2 interrupts: These are set when the corresponding PM1 register has
been written by the host.
Note 2: The RTC_ALRM Wake-up is an internally generated Low-to-High edge, produced when the
RTC time updates to match the Time Of Day (TOD) alarm setting. This edge will set bit D0 of Wakeup Source 1 Register. Bit D0 will remain set and will only be reset on a read of Wake-up Source 1
Register. If the Wake-up source register is read before the clock has updated (i.e., RTC still equals
the TOD alarm) bit D0 is reset and stays reset until the next occurrence of a RTC_ALRM Wake-up
event.
Note 3: Wake event is asserted when only when both VCC2 is active and IRRX input changes from
high to low.
Note 4: The interrupt source bits in this register are cleared by a writing a “1” to the bit.
172
TABLE 98 - WAKEUP SOURCE REGISTER 2
N/A
HOST ADDRESS
0x7F2B
8051 ADDRESS
VCC1
POWER
0x00
DEFAULT
HOST
TYPE
8051 R/W
BIT NAME
AND DESCRIPTION
D7
-
D6
-
D5
-
D4
-
D3
-
D2
-
D1
-
D0
-
R
R/WC
1=
UART
_RI1
assert
ed
R/WC
1=
WK_
EE4
R/WC
1=
WK_
EE2
transiti
on
(both
edges)
R/WC
1=
WK_
EE3
transiti
on
(both
edges)
R/WC
1=
HTIM
ER
timeout
s
R/WC
1=
WK_
ANYKEY
is
asserted
R/WC
1=
nGPWK
UP is
asserted
RES
HTIMER Interrupt When HTIMER=1, the hibernation timer counted down to zero.
Note 1: Anykey Wake-up (WK_ANYKE– -- When unmasked, the WK_ANYKEY will wake the 8051
from the “SLEEP” state when any of the Keyboard Scan In (KSI) pins goes low. The Boolean equation
below defines the WK_ANYKEY function.
WK_ANYKEY = !(KSI0 & KSI1 & KSI2 & KSI3 & KSI4 & KSI5 & KSI6 & KSI7)
NOTE: The interrupt source bits in this register are cleared by a writing a “1” to the bit.
TABLE 99 - WAKEUP SOURCE REGISTER 4
N/A
HOST ADDRESS
0x7F59
8051 ADDRESS
VCC1
POWER
0x00
DEFAULT
HOST TYPE
8051 R/W
BIT NAME
AND DESCRIPTION
D7
R/WC
1=
WK_
SE07
assert
ed
D6
R/WC
1=
WK_
SE06
assert
ed
D5
R/WC
1=
WK_
SE05
assert
ed
D4
R/WC
1=
WK_
SE04
assert
ed
D3
R/WC
1=
WK_
SE03
assert
ed
D2
R/WC
1=
WK_
SE02
assert
ed
D1
R/WC
1=
WK_
SE01
assert
ed
D0
R/WC
1=
WK_
SE00
assert
ed
Note : The bits in this register are cleared on a WRITE OF “1” TO THE CORRESPONDING BIT.
173
TABLE 100 - WAKEUP SOURCE REGISTER 5
Host address
N/A
0x7F5E
8051 ADDRESS
VCC1
POWER
0x00
DEFAULT
HOST TYPE
8051 R/W
BIT NAME AND
DESCRIPTION
D7
R/WC
1=
WK_
SE17
assert
ed
D6
R/WC
1=
WK_
SE16
assert
ed
D5
R/WC
1=
WK_
SE15
assert
ed
D4
R/WC
1=
WK_
SE14
assert
ed
D3
R/WC
1=
WK_
SE13
assert
ed
D2
R/WC
1=
WK_
SE12
assert
ed
D1
R/WC
1=
WK_
SE11
assert
ed
D0
R/WC
1=
WK_
SE10
assert
ed
Note : the bits in this register are cleared on a WRITE OF “1” TO THE CORRESPONDING BIT.
TABLE 101 - WAKEUP SOURCE REGISTER 6
Host address
N/A
0x7F63
8051 ADDRESS
VCC1
POWER
0x00
DEFAULT
HOST TYPE
8051 R/W
BIT NAME AND
DESCRIPTION
D7
R/WC
1=
WK_
SE27
assert
ed
D6
R/WC
1=
WK_
SE26
assert
ed
D5
R/WC
1=
WK_
SE25
assert
ed
D4
R/WC
1=
WK_
SE24
assert
ed
D3
R/WC
1=
WK_
SE23
assert
ed
D2
R/WC
1=
WK_
SE22
assert
ed
D1
R/WC
1=
WK_
SE21
assert
ed
D0
R/WC
1=
WK_
SE20
assert
ed
Note : The bits in this register are cleared on a WRITE OF “1” TO THE CORRESPONDING BIT.
174
TABLE 102 - WAKEUP MASK REGISTER 1
N/A
HOST ADDRESS
0x7F2C
8051 ADDRESS
VCC1
POWER
0x00
DEFAULT
HOST TYPE
8051 R/W
BIT NAME AND
DESCRIPTION
D7
R/W
D6
R/W
D5
R/W
D4
R/W
D3
R/W
D2
R/W
D1
R/W
D0
R/W
1=
Mask
PM1
CTL2
1=
Mask
PM1
EN2
1=
mask
PM1
STS2
1=
mask
AB_D
ATA
ACCE
SS
BUS 1
1=
mask
AB_D
ATA
ACCE
SS.
BUS 2
1=
MASK
IRRX
1=Ma
sk
WK_
EE1
1 = Mask
RTC_
ALARM
TABLE 103 - WAKEUP MASK REGISTER 2
Host address
N/A
0x7F2D
8051 ADDRESS
VCC1
POWER
0x00
DEFAULT
HOST TYPE
8051 R/W
BIT NAME AND
DESCRIPTION
D7
R
RE
SE
RV
ED
D6
R/W
D5
R/W
D4
R/W
D3
R/W
D2
R/W
D1
R/W
D0
R/W
1=mask
UART_
RI1
1=Mask
WK_EE
4
1=
Mask
WK_
EE2
1=
Mask
WK_
EE3
1=
Mask
HTIM
ER
1=
Mask
WK_
ANY
KEY
1= mask
nGPWK
UP
175
TABLE 104 - WAKEUP MASK REGISTER 4
N/A
HOST ADDRESS
0x7F5A
8051 ADDRESS
VCC1
POWER
0x00
DEFAULT
HOST TYPE
8051 R/W
BIT NAME
AND
DESCRIPTION
D7
R/W
1=
mask
WK_
SE07
D6
R/W
1=
mask
WK_
SE06
D5
R/W
1=
mask
WK_
SE05
D4
R/W
1=
mask
WK_
SE04
D3
R/W
1=
mask
WK_
SE03
D2
R/W
1=
mask
WK_
SE02
D1
R/W
1=
mask
WK_
SE01
D0
R/W
1=
mask
WK_
SE00
D1
R/W
1=
mask
WK_
SE11
D0
R/W
1=
mask
WK_
SE10
TABLE 105 - WAKEUP MASK REGISTER 5
N/A
HOST ADDRESS
0x7F5F
8051 ADDRESS
VCC1
POWER
0x00
DEFAULT
HOST TYPE
8051 R/W
BIT NAME
AND
DESCRIPTION
D7
R/W
1=
mask
WK_S
E17
D6
R/W
1=
mask
WK_
SE16
D5
R/W
1=
mask
WK_
SE15
176
D4
R/W
1=
mask
WK_
SE14
D3
R/W
1=
mask
WK_
SE13
D2
R/W
1=
mask
WK_
SE12
TABLE 106 - WAKEUP MASK REGISTER 6
N/A
HOST ADDRESS
0x7F66
8051 ADDRESS
VCC1
POWER
0x00
DEFAULT
HOST TYPE
8051 R/W
BIT NAME AND
DESCRIPTION
D7
D6
D5
D4
R/W
1=
mask
WK_
SE27
R/W
1=
mask
WK_
SE26
R/W
1=
mask
WK_
SE25
R/W
1=
mask
WK_
SE24
D3
R/W
1=
mask
WK_
SE23
D2
R/W
1=
mask
WK_
SE22
D1
R/W
1=
mask
WK_S
E21
D0
R/W
1=
mask
WK_SE
20
8051 HIBERNATION TIMER REGISTER
TABLE 107 - HTIMER REGISTER
Host
N/A
8051
0x7FF3
Power
VCC1
Default
0x00
Hibernation Timer - This 8 bit binary count-down timer can be programmed for from 30 seconds to
128 minutes in 30 second increments. When it expires (reaches “0”), it stops (remains at “0”) and
causes a hardware event that will wake up the 8051. This timer is clocked by the 32 KHz clock and is
powered by VCC1. Writing a non-zero value to this register starts the counter from that value.
8051 EDGE SELECT REGISTERS
Selectable Edge interrupts
Selectable interrupts SE00-SE07 are on External INT2.
Selectable interrupts SE10-SE17 are on External INT3.
Selectable interrupts SE20-SE27 are on External INT4.
177
TABLE 108 - EDGE SELECT 4A
N/A
HOST ADDRESS
0x7F57
8051 ADDRESS
VCC1
POWER
0x00
DEFAULT
HOST TYPE
8051 R/W
BIT NAME
AND
DESCRIPTION
D7:6
R/W
D5:4
R/W
D3:2
R/W
D1:0
-
SE03 Select
SE02 Select
SE01 Select
SE00 Select
TABLE 109 - EDGE SELECTION
D7:6
D5:4
D3:2
D1:0
Edge Selection Table
EDGE High to low
00
Edge Low to High
01
Either Edge
10
Reserved
11
TABLE 110 - EDGE SELECT 4B
N/A
HOST ADDRESS
0x7F58
8051ADDRESS
VCC1
POWER
0x00
DEFAULT
HOST TYPE
8051 R/W
BIT NAME AND
DESCRIPTION
D7:6
R/W
D5:4
R/W
D3:2
R/W
D1:0
-
SE07 Select
SE06 Select
SE05 Select
SE04 Select
Refer to TABLE 109 - EDGE SELECTION for the edge
selection table
TABLE 111 - EDGE SELECT 5A
N/A
HOST ADDRESS
0x7F5C
8051 ADDRESS
VCC1
POWER
0x00
DEFAULT
178
HOST TYPE
8051 R/W
BIT NAME AND
DESCRIPTION
D7:6
R/W
D5:4
R/W
D3:2
R/W
D1:0
-
SE13 Select
SE12 Select
SE11 Select
SE10 Select
Refer to TABLE 109 for the edge selection table.
TABLE 112 - EDGE SELECT 5B
N/A
HOST ADDRESS
0x7F5D
8051 ADDRESS
VCC1
POWER
0x00
DEFAULT
HOST TYPE
8051 R/W
BIT NAME AND
DESCRIPTION
D7:6
R/W
D5:4
R/W
D3:2
R/W
D1:0
-
SE17 Select
SE16 Select
SE15 Select
SE14 Select
Refer to TABLE 109 for the edge selection table.
TABLE 113 - EDGE SELECT 6A
N/A
HOST ADDRESS
0x7F61
8051 ADDRESS
VCC1
POWER
0x00
DEFAULT
HOST TYPE
8051 R/W
BIT NAME AND
DESCRIPTION
D7:6
R/W
D5:4
R/W
D3:2
R/W
D1:0
-
SE23 Select
SE22 Select
SE21 Select
SE20 Select
Refer to TABLE 109 for the edge selection table.
179
TABLE 114 - EDGE SELECT 6B
N/A
HOST ADDRESS
0x7F62
8051 ADDRESS
VCC1
POWER
0x00
DEFAULT
HOST TYPE
8051 R/W
BIT NAME AND
DESCRIPTION
D7:6
R/W
D5:4
R/W
D3:2
R/W
D1:0
-
SE27 Select
SE26 Select
SE25 Select
SE24 Select
Refer to TABLE 109 for the edge selection table.
POWER FAIL IRQ
The PWRGD_INT register (TABLE 115) contains the Power Good Interrupt (PGI) bit, D0. When PGI
= ‘1’, the (VCC2) PWRGD input has been deasserted; otherwise, PGI = ‘0’. NOTE: PGI is not
asserted when PWRGD is asserted.
The PGI bit is the source for the high-performance 8051 Power Fail Interrupt (pfi) input (FIGURE 19).
The VCC2 power fail detect function is implemented as described in 8051 RING OSCILLATOR FAILSAFE CONTROLS on page 147.
The PGI bit is readable and is cleared by writing a ‘1’ to D0 in the PWRGD_INT register.
TABLE 115 - POWER GOOD INTERRUPT REGISTER (PWRGD_INT)
HOST ADDRESS 8051 ADDRESS
POWER PLANE
DEFAULT
0x7F84
VCC1
0x00
HOST TYPE
8051 TYPE
BIT NAME
D7
R
D6
R
D5
-
D4
-
R
R
RESERVED
180
D3
R
D2
R
D1
R
D0
R/WC
PGI
8051 External Serial IRQ Generation
The 8051 can assert an interrupt on the serial IRQ stream to support software-generated SCI, SMI, or
PME events (FIGURE 21).
FIGURE 21
NOTE: The 8051 External Serial IRQ is generated and cleared by software.
The 8051 External Serial IRQ interface is controlled by the 8051_SIRQ register (TABLE 116).
Serial
IRQ
8051_IRQ SELECT
8051_IRQ
IRQ Mapping
logic
FIGURE 21 - 8051 EXTERNAL SERIAL IRQ BLOCK DIAGRAM
TABLE 116 - 8051_SIRQ REGISTER
HOST ADDRESS 8051 ADDRESS
POWER PLANE
0x7F52
VCC1
HOST TYPE
8051 TYPE
BIT NAME
D7
D6
D5
R/W
R/W
R/W
8051_IRQ SELECT
D4
R/W
D3
R/W
8051_IRQ
ENABLE
D2
R/W
8051_IRQ
DEFAULT
0x00
D1 D0
R
R
RESERVED
8051_IRQ SELECT
Four bits that selects which IRQ is utilized when an interrupt occurs. See TABLE 117 - 8051 IRQ
MAPPING CONTROL BITS
8051_IRQ ENABLE
This bit must be set to one in order for an interrupt to occur.
181
8051 IRQ
This bit must set to one in order for the 8051 to assert the mapped interrupt request corresponding to
the 8051_IRQ SELECT bits. The defualt state for a disabled IRQ is asserted.
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
TABLE 117 - 8051 IRQ MAPPING CONTROL BITS
8051_IRQ
8051_IRQ
ENABLE
SELECT
DESCRIPTION
XXXX
DISABLED
0000
NO INTERRUPT
0001
MAP TO IRQ1
0010
MAP TO IRQ2
0011
MAP TO IRQ3
0100
MAP TO IRQ4
0101
MAP TO IRQ5
0110
MAP TO IRQ6
0111
MAP TO IRQ7
1000
MAP TO IRQ8
1001
MAP TO IRQ9
1010
MAP TO IRQ10
1011
MAP TO IRQ11
1100
MAP TO IRQ12
1101
MAP TO IRQ13
1110
MAP TO IRQ14
1111
MAP TO IRQ15
182
WATCH DOG TIMER
D1) is set by 8051 firmware. The WDT may be
disabled under software control through a
specific sequence. Software can clear the SDT
enable bit by:
Setting the WLE-WDT Load enable bit in the
WDT Control/Status Register.
Writing 00h to the WDT Timer Register (this
causes the WDT Enable and the WLE_WDT
Load Enable bits to each reset to 0).
WDT OPERATION
When enabled, the Watch Dog Timer (WDT)
circuit will generate a system reset if the user
program fails to reload the watchdog timer
(WDT) within a specified length of time known
as the ‘watchdog interval’.
The WDT consists of an 8-bit timer (WDT) with
a 9-bit prescaler. The prescaler is fed with 32
kHz which always runs, even if the 8051 is in
SLEEP state.
The 8 bit WDT timer is
decremented every (1/32KHz) *512 seconds or
16.0 ms.
Thus, the watchdog interval is
programmable between 16ms and 4.08 seconds
on 16ms intervals.
Once the WDT has been activated, this
sequence must be executed in order to disable
watchdog operation via software control. Note:
Since a VCC1 POR will reset the WDT enable
bit, the WDT must be re-enabled after each
occurrence.
WDT RESET MECHANISM
WDT ACTION
The watchdog timer (WDT) must be reloaded
within periods that are shorter than the
programmed watchdog interval; otherwise the
WDT will underflow and a VCC1 POR will be
generated. It is the responsibility of the user
program to continually execute sections of code
which reload the 8 bit timer (WDT).
If the 8 bit timer (WDT) underflows, a VCC1
POR is generated
8051 in Idle Mode - WDT will be active if
enabled. When the WDT timer underflows in
idle mode, the 8051 will be reset. It is up to the
firmware engineer to design code that uses a
timer to generate an interrupt that will exit idle
mode and re-initialize the WDT timer and then
put the 8051 back into idle mode.
The WDT is reloaded in two stages in order to
prevent erroneous software from reloading the
watchdog. First WDT CONTROL bit D0 (WLEWDT Load Enable) must be set. Then the WDT
may be loaded. When the WDT is loaded WLE
is automatically reset. WDT can not be loaded
when WLE is reset. Since the WDT timer is a
down counter, a reload value of 01h results in
the minimum WDT interval (16ms) and a reload
value of 0FFh results in the maximum WDT
interval (4.08 seconds). Loading 00h into the
WDT disables the WDT and clears the WDT
Enable bit. Note, the 9 bit prescaler is initialized
whenever the WDT timer is loaded.
8051 in Sleep Mode - If enabled, the WDT is
active since it is running off of the 32 KHz clock.
Therefore, if the WDT is enabled the 8051
should never remain in the SLEEP state for
more than 4 seconds.
WDT ACTIVATION
Upon VCC1 POR the Watch Dog Timer powers
up inactive. The Watch Dog Timer is activated
when the WDT enable bit (WDT CONTROL bit
183
WDT MEMORY MAPPED REGISTERS
TABLE 118 - WDT
N/A
HOST ADDRESS
0x 7F38
8051 ADDRESS
VCC1
POWER
0xFF
DEFAULT
8051 R/W
SYSTEM R/W
BIT DEF
D7
R/W
N/A
WDT
Timer
D6
R/W
N/A
WDT
Timer
D5
R/W
N/A
WDT
Timer
D4
R/W
N/A
WDT
Timer
D3
R/W
N/A
WDT
Timer
D2
R/W
N/A
WDT
Timer
D1
R/W
N/A
WDT
Timer
D0
R/W
N/A
WDT
Timer
TABLE 119 - WDT CONTROL/STATUS
N/A
HOST ADDRESS
0x 7F37
8051 ADDRESS
VCC1
POWER
0x00
DEFAULT
8051 R/W
SYSTEM R/W
BIT DEF
D7-D2
R
N/A
Reserved
D1
R/W
N/A
WDT Enable
D0
R/W
N/A
WLE-WDT Load Enable
WLE
Watchdog Load Enable bit must be set to enable writing to the WDT Timer register. This bit is
automatically reset when the 8051 writes to the WDT register. If this bit is reset, writes to the WDT
register are ignored.
WDT Enable
The WDT enable bit must be set by 8051 firmware to enable or start the Watch Dog Timer. A VCC1
POR or the above described software sequence will reset this bit.
184
SHARED FLASH INTERFACE
system in blocks of 64KB or from the 8051 in
blocks of 32KB. The procedure to access the
FLASH memory is described in the Host Flash
Access section.
A 256KB Flash Device (i.e., 28F004) is
recommended to store the program code for the
8051 (Keyboard BIOS+) and the system BIOS.
The FLASH memory can be accessed from the
FLASH INTERFACE DIAGRAM
not asserted and the 8051 STP_CLK bit-0 is set.
Please refer to the timing section for details on
this interface.
Access to the Flash Memory is multiplexed
inside of the FDC37N972. The host CPU only
has access to the Flash when nRESET_OUT is
HOST CPU
I
S
A
R
O
M
B
U
S
n
C
S
AD[7:0]
LATCH
ALE
ADDR[17:8]
FDC37N972
FLASH
512K x 8
nKBWR
nKBRD
nCE
FIGURE 22 - FLASH INTERFACE DIAGRAM
185
SYSTEM MEMORY MAP
64K
Host
Interface
512K
FLASH
ROM
FFFF
16x
32K Blocks
0
64K
8051
External
RAM
64K
8051
ROM
FFFF
FFFF
8000
Internal
Registers
Invalid
7FF
0
8000
0
FIGURE 23 - SYSTEM FLASH ACCESS MAP (ALT BONDOUT)
186
64K
Host
Interface
512K
FLASH
ROM
FFFF
16x
32K Blocks
0
64K
8051
External
RAM
64K
8051
ROM
FFFF
FFFF
Same as
0-7FFF
8000
8000
Internal
Registers
0
0
FIGURE 24 - SYSTEM FLASH ACCESS MAP (SMSC BONDOUT)
KEYBOARD BIOS (KMEM)
The 8051 uses this register to access the Flash
ROM in a 32K window. The 8051 is only barred
from accessing the Flash when 8051STP_CLK
bit D0 =1 and nRESET_OUT= high or
deasserted. Bit D3 is added to the KMEM
Register to accommodate the high-order Flash
ROM address bit FA18 (TABLE 120). The Flash
ROM Memory Ranges are decoded as shown in
TABLE 121.
187
HOST INDEX
-
HOST
TYPE
8051 TYPE
BIT
NAME
D7
-
D6
-
R
R
RESERVED
KMEM
17
0
0
0
0
1
1
1
1
TABLE 120 - KMEM REGISTER
8051 ADDRESS
POWER PLANE
0x7F29
VCC1
DEFAULT
0x00
D5
-
D4
-
D3
-
D2
-
D1
-
D0
-
R
R
R/W
A18
R/W
A17
R/W
A16
R/W
A15
16
0
0
1
1
0
0
1
1
15
0
1
0
1
0
1
0
1
Flash Memory Range
000- 7FFF
8000- FFFF
10000-17FFF
18000-1FFFF
20000-27FFF
28000-2FFFF
30000-37FFF
38000-3FFFF
TABLE 121 - FLASH ROM ADDRESS ENCODING
KMEM REGISTER ADDRESS
DECODED FLASH ROM MEMORY
RANGE SELECT BITS
RANGE
D3
D2
D1
D0
0
0
0
0
00000 – 07FFF
0
0
0
1
08000 – 0FFFF
0
0
1
0
10000 – 17FFF
0
0
1
1
18000 – 1FFFF
0
1
0
0
20000 – 27FFF
0
1
0
1
28000 – 2FFFF
0
1
1
0
30000 – 37FFF
0
1
1
1
38000 – 3FFFF
1
0
0
0
40000 – 47FFF
1
0
0
1
48000 – 4FFFF
1
0
1
0
50000 – 57FFF
1
0
1
1
58000 – 5FFFF
1
1
0
0
60000 – 67FFF
1
1
0
1
68000 – 6FFFF
1
1
1
0
70000 – 77FFF
1
1
1
1
78000 – 7FFFF
188
SYSTEM BIOS (HMEM)
Host
8051
Power
Default
HMEM REGISTER
MBX 0x95
N/A
VCC1
VCC1 POR = 0x03
VCC2 POR = 0x03
The system uses this register to select a 64K window for access from the 256K Flash ROM. The host
may access the Flash when RESET_OUT pin is de-asserted and 8051STP_CLK bit D0 = 1.
Bit D2 is added to the HMEM Register to accommodate the high-order Flash ROM address bit FA18
(TABLE 122).
TABLE 122 - HMEM REGISTER
8051 ADDRESS
POWER PLANE
VCC1
HOST INDEX
MBX95h
HOST TYPE
8051 TYPE
BIT NAME
D7
R
RESERVED
D6
R
-
D5
R
-
D4
R
-
D3
R
-
D2
R/W
A18
DEFAULT
0x07 (VCC1 POR)
0x07 (VCC2 POR)
D1
R/W
A17
D0
R/W
A16
are supplied by SA[15:0], address bits A[17:16]
are supplied by configuration register HMEM.
For Flash access, these address lines and bits
are qualified (selected) by 8051STP_CLK=1,
and
the
nRESET_OUT
pin
=
high
(nRESET_OUT is driven by the 8051). The 8051
STP_CLK is set to “1” and HMEM is set to 03h
(effectively resulting in A[17:16] initializing as
"11")
whenever
the
8051
clears
the
IRESET_OUT bit from “1” to “0”. This allows
the system to execute from the upper 64K of the
Flash memory at boot time. To access the
other portions of the Flash memory, the system
software must first change the values of
HMEM[1:0] register to control address lines
A[17:16]. The access to the Flash memory uses
nFWR for a write and nFRD for a read.
HOST FLASH ACCESS
The FDC37N972 has a special shared Flash
ROM interface. The 8051 can be stopped to
allow the Host CPU to access the flash ROM
after a special handshake sequence is followed.
HOST INITIATED FLASH ACCESS
To access the FLASH memory, the 8051 must
first be placed into idle mode, and then the 8051
clock must be stopped. Host flash reads and
writes occur when the nROMCS pin is asserted
along with nMEMRD or nMEMWR. The register
bit “8051_STPCLK” needs to be set by the host
to make the 8051 clock stop. The 8051 clock is
only stopped when 8051STP_CLK=1 and when
nRESET_OUT pin = high. Address bits A[15:0]
189
System fully powered
up and running.
RESET_OUT=low, 8051STP_CLK=0.
8051 owns Flash interface,
running keyboard code.
The host, wishing to access
Flash memory, issues a userdefined command to put the
8051into idle mode.
8051goes into idle mode
The host sets
8051STP_CLK = 1
combined with
RESET_OUT = low; this
causes 8051 clock to stop.
Host now owns Flash
interface.
When done using Flash,
the host resets
8051STP_CLK bit
Note: In order to leave idle mode the 8051 must receive an interrupt;
typically a software timer interupt will be used.
N
8051 Timer
IRQ ?
(Note)
Y
8051 wakes up from idle
mode and starts executing
from where it left off.
FIGURE 25 - DYNAMIC SHARING OF FLASH INTERFACE BETWEEN HOST AND 8051
190
TABLE 123 - 8051 STP_CLK REGISTER
Host
MBX 0x94
8051
N/A
Power
VCC1
Default
0x00
D7
IDLE
D6
HOST_
FLASH
D5-D1
Reserved, set to “0”
D0
0=8051 Clock can run
1=8051 Clock stop
Note:
When bit D0=1 the 8051’s clock is not
stopped unless the nRESET_OUT pin is also
de-asserted at which point the host has access
to the Flash Memory.
Note:
Only bit D0 is R/W, bits[7:1] are Read
only.
HOST BOOT BLOCK SELECT
IDLE : 0 = 8051 not in idle mode
1= 8051 in idle mode
The 64K HOST BOOT bit and the 16K HOST
BOOT bit, D1 and D0 respectively in the Flash
Configuration register (TABLE 127) determine
the host boot block options (TABLE 124). For
more information regarding the 64K HOST
BOOT bit and the 16K HOST BOOT bit, see
FLASH CONFIGURATION REGISTER on page
197.
The FDC37N972 can optionally support 16k and
64k boot block Flash ROMs and can boot out of
the same Flash ROM address space as the
8051.
HOST_FLASH: 0 = Host does not have
access to Flash, in use by 8051
1 = Host has access to Flash
The host boot block options described in TABLE
124 apply to host flash addresses, only.
TABLE 124 - HOST BOOT BLOCK OPTION
FLASH
CONFIGURATION
REGISTER
MODE
DESCRIPTION
D1
D0
0
0
NORMAL
Host Flash Address Bits 18 – 16 are
under control of the HMEM register
(default).
0
1
16K MODE
Host Flash Address Bits 18 – 14 are
forced to “0”.
1
0
64K MODE
Host Flash Address Bits 18 – 16 are
forced to “0”.
1
1
UNDEFINED
DO NOT USE.
191
PROGRAMMABLE FLASH CHIP SELECT
Flash ROM Chip Select Option. The effects of
the ALT CHIP SELECT bit are shown in TABLE
125. For more information regarding the ALT
CHIP
SELECT
bit,
see
FLASH
CONFIGURATION REGISTER on page 197.
The FDC37N972 Flash ROM Chip Select output
nFCS can be optionally deasserted “1” when the
8051 is sleeping with control of the Flash, or
asserted and deasserted according to the Flash
ROM read strobe nFRD.
The ALT CHIP SELECT bit D2 in the Flash
Configuration register (TABLE 127) selects the
TABLE 125 - FLASH ROM CHIP SELECT OPTIONS
FLASH
CONFIG.
REGISTER
MODE
DESCRIPTION
D2
0
NORMAL
nFCS deasserted when 8051 is
sleeping with control of the Flash
(default).
1
READ
nFCS follows nFRD.
FLASH ROM WRITE REDIRECTION
The Flash ROM write control nFWR can be
optionally redirected to an alternate function of
the OUT3 pin to support functions like an I/O
port expander.
effects of the ALT WRITE SELECT bit are
shown in TABLE 126 - FLASH ROM WRITE
REDIRECTION OPTIONS.
For more information regarding the ALT WRITE
SELECT bit, see FLASH CONFIGURATION
REGISTER on page 197.
The ALT WRITE SELECT bit D3 in the Flash
Configuration register (TABLE 127) selects the
Flash ROM Write Redirection Option. The
192
TABLE 126 - FLASH ROM WRITE REDIRECTION OPTIONS
FLASH
CONFIG.
REGISTER
D3
0
1
MODE
NORMAL
WRITE
REDIRECTION
DESCRIPTION
The OUT3 pin is configured as a General Purpose
Output and Flash ROM “writes” appear on the nFWR
pin (default).
The OUT3 pin is configured as an inverted Flash
ROM “write” strobe, FWR. NOTE: Flash ROM
“writes” do not appear on the nFWR pin but appear
inverted on the FWR pin.
FLASH CONFIGURATION REGISTER
OVERVIEW
The Flash Configuration register (TABLE 127 is used to select the various options described in this
document.)
The FCR is a VCC1 register. The bits in the FCR are R/W and cleared by VCC1 POR. Detailed
descriptions of these bits follow, below.
TABLE 127 - FLASH CONFIGURATION REGISTER
HOST ADDRESS
0x7FFC
8051 ADDRESS
VCC1
POWER
0x00
DEFAULT
HOST
TYPE
8051
TYPE
BIT
NAME
D7
-
D6
-
D5
-
D4
-
D3
-
D2
-
D1
-
D0
-
R
R
R
R
R/W
R/W
R/W
R/W
ALT
WRITE
SELECT
ALT
CHIP
SELECT
64K
HOST
BOOT1
16K
HOST
BOOT1
RESERVED
NOTE1 Bits D0 and D1 are cleared by VCC1_POR or host writes to the HMEM register.
193
The 16K HOST BOOT bit is used to select the
16K MODE Host Boot Block option shown in
TABLE 124.
See HOST BOOT BLOCK
SELECT, above, for a description of this
function.
ALT WRITE SELECT Bit, D3
The ALT WRITE SELECT bit is used to select
Flash ROM Write Redirection Option shown in
TABLE 126 - FLASH ROM WRITE
REDIRECTION OPTIONS.
NOTE: The 64K HOST BOOT Bit D1 must not
be set to a “1” when the 16K HOST BOOT bit is
“1”.
See FLASH ROM WRITE REDIRECTION,
above, for a description of this function. The
ALT WRITE SELECT bit is also used as the
OUT3 pin alternate function multiplex control
(TABLE 4). The 8051 can read and write the
ALT WRITE SELECT bit. The bit is “0” by
default and is cleared by VCC1_POR.
ALT CHIP SELECT Bit, D2
The 8051 can read and write the 16K HOST
BOOT bit. The 16K HOST BOOT bit is cleared
by VCC1_POR or host writes to the HMEM
register.
8051 SYSTEM POWER MANAGEMENT
The ALT CHIP SELECT bit selects the Flash
ROM Chip Select Option shown in TABLE 125.
See PROGRAMMABLE FLASH CHIP SELECT,
above, for a description of this function. The
8051 can read and write the ALT CHIP SELECT
bit. The bit is “0” by default and is cleared by
VCC1_POR.
64K HOST BOOT Bit, D1
The High-Performance 8051 core provides
support for two further power-saving modes,
available when inactive: Idle mode, typically
entered between keystrokes; and sleep mode,
entered upon command from the host. The
High Performance 8051 is wakeable from sleep
mode through a set of external and internal
events called Wake-Up events. The events are
listed in Table 128. When exiting the Sleep
mode, the High Performance 8051 will continue
executing code from where it left off when put
into sleep with no changes to the SFR and pins.
The 64K HOST BOOT bit is used to select the
64K MODE Host Boot Block option shown in
TABLE 124.
See HOST BOOT BLOCK
SELECT, above, for a description of this
function.
The FDC37N972 is fully static and will pickup
from where it left off in the event of a wake-up
event.
NOTE: The 16K HOST BOOT Bit D0 must not
be set to a “1” when the 64K HOST BOOT bit is
“1”.
The 8051 can read and write the 64K HOST
BOOT bit. The 64K HOST BOOT bit is cleared
by VCC1_POR or host writes to the HMEM
register.
16K HOST BOOT Bit, D0
194
Interrupt Timer and Serial Port functions. The
CPU status is preserved in its entirety: The
Stack Pointer, Program Counter, Program
Status Word, Accumulator, and all other
registers maintain their data. The port pins hold
the logical levels they had when Idle mode was
activated.
IDLE MODE
Entering IDLE mode:
Idle mode is initiated by an instruction that sets
the PCON.0 bit (SFR address 87H) in the
keyboard. In idle mode, the internal clock signal
to the keyboard CPU is gated off, but not to the
195
System fully powered
up and running.
RESET_OUT=low, 8051STP_CLK=0.
8051 owns Flash interface,
running keyboard code.
The host either issues a userdefined command to put the
8051into idle mode, or the
8051 code determines that
the 8051 should enter
Idle mode.
SLEEPFLAG = 0
PCON.0 = 1
8051 now in Idle mode,
8051 clock running.
FIGURE 26 - ENTERING IDLE MODE
196
8051 in Idle mode,
8051 clock running.
N
Unmasked
8051 IRQ ?
(Note)
Note: In order to leave idle mode the
8051 must receive an interrupt, typically
a software timer interrupt will be used.
Y
8051 leaves Idle mode,
executes IRQ service routine
code and executes an IRET
when done.
8051 returns to executing
from where it left off prior to
entering Idle mode.
FIGURE 27 - EXITING IDLE MODE DUE TO IRQ
clear the registers. The CPU will not resume
program execution from where it left off.
EXITING IDLE MODE
There are two ways to terminate Idle mode.
First, activation of any enabled interrupt will
cause the PCON.0 bit to be cleared by
hardware. The interrupt will be serviced and,
following the RETI, the CPU will resume
operation by executing the instruction following
the one that put the CPU into Idle mode.
SLEEP MODE
When the CPU enters sleep mode, all internal
clocks, including the core clocks, are turned off.
If an external crystal is used, the internal
oscillator is turned off. RAM contents are
preserved. Sleep mode is initiated by a user
defined 8051 command sequence.
The second way to terminate the Idle mode is
with a VCC1 POR. Note that a VCC1 POR will
197
RTC and 8051 are in powerdown (sleep) mode.
In Sleep mode the FDC37N972 consumes less
than 20µA, and all wake-up pins are still active.
Sleep mode sequence
To enter sleep mode, the 8051:
turns on the ring oscillator (KSTP_CLK[4] = 1)
switches the clock source (KSTP_CLK[5] = 0)
turns off the clock chip (or the whole system
power, VCC2) masks all interrupts except for
INT5_h
sets SLEEPFLAG = 1
sets PCON.0 = 1
The ring oscillator will be automatically turned
off
The 8051 goes into Sleep mode.
When the 8051 is in sleep mode, all of the
clocks are stopped and the 8051 is waiting for
an unmasked wake-up event. When the wakeup event occurs, the ring oscillator is started the
8051 starts executing from where it stopped in
the sleep Mode Sequence. Once running, the
8051 can access all of the registers that are on
VCC1 and if VCC2 is at 3.3V it can access all of
the registers on VCC2. The 8051 running from
the ring oscillator (internal) clock source switch
to an external clock sourceand then turn off the
ring oscillator (internal) clock source.
In sleep mode, the FDC, UART and parallel port
are powered off if VCC2 is removed, but the
198
System fully powered
up and running.
RESET_OUT= low, 8051STP_CLK= 0.
8051 owns Flash interface,
running keyboard code.
The host either issues a userdefined command to put the
8051into sleep mode, or
the 8051 code determines
that the 8051 should enter
sleep mode.
8051 switches its clock source
to the ring oscillator.
8051 masks all interrupts
except for T5INT.
The 8051 may/may not turn
off VCC2 to rest of system.
SLEEPFLAG = 1
PCON.0 = 1
Ring oscillator first gated off
from 8051, then turned off.
8051 now in
sleep mode,
8051 clock stopped.
FIGURE 28 - ENTERING SLEEP MODE
199
8051 in sleep mode.
RTC, 8051 and other VCC1
driven pins are active
Wake Up Events
RTC Alarm,
Power Button,
Ring Indicator,
etc.
N
Unmasked
Wake-up
Event ?
Y
int5_n generated.
Turn on ring oscillator.
SLEEPFLAG = 0.
Once stabilized, the ring
oscillator is gated through to
the 8051.
The 8051 is now running in
Idle mode and responds
immediately to T5INT.
8051 leaves Idle mode,
executes int5_n service
routine (disables int5_n) and
executes an IRET when
done.
8051 returns to executing
from where it left off prior to
entering sleep mode.
FIGURE 29 - EXITING SLEEP MODE
200
WAKE-UP EVENTS
There are two types of wake-up events that can
occur, internal (TABLE 128 – INTERNAL
SYSTEM WAKE-UP EVENTS) and external
(TABLE 129). Wake-up events on General
Purpose Pins can be either edge or selectable
edges. Refer to table TABLE 109 for further
description. Wake-up events can occur when
VCC2 is off. VCC1 must be on for a wake-up
event to occur, but the high-performance 8051
can be in sleep mode.
TABLE 128 – INTERNAL SYSTEM WAKE-UP EVENTS
WAKE-UP
EVENTS
REGISTER
DESCRIPTION
RTC_ALRM
Wake Up Src 1
RTC Alarm
(0x7F2B) [D0]
HTIMER
Wake Up Src 2
Hibernation Timer
(0x7F2B) [D2]
PM1_STS2
Wake Up Src 1
PM1 Status
(0x7F2A) [D5]
PM1_EN2
Wake Up Src 1
PM1 Enable
(0x7F2A) [D6]
PM1_CTL2
Wake Up Src 1
PM1 Control
(0x7F2A) [D7]
PIN
nRI
AB1_DATA
AB2_DATA
IRRX
KSI[7:0]
GPIO0/
GPIO1
GPIO2
GPIO3
GPIO4
TABLE 129 - EXTERNAL SYSTEM WAKE-UP EVENTS
WAKE-UP
EVENTS
ACTIVE EDGE
REGISTER
DESCRIPTION
UART_RI1
Edge, high-toWake Up Src 2
UART Ring Indicator
low
(0x7F2B) [D6]
ACCBUS1
Leading edge,
Wake Up Src1
AB_DAT
high-to-low
(0x7F2A) [D4]
ACCESS BUS1
ACCBUS2
Leading edge,
Wake Up Src1
AB_DAT
high-to-low
(0x7F2A) [D3]
ACCESS BUS2
IR_RX
Edge, high-toWake Up Src1
IR energy detected on the
low
(0x7F2B) [D2]
IRRX Receive pin
WK_ANYKEY
Edge, high-toWake Up Src 2
Any Keyboard Key
low
(0x7F2B) [D1]
pressed
PROGRAMMABLE
WK_SE02
Wake Up Src 4
General Purpose Pin
(0x7F59) [D2]
PROGRAMMABLE
WK_SE03
Wake Up Src 4
General Purpose Pin
(0x7F59) [D3]
PROGRAMMABLE
WK_SE04
Wake Up Src 4
General Purpose Pin
(0x7F59) [D4]
PROGRAMMABLE
TRIGGER
INT SRC 1
General Purpose Pin
(0x7F02) [D3]
PROGRAMMABLE
WK_SE07
Wake Up Src 4
General Purpose Pin
(0x7F59) [D7]
201
PIN
GPIO5
WAKE-UP
EVENTS
WK_SE10
PROGRAMMABLE
GPIO6
WK_SE11
PROGRAMMABLE
GPIO7
WK_SE06
PROGRAMMABLE
GPIO8
WK_SE12
PROGRAMMABLE
GPIO9
WK_SE13
PROGRAMMABLE
GPIO10
WK_SE14
PROGRAMMABLE
GPIO11
WK_SE15
PROGRAMMABLE
GPIO12
WK_SE16
PROGRAMMABLE
GPIO13
WK_SE17
PROGRAMMABLE
GPIO14
WK_SE20
PROGRAMMABLE
GPIO15
WK_SE21
PROGRAMMABLE
GPIO16
WK_SE22
PROGRAMMABLE
GPIO17
WK_SE23
PROGRAMMABLE
GPIO18
WK_SE27
PROGRAMMABLE
GPIO19
WK_SE24
PROGRAMMABLE
GPIO20/
PS2CLK/
8051RX
GPIO21/
PS2DAT/
8051TX
IN0
WK_SE25
PROGRAMMABLE
WK_SE26
PROGRAMMABLE
Wake Up Src6
(0x7F63) [D6]
WK_EE4
Either Edge
Wake Up Src 2
(0x7F2B) [D5]
ACTIVE EDGE
202
REGISTER
Wake Up Src 5
(0x7F5E) [D0]
Wake Up Src 5
(0x7F5E) [D1]
Wake Up Src 4
(0x7F59) [D6]
Wake Up Src 5
(0x7F5E) [D2]
Wake Up Src 5
(0x7F5E) [D3]
Wake Up Src 5
(0x7F5E) [D4]
Wake Up Src5
(0x7F5E) [D5]
Wake Up Src5
(0x7F5E) [D6]
Wake Up Src5
(0x7F5E) [D7]
Wake Up Src6
(0x7F63) [D0]
Wake Up Src6
(0x7F63) [D1]
Wake Up Src6
(0x7F63) [D2]
Wake Up Src6
(0x7F63) [D3]
Wake Up Src6
(0x7F63) [D7]
Wake Up Src6
(0x7F63) [D4]
Wake Up Src6
(0x7F63) [D5]
DESCRIPTION
General Purpose Pin
General Purpose Pin
Or FIR Mode Output/ 2nd
Receive Input
General Purpose Pin
GPIO8 or IR energy
detected on the
GPIO/COM-RX Receive
pin.
General Purpose Pin
General Purpose Pin
Or FIR Mode Output/ 2nd
Receive Input
GPIO11 or ACCESS.bus
2 Serial Data
GPIO12 or ACCESS.bus
2 Clock
General Purpose Pin
General Purpose Pin
General Purpose Pin
General Purpose Pin
General Purpose Pin
GPIO18 or DMA
Acknowledge
General Purpose Pin
/DMA Acknowledge
General Purpose Pin /PS2
Serial Clock
8051 RX Input
General Purpose Pin /PS2
Serial Data
8051 TX Input
General Purpose Wakeup
Source
IN1
WAKE-UP
EVENTS
WK_EE2
ACTIVE EDGE
Either Edge
IN2
WK_EE3
Either Edge
IN3
nGPWKUP
Either Edge
IN4
WK_SE00
Either Edge
IN5
WK_SE01
Either Edge
IN6
WK_SE05
Either Edge
IN7
WK_EE1
Either Edge
PIN
REGISTER
Wake Up Src 2
(0x7F2B) [D4]
Wake Up Src 2
(0x7F2B) [D5]
Wake Up Src 2
(0x7F2B) [D3]
Wake Up Src 4
(0x7F59) [D0]
Wake Up Src 4
(0x7F59) [D1]
Wake Up Src 4
(0x7F59) [D5]
Wake Up Src1
(0x7F2B) [D1]
DESCRIPTION
General Purpose Wakeup
Source
General Purpose Wakeup
Source
General Purpose Wakeup
Source
General Purpose Wakeup
Source
General Purpose Wakeup
Source
General Purpose Wakeup
Source
General Purpose Wakeup
Source
NOTE: All GPIO pins can generate wake events and all alternate functions of GPIO primary function
pins can generate wake events.
203
the High-Performance 8051 to emulate standard
8042 keyboard controller and preserve software
backward compatibility with the system BIOS.
The FDC37N972’s keyboard ISA interface is
functionally compatible with the 8042-style host
interface. It consists of the SD[0:7] data bus; the
nIOR, nIOW and the KBD (Keyboard) Status
register, KBD Data/Command Write register,
and KBD Data Read register. Table 130 shows
how the interface decodes the control signals.
In addition to the above signals, the host
interface includes keyboard and mouse IRQ's.
KEYBOARD CONTROLLER
8042 STYLE HOST INTERFACE
The FDC37N972 keyboard controller uses a
High-Performance 8051 microcontroller CPU
core to produce a superset of the features
provided by the industry-standard 8042
keyboard controller. Added features include two
high-drive serial interfaces, and additional
interrupt sources. The FDC37N972 provides an
industry standard 8042-style host interface to
TABLE 130 - KEYBOARD CONTROLLER ISA I/O ADDRESS MAP
ISA ADDRESS
NIOW
NIOR
FUNCTION (NOTE 1, 2 )
0x60
0
1
Keyboard Data Write (C/D=0)
1
0
Keyboard Data Read
0x64
0
1
Keyboard Command Write (C/D=1)
1
0
Keyboard Status Read
All addresses are qualified by AEN.
Note 1: The Keyboard Interface can be enabled or disabled through the configuration registers.
Note 2: These registers consist of three separate 8 bit registers: KBD Status, KBD Data/Command
Write and KBD Data Read.
KEYBOARD DATA READ
KEYBOARD DATA WRITE
This is an 8 bit read only register. When read,
This is an 8 bit write only register. When
the PBOBF and/or AUXOBF interrupts are
written, the C/D status bit of the status register
cleared and the OBF flag in the status register is
is cleared to zero and the IBF bit is set.
cleared.
204
KEYBOARD COMMAND WRITE
This is an 8 bit write only register. When
written, the C/D status bit of the status register
is set to one and the IBF bit is set.
This is an 8 bit read only register. Refer to the
description of the Status Register (7FF2H) for
more information.
8051TOCOMMUNICATION
HOST
KEYBOARD
KEYBOARD STATUS READ
The 8051 can write to the KBD Data Read
register via address 7FF1H and 7FFAH (Aux
Host Data Register) respectively. A write to
either of these addresses automatically sets bit
0 (OBF) in the Status register. A write to 7FF1H
also sets PCOBF. A write to 7FFAH also sets
AUXOBF1. See TABLE 132 below.
TABLE 131 - HOST-INTERFACE FLAGS
8051
ADDRESS
FLAG
7FF1H (R/W)
PCOBF (KIRQ) output signal goes high
7FFAH (W)
AUXOBF1 (MIRQ) output signal goes high
HOST I/F DATA REGISTER
Host
ISA 0x60
8051
0x7FF1
Power
VCC1
Default
N/A
The Input Data register and Output Data register
are each 8 bits wide. A write to this 8 bit register
by the 8051 will load the Keyboard Data Read
Buffer, set the OBF flag and set the PCOBF
output if enabled. A read of this register by the
8051 will read the data from the Keyboard Data
or Command Write Buffer and clear the IBF
flag. Refer to the PCOBF and Status register
descriptions for more information.
HOST I/F COMMAND REGISTER
Host
ISA 0x64 (W)
8051
0x7FF1
Power
VCC1
Default
N/A
The host CPU sends commands to the keyboard controller by writing command bytes to ISA port
0x64.
HOST I/F STATUS REGISTER
Host
ISA 0x64 (R)
8051
0x7FF2
Power
VCC1
Default
N/A
205
The Status register is 8 bits wide. Shows the contents of the KBD Status register.
D7
UD
D6
UD
TABLE 132 - KBD STATUS REGISTER
D5
D4
D3
D2
AUXOBF/UD
UD
C/D
UD
D0
OBF
whenever the 8051 writes into the data registers
at 7FF1H.
PCOBF
Host
N/A
8051
0x7FFD
Power
VCC1
Default
0x00
This register is read-only for the Host and
read/write by the 8051. The 8051 cannot write to
bits 0, 1, or 3 of the Status register.
UD
Read/Writeable by 8051.
are user-definable.
D1
IBF
These bits
C/D
Refer to the PCOBF description for information
on this register. This is a “1” bit register (bits 17=0 on read)
Command Data - This bit specifies whether the
input data register contains data or a command
(“0” = data, “1” = command). During a host
data/command write operation, this bit is set to
"1" if SA2 = “1” or reset to "0" if SA2 = 0.
HOST-TO
8051
COMMUNICATION
KEYBOARD
The host system can send both commands and
data to the KBD Data/Command Write register.
The CPU differentiates between commands and
data by reading the value of bit 3 of the Status
register. When bit 3 is "1", the CPU interprets
the register contents as a command. When Bit
3 is "0", the CPU interprets the register contents
as data. During a host write operation, bit 3 is
set to "1" if SA2 = 1 or reset to "0" if SA2 = 0.
IBF
Input Buffer Full - This flag is set to “1”
whenever the host system writes data into the
input data register. Setting this flag activates
the 8051's nIBF interrupt if enabled. When the
8051 reads the input data register, this bit is
automatically reset and the interrupt is cleared.
There is no output pin associated with this
internal signal.
PCOBF DESCRIPTION
OBF
(The following description assumes that OBFEN
= 1 in Configuration Register 0); PCOBF is
gated onto KIRQ. The KIRQ signal is a system
interrupt which signifies that the 8051 has
written to the KBD Data Read register via
address 7FF1H. On power-up, PCOBF is reset
to 0. PCOBF will normally reflect the status of
writes to 7FF1H, if PCOBFEN (bit 2 of
Configuration register “0”) = “0”. (KIRQ is
normally selected as IRQ1 for keyboard
Output Buffer Full - This flag is set to “1”
whenever the 8051 writes into the data registers
at 7FF1H or 7FFAH. When the host system
reads the output data register, this bit is
automatically reset.
AUXOBF
Auxiliary Output Buffer Full - This flag is set to
“1” whenever the 8051 writes into the data
registers at 7FFAH. This flag is reset to “0”
206
the in-process status of write cycles to 7FF1H
(i.e., if the value read back is high, the host
interface output data register has just been
written to). If OBFEN=0, then KIRQ is driven
inactive (low).
support.) PCOBF is cleared by hardware on a
read of the Host Data Register.
Additional flexibility has been added which
allows firmware to directly control the PCOBF
output signal, independent of data transfers to
the host-interface data output register. This
feature allows the FDC37N972 to be operated
via the host "polled" mode. This firmware
control is active when PCOBFEN = 1 and
firmware can then bring PCOBF high by writing
a "1" to the LSB of the 1 bit data register,
PCOBF, allocated at 7FFDH. The firmware
must also clear this bit by writing a "0" to the
LSB of the 1 bit data register at 7FFDH.
AUXOBF1 DESCRIPTION
(The following description assumes that OBFEN
= 1 in Configuration Register 0); This bit is
multiplexed onto MIRQ. The AUXOBF1/MIRQ
signal is a system interrupt which signifies that
the 8051 has written to the output data register
via address 7FFAH.
On power-up, after VCC1 POR, AUXOBF1 is
reset to 0. AUXOBF1 will normally reflects the
status of writes to 7FFAH. (MIRQ is normally
selected as IRQ12 for mouse support.)
AUXOBF1 is cleared by hardware on a read of
the Host Data Register. If OBFEN=0, then
KIRQ is driven inactive (low).
The PCOBF register is also readable; bits 1-7
will return a "0" on the read back. The value
read back on bit 0 of the register always reflects
the present value of the PCOBF output. If
PCOBFEN = 1, then this value reflects the
output of the firmware latch at 7FFDH. If
PCOBFEN = 0, then the value read back reflects
Write to
Register
7FF1
7FFA
HOST I/F STATUS REGISTER BITS
AUXOBF (D5)
OBF (D0)
OBFEN=0
OBFEN=1
0
1
KIRQ=0
MIRQ=0
KIRQ=1
MIRQ=1
1
1
OBFEN
0
1
1
OBFEN
0
1
AUXH
X
0
1
1
PCOBFEN
X
0
1
KIRQ is inactive and driven low
KIRQ = PCOBF@7FF1
KIRQ = PCOBF@7FFD
MIRQ is inactive and driven low
MIRQ = PCOBF@7FFA; Status Register D5 = User
Defined
MIRQ = PCOBF@7FFA; Status Register D5 =
Hardware Controlled
207
8051 AUXOBF1 CONTROL REGISTER
AUX HOST DATA REGISTER
Host
ISA 0x60
8051
0x7FFA
Power
VCC1
Default
N/A
Refer to the AUXOBF1 description for information on this register.
GATEA20 HARDWARE SPEED-UP
configuration bit called "SAEN" (Software Assist
Enable, bit 1 of Configuration register 0) is
provided; when set, SAEN allows firmware to
control the GATEA20 output.
GATEA20 is multiplexed onto GPIO17 using
MISC6. The FDC37N972 contains on-chip logic
support for the GATEA20 hardware speed-up
feature. GATEA20 is part of the control required
to mask address line A20 to emulate 8086
addressing.
When SAEN is set, a 1 bit register assigned to
address 7FFBH controls the GATEA20 output.
The register bit allocation is shown in Table 133.
In addition to the ability for the host to control
the GATEA20 output signal directly, a
D7
x
TABLE 133 - REGISTER BIT ALLOCATION
D6
D5
D4
D3
D2
D1
D0
x
x
x
x
x
x
GATEA20
Writing a "0" into location D0 causes the
GATEA20 output to go low, and vice versa.
When the register at location 7FFBH is read, all
unused bits (D7-D1) are read back as "0".
When the FDC37N972 receives a "D1"
command followed by data (via the host
interface), the on-chip hardware copies the
value of data bit 1 in the received data field to
the GATEA20 host latch. At no time during this
host-interface transaction will PCOBF or the IBF
flag (bit 1) in the Status register be activated;
i.e., this host control of GATEA20 is transparent
to firmware, with no consequent degradation of
overall system performance. Table 134 details
the possible GATEA20 sequences and the
FDC37N972 responses.
Host control and firmware control of GATEA20
affect two separate register elements. Read
back of GATEA20 through the use of 7FFBH
reflects the present state of the GATEA20 output
signal: if SAEN is set, the value read back
corresponds to the last firmware-initiated control
of GATEA20; if SAEN is reset, the value read
back corresponds to the last host-initiated
control of GATEA20.
On VCC1 POR, GATEA20 will be set.
Host control of the GATEA20 output is provided
by the hardware interpretation of the "GATEA20
sequence" (see TABLE 134). The foregoing
description
assumes
that
the
SAEN
configuration bit is reset.
An additional level of control flexibility is offered
via a memory-mapped synchronous set and
reset capability. Any data written to 7FFEH
causes the GATEA20 host latch to be set; any
208
via this mechanism, a potential conflict could
arise. Therefore, after using the 7FFEH and
7FFFH addresses, firmware should read back
the GATEA20 status via 7FFBH (with SAEN =
0) to confirm the actual GATEA20 response.
data written to 7FFFH causes it to be reset.
This control mechanism should be used with
caution. It was added to augment the "normal"
control flow as described above, not to replace
it. Since the host and the firmware have
asynchronous control capability of the host latch
SA2
1
0
1
1
0
1
1
1
0
1
SA2
1
1
0
1
1
1
1
TABLE 134 - GATE20 COMMAND/DATA SEQUENCE EXAMPLES
R/W
D[0:7]
IBF
GATEA20
COMMENTS
FLAG
GATEA20 Turn-on Sequence
Q
0
D1
W
1
0
DF
W
1
0
FF
W
GATEA20 Turn-off Sequence
Q
0
D1
W
0
0
DD
W
0
0
FF
W
GATEA20 Turn-on Sequence(*)
Q
0
D1
W
Q
0
D1
W
1
0
DF
W
1
0
FF
W
R/W
D[0:7]
IBF
GATEA20
COMMENTS
FLAG
W
D1
0
Q
GATEA20 Turn-off Sequence(*)
W
D1
0
Q
W
DD
0
0
W
FF
0
0
W
D1
0
Q
Invalid Sequence
W
XX**
1
Q
W
FF
1
Q
Notes:
All examples assume that the SAEN configuration bit is 0.
"Q" indicates the bit remains set at the previous state.
*Not a standard sequence.
**XX = Anything except D1.
If multiple data bytes, set IBF and wait at state 0. Let the software know something unusual
happened.
For data bytes SA2=0, only D[1] is used; all other bits are don't care.
209
8051 GATEA20 CONTROL REGISTERS
Host
8051
Power
Default
GATEA20
N/A
0x7FFB
VCC1
0x01
Refer to the GATEA20 Hardware Speed-up description for information on this register. This is a one
bit register (Bits 1-7=0 on read)
Host
8051
Power
Default
SETGA20L
N/A
0x7FFE (W)
VCC1
N/A
Refer to the GATEA20 Hardware Speed-up description for information on this register. A write to this
register sets GateA20.
Host
8051
Power
Default
RSTGA20L
N/A
0x7FFF (W)
VCC1
N/A
Refer to the GATEA20 Hardware Speed-up description for information on this register. A write to this
register re-sets GateA20.
210
GateA20 Logic
nIOW_DLY
SAEN
To KRESET Gen
64&nAEN
nIOW
nIOW
nIOW_DLY
nIOW
DD1
SD[7:0] = D1
D
Q
IBF Bit
Address
SD[7:0] = FF
DFF
SD[7:0] = FE
DFE
IBF
Data
CPU_RESET
0
nAEN&60
MUX
SETGA20L Reg
Any Write
DD1
D
nIOW
nAEN&64
Q
After D1
1
SD[1]
D
R
nIOW
nAEN&60
S
Q
Fast_GateA20
Write
GATEA20 Reg
d0
Read
GATEA20 Reg
d0
R
RSTGA20L Reg
Any Write
D
Trailing Edge Delay
SAEN
bit-1 of
Config Reg 0
bit-0
bit-0
Port92 Reg
ENAB_P92
ALT_A20
Bit 1
VCC
Delay
nIOW_DLY
nIOW
D
Q
D
Q
D
24MHz
R
nQ
FIGURE 30 - GATEA20 IMPLEMENTATION DIAGRAM
211
A20
GATEA20
CPU_RESET HARDWARE SPEED-UP
The ALT_CPU_RESET bit generates, under
program control, the nALT_RST signal, which
provides an alternate, means to drive the
FDC37N972 CPU_RESET pin which in turn is
used to reset the Host CPU. The nALT_RST
signal is internally NANDed together with the
nKBDRESET pulse from the KRESET Speed up
logic to provide an alternate software means of
resetting the host CPU. Note: before another
nALT_RST
pulse
can
be
generated,
ALT_CPU_RESET must be cleared to “0” either
by a system reset (nRESET_OUT asserted) or
by a write to the Port92 register with bit 0 = “0”.
A nALT_RST pulse is not generated in the event
that the ALT_CPU_RESET bit is cleared and set
before the prior nALT_RESET pulse has
completed.
14 us
6us
FE
Command
From
KRESET
Speed up
Logic
SAEN
KRESET
Pulse
Gen
CPU_RESET
ENAB_P92
Port92 Reg
Bit 0
Pulse
Gen
nALT_RST
14 us
6us
FIGURE 31 - CPU_RESET IMPLEMENTATION DIAGRAM
PORT 92
The FDC37N972 supports ISA I/O writes to port 92h as a quick alternate mechanism for generating a
CPU_RESET pulse or controlling the state of GATEA20.
212
Host R/W
Bit Def
PORT 92 REGISTER DESCRIPTION
D7-D2
D1
D0
R/W
R/W
R/W
0
ALT_GATEA20
ALT_CPU_RESET
Reserved
The Port92h register resides at ISA address
0x92 and is used to support the alternate reset
(nALT_RST)
and
alternate
GATEA20
(ALT_A20) functions. This register defaults to
0x00 on assertion of nRESET_OUT or on VCC2
Power On Reset.
Setting the Port 92 Enable bit (bit 0 of Logical
Device 7 Configuration Register 0xF0) enables
the Port92h Register. When Port92 is disabled,
by clearing the Port 92 Enable bit, then access
to this register is completely disabled (I/O writes
to ISA 92h are ignored and I/O reads float the
system data bus SD[7:0]).
When Port92h is enabled the bits have the
following meaning:
D7-D2 RESERVED
A write are ignored and a read return 0.
D1 - ALT_GATEA20
This bit provides an alternate means for system
control of the FDC37N972 GATEA20 pin.
213
= 0: ALT_A20 is driven low
= 1: ALT_A20 is driven high
When Port 92 is enabled, writing a 0 to bit 1 of
the Port92 Register forces ALT_A20 low.
ALT_A20 low drivesGATEA20 low, if A20 from
the keyboard controller is also low. When Port
92 is enabled, writing a 1 to bit 1 of the Port92
register forces ALT_A20 high. ALT_A20 high
drives GATEA20 high regardless of the state of
A20 from the keyboard controller.
D0 - ALT_CPU_RESET
This bit provides an alternate means to generate
a CPU_RESET pulse. The CPU_RESET output
provides a means to reset the system CPU to
effect a mode switch from Protected Virtual
Address Mode to the Real Address Mode. This
provides a faster means of reset than is
provided through the 8051 keyboard controller.
Writing a “1” to this bit will cause the nALT_RST
internal signal to pulse (active low) for a
minimum of 6µs after a delay of 14µs. Before
another nALT_RST pulse can be generated, this
bit must be written back to “0”.
GATEA20
The hardware GATEA20 state machine returns to state S1 from state S2 when CMD = D1 (FIGURE
32).
CMD !=D1 or
DATA
[IBF=1]
RESET
S0
CMD = D1
[IBF=0]
CMD = FF
[IBF=0]
CMD !=D1 or
CMD !=FF or
DATA
[IBF=1]
S2
CMD !=D1
[IBF=1]
CMD = D1
[IBF=0]
S1
Data
[IBF=0, Latch DIN
Notes: GateA20 Changes When in S1 going to S2
Clock = wrdinB
CMD = [SA2=1]
Data = [SA2=0]
GateA20 State Machine
FIGURE 32 - GATEA20 STATE MACHINE
214
CMD = D1
[IBF=0]
DIRECT KEYBOARD SCAN
The FDC37N972 scanning keyboard controller
is designed for intelligent keyboard management
in computer applications.
By properly
configuring GPIO4 and GPIO5, the FDC37N972
may be programmed to directly control
keyboard interface matrixes of up to 16x8.
KEYBOARD SCAN-OUT REGISTER
Host
N/A
8051
0x7F04 (W)
Power
VCC1
Default
0x20
8051
R/W
Bit Def
D7-D6
W
N/A
D5
W
D4
W
D3
W
KSEN
1 = forces all
KSO lines to
go low
D2
W
D1
W
D0
W
D5 and D4 must be ‘0’
D[3:0] = 0000 KSO[0] is asserted low
D[3:0] = 0001 KSO[1] is asserted low
D[3:0] = 0010 KSO[2] is asserted low
D[3:0] = 0011 KSO[3] is asserted low
•
•
•
D[3:0] = 1101 KSO[13] is asserted low
D[3:0] = 1110 KSO[14] is asserted low
D[3:0] = 1111 KSO[15] is asserted low
KSEN 1 = disable scanning of internal keyboard (all the KSOUT lines going high) (D4-D0 are don’t
cares)
0 = enable scanning of internal keyboard
Note:
Setting D[3:0] to 111x puts KSO0 - KSO13 outputs as Hi-Z.
KEYBOARD SCAN-IN REGISTER
Host
N/A
8051
0x7F04 (R)
Power
VCC1
Default
N/A
8051 R
Bit description
D7-D0
R
Reflects the state of KSI [7:0]
The value of the KSI[x] pins can be read through this register.
The pin values are latched during the read.
215
EXTERNAL KEYBOARD AND MOUSE INTERFACE
Industry-standard PC/AT-compatible keyboards
employ a two-wire, bidirectional TTL interface
for data transmission. Several sources also
supply PS/2 mouse products that employ the
same type of interface. To facilitate system
expansion, the FDC37N972 provides four pairs
of signal pins that may be used to implement
this interface directly for an external keyboard
and mouse.
The FDC37N972 has four high-drive, open-drain
output (external pull-ups are required),
bidirectional port pins that can be used for
external serial interfaces, such as ISA external
keyboard and PS/2-type mouse interfaces.
They are KBCLK, KBDAT, EMCLK, EMDAT,
IMCLK, IMDAT, PS2CLK and PS2DAT.
The following function is assumed to be in the
PS/2 PORT logic: The serial clock lines,
KBCLK, EMCLK, IMCLK and PS2CLK, are
cleared to a low by VCC2 POR. This is so that
any power-on self-test completion code
transmitted from the serial keyboard will not be
missed by the FDC37N972 due to power-up
timing mismatches.
PS/2 DEVICE INTERFACE
The FDC37N972 has four independent PS/2
serial ports implemented in hardware which are
directly controlled by the on chip 8051. The
hardware implementation eliminates the need to
bit bang I/O ports to generate PS/2 traffic,
however bit banging is still available if required.
216
Each of the four PS/2 serial channels use a
synchronous serial protocol to communicate
with the auxiliary device. Each PS/2 channel
has two signal lines: Clock and Data. Both
signal lines are bi-directional and employ open
drain outputs capable of sinking 16mA. A pullup resistor (typically 10K) is connected to the
clock and data lines. This allows either the
FDC37N972 SMSC PS/2 logic or the auxiliary
device to control both lines. Regardless, the
auxiliary device provides the clock for transmit
and receive operations. The serial packet is
made up of eleven bits, listed in order as they
will appear on the data line: start bit, eight data
bits (least significant bit first), odd parity, and
stop bit. Each bit cell is from 60µS to 100µS
long.
The SMSC PS/2 and the Devil Logic interfaces
are available in the FDC37N972. The PS2_SEL
Control bit D4 in Configuration Register 0
(0x7FF4) is used select between these two
mutually exclusive options. (See TABLE 90 CONFIGURATION REGISTER 0.) Many of the
SMSC PS/2 and the Devil Logic registers share
the same address space in the 8051 MMCRs.
These are shown in TABLE 86 between
addresses 0x7F41 and 0x7F4F.
See 8051 INT0 Source REGISTER on page
172 for a description of the Devil Logic versus
the SMSC PS/2 interrupts and a description of
the repsective pin mapping.
PIN NUMBER
45
46
47
48
50
51
52
53
PIN NAME
GPIO20
GPIO[21]
IMCLK
IMDAT
KCLK
KDAT
EMCLK
EMDAT
TABLE 135 - PIN DEFINITIONS
SMSC PS/2 FUNCTION
SMSC PS/2 DESCRIPTION
PS2CLK
Channel D Serial Clock
PS2DAT
Channel D Serial Data
IMCLK
Channel C Serial Clock
IMDAT
Channel C Serial Data
KCLK
Channel B Serial Clock
KDAT
Channel B Serial Data
EMCLK
Channel A Serial Clock
EMDAT
Channel A Serial Data
All PS/2 Serial Channel signals (CLK and DAT) are driven by open collector (TYPE I/OD16) drivers
pulled to VCC2 (+3.3V nominal) through 10K-ohm resistors.
SMSC PS/2 LOGIC OVERVIEW
The SMSC PS/2 logic allows the host to
communicate to any serial auxiliary devices
compatible with the PS/2 interface through any
one of four channels. The PS/2 Logic consists
of four identical SMSC PS/2 channels, each
containing a set of four operating registers. The
four Channels are PS/2 Chan A, PS/2 Chan B,
PS/2 Chan C, and PS/2 Chan D. During a
reception, the FDC37N972 latches the data on
the high to low transition of the clock. During a
transmission, the FDC37N972 transitions the
data line on the high to low transition of the
clock. See FIGURE 33 - SMSC PS/2 LOGIC
BLOCK DIAGRAM.
Notes:
1) Each PS/2 channel has the ability to “busy” the communication link by pulling the clock line low.
This is accomplished by simultaneously clearing the PS2_EN and WR_CLK bits in the Control
Register.
2) Each PS/2 channel has the ability to abort, prior to the parity bit (10th bit), the transfer in
progress.
3) Clock bit time (cycle time) typically varies between 60 and 100 us. The FDC37N972 PS/2 Logic
is designed such that it is immune to variations in the clock cycle times within the limit of the
transfer timeout.
4) Once a transmission has begun, the PS/2 `peripheral is allowed up to 300us per bit transfer. If
the time between falling clock edges exceeds 300us a transfer timeout occurs resulting in either
XMIT_TIMEOUT or REC_TIMEOUT being set along with the generation of an interrupt.
5) Once a transmission has started, the PS/2 peripheral has approximately 2ms to complete the
transfer. This transfer timeout applies to transmissions as well as receptions. In the case of a
transmission(reception), if a 2ms timeout occurs the XMIT_TIMEOUT(REC_TIMEOUT) bit in the
status register is set and an interrupt is generated.
6) When the controller is ready to transmit data it floats the data line and drives the clock line low.
Once data is written to the Transmit Register the data line is driven low and after a delay the clock
line is released (floated) so that the PS/2 peripheral knows data is ready. Releasing the clock
signals the start of a trasmission. The PS/2 peripheral has 25ms to acknowledge the transmit
start condition above by driving the clock line low. If the PS/2 peripheral does not acknowledge in
217
7)
8)
the allotted time then a Trasmit timeout occurs: setting the XMIT_TIMEOUT error bit in the Status
register and generating an interrupt.
By clearing the PS/2 channels PS2_EN bit in its Control Register the PS/2 Channel can be
operated in a fully software controlled “Bit-bang” mode. This allows operation of auxilliary devices
that do not meet standard PS/2 protocol timing handled by the FDC37N972’s PS/2 Logic block.
See Sections 0 through 0 for timing information.
8051
MEMORY
MAPPED
CONTROL
REGISTERS
PS2_CHAN_A
PDAT_A
PCLK_A
PS2_CHAN_B
PDAT_B
PCLK_B
PS2_CHAN_C
PDAT_C
PCLK_C
PS2_CHAN_D
PDAT_D
PCLK_D
FIGURE 33 - SMSC PS/2 LOGIC BLOCK DIAGRAM
PS/2 DATA FRAME
Data transmissions to and from the auxilliary device connector on each PS/2 channel consist of an 11bit data stream sent serially over the data line. The following figure shows the function of each bit.
Start Bit
Always 0
8 data bits, least sig bit first
Parity Bit
Odd on xmit
Prog. on rec.
Stop Bit
High on xmit
Prog. on rec.
FIGURE 34 - PS/2 DEVICE DATA STREAM BIT DEFINITIONS
SMSC PS/2 MEMORY MAPPED CONTROL
REGISTERS
one register is shared by all four channels to
provide RX_Busy indicators.
Each SMSC PS/2 channel has a separate set of
identical control registers: Transmit, Receive,
Control,and Status. These are shown in TABLE
86 between addresses 0x7F41 and 0x7F4F. The
transmit and receive register share the same
address (ie. . PS/2 Chan A Tx/Rx) In addition
SMSC PS/2 TRANSMIT REGISTERS
218
The byte written to this register, when PS2_T/R,
PS2_EN, and XMIT_IDLE are set, is transmitted
automatically by the PS/2 channel control logic.
If any of these three bits (PS2_T/R, PS2_EN,
and XMIT_IDLE) are not set, then writes to this
register are ignored. On successful completion
of this transmission or upon a Transmit Timeout condition the PS2_T/R bit is automatically
cleared and the XMIT_IDLE bit is automatically
set. The PS2_T/R bit must be written to a ‘1’
before initiating another transmission to the
remote device.
Notes:
1) Even if PS2_T/R, PS2_EN, and XMIT_IDLE
are all set, writing the Transmit Register will
not kick off a transmission if RDATA_RDY
is set. The automatic PS2 logic forces data
to be read from the Receive Register before
allowing a transmission.
2) An interrupt is generated on the low to high
transition of XMIT_IDLE.
3) All bits of this register are write only.
SMSC PS/2 RECEIVE REGISTERS
When PS2_EN=1 and PS2_T/R=0 the PS2
Channel is set to automatically receive data on
that channel (both the CLK and DATA lines will
float waiting for the peripheral to initiate a
reception by sending a start bit followed by the
data bits). After a successful reception data is
placed in this register and the RDATA_RDY bit
219
is set and the CLK line is forced low by the PS2
channel logic. RDATA_RDY is cleared and the
CLK line is released to hi-z following a read of
this register. This automatically holds off further
receive transfers until the 8051 has had a
chance to get the data.
Notes:
1) The Receive Register is initialized to 0xFF
after a read or after a Timeout has occured.
2) The channel can be enabled to
automatically transmit data (PS2_EN=1) by
setting PS2_T/R while RDATA_RDY is set,
however a transmission can not be kicked
off until the data has been read from the
Receive Register.
3) An interrupt is generated on the low to high
transition of RDATA_RDY.
4) If a receive timeout (REC_TIMEOUT=1) or
a transmit timeout (XMIT_TIMEOUT=1)
occurs the channel is busied (CLK held low)
for 300us (Hold Time) to guarantee that the
peripheral aborts. Writing to the Transmit
Register will be allowed, however the data
written will not be transmitted until the Hold
Time expires.
5) All bits in this register are read only
SMSC PS/2 CONTROL REGISTERS
TABLE 136 - SMSC PS/2 CONTROL REGISTERS (A - D)
HOST ADDRESS
0x7F42 (CHAN A),
8051 ADDRESS
0x7F46 (CHAN B),
0x7F4A (CHAN C),
0x7F4E (CHAN D)
VCC2
POWER
0x40
DEFAULT
HOST
TYPE
8051
TYPE
BIT
NAME
D7
-
D6
-
D5
-
D4
-
D3
-
D2
-
D1
-
D0
-
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
WR_CLK
WR_DATA
STOP
PS2_EN
PS2_T/R
PARITY
Default = 0x40 on VCC2 POR only.
Note: There are four PS/2 Control Registers, one for each channel.
PS2_T/R
PS/2 Channel Transmit/Receive (default = 0).
This bit is only valid when PS2_EN=1 and sets
the PS2 logic for automatic transmission or
reception when PS2_T/R equals ‘1’ or ‘0’
respectively.
When set the PS/2 channel is enabled to
transmit data. To properly initiate a transmit
operation this bit must be set prior to writing to
the Transmit Register; writes are blocked to the
Transmit Register when this bit is not set. Upon
setting the PS2_T/R bit the channel will drive its
CLK line low and then float the DATA line and
hold this state until a write occurs to the
Transmit Register or until the PS2_T/R bit is
cleared.
Writing to the Transmit Register
initiates the transmit operation. FDC37N972
drives the data line low and, within 80ns, floats
the clock line (externally pulled high by the pullup resistor) to signal to the external PS/2 device
220
that data is now available. The PS2_T/R bit is
cleared on the 11th clock edge of the
transmission or if a Transmit Timeout error
condition occurs. NOTE: if the PS2_T/R bit is
set while the channel is actively receiving data
prior to the leading edge of the 10th (parity bit)
clock edge the receive data is discarded. If this
bit is not set prior to the 10th clock signal then
the receive data is saved in the Receive
Register.
When the PS2_T/R bit is cleared the PS/2
channel is enabled to receive data. Upon
clearing this bit, if RDATA_RDY=0, the
channel’s CLK and DATA will float waiting for
the external PS/2 device to signal the start of a
transmission. If the PS2_T/R bit is set while
RDATA_RDY=1 then the channel’s DATA line
will float but its CLK line will be held low, holding
off the peripheral, until the Receive Register is
read.
PS2_EN
PS2 Channel ENable (default = 0). When PS2_EN=1 the PS/2 State machine is enabled allowing the
channel to perform automatic reception or transmission depending on the bit value of PS2_T/R.
When PS2_EN = 0, the channel’s automatic PS/2 state machine is disabled and the channel can be
bit-banged through the WR_DATA and WR_CLK bits in the Contol Register and the RD_DATA and
RD_CLK bits in the Status Register. Thus, when PS2_En=0, the channel’s CLK and DATA lines are
forced to the level specified in the Control Register WR_CLK and WR_DATA bits.
NOTE: If the PS2_EN bit is cleared prior to the leading edge (falling edge) of the 10th (parity bit) clock
edge the receive data is discarded (RDATA_RDY remains low). If the PS2_EN bit is cleared following
the leading edge of the 10th clock signal then the receive data is saved in the Receive Register
(RDATA_RDY goes high) assuming no parity error.
PARITY
Bits [3:2] of the Control Register are used to set the parity expected by the PS/2 channel state
machine. These bits are therefore only valid when PS2_EN=1.
Bits[3:2] = 00
: Receiver expects Odd Parity (default).
= 01
: Receiver expects Even Parity.
= 10
: Receiver ignores level of the parity bit (10th bit is not interpreted as a parity bit).
= 11
: Reserved.
STOP
Bits [5:4] of the Control Register are used to set the level of the stop bit expected by the PS/2 channel
state machine. These bits are therefore only valid when PS2_EN=1.
Bits[5:4] = 00
: Receiver expects an active high stop bit.
= 01
: Receiver expects an active low stop bit.
= 10
: Receiver ignores the level of the Stop bit (11th bit is not interpreted as a stop bit).
= 11
: Reserved.
WR_DATA
Write DATA bit: When PS2_EN=1, writes to the WR_DATA bit are accepted but result in no action
other than setting or clearing this bit. When PS2_EN=0, setting this bit to a 1 or 0 either floats or
drives low the PS/2 channel’s Serial DATA pin. This bit is used for transmitting bit-banged data over
the PS2 channel. Bit-banging of the PS/2 channel is enabled when PS2_EN= 0.
Note : while the Hold timeout is in effect (300us following a Receive or Transmit Timeout) writes to
this bit are blocked.
WR_CLK
Write CLK bit: When PS2_EN=1, writes to the WR_CLK bit are accepted but result in no action other
than setting or clearing this bit. When PS2_EN=0, setting this bit to a 1 or 0 either floats or drives low
the PS/2 channel’s Serial CLK pin. Bit-banging of the PS/2 channel is enabled when the PS2_EN bit
is set to 0.
221
SMSC PS/2 Status Registers
Note : While the Hold timeout is in effect (300us following a Receive or Transmit Timeout) writes to
this bit are blocked.
Note : When PS2_EN = 0, high to low transitions on the CLK pin caused by the peripheral will
generate a PS2 Chan interrupt. A timeout event or writing this bit low will not cause an interrupt.
The default for the WR_DATA bit D6 in the four SMSC PS/2 Control Registers is “1”. The default in
earlier devices is “0” (TABLE 136). The VCC2 Power-on Default for each Control Register is 40h.
TABLE 137 - SMSC PS/2 STAUS REGISTERS (A - D)
HOST ADDRESS
0x7F43 (CHAN A),
8051 ADDRESS
0x7F47 (CHAN B),
0x7F4B (CHAN C),
0x7F4F (CHAN D)
VCC2
POWER
0x00
DEFAULT
HOST
TYPE
8051
TYPE
BIT
NAME
D7
-
D6
-
D5
-
D4
-
D3
-
D2
-
D1
-
D0
-
R
R
R
R
R
R
R
R
RD_CLK
RD_DATA
XMIT_
TIMEOUT
XMIT_IDLE
FE
PE
REC_
TIMEOUT
RDAT
_RDY
Default = 0x40 on VCC2 POR only.
Note: There are four PS/2 Status Registers, one for each channel.
Note : XMIT_TIMEOUT, FE, PE, REC_TIMEOUT, RDATA_RDY are cleared to zero upon a read of
this register.
222
RDATA_RDY
PE
Receive Data Ready: Under normal operating
conditions, this bit is set following the falling
edge of the 11th clock given successful
reception of a data byte from the PS/2
peripheral (i.e., no parity, framing, or receive
timeout errors) and indicates that the received
data byte is available to be read from the
Receive Register. This bit may also be set in
the event that the PS2_EN bit is cleared
following the 10th CLK edge (see the PS2_EN
bit description for further details). Reading the
Receive Register clears this bit.
Parity Error: When receiving data the parity bit
is clocked in on the falling edge of the 10th CLK
edge. If the channel has been set to expect
either even or odd parity and the 10th bit is
contrary to the expected parity, then the PE and
REC_TIMEOUT bits are set following the falling
edge of the 10th CLK edge and an Interrupt is
generated.
Note : An Interrupt is generated on the low to
high transition of the RDATA_RDY bit.
REC_TIMEOUT
Under PS2 automatic operation, PS2_EN=1,
this bit is set on one of 4 receive error
conditions, and in additon the channel’s CLK
line is automatically pulled low and held for a
period of 300us following assertion of the
REC_TIMEOUT bit :
1)
2)
3)
4)
When the receiver bit time (time between
falling edges) exceeds 300us.
If the time from the 1st (start) bit to the 10th
(parity) bit exceeds 2ms.
On a receive parity error along with the
parity error (PE) bit.
On a receive framing error due to an
incorrect STOP bit along with the framing
error (FE) bit.
The REC_TIMEOUT bit is cleared when the
Status Register is read.
Note : An Interrupt is generated on the low to
high transition of the REC_TIMEOUT bit.
FE
Framing Error: When receiving data the stop bit
is clocked in on the falling edge of the 11th CLK
edge. If the channel has been set to expect
either a high or low stop bit and the 11th bit is
contrary to the expected stop polarity, then the
FE and REC_TIMEOUT bits are set following
the falling edge of the 11th CLK edge and an
Interrupt is generated.
XMIT_IDLE
Transmiter Idle: When low, the XMIT_IDLE bit
is a status bit indicating that the PS2 channel is
actively transmitting data to the PS2 peripheral
device. Writing to the Transmit Register when
the channel is ready to transmit will cause the
XMIT_IDLE bit to deassert and remain
deasserted until one of the following conditions
occur:
1) the falling edge of the 11th CLK; upon a
Transmit
Timeout
condition
(XMIT_TIMEOUT goes high);
2) upon the PS2_T/R bit being written to 0;
3) upon the PS2_EN bit being written to 0.
Note : An interrupt is generated on the low to
high transition of XMIT_IDLE.
XMIT_TIMEOUT
This bit is set on one of 3 transmit conditions,
and in additon the channel’s CLK line is
automatically pulled low and held for a period of
223
pin. This bit is used when receiving bit-banged
data over the PS2 channel. Bit-banging of the
PS2 channel is enabled when the PS2_EN bit is
set to 0. To receive bit banged data properly the
PS2_EN must be set to 0 and the WR_CLK bit
in the PS2 Channel’s Control Register must be
set to 1.
300us
following
assertion
of
the
XMIT_TIMEOUT bit during which time the
PS2_T/R is also held low :
When the transmitter bit time (time between
falling edges) exceeds 300us.
When the transmitter start bit is not received
withing 25ms from signaling a transmit start
event.
If the time from the 1st (start) bit to the 10th
(parity) bit exceeds 2ms.
Note : When PS2_EN = 0, high to low
transitions on the CLK pin will generate a PS2
Chan interrupt. A timeout event or writing this bit
low will not cause an interrupt.
RD_DATA
Note : When PS2_EN=1, bit-banging is disabled
for any of the following 3 conditions:
Time-out is active.
300us following a time-out (Hold Time).
RDATA_RDY = 1.
Read DATA bit: Reading this bit returns the
current level of the PS2 channel’s Serial DATA
pin. This bit is used for receiving bit-banged
data over the PS2 channel. Bit-banging of the
PS2 channel is enabled when the PS2_EN bit is
set to 0. To receive data properly using this bit,
PS2_EN must be set to 0 and the WR_DATA bit
in the PS2 Channel’s Control Register must be
set to 1.
SMSC PS/2 STATUS_2 REGISTERS
The PS/2_STATUS_2 Register supports the
RX_Busy indicators for each of the four PS/2
Channels (A - D) When a RX_BUSY bit is set
the associated channel is actively receiving
PS/2 data; when a RX_BUSY bit is clear the
channel is idle.
RD_CLK
Read CLK bit: Reading this bit returns the
current level of the PS2 channel’s Serial CLK
TABLE 138 - SMSC PS/2_STATUS_2 REGISTER
HOST ADDRESS`
0x7F48
8051 ADDRESS
VCC2
POWER
0x00
DEFAULT
HOST
TYPE
8051
TYPE
D7
-
D6
-
D5
-
D4
-
D3
-
D2
-
D1
-
D0
-
R
R
R
R
R
R
R
R
224
PROGRAMMER’S NOTE:
Always check that an SMSC PS/2 channel is
idle, i.e. the RX_BUSY bit is ”0”, before
attempting to transmit on that channel. Receive
data may or may not be lost by setting an
SMSC PS/2 channel to transmit while the
RX_BUSY bit is asserted depending where in
the message frame the tranmit mode change
occurs.
3)
DEVIL LOGIC OVERVIEW
The Devil PS/2 logic allows the host to
communicate to any serial auxiliary devices
compatible with the PS/2 interface through any
one of four ports: EM, KB, IM and PS2. There
are two identical PS/2 channels, each containing
a set of five operating registers. Channel 1
(PS/2 Port 1) consists of ports EM and KB and
channel 2 (PS/2 Port 2) consists of ports IM and
PS2. The FDC37N972 latches data on the high
to low transition of the clock.
THE DEVIL PS/2 LOGIC COMMANDS
The Devil PS/2 logic supports three commands:
Transmit, Receive, and Inhibit.
Notes:
1)
2)
4)
counter will reset and you will either get
receive time-outs (all bits not received
within 2 ms), or you will get parity errors. If
there is a receive error, the BUSY bit can be
used to determine which device was
sending when the error occurred. If there is
a transmit error, the ENABLE bit in the
Control register can be used to determine
which device was selected.
If your PS/2 code is interrupt driven, is best
to send the inhibit command while the
interrupts are enabled so any byte being
received can finish and get picked up by the
interrupt handler.
This is necessary
because a receive may have been in
progress when the Inhibit command was
issued, and a receive will complete if the
parity bit is reached.
If there is a Request To Send (RTS) timeout or other condition which results in no
byte being received from the DEVIL PS/2
device, there will be no device 'data ready'
flag set in the status register. It will be
necessary to read the device enable bits in
the status register, or use some other
means to remember which.
THE
DEVIL
COMMAND
The hardware state machine requires that
you read any pending command response
byte from the input register before you send
an Inhibit command to the device. Since
only one response byte is allowed to be
automatically received, there is no need to
inhibit the port before you read the
response.
After sending a Transmit or Receive
command to the Control register, do not
read the status register until the PS/2
Interrupt Flag is set. If you read the status
register to check the BUSY bits, the bit
225
PS/2
LOGIC
TRANSMIT
The Devil PS/2 serial protocol requires that the
auxiliary device respond to all transmissions
that it receives. The response is usually a 0xFA
, 0xFE, 0xFC or 0xEE. The response is stored
in the DEVIL PS/2 ports RECEIVE register.
Thus, after each transmission the RECEIVE
register should contain some response byte.
When sending a byte to a DEVIL PS/2 device,
Two writes to the control register are required to
avoid race conditions: first the device select
bit(s) (bits[4:3]) in the control register must be
set, clearing the command bits[2:0]; then
another write to the control register selecting
ONE command, and preserving the device
select bits. The DEVIL PS/2 logic will assume
that the byte being sent is a 'command', and will
automatically go into receive mode for a single
response byte. The DEVIL PS/2 logic must be
placed into receive mode to receive additional
response bytes. An error will be reported if the
device does not start clocking out the command
byte within 15 ms, or if the device does not send
a response within 32 ms of receiving the
command. The DEVIL PS/2 logic will cause an
interrupt after the response byte is received, or if
there is a send or receive time-out.
The DEVIL PS/2 logic drives the clock line low
and then floats the data line when the port is
selected to transmit. Writing to the TRANSMIT
register initiates the transmit operation. The
data line is driven low and, within 80ns, the
clock line is floated (externally pulled high by the
pull-up resistor).
The auxiliary device
recognizes this as the start bit, and responds by
providing the eleven clocks (each clock
corresponds to a bit). The Logic provides a
3.2µS bit hold time. If the auxiliary device did
not respond within 15 mS after the start bit,
transmit is terminated and ERROR bit of the
STATUS register and the RTSTIMOUT bit of the
ERROR register are set. The auxiliary device
has 2 ms to complete the transmission or the
DEVIL PS/2 logic will set the ERROR bit of the
STATUS register and the XMTTIMOUT bit of the
ERROR register.
If the transmission is
successful, the clock and data lines are floated
waiting for the auxiliary device to send the
response packet.
If the first byte of the
response packet is not received within 32 mS,
the ERROR bit of the STATUS register is set,
the RESTIMOUT bit of the ERROR register is
set. If, on the other hand, the response packet is
received and there are no errors, the DEVIL
PS/2 logic sets the READY bit of the STATUS
register, clears the ERROR bit of the STATUS
register, and clears the ERROR register. The
RECEIVE register contains the received
response byte.
226
THE DEVIL PS/2 LOGIC RECEIVE COMMAND
When receiving scan codes or mouse packets,
select one or both DEVIL PS/2 devices in the
Control register (bits[4:3]), clearing the
command bits[2:0]. Then do another write
setting the Receive command bit while
preserving the device select bits. The DEVIL
PS/2 logic will only let one device send at a
time (whichever starts sending first), and will
cause an interrupt for each received byte.
Reading the byte from the Receive register
causes the DEVIL PS/2 logic to go into receive
mode again.
The DEVIL PS/2 logic floats the DEVIL PS/2
port’s clock and data line when the port is
selected to receive.
The auxiliary device
initiates the transfer by driving the data line low
and 12µS later driving the clock low. The DEVIL
PS/2 Logic recognizes this as a start bit and
sets the BUSY bit.
The auxiliary device
proceeds by transmitting ten more bits to the
DEVIL PS/2 logic. The DEVIL PS/2 Logic
latches the data on the high to low transition of
the clock. After the stop bit, the DEVIL PS/2
Logic clears the BUSY bit and drives the clock
line low until the RECEIVE register is read by
the 8051. If there is no error in the transfer, the
DEVIL PS/2 logic sets the READY bit of the
STATUS register, clears the ERROR bit of
STATUS register, and clears the ERROR
register. If, however, the receive operation does
not complete in 2 ms of receiving a start bit, the
ERROR bit of the STATUS register is set
together with the RECTIMOUT bit of the
ERROR register, and the READY bit is not set.
Note that the logic can be left in receive mode
indefinitely and is normally used to receive
keyboard scan codes and mouse packets.
THE DEVIL PS/2 LOGIC INHIBIT COMMAND
When you abort a transmission from a DEVIL
PS/2 device, it is necessary to hold the clock
line low for at least 100 us in order for the
device to note that the transmission has been
aborted. This 100 us low clock time is called a
device 'Inhibit'. When you want to perform the
Inhibit command, select one or both DEVIL
PS/2 devices in the Control register, clearing the
command bits. Then do another write setting the
Inhibit command bit while preserving the device
select bits. The DEVIL PS/2 logic will hold the
device clock lines low and count down 100 us,
then it will generate an interrupt to indicate that
the time-out is over. The interrupt handler
should then clear the Inhibit command bit in the
Control register. After an Inhibit, the device
clock lines will remain low until the next
Transmit or Receive command.
Note that if the device is receiving a byte when
the Inhibit command is sent, and the parity bit
has already been started, the device will
complete the receipt and set the READY bit
before the inhibit takes effect, so it is necessary
to check for data even when the INHIBIT DONE
bit is set.
DEVIL PS/2 MEMORY MAPPED CONTROL
REGISTERS
Each Devil PS/2 channel has a separate set of
identical control registers: Control, Status, Error
Status, Transmit, and Receive. These are
shown in TABLE 86 between addresses 0x7F41
and 0x7F4F.
DEVIL PS/2 CONTROL REGISTERS
TABLE 139 - DEVIL PS/2 CONTROL REGISTERS (PORT1 & PORT2)
HOST ADDRESS
0x7F41 (PORT 1),
8051 ADDRESS
0x7F49 (PORT 2),
VCC2
POWER
0x00
DEFAULT
D7
HOST
TYPE
8051
TYPE
BIT
NAME
Port1
(Port2)
-
D6
-
R
Res
D5
-
R
Res
D4
-
R
Res
D3
-
D2
-
D1
-
D0
-
R/W
R/W
R/W
R/W
R/W
EM_EN
(IM_EN)
KB_EN
(PS2_EN)
Inhibit
RX_EN
TX_EN
227
Inhibit
0
0
0
0
0
0
1
TABLE 140 - PS/2 PORT1 (PORT2) CONTROL REGISTER OPERATION
EM_EN
KB_EN
RX_EN
TX_EN
(IM_EN)
(PS2_EN)
OPERATION STATUS
0
1
0
1
Transmission sent to Keyboard, echo
cmd received
0
1
1
0
Transmission sent to Ext Mouse, echo
cmd rcvd
0
1
1
1
Transmission inhibited, RTS_timeout
error,
(illegal state)
1
0
0
1
Data received from Keyboard,
Transmission initiated by Keyboard.
1
0
1
0
Data received from Mouse, Transmission
initiated by Mouse.
1
0
1
1
Data received from Keyboard and Mouse,
transmissions are initiated by Keyboard
and Mouse and interlaced to PS/2 Port1
receive register.
X
X
X
X
EM and KB PS/2 interfaces are disabled.
Data written to the PS2 Port1 transmit
register is not transmitted and no data is
received from the external Mouse or
Keyboard.
Notes:
1.
2.
The operation of the PS/2 Port2 control register is similar for the IM and PS/2 devices.
Only one of bits D2-D0 can be set to one.
228
DEVIL PS/2 STATUS REGISTERS
TABLE 141 - DEVIL PS/2 STATUS REGISTERS (PORT1 & PORT2)
HOST ADDRESS
0x7F42 (PORT 1),
8051 ADDRESS
0x7F4A (PORT 2),
VCC2
POWER
0x40
DEFAULT
HOST
TYPE
8051
TYPE
BIT
NAME
Port1
(Port2)
D7
-
D6
-
D5
-
D4
-
D3
-
D2
-
D1
-
D0
-
R
R
R
R
R
R
R
R
Res
Res
EM_busy
(IM_busy)
KB_busy
(PS2_busy)
Inhibit
done
EM_drdy
(IM_drdy)
KB_drdy
(PS2_drdy)
Error
ERROR
This bit is set in the event of a transmit or receive error condition on either the EM or KB PS/2 ports or
the IM or PS/2 ports. The cause of the error can be determined by reading the PS/2 Port1 or PS/2
Port2 Status register.
KB_DRDY
This bit is set if KB_EN is set and a character has been received successfully from the PS/2 KB port.
This bit is cleared when the data has been read from the PS/2 Port1 Receive register.
EM_DRDY
This bit is set if EM_EN is set and a character has been received successfully from the PS/2 EM port.
This bit is cleared when the data has been read from the PS/2 Port1 Receive register.
PS2_DRDY
This bit is set if PS2_EN is set and a character has been received successfully from the PS/2 port.
This bit is cleared when the data has been read from the PS/2 Port2 Receive register.
IM_DRDY
This bit is set if IM_EN is set and a character has been received successfully from the PS/2 IM port.
This bit is cleared when the data has been read from the PS/2 Port2 Receive register.
229
INHIBIT DONE
This bit is set when the INHIBIT bit of
sequence has finished.
the CONTROL register was set and the 100 uS inhibit
KB_BUSY
This bit is set when the PS/2 KB port is actively receiving a character.
EM_BUSY
This bit is set when the PS/2 EM port is actively receiving a character.
PS2_BUSY
This bit is set when the PS/2 port is actively receiving a character.
IM_BUSY
This bit is set when the PS/2 IM port is actively receiving a character.
Note:
1) On receive the BUSY bit is set while receiving the first data bit and cleared while receiving the
parity bit. On transmit, the BUSY bit is not set at all.
2) The operation of the PS/2 Port2 status register is similar for the IM and PS/2 devices.
230
DEVIL PS/2 ERROR STATUS
TABLE 142 - DEVIL PS/2 ERROR STATUS REGISTERS (PORT1 & PORT2)
HOST ADDRESS
0x7F43(PORT 1),
8051 ADDRESS
0x7F4B(PORT 2),
VCC2
POWER
0x00
DEFAULT
HOST
TYPE
8051
TYPE
BIT
NAME
D7
-
D6
-
D5
-
D4
-
D3
-
D2
-
D1
-
D0
-
R
R
R
R
R
R
R
R
Res
Res
Res
Parity
RES_
timeou
t
REC_
timeou
t
RTS_
timeou
t
XMT_
timeout
XMT_TIMEOUT
(Transmit_timeout) is set when the device fails to clock out a command within 2ms of clocking out the
start bit.
RTS_TIMEOUT
(ReadyToSend_timeout) is set when the device fails to start clocking out the command within 15 ms.
REC_TIMEOUT
(RECeiver_timeout) is set when the device does not finish sending a byte within 2 ms of sending the
start bit.
RES_TIMEOUT
(RESponse_timeout) is set when the response to a command is not received within 32 ms.
PARITY
The PS/2 ports use Odd parity, in the event of a receive parity error this bit is set.
231
DEVIL PS/2 TRANSMIT REGISTERS
TABLE 143 - DEVIL PS/2 TRANSMIT REGISTERS (PORT1 & PORT2)
HOST ADDRESS
0x7F44(PORT 1),
8051 ADDRESS
0x7F4C(PORT 2),
VCC2
POWER
0x00
DEFAULT
The byte written to the PS/2 Port1(Port2) Transmit register is immediately transmitted onto the
enabled PS/2 Port1/Port2 provided that the PS/2 Port1(Port2) Inhibit bit is not set and that both PS/2
Port1and Port2 devices are not enabled for transmit at the same time. This register is write only.
DEVIL PS/2 RECEIVE REGISTERS
TABLE 144 - DEVIL PS/2 RECEIVE REGISTERS (PORT1 & PORT2)
HOST ADDRESS
0x7F45(PORT 1),
8051 ADDRESS
0x7F4D(PORT 2),
VCC2
POWER
0x00
DEFAULT
If KB_EN, and/or EM_EN is set and PS/2 Port1 RX_EN is set any successfully received characters
over the KB and/or the EM PS/2 Port are placed into this register and the EM_drdy or KB_drdy PS/2
Port1 status bit is set. Similarly, if PS2_EN and/or IM_EN is set and PS/2 Port2 RX_EN is set any
successfully received characters over the PS2 and/or IM PS2 Ports are placed into this register and
the PS2_drdy or IM_drdy PS/2 Port2 status bit is set.
232
BACKGROUND
ACCESS.BUS
The FDC37N972
supports ACCESS.bus.
ACCESS.bus is a serial communication protocol
between a computer host and its peripheral
devices. It provides a simple, uniform and
inexpensive way to connect peripheral devices
to a single computer port. A single ACCESS.bus
on a host can accommodate up to 125
peripheral devices.
For a description of the ACCESS.bus protocol,
please refer to the ACCESS.bus Specifications
Version 2.2, February 1994, available from the
ACCESS.bus Industry Group (ABIG).
The ACCESS.bus interface is based on the
PCF8584 controller. The registers are mapped
into the 8051’s external memory mapped
register space. The addresses for the registers
are shown in TABLE 145 - ACCESS.BUS
REGISTER ADDRESSES.
The ACCESS.bus protocol includes a physical
layer based on the I2CTM serial bus developed by
Philips, and several software layers.
The
software layers include the base protocol, the
device driver interface, and several specific
device protocols.
TABLE 146 - ACCESS.BUS REGISTER ADDRESSES
ADDRESS (NOTE 1)
ACCESS RIGHTS
REGISTER
7F31h
W
Control
7F31h
R
Status
7F32h
R/W
Own Address
7F33h
R/W
Data
7F34h
R/W (1)
Clock
Note:
S1
S1
S0’
S0
S2
These Registers are only directly accessible by the 8051 and reside within the 8051’s external
Memory Mapped Data address space.
Note 1: Bits 2 through 6 are read only reserved.
233
ACCESS.bus status information required for bus
access and/or monitoring.
REGISTER DESCRIPTION
The ACCESS.bus interface has four internal
register locations. Two of these, Own Address
register S0’ and Clock register S2, are used for
initialization of the chip. Normally they are only
written once directly after resetting of the chip.
The other two registers, the Data register S0,
and the Control/Status register S1, (which
functions as a double register) are used during
actual data transmission/reception. Register s0
performs all serial-to-parallel interfacing with the
ACCESS.bus.
Register
S1
contains
CONTROL
R/W
Bit Def
Status
R/W
Bit Def
D7
W
PIN
D7
R
PIN
ACCESS.BUS CONTROL/STATUS REGISTER
S1
The control/status register controls the
ACCESS.bus operation and provides status
information. This register has separate read
and write functions for all bit positions. The
write-only section provides register access
control and control over ACCESS.bus signals,
while
the
read-only
section
provides
ACCESS.bus status information.
ACCESS.BUS CONTROL/STATUS REGISTER S1:
D6
D5
D4
D3
D2
W
W
W
W
W
ES0
Reserved
Reserved
ENI
STA
D6
D5
D4
D3
D2
R
R
R
R
R
0
STS
BER
LRB
AAS
D1
W
STO
D1
R
LAB
D0
W
ACK
D0
R
nBB
enabled; communication with serial shift register
S0 is enabled and the S1 bus status bits are
made available for reading. With ESO = 0, bits
ENI, STA, STO and ACK of S1 can be read for
test purposes.
BIT DEFINITIONS
REGISTER S1 CONTROL SECTION
The write-only sections of S1 enables access
to registers S0, S1 and S2, and also control of
ACCESS.bus operation.
BIT 5 and 4 Reserved
BIT 7 PIN
BIT 3 ENI
Pending Interrupt Not. Writing the PIN bit to a
logic “1” deasserts all status bits except for the
nBB (Bus Busy) - nBB is not affected. The
PIN bit is a self-clearing bit. Writing this bit to
a logic “0” has no effect. This may serve as a
software reset function.
This bit enables the internal interrupt, nINT, which
is generated when the PIN bit is active (logic 0).
BIT 2 and 1 STA and STO
These bits control the generation of the
ACCESS.bus Start condition and transmission of
slave address and R/nW bit, generation of
repeated Start condition, and generation of the
STOP condition (see TABLE 147).
BIT 6 ESO
Enable Serial Output.
ESO enables or
disables the serial ACCESS.bus I/O. When
ESO is high, ACCESS.bus communication is
234
STA
1
STO
0
1
0
0
1
1
1
0
0
TABLE 147 - INSTRUCTION TABLE FOR SERIAL BUS CONTROL
PRESENT MODE
FUNCTION
OPERATION
SLV/REC
START
Transmit START+address, remain
MST/TRM if R/nW=0; go to MST/REC if
R/nW=1.
MST/TRM
REPEAT START Same as for SLV/REC
MST/REC;
STOP READ;
Transmit STOP go to SLV/REC mode;
MST/TRM
STOP WRITE
Note 1
MST
DATA
Send STOP, START and address after
CHAINING
last master frame without STOP sent;
Note 2
ANY
NOP
No operation; Note 3
Note 1: In master receiver mode, the last byte must be terminated with ACK bit high (‘negative
acknowledge’).
Note 2: If both STA and STO are set high simultaneously in master mode, a STOP condition followed
by a START condition + address will be generated. This allows ‘chaining’ of transmissions
without relinquishing bus control.
Note 3: All other STA and STO mode combinations not mentioned in TABLE 146 are NOPs.
bit is normally read in polled applications to
determine
when
an
ACCESS.bus
byte
transmission/reception is completed.
BIT 0 ACK
This bit must be set normally to logic “1”. This
causes the ACCESS.bus to send an
acknowledge automatically after each byte
(this occurs during the 9th clock pulse). The
bit must be reset (to logic “0”) when the
ACCESS.bus controller is operating in
master/receiver mode and requires no further
data to be sent from the slave transmitter.
This causes a negative acknowledge on the
ACCESS.bus, which halts further transmission
from the slave device.
When acting as transmitter, PIN is set to logic “1”
(inactive) each time S0 is written. In receiver
mode, the PIN bit is automatically set to logic “1”
each time the data register S0 is read.
After transmission or reception of one byte on the
ACCESS.bus (nine clock pulses, including
acknowledge) the PIN bit will be automatically
reset to logic “0” (active) indicating a complete
byte transmission/reception. When the PIN bit is
subsequently set to logic “1” (inactive) all status
bits will be reset to “0” on a BER (bus error)
condition.
REGISTER S1 STATUS SECTION
The read-only section of S1 enables access to
ACCESS.bus status information.
In polled applications, the PIN bit is tested to
determine when a serial transmission/reception
has been completed. When the ENI bit (bit 4 of
write-only section of register S1) is also set to
logic “1” the hardware interrupt is enabled. In this
case, the PI flag also triggers and internal
BIT 7 PIN
Pending Interrupt Not. This bit is a status flag
which is used to synchronize serial
communication and is set to logic
“0”
whenever the chip requires servicing. The PIN
235
interrupt (active low) via the nINT output each
time PIN is reset to logic “0”.
BIT 5 STS
When in slave receiver mode, this flag is asserted
when an externally generated STOP condition is
detected (used only in slave receiver mode).
When acting as a slave transmitter or slave
receiver, while PIN = “0”, the chip will suspend
ACCESS.bus transmission by holding the SCL
line low until the PIN bit is set to logic “1”
(inactive). This prevents further data from
being transmitted or received until the current
data byte in S0 has been read (when acting as
slave receiver) or the next data byte is written
to S0 (when acting as slave transmitter).
BIT 4 BER
Bus error; a misplaced START or STOP condition
has been detected. Resets nBB (to logic “1”;
inactive), sets PIN = “0” (active).
BIT 3 LRB/AD0
PIN BIT SUMMARY
Last Received Bit or Address 0 (general call) bit.
This status bit serves a dual function, and is valid
only while PIN=0: LRB holds the value of the last
received bit over the ACCESS.bus while AAS=0
(not addressed as slave). Normally this will be
the value of the slave acknowledgment; thus
checking for slave acknowledgment is done via
testing of the LRB.
ADO; when AAS = “1” (Addressed as slave
condition) the ACCESS.bus controller has been
addressed as a slave. Under this condition, this
bit becomes the AD0 bit and will be set to logic “1”
if the slave address received was the ‘general call’
(00h) address, or logic “0” if it was the
ACCESS.bus controller’s own slave address.
The PIN bit can be used in polled applications
to test when a serial transmission has been
completed. When the ENI bit is also set, the
PIN flag sets the internal interrupt via the nINT
output.
In transmitter mode, after successful
transmission of one byte on the ACCESS.bus
the PIN bit will be automatically reset to logic
“0” (active) indicating a complete byte
transmission.
In transmitter mode, PIN is set to logic “1”
(inactive) each time register S0 is written. In
receiver mode, PIN is set to logic “0” (inactive)
on completion of each received byte.
Subsequently, the SCL line will be held low
until PIN is set to logic “1”.
BIT 2 AAS
Addressed As Slave bit. Valid only when PIN=0.
When acting as slave receiver, this flag is set
when an incoming address over the ACCESS.bus
matches the value in own address register S0’
(shifted by one bit) or if the ACCESS.bus ‘general
call’ address (00h) has been received (‘general
call’ is indicated when AD0 status bit is also set to
logic “1”).
In receiver mode, when register S0 is read,
PIN is set to logic “1” (inactive).
In slave receiver mode, an ACCESS.bus
STOP condition will set PIN=0 (active).
PIN=0 if a bus error (BER) occurs.
BIT 6 RESERVED, Logic 0.
236
BIT 1 LAB
OWN ADDRESS REGISTER S0’
Lost Arbitration Bit. This bit is set when, in
multi-master operation, arbitration is lost to
another master on the ACCESS.bus.
When the chip is addressed as slave, this register
must be loaded with the 7-bit ACCESS.bus
address to which the chip is to respond. During
initialization, the own address register S0’ must be
written to, regardless whether it is later used. The
Addressed As Slave (AAS) bit in status register
S1 is set when this address is received (the value
in S0 is compared with the value in S0’). Note
that the S0 and S0’ registers are offset by one bit;
hence, programming the own address register S0’
with a value of 55h will result in the value AAh
being recognized as the chip’s ACCESS.bus slave
address.
BIT 0 NBB
Bus Busy bit.
This is a read-only flag
indicating when the ACCESS.bus is in use. A
zero indicates that the bus is busy, and access
is not possible. This bit is set/reset (logic
“1”/logic “0”) by Start/Stop conditions.
After reset, S0’ has default address 00h.
TABLE 148 - ACCESS.BUS OWN ADDRESS REGISTER S0
OWN
ADDR
R/W
Bit Def
D7
R/W
Reserved
D6
R/W
Slave
Address
6
D5
R/W
Slave
Address
5
D4
R/W
Slave
Address
4
DATA SHIFT REGISTER S0
Register S0 acts as serial shift register and read
buffer interfacing to the ACCESS.bus. All read
and write operations to/from the ACCESS.bus
are done via this register. ACCESS.bus data is
always shifted in or out of shift register S0.
D3
R/W
Slave
Address
3
D2
R/W
Slave
Address
2
D1
R/W
Slave
Address
1
D0
R/W
Slave
Address
0
acknowledge phase. Further reception of data
is inhibited (SCL held low) until the S0 data shift
register is read.
In the transmitter mode data is transmitted to
the ACCESS.bus as soon as it is written to the
S0 shift register if the serial I/O is enabled
(ESO=1).
In receiver mode the ACCESS.bus data is
shifted into the shift register until the
DATA
R/W
TABLE 149 - ACCESS.BUS DATA REGISTER S0
D7
D6
D5
D4
D3
D2
D1
R/W
R/W
R/W
R/W
R/W
R/W
R/W
CLOCK REGISTER S2
Register S2 controls the selection of the internal
chip clock frequency used for the ACCESS.bus
block. This determines the SCL clock frequency
237
D0
R/W
generated by the chip. The selection is made
via Bits[2:0] (see Table 151 - INTERNAL
CLOCK RATES AND ACCESS.BUS DATA
RATES).
8051 R/W
TABLE 150 - ACCESS.BUS CLOCK REGISTER
D7
D6-D2
D1
D0
R/W
R
R/W
R/W
AB_RST
Reserved 00 - clock off (default)
(Note 1)
01 - 32 kHz clock
10 - 8051 clock
11 - 24 MHz clock (see table below)
Note 1: ACCESS.bus Reset, not self-clearing, must be written high and then written low. Bit 7
AB_RST: (ACCESS.bus Reset) setting this bit re-initializes all logic and registers in the ACCESS.bus
block.
TABLE 151 - INTERNAL CLOCK RATES AND ACCESS.BUS DATA RATES
ACCESS
BUS
DATA
NOMINAL
NOMINAL
MINIMUM
CLOCK
CLOCK RATE
RATE
HIGH
LOW
HIGH
D[1-0]
00
Off
10
Ring Osc
f/240
96/f
144/f
18/f
Ring Osc=4 MHz
16.7 kHz
24µs
36µs
4.5µs
Ring Osc=6 MHz
25 kHz
16µs
24µs
3µs
Ring Osc=8 MHz
33.3 kHz
12µs
18µs
2.25µs
10
12MHz
50 kHz
8µs
12µs
4µs
10
14.3 MHz
60 kHz
6.7µs
10.1µs
4µs
10
16 MHz
67 kHz
6µs
9µs
4µs
11
24 MHz
100 kHz
4µs
6µs
4µs
f = frequency of the ring oscillator.
ACCESS.BUS INTERFACE DESCRIPTION
The ACCESS.Bus interface is fully and directly
controlled by the on-chip 8051 through its set of
on-chip memory mapped control registers. The
ACCESS.bus logic is based on the PCF8584
238
I2C controller and is powered on the VCC1
powerplane to provide the ability to wake-up the
8051 on an ACCESS.bus event.
MEMORY MAPPED CONTROL REGISTERS
TABLE 152 - ACCESS.BUS CONTROL REGISTER
Host
N/A
8051
0x7F31 (W)
Power
VCC1
Default
0x00
8051 R/W
Bit Def
D7
W
PIN
D6
W
ES0
D5
W
Reserved
D4
W
Reserved
D3
W
ENI
D2
W
STA
D1
W
STO
D0
W
ACK
Bit 7 PIN: Pending Interrupt Not - Writing this bit to a logic “1” deasserts all status bits except for nBB
(Bus
Busy), nBB is not affected. This is a self-clearing bit. Writing this bit to a logic “0” has no effect.
TABLE 153 - ACCESS.BUS STATUS REGISTER
Host
N/A
8051
0x7F31 (R)
Power
VCC1
Default
0x81
8051 R/W
Bit Def
D7
R
PIN
D6
R
0
D5
R
STS
D4
R
BER
D3
R
LRB
D2
R
AAS
D1
R
LAB
D0
R
NBB
ACCESS.BUS OWN ADDRESS REGISTER
Host
N/A
8051
0x7F32
Power
VCC1
Default
0x00
8051
R/W
Bit
Def
D7
R/W
D6
R/W
D5
R/W
D4
R/W
D3
R/W
D2
R/W
D1
R/W
D0
R/W
Reserved
Slave
Address
6
Slave
Address
5
Slave
Address
4
Slave
Address
3
Slave
Address
2
Slave
Address
1
Slave
Address
0
239
ACCESS.BUS DATA REGISTER
Host
N/A
8051
0x7F33
Power
VCC1
Default
0x00
8051 R/W
D7
R/W
D6
R/W
D5
R/W
D4
R/W
D3
R/W
D2
R/W
D1
R/W
D0
R/W
ACCESS.BUS CLOCK REGISTER
Host
N/A
8051
0x7F34
Power
VCC1
Default
0x00
8051 R/W
D7
R/W
AB_RST*
ACCESS.BUS CLOCK
D6-D2
D1
R
R/W
Reserved 00 - clock off (default)
10 - 8051 clock
11 - 24 MHz clock
D0
R/W
(*) ACCESS.bus Reset, not self-clearing, must be written high and then written low.
Bit 7 AB_RST: (ACCESS.bus Reset) setting this bit re-initializes all logic and registers in the
ACCESS.bus block.
ACCESS.
bus CLOCK
D[1:0]
00
10
10
10
10
11
TABLE 154 - ACCESS.BUS CLOCK RATES
DATA
NOMINAL
NOMINAL
CLOCK RATE
RATE
HIGH
LOW
Off
Ring Osc
Ring Osc=4 MHz
Ring Osc=6 MHz
Ring Osc=8 MHz
12 MHz
14.3 MHz
16 MHz
24 MHz
f/240
16.7 kHz
25 kHz
33.3 kHz
50 kHz
60 kHz
67 kHz
100 kHz
f = frequency of the ring oscillator.
240
96/f
24µs
16µs
12µs
8µs
6.7µs
6µs
4µs
144/f
36µs
24µs
18µs
12µs
10.1µs
9µs
6µs
MINIMUM
HIGH
18/f
4.5µs
3µs
2.25µs
4µs
4µs
4µs
4µs
SECOND I2C BUS INTERFACE
OVERVIEW
A second I2C controller (ACCESS.bus 2) is in
the FDC37N972. ACCESS.bus 2 is powered by
VCC1. There are 5 Memory-Mapped Control
Registers to support the ACCESS.bus 2
controller (TABLE 155 to TABLE 159).
The two ACCESS.bus 2 controller pins,
AB2_DATA and AB2_CLK, are multiplexed on
GPIO11 and GPIO12 (see MULTIFUNCTION
PIN on page 271). An I2C input clock divider bit
D2 is added to the ACCESS.bus CLOCK
registers (see section 0 I2C Clock Divider BIT,
below).
MEMORY MAPPED CONTROL REGISTERS
TABLE 155 - ACCESS.BUS 2 CONTROL REGISTER
HOST
ADDRESS
8051 ADDRESS
POWER PLANE
DEFAULT
0x7F67 (W)
VCC1
0x00
HOST
TYPE
8051
TYPE
BIT
NAME
D7
-
D6
-
D5
-
D4
-
D3
-
D2
-
D1
-
D0
-
W
W
W
W
W
W
W
W
PIN
ES0
RESERVED
ENI
STA
STO
ACK
TABLE 156 - ACCESS.BUS 2 STATUS REGISTER
HOST
ADDRESS
8051 ADDRESS
POWER PLANE
0x7F67 (R)
VCC1
HOST
TYPE
8051
TYPE
BIT
NAME
DEFAULT
0x81
D7
-
D6
-
D5
-
D4
-
D3
-
D2
-
D1
-
D0
-
R
R
R
R
R
R
R
R
PIN
0
STS
BER
LRB
AAS
LAB
nBB
241
TABLE 157 - ACCESS.BUS 2 OWN ADDRESS REGISTER
HOST ADDRESS 8051 ADDRESS
POWER PLANE
DEFAULT
0x7F68
VCC1
0x00
HOST
TYPE
8051
TYPE
BIT
NAME
D7
-
D6
-
D5
-
D4
-
D3
-
D2
-
D1
-
D0
-
R
R/W
R/W
R/W
R/W
R/W
R/W
R/W
RESER
VED
SLAVE
ADDR.
6
SLAVE
ADDR.
5
SLAVE
ADDR.
4
SLAVE
ADDR.
3
SLAVE
ADDR.
2
SLAVE
ADDR.
1
SLAVE
ADDR.
0
TABLE 158 - ACCESS.BUS 2 DATA REGISTER
HOST ADDRESS
8051 ADDRESS
POWER PLANE
0x7F69
VCC1
HOST
TYPE
8051
TYPE
BIT
NAME
DEFAULT
0x00
D7
-
D6
-
D5
-
D4
-
D3
-
D2
-
D1
-
D0
-
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
D7
D6
D5
D4
D3
D2
D1
D0
TABLE 159 - ACCESS.BUS 2 CLOCK REGISTER
HOST ADDRESS
8051 ADDRESS
POWER PLANE
DEFAULT
0x7F6A
VCC1
0x00
HOST
TYPE
8051
TYPE
BIT
NAME
D7
-
D6
-
D5
-
D4
-
D3
-
D2
-
D1
-
D0
-
R/W
R
R
R
R
R
R/W
R/W
AB_RST
RESERVED
CLK_D
IV
CLOCK SELECT
242
I2C CLOCK DIVIDER BIT
An input clock divider bit D2 is added to the ACCESS.bus CLOCK registers 0x7F34 (TABLE 160) and
0x7F6A (TABLE 159). The clock divider bit CLK_DIV affects all I2C clock inputs. When CLK_DIV is
“1”, the I2C input clock is divided by 2. When CLK_DIV is “0”, the I2C input clock is not divided.
TABLE 160 - ACCESS.BUS 1 CLOCK REGISTER
n/a
HOST ADDRESS
0x7F34
8051 ADDRESS
VCC1
POWER
0x00
DEFAULT
HOST
TYPE
8051
TYPE
BIT
NAME
D7
-
D6
-
D5
-
D4
-
D3
-
D2
-
D1
-
D0
-
R/W
R
R
R
R
R/W
R/W
R/W
AB_RST
RESERVED
CLK_DIV
CLOCK SELECT
CLOCK SELECT ENCODING
The encoding for the two CLOCK SELECT bits is shown in Table 161. The CLOCK SELECT bits are
located in the ACCESS.bus 1 Clock Register (TABLE 160) and the ACCESS.bus 2 Clock Register
(TABLE 159).
TABLE 161 - ACCESS.BUS CLOCK SELECT BIT ENCODING
CLOCK
SELECT BITS
FDC37N972
D1
D0
0
0
CLOCK OFF
0
1
RESERVED
1
0
8051 CLOCK
1
1
24 MHz CLOCK
243
MAILBOX REGISTER INTERFACE
OVERVIEW
The Mailbox Registers Interface provides a
standard run-time mechanism for the host to
communicate with the 8051 and other logical
components in the FDC37N972. The Mailbox
Registers Interface includes a total of 44 indexaddressable 8-bit registers (TABLE 162) and
two 8-bit host access ports (TABLE 164).
Thirty-two of these 44 registers are 8051
Mailbox registers.
The Mailbox Registers Interface host access
ports are run-time registers that occupy two
addresses in the system I/O space. The access
ports are used by the host to read and write the
44 registers. The access ports base address is
determined by the Mailbox Registers Interface
Base Address that is initialized in Logical Device
Number 9 in FDC37N972 configuration registers
CR60 and CR61 (TABLE 163).
The 32 Mailbox registers as well as the PWM0,
PWM1, and Fan Control registers are directly
addressable by the 8051 through MemoryMapped Control Registers (see TABLE 86 8051 ON-CHIP EXTERNAL MEMORY MAPPED
REGISTERS on page 159).
In this
specification, the registers in the Mailbox
Registers Interface are identified by the prefix
MBX in front of a hexadecimal index address.
TABLE 162 below summarizes the 44 registers
in the Mailbox Registers Interface.
TABLE 162 - MAILBOX REGISTERS INTERFACE
System-to8051
Mailbox
register 0
8051-tosystem
Mailbox
register 1
Mailbox
register [2F]
PWM0
register
PWM1
register
8051STP_
CLK
HMEM
ESMI
source
register
ESMI mask
MAILBOX
INDEX
ADDRESS
N
O
T
E
S
2
3
MBX82h
SYSTEM
R/W
R/W
8051
ADDR.
(7F00+)
08h
8051
R/W
RC
POWER
PLANE
VCC1
VCC
1
POR
00
1
MBX83h
RC
09h
R/W
VCC1
00
Y
14
MBX 84h91h
R/W
0Ah 17h
R/W
VCC1
00h
Y
1
MBX92h
R/W
25h
R/W
VCC1
00h
Y
1
MBX93h
R/W
26h
R/W
VCC1
00h
Y
1
MBX94h
R/W
-
-
VCC1
00h
Y
4
1
MBX95h
R/W
-
-
VCC1
07h
07h
Y
4
,
5
1
MBX96h
R/W
-
-
VCC2
00h
Y
1
MBX97h
R/W
-
-
VCC2
00h
Y
TOTAL
REGS.
1
244
VCC
2
POR
ZERO
WAIT
STATE
(1)
Y
TOTAL
REGS.
register
IR data
register
Force Disk
Change
register
Floppy
Data Rate
Select
Shadow
register
UART1
FIFO
Control
Shadow
register
UART2
FIFO
Control
Shadow
register
Fan Control
Register
Mailbox
Register
[10-1F]
MAILBOX
INDEX
ADDRESS
SYSTEM
R/W
8051
ADDR.
(7F00+)
8051
R/W
POWER
PLANE
VCC
1
POR
VCC
2
POR
ZERO
WAIT
STATE
(1)
1
MBX98h
R/W
-
-
VCC2
00h
Y
1
MBX99h
R/W
-
-
VCC2
03h
Y
1
MBX9Ah
R
-
-
VCC2
N/A
Y
1
MBX9Bh
R
-
-
VCC2
00h
Y
1
MBX9Ch
R
-
-
VCC2
00h
Y
1
MBX9Dh
R/W
28h
R/W
VCC1
0x30
Y
16
MBX
A0h-AFh
R/W
70h –
7Fh
R/W
VCC1
00h
Y
N
O
T
E
S
44
NOTES:
1. When accessed for a read or write by the System the registers marked with a “Y” will drive the
Zero wait state pin active.
2. Interrupt is cleared when read by the 8051
3. Interrupt is cleared when read by the host
4. When IRESET_OUT is cleared (written from “1” to”0”) 8051STP_CLK bit D0 as well as HMEM
bits D1 and D0 are all set to “1”.
5. These registers are reset 500us to 1ms following the condition that BOTH VCC2 is valid and
PWRGD is asserted given that the RTC is in normal mode and the VRT bit is set (refer to the
RTC section). If the RTC is not in normal mode and/or the VRT bit is not set then these registers
are reset within 10us following the condition that BOTH VCC2 is valid and PWRGD is asserted.
245
MAILBOX REGISTERS INTERFACE BASE
ADDRESS
Logical Device 9 in the FDC37N972
configuration space supports the Mailbox
Registers Interface.
The three device
configuration registers in LDN9 provide
activation control and the base address for the
Mailbox Registers Interface run-time registers
(TABLE 163).
Register 0x30 is the Activate register. The
activation control (LDN9:CR30.0) qualifies
address decoding for the Mailbox Registers
Interface; e.g., if the Activate bit D0 in the
Activate register is “0”, the MBX access port
addresses will not be decoded; if the Activate bit
is “1”, MBX access port addresses will be
decoded depending on the values programmed
in the MBX Primary Base Address registers.
Registers 0x60 and 0x61 are the MBX Primary
Base Address registers. Register 0x60 is the
MBX Primary Base Address High Byte, register
0x61 is the MBX Primary Base Address Low
Byte.
NOTE: Bit D0 in the MBX Primary Base Address
Low Byte must be “0”. Valid Mailbox Registers
Interface Base Address values are 0x0000 –
0x0FFE.
TABLE 163 - MAILBOX REGISTERS INTERFACE CONFIGURATION CONTROLS (LDN9)
INDEX
TYPE
HARD
RESET
SOFT
RESET
VCC2
POR
VCC1
&
VCC0
POR
D7
0x30
0x60
R/W
R/W
0x00
0x00
0x00
0x00
0x00
0x00
-
-
R/W
0x00
0x00
0x00
-
D5
DESCRIPTION
D4
D3
D2
D1
Activate
RESERVED
D0
Act
iva
te
MBX Primary Base Address High Byte
“0”
0x61
D6
“0”
“0”
“0”
A1
1
A1
0
A9
A8
MBX Primary Base Address Low Byte
A7
A6
A5
A4
A3
A2
A1
“0”
MAILBOX REGISTERS INTERFACE ACCESS PORTS
The Mailbox registers access ports are runtime registers that occupy two addresses in the Host I/O
space (TABLE 164).
To access a Mailbox register once the Mailbox Registers Interface Base Address has been initialized,
write the Mailbox register index address to the MBX Index port and read or write the Mailbox register
data from the MBX data port.
246
TABLE 164 - MAILBOX REGISTERS INTERFACE ACCESS PORTS
ACCESS
HOST
POWER
VCC2
PORT NAME
HOST ADDRESS
TYPE
PLANE
POR
MBX INDEX
MBX Base Address
R/W
VCC2
0x00
MBX DATA
MBX Base Address + 1
R/W
VCC2
-
MAILBOX REGISTERS
There are 32 Mailbox Registers in the
FDC37N972. The MBXA0–AF and MBX84– 91
Mailbox Registers are general purpose registers.
There are no interrupts for these registers.
THE SYSTEM/8051 INTERFACE REGISTERS`
Mailbox Register 0, System-to-8051, and
Mailbox Register 1, 8051-to-System, are
specifically designed to pass commands
between the host and the 8051 (FIGURE 35). If
enabled, these registers can generate interrupts.
Mailbox Register 0 and Mailbox Register 1 are
not dual-ported, so the System BIOS and
Keyboard BIOS must be designed to properly
share these registers. When the host performs
a write of the System-to-8051 mailbox register,
an 8051 INT1 will be generated and seen by the
8051 if unmasked. When the 8051 writes to the
247
VCC1
POR
-
System-to-8051 mailbox register, the data is
blocked but the write forces the register to 0x00,
providing a simple means for the 8051 to inform
that host that an operation has been completed.
When the 8051 writes the 8051-to-System
mailbox register, an SMI may be generated and
seen by the host if unmasked. When the Host
CPU writes to the 8051-to-System mailbox
register, the data is blocked but the write forces
the 8051-to-System register to clear to zero,
providing a simple means for the host to inform
that 8051 that an operation has been completed.
PROGRAMMER’S NOTE: The protocol used to
pass commands back and forth through the
Mailbox Registers Interface is left to the system
designer. SMSC can provide an application
example of working code in which the host uses
the Mailbox registers to gain access to all of the
8051 registers.
System-to-8051
8051-to-System
INT1
SMI
32 8-bit
Mail-Box
Registers
HOST CPU
8051
FIGURE 35 - SYSTEM-TO-8051 MAILBOX INTERFACE REGISTERS BLOCK DIAGRAM
Mailbox Register 0: System-to-8051
If enabled, an INT1 will be generated when the System writes to Mailbox Register 0 (TABLE 165). The
interrupt source bit will be cleared when the 8051 reads this register.
After reading Mailbox Register 0, the 8051 can clear the register to “00H” by a dummy write to inform
the host that the register contents have been read.
TABLE 165 - MAILBOX REGISTER 0 (SYSTEM-TO-8051)
MAILBOX INDEX 8051 ADDRESS
POWER PLANE
DEFAULT
0x82
0x7F08
VCC1
0x00
MBX
1
TYPE
8051
TYPE
BIT
NAME
D7
RC
D6
RC
D5
RC
D4
RC
D3
RC
D2
RC
D1
RC
D0
RC
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
D7
D6
D5
D4
D3
D2
D1
D0
NOTE1 RC = Read-only register is cleared when written.
Mailbox Register 1: 8051-to-system
If enabled, an SMI will be generated when the 8051 writes to Mailbox Register 1 (TABLE 166). The
SMI interrupt will be cleared when the host reads this register.
248
After reading Mailbox Register 1, the system can clear the register to “00H” by a dummy write to
inform the 8051 that the register has been read.
TABLE 166 - MAILBOX REGISTER 1 (8051-TO-SYSTEM)
MAILBOX INDEX 8051 ADDRESS
POWER PLANE
0x83
0x7F09
VCC1
MBX TYPE
8051 TYPE
1
BIT NAME
D7
RC
R/W
D7
D6
RC
R/W
D6
D5
RC
R/W
D5
D4
RC
R/W
D4
D3
RC
R/W
D3
D2
RC
R/W
D2
DEFAULT
0x00
D1
RC
R/W
D1
D0
RC
R/W
D0
NOTE1 RC = Read-only register is cleared when written.
LED CONTROLS
The FDC37N972 has three independent LED outputs that are programmable under 8051 control.
Host
8051
Power
Default
Default
8051
access
Bit def
LED REGISTER
N/A
0x7F21
VCC1
0x00
D7
0
R/W
D6
0
R/W
FDD Led
Enable
FDD_
FDD_
LED1
LED0
00 FDD LED is
off
01 LED flash;
P=1.0 sec
10 LED flash;
P=0.5 sec
11 LED is fully
on
Note 1
D5
0
R/W
D4
N/A
R
Status of
pin MODE
D3
0
R/W
D2
0
R/W
PWR_
PWR_
LED1
LED0
00 PWR LED is
off
01 LED flash;
P=3.0 sec
10 LED flash;
P=1.5 sec
11 LED is fully on
D1
0
R/W
D0
0
R/W
BAT_
BAT_
LED1
LED0
00 Battery LED
is off
01 LED flash;
P=1.0 sec
10 LED flash;
P=0.5 sec
11 LED is fully
on
Note 1: D7 =1; FDD_LED Pin is controlled by D6, D5, D7=0; FDD_LED is controlled by the Motor
Enable 0 pin from the FDC. When Motor Enable 0 pin is asserted the LED is on.
LED on time is T=125msec; “0” is on, “1” is off. Period “P” is indicated above.
249
P
T
FIGURE 36 - LED OUTPUT
PULSE WIDTH MODULATORS
OVERVIEW
In the FDC37N972 there are two independent programmable Pulse-Width Modulated Fan Speed
Controllers. The FDC37N972 PWM Fan Speed Controllers each include 11 fan speeds (FOUT), 6-bit
pulse-width resolution, and the ability to force the PWM outputs always high or low (TABLE 167 FAN SPEED CONTROL SUMMARY (STDBY CLOCK BIT = “0”). NOTE: each PWM Fan Speed
Controller in the FDC37N972 has two fan speeds, 7-bit pulse-width resolution, and can only force the
PWM output always low (when DCC = 0).
The FDC37N972 PWM Fan Speed Controllers can be driven by the system clock when VCC2 is
active, or by the 32.768kHz standby clock (RTC) that is available when either VCC2 or VCC1 are
active.
PROGRAMMER’S NOTE: the availability of the 32kHz standby clock is subject to the affects of the
RTC clock control bits.
The PWM Fan Speed Control and Fan Control registers are accessible to both the Host and the 8051
through the Mailbox register interface (see MAILBOX REGISTER INTERFACE on page 249).
250
TABLE 167 - FAN SPEED CONTROL SUMMARY (STDBY CLOCK BIT = “0”)
FANx
6-BIT
CLOCK
FANx
FANx
DUTY
FANx
FANx
DUTY
MULTICLOCK
CLOCK
CYCLE
STDBY
CLOCK
CYCLE
PLIER
SELECT 1
SELECT
FOUT6
CONTROL
CLOCK
CONTROL
(%)
BIT2
BIT3
0 BIT4
(DCC)
BIT5
BIT1
(kHz)
0
0
X
X
X
0 (low)
0
0
0
0
0
0
15.625
1-63
(DCC ÷
64)
0
0
0
0
1
23.438
× 100
0
0
0
1
0
.040
0
0
0
1
1
.060
0
0
1
0
0
31.25
0
0
1
0
1
46.876
0
0
1
1
0
.080
0
0
1
1
1
.120
0
1
X
X
X
0 (high)
TABLE 168 – FAN SPEED CONTROL SUMMARY (STDBY CLOCK BIT = “1”)
FANx
FANx
FANx
CLOCK
FANx
FANx
6-BIT DUTY
STDBY
CLOCK
MULTICLOCK
CLOCK
CYCLE
DUTY
CLOCK CONTROL
PLIER
SELECT
SELECT
FOUT6
CONTROL
CYCLE
BIT5
BIT1
BIT2
1 BIT3
0 BIT4
(kHz)
(DCC)
(%)
1
0
X
X
X
0 (low)
0
1
0
X
0
0
.032
1-63
(DCC ÷
64)
1
0
X
0
1
.064
× 100
1
0
X
1
0
.128
RESERVED
1
0
X
1
1
1
1
X
X
X
0 (high)
NOTE1
NOTE2
NOTE3
NOTE4
NOTE5
NOTE6
This is Fan Speed Control register bit 0
This is Fan Control register Bit 2 or Bit 3
This is Fan Control register Bit 0 or Bit 1
This is Fan Speed Control register Bit 7
This is Fan Control register Bit 4 or Bit 5
The FOUT frequency tolerance is 5%
There are two Fan Speed Control registers: PWM0 and PWM1. Both of these registers are located in
the FDC37N972 Mailbox Registers Interface. PWM0 is MBX92 and PWM1 is MBX93 (see MAILBOX
REGISTER INTERFACE on page 249).
The Fan Speed Control registers are in the FDC37N972 as shown in TABLE 169 and TABLE 170.
251
The default values for both the PWM0 and the PWM1 registers are 0x00. These defaults take effect
on VCC1 POR.
TABLE 169 - FAN 1 SPEED CONTROL REGISTER (PWM0)
MAILBOX INDEX
8051 ADDRESS
POWER PLANE
DEFAULT
0x92
0x7F25
VCC1
0x00
MBX
TYPE
8051
TYPE
BIT
NAME
D7
R/W
D6
R/W
D5
R/W
D4
R/W
D3
R/W
D2
R/W
D1
R/W
D0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
FAN
CLOCK
SELECT 0
DUTY CYCLE CONTROL
FAN CLOCK
CONTROL
TABLE 170 – FAN 2 SPEED CONTROL REGISTER (PWM1)
MAILBOX INDEX 8051 ADDRESS
POWER PLANE
DEFAULT
0x93
0x7F26
VCC1
0x00
MBX TYPE
8051 TYPE
BIT NAME
D7
R/W
R/W
D7
FAN
CLOCK
SELECT
0
D6
R/W
R/W
D5
R/W
R/W
D4
R/W
R/W
D6
D5
D4
DUTY CYCLE CONTROL
FAN CLOCK SELECT 0, D7
The Fan Clock Select 0 bit D7 in the Fan Speed
Control registers is used with the Fan Clock
Select 1 and the Fan Clock Multiplier bits in the
Fan Control register to determine the fan speed
FOUT.
NOTE: there are separate PWM0 and PWM1
Fan Clock Select 1 and Fan Clock Multiplier bits
in the Fan Control register (see Section 0 Fan
Control Register).
The affects of the Fan Clock Select[1:0] bits are
shown TABLE 167 - FAN SPEED CONTROL
252
D3
R/W
R/W
D3
D2
R/W
R/W
D2
D1
R/W
R/W
D1
D0
R/W
R/W
D0
FAN
CLOCK
CONTROL
SUMMARY (STDBY CLOCK BIT = “0”) and in
TABLE 168 – FAN SPEED CONTROL
SUMMARY (STDBY CLOCK BIT = “1”).
DUTY CYCLE CONTROL, D6 – D1
The Duty Cycle Control (DCC) bits determine
the PWM fan duty cycle. The FDC37N972 has
≈1.56% duty cycle resolution.
When DCC = “000000” (min. value), FOUT is
always low. When DCC is “111111” (max.
value), FOUT is almost always high; i.e., high for
th
th
63/64 and low for 1/64 of the FOUT period.
Generally, the FOUT duty cycle (%) is (DCC ÷ 64)
× 100.
Fan Clock Control, D0
The Fan Clock Control bit D0 is used to override
the Duty Cycle Control bits and force FOUT
always high.
When D0 = “0”, the DCC bits determine the FOUT
duty cycle. When D0 = 1, FOUT is always high,
regardless of the state of the DCC bits.
MBX
TYPE
8051
TYPE
BIT
NAME
The Fan Control register is MBX9D register (See
Mailbox Registers Interface (TABLE 171)). The
default value for the Fan Control Register is
0x30. The default value takes effect on VCC1
POR.
RESERVED bits in the Fan Control Register
cannot be written and return “0” when read.
Fan Control Register
MAILBOX INDEX
0x9D
The Fan Control register contains Fan Clock
Select 1, Fan Clock Multiplier, and Standby
Clock control bits for each of the two Fan Speed
Controllers PWM0 and PWM1.
TABLE 171 - FAN CONTROL REGISTER
8051 ADDRESS
POWER PLANE
0x7F28
VCC1
DEFAULT
0x30
D7
R
D6
R
D5
R/W
D4
R/W
D3
R/W
D2
R/W
D1
R/W
D0
R/W
R
R
R/W
R/W
R/W
R/W
R/W
R/W
FAN2
(PWM1)
STDBY
CLOCK1
FAN1
(PWM0)
STDBY
CLOCK1
FAN2
(PWM1)
CLOCK
MULTIPLIER
FAN1
(PWM0)
CLOCK
MULTIPLIER
FAN2
(PWM1)
CLOCK
SELECT
1
FAN1
(PWM0)
CLOCK
SELECT
1
RESERVED
NOTE1: The FANx STDBY CLOCK bits, D4 and D5, should not be switched when PWRGD is inactive;
i.e., when VCC2 = 0V.
253
FAN2 (PWM1) STDBY CLOCK, D5
FAN2 (PWM1) CLOCK MULTIPLIER, D3
The FAN2 (PWM1) STDBY CLOCK bit D5 is
used to determine the Fan2 controller clock
source.
The FAN2 Clock Multiplier bit D3 is used with
the FAN2 Clock Select 1 bit D1 and the PWM1
Clock Select 0 bit MBX93.7 to determine the
FAN2 FOUT when the FAN2 STDBY CLOCK
select bit is “0”.
When the FAN2 STDBY CLOCK bit = “1”, the
Fan2 controller clock source is the 32.768kHz
RTC clock (VCC1/VCC2). The available Fan2
FOUT frequencies when D5 = “1” are shown in
TABLE 167 - FAN SPEED CONTROL
SUMMARY (STDBY CLOCK BIT = “0”).
When the FAN2 STDBY CLOCK bit = “0”, the
Fan2 controller clock source is the system clock
(VCC2). The available Fan2 FOUT frequencies
when D5 = “0” are shown in TABLE 167 - FAN
SPEED CONTROL SUMMARY (STDBY
CLOCK BIT = “0”).
The FAN2 (PWM1) STDBY CLOCK bit default =
“1”.
FAN1 (PWM0) STDBY CLOCK, D4
The FAN1 (PWM0) STDBY CLOCK bit D4 is
used to determine the Fan1 controller clock
source.
When the FAN1 STDBY CLOCK bit = “1”, the
Fan1 controller clock source is the 32.768kHz
RTC clock (VCC1/VCC2). The available Fan1
FOUT frequencies when D4 = “1” are shown in
TABLE 167 - FAN SPEED CONTROL
SUMMARY (STDBY CLOCK BIT = “0”).
When the FAN1 STDBY CLOCK bit = “0”, the
Fan1 controller clock source is the system clock
(VCC2). The available Fan1 FOUT frequencies
when D4 = “0” are shown in TABLE 167 - FAN
SPEED CONTROL SUMMARY (STDBY
CLOCK BIT = “0”).
The FAN1 (PWM0) STDBY CLOCK bit default =
“1”.
254
When the FAN2 Clock Multiplier bit = “0”, no
clock multiplier is used. When the FAN2 Clock
Multiplier bit = “1”, the clock speed determined
by the FAN2 Clock Select [1:0] bits is doubled
(TABLE 167 - FAN SPEED CONTROL
SUMMARY (STDBY CLOCK BIT = “0”)).
The FAN2 Clock Multiplier bit does not affect the
FAN2 FOUT when the FAN2 STDBY CLOCK
select bit is “1”. Fan1 (PWM0) Clock Multiplier,
D2
The FAN1 Clock Multiplier bit D2 is used with
the FAN1 Clock Select 1 bit D0 and the PWM0
Clock Select 0 bit MBX92.7 to determine the
FAN1 FOUT when the FAN1 STDBY CLOCK
select bit is “0”.
When the FAN1 Clock Multiplier bit = “0”, no
clock multiplier is used. When the FAN1 Clock
Multiplier bit = “1”, the clock speed determined
by the FAN1 Clock Select [1:0] bits is doubled
(TABLE 167 - FAN SPEED CONTROL
SUMMARY (STDBY CLOCK BIT = “0”)).
The FAN1 Clock Multiplier bit does not affect the
FAN1 FOUT when the FAN1 STDBY CLOCK
select bit is “1”.
FAN2 (PWM1) CLOCK SELECT 1, D1
The FAN2 Clock Select 1 bit D1 is used with the
FAN2 Clock Multiplier bit D3 and the PWM1
Clock Select 0 bit MBX93.7 to determine the
FAN2 FOUT.
The affects of the Fan Clock Select [1:0] bits are
shown in TABLE 167 - FAN SPEED CONTROL
SUMMARY (STDBY CLOCK BIT = “0”) and
TABLE 168.
The affects of the Fan Clock Select [1:0] bits are
shown in TABLE 167 - FAN SPEED CONTROL
SUMMARY (STDBY CLOCK BIT = “0”) and
TABLE 168.
FAN1 (PWM0) CLOCK SELECT 1, D0
ESMI REGISTERS
The FAN1 Clock Select 1 bit D0 is used with the
FAN1 Clock Multiplier bit D2 and the PWM0
Clock Select 0 bit MBX92.7 to determine the
FAN1 FOUT .
The host cam enable/disable the SMI interrupts
generated as a result of the 8051 writing to
Mailbox register 1. The host can read the ESMI
source register to determine fo the FDC37N972
Mailbox interface was the cause of the SMI.
TABLE 172 - ESMI SOURCE REGISTER
MBX96
HOST ADDRESS
N/A
8051 ADDRESS
VCC2
POWER
0x00
DEFAULT
HOST
TYPE
8051
TYPE
BIT
NAME
D7
-
D6
-
D5
-
D4
-
D3
-
D2
-
D1
-
D0
-
R
R
R
R
R/W
R/
R/
R/
Reserved
Res
Res
Res
8051_WR
Res
Res
Res
8051_WR
This bit is set when a 8051-to-host mailbox has been written. This bit is cleared by a read of Mailbox
Register 1 (MBX83.)
TABLE 173 - ESMI MASK REGISTER
MBX97
HOST ADDRESS
N/A
8051 ADDRESS
VCC2
POWER
0x00
DEFAULT
HOST TYPE
8051 TYPE
BIT NAME
D7
R
Reserved
D6
R
Res
D5
R
Res
D4
R
Res
255
D3
R/W
ESMI_
MASK
D2
-
D1
-
D0
-
R
R
R/
Reserved
Reserved
Reserved
8051 is able to take control of the parallel port
interface. The 8051 has three memory mapped
registers that look like the host’s standard
parallel port registers (Status, Control, and
Data) with one exception: the 8051’s Parallel
Port Status register contains a write bit (bit 0)
that allows the 8051 to disconnect the interface
from the host and take control. Refer to the
Parallel Port section for more information.
ESMI_MASK
Setting this bit masks the 8051-to-host mailbox
SMI.
8051 CONTROLLED PARALLEL PORT
To facilitate activities such as reprogramming
the Flash Memory without opening the unit, the
From/to Host Parallel Port Interface
1
Parallel Port
From/to 8051 Parallel port interface
0
SEL 1
Parallel Port Connector
PP_HA
FIGURE 37 - PARALLEL PORT MULTIPLEXOR
256
OPERATION REGISTERS
The 8051 uses the following three memory mapped registers to gain access to and control the parallel
port interface.
PARALLEL PORT STATUS REGISTER
Host
N/A
8051
0x7F3A
Power
VCC2
Default
0x00
8051
R/W
System
R/W
Bit Def
D7
R
D6
R
D5
R
D4
R
D3
R
D2
R
D1
R
D0
R/W
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
nBUSY
nACK
PE
SLCT
nERR
0
0
PP_HA
1 = Host (or FDC)
controls the
Parallel Port
Interface.
0 = 8051 controls
the Parallel Port
Interface (default).
If 8051 access to the parallel port pins is enabled; The level of the parallel port status pins can be
read by reading this register.
Bit D7 (nBUSY):
Bit D6 (nACK):
Bit D5 (PE):
Bit D4 (SLCT):
Bit D3 (nERR):
reflects the inverse state of pin BUSY
reflects the current state of pin nACK
reflects the current state of pin PE
represents the current state of pin SLCT
reflects the current state of pin nERR
257
PARALLEL PORT CONTROL REGISTER
Host
N/A
8051
0x7F3B
Power
VCC2
Default
0x00
8051 R/W
System
R/W
Bit Def
D7
R/W
N/A
D6
R/W
N/A
D5
R/W
N/A
D4
R/W
N/A
D3
R/W
N/A
D2
R/W
N/A
D1
R/W
N/A
D0
R/W
N/A
0
0
PCD
0
SLCTIN
nINIT
ALF
STROBE
If 8051 access to the parallel port pins is enabled, the value of STROBE, ALF and SLCTIN are
inverted and output onto the parallel port control pins. The value of nINIT is output onto the parallel
port control pins. If PCD (Parallel Control Direction) = 0, the data bus is output. If PCD = 1 the
parallel port data bus is floating to allow read data in.
PARALLEL PORT DATA REGISTER
Host
N/A
8051
0x7F3C
Power
VCC2
Default
0x00
8051 R/W
System R/W
Bit Def
D7
R/W
N/A
PD7
D6
R/W
N/A
PD6
D5
R/W
N/A
PD5
D4
R/W
N/A
PD4
D3
R/W
N/A
PD3
D2
R/W
N/A
PD2
D1
R/W
N/A
PD1
D0
R/W
N/A
PD0
If 8051 access to the parallel port pins is enabled; When read, this register reads the logic levels on
the parallel port pins.
258
HOST CONTROLLED IR PORT
It is possible to give direct control of the IRRX
and IRTX pins to the Host CPU by setting bit 2
of the Multiplexing_1 Register. The Host
communicates to the pins through its memory
mapped IR Data Register shown here.
IR DATA REGISTER
Host
MBX 0x98
8051
N/A
Power
VCC2
Default
0x00
8051 R/W
System R/W
Bit Def
D7-D2
N/A
R/W
Reserved
D1
N/A
R
IR_REC
Bit 1 and bit 0 are don’t care if bit 2 of the
Multiplexing_1 Register is reset. (These bits are
multiplexed onto the IRTX and IRRX pins when
bit 2 of the Multiplexing Register is set).
Therefore, if the IR interface is on IRRX (pin 21)
and IRTX (pin 20), then MISC2 allows the IR
259
D0
N/A
R/W
IR_TX
interface to be switched between the IRCC 2.0
block and the IR Data Register.
Note that MISC7 allows the control of the COMRX/GPIO8 (pin 141) and COM-TX/GPIO9 (pin
142) pins. If the COM-RX and COM-TX pins are
used for IR, then this allows the IR interface
access to be switched between the IRCC 2.0
block and the 8051.
GENERAL PURPOSE I/O (GPIO)
The GPIO defaults are shown in TABLE 86 8051 ON-CHIP EXTERNAL MEMORY MAPPED
REGISTERS on page 159.
All General Purpose registers are powered by
VCC1. When GPIO6, GPIO10, OUT1, OUT5 OUT9, GPIO17, GPIO20, GPIO21, and KSO12
are configured as alternate function outputs and
PWRGD is inactive, i.e. VCC2 is 0v, these pins
will tri-state to prevent back-biasing of external
circuitry.
•
PROGRAMMER’S NOTE: The direction of
alternate function pins that are multiplexed with
general purpose I/O pins, i.e. where the GPIO
function is the default, is determined by the
GPIO direction bit. For example if the KS014
function of GPIO4 is selected, bit 4 in GPIO
Direction Register A must be set to “1”. This
rule does not apply to default non-GPIO pin
functions that may have a GPIO as an alternate
function.
GPIO9 defaults to “output”, “low”, for both
the default (GPIO) function and the
alternate (IRTX) function, regardless of the
state of PWRGD. This is done to prevent
infrared transceiver damage
OUTPUT EN
ALT FUNC
Control bit
nRD
nWR
ALT FUNC OUTPUT
1
GPIO OUT REG BIT
0
FIGURE 38 - OUTPUT PIN TYPE
260
OUT PIN
nRD
IN REG BIT
Wake-up Source Bit
nWR
IN PIN
Edge detector
Wake-up Mask Bit
Wake-up
IRQ
FIGURE 39 - INPUT PIN TYPE
nRD
nWR
GPIO DIR BIT
ALT FUNC
Control bit
ALT FUNC OUTPUT
1
GPIO OUT REG BIT
0
GPIO IN REG BIT
ALT FUNC INPUT
FIGURE 40 - GPIO PIN TYPE
261
GPIO PIN
MEMORY MAPPED CONTROL REGISTERS
GPIO DIRECTION REGISTER A
Host
N/A
8051
0x7F18
Power
VCC1
Default
0x00
Bit
Def
D7
GPIO7
1=output
0=input
D6
D5
D4
D3
D2
D1
D0
GPIO6
1=output
0=input
GPIO5
1=output
0=input
GPIO4
1=output
0=input
GPIO3
1=output
0=input
GPIO2
1=output
0=input
GPIO1
1=output
0=input
GPIO0
1=output
0=input
D2
status
of pin
GPIO2
D1
status
of pin
GPIO1
D0
status
of pin
GPIO0
D1
GPIO1
D0
GPIO0
GPIO INPUT REGISTER A
Host
N/A
8051
0x7F1A (R)
Power
VCC1
Default
N/A
Bit Des.
D7
status
of pin
GPIO7
D6
status
of pin
GPIO6
D5
status
of pin
GPIO5
D4
status
of pin
GPIO4
D3
status
of pin
GPIO3
GPIO OUTPUT REGISTER A
Host
N/A
8051
0x7F19
Power
VCC1
Default
0x00
Bit Des.
D7
GPIO7
D6
GPIO6
D5
GPIO5
D4
GPIO4
262
D3
GPIO3
D2
GPIO2
GPIO DIRECTION REGISTER B
Host
N/A
8051
0x7F1B
Power
VCC1
Default
0x00
Bit Def.
D7
D6
D5
D4
D3
D2
D1
D0
GPIO15
1=output
0=input
GPIO14
1=output
0=input
GPIO13
1=output
0=input
GPIO12
1=output
0=input
GPIO11
1=output
0=input
GPIO10
1=output
0=input
GPIO9
1=output
0=input
GPIO8
1=output
0=input
D2
GPIO
10
D1
GPIO
9
D0
GPIO
8
D2
status
of pin
GPIO10
D1
status
of pin
GPIO9
GPIO OUTPUT REGISTER B
1Host
N/A
8051
0x7F1C
Power
VCC1
Default
0x00
Bit Def.
D7
GPIO
15
D6
GPIO
14
D5
GPIO
13
D4
GPIO
12
D3
GPIO
11
GPIO INPUT REGISTER B
Host
N/A
8051
0x7F1D (R)
Power
VCC1
Default
N/A
Bit Def.
D7
status
of pin
GPIO15
D6
status
of pin
GPIO14
D5
status
of pin
GPIO13
D4
status
of pin
GPIO12
263
D3
status
of pin
GPIO11
D0
status
of pin
GPIO8
GPIO DIRECTION REGISTER C
Host
N/A
8051
0x7F1E
Power
VCC1
Default
0x00
Bit
Des.
D7
0
D6
0
D5
D4
D3
D2
D1
D0
GPIO21
1=output
0=input
GPIO20
1=output
0=input
GPIO19
1=output
0=input
GPIO18
1=output
0=input
GPIO17
1=output
0=input
GPIO16
1=output
0=input
GPIO OUTPUT REGISTER C
Host
N/A
8051
0x7F1F
Power
VCC1
Default
0x00
Bit Def.
D7
0
D6
0
D5
GPIO21
D4
GPIO20
D3
GPIO19
D2
GPIO18
D1
GPIO17
D0
GPIO16
GPIO INPUT REGISTER C
Host
N/A
8051
0x7F20 (R)
Power
VCC1
Default
N/A
Bit
Def.
D7
0
D6
0
D5
status of
pin
GPIO21
D4
status of
pin
GPIO20
264
D3
status of
pin
GPIO19
D2
status of
pin
GPIO18
D1
status of
pin
GPIO17
D0
status of
pin
GPIO16
OUT REGISTER D
Host
N/A
8051
0x7F22
Power
VCC1
Default
0x00
Bit Def.
D7
OUT7
D6
OUT6
D5
OUT5
D4
OUT4
D3
OUT3
D2
OUT2
D1
OUT1
D0
OUT0
OUT REGISTER E
Host
N/A
8051
0x7F23
Power
VCC1
Default
0x00
Bit Def.
D7
0
D6
0
D5
0
Host
8051
Power
Default
Bit Def.
D7
status
of pin
IN7
D6
status
of pin
IN6
D5
status
of pin
IN5
D4
0
D3
OUT11
D2
OUT10
D1
OUT9
D0
OUT8
IN REGISTER F
N/A
0x7F24 (R)
VCC1
N/A
D4
status
of pin
IN4
265
D3
status
of pin
IN3
D2
status
of pin
IN2
D1
status
of pin
IN1
D0
status
of pin
IN0
MULTIFUNCTION PIN
OVERVIEW
The FDC37N972 multifunction pins are mutliplexed on the following pins :
1.
2.
3.
4.
5.
6.
Multiplexing is required for nIRQ8.
PWM0 and PWM1 have independent multiplex controls.
Multiplexing is required for the Flash ROM address bit FA18.
Multiplexing is required for the Flash ROM chip select nFCS.
Multiplexing is required for the ACCESS.bus 2 interface pins AB2_DATA and AB2_CLK.
OUT0 can be an open-drain or push-pull driver.
Refer to TABLE 4 - ALTERNATE FUNCTION PINS on page 26 for a complete list of the FDC37N972
multifunction pins.
The 8051 firmware, alone, controls the multiplexing functions for each of the multiplexed pins
described in this section.
MULTIPLEXING_1 REGISTER
TABLE 174 - MULTIPLEXING_1 REGISTER
HOST ADDRESS
8051 ADDRESS
POWER PLANE
0x7F3D
VCC1
HOST
TYPE
8051
TYPE
BIT
NAME
DEFAULT
0x00
D7
-
D6
-
D5
-
D4
-
D3
-
D2
-
D1
-
D0
-
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
MISC7
MISC6
MISC5
MISC4
MISC3
MISC2
MISC1
MISC0
MISC7 – D7
The MISC7 bit is used in the FDC37N972 to select the pin function and the buffer mode between
GPIO8 – GPIO9 and IRRX and IRTX TABLE 175.
266
PIN
GPIO8
GPIO9
TABLE 175 - MISC7 BIT
MISC7 = 0 (DEFAULT) MISC7 = 1
GPIO8
IRCC BLOCK COM-RX PORT
GPIO9
IRCC BLOCK COM-TX PORT
MISC6 – D6
The MISC6 bit is used in the FDC37N972 to select the pin function and the buffer mode between
GPIO17 and GATEA20 (TABLE 176).
PIN
GPIO17
TABLE 176 - MISC6 BIT
MISC6 = 0 (DEFAULT) MISC6 = 1
GPIO17
GATEA20
MISC5 – D5
The MISC5 bit is used in the FDC37N972 to select the pin function and the buffer mode between
OUT5 and OUT6 and the FDC Floppy 1 drive controls nDS1 and nMTR1 (TABLE 177).
PIN
OUT5
OUT6
TABLE 177 - MISC5 BIT
MISC5 = 0 (DEFAULT) MISC5 = 1
OUT5
nDS1
OUT6
nMTR1
MISC4 – D4
The MISC4 bit is used in the FDC37N972 to select the pin function and the buffer mode between
OUT10 and PWM0 for the OUT10 pin (TABLE 178).
NOTE: This function only applies to the OUT10/PWM0 pin. The OUT11/PWM1 functions are selected
by MISC12 (Multiplexing_2 Register, below).
NOTE: The MISC4 bit in the FDC37C95X applies to both OUT10/PWM0 and OUT11/PWM1.
MISC4
0
1
TABLE 178 - MISC4 BIT
DESCRIPTION
OUT10 Pin Function Selected (DEFAULT)
PWM0 Pin Function Selected
MISC3 – D3
The MISC3 bit, along with the MISC1 bit, is used in the FDC37N972 to select the pin function and the
buffer mode between GPIO20 and GPIO21, the 8051 UART RX and TX, and the PS/2 CLK and DATA
(TABLE 179).
267
MISC[3,1]
[0,0] (DEFAULT)
[0,1]
[1,0]
[1,1]
TABLE 179 - MISC3 AND MISC1 BITS
PIN GPIO20
PIN GPIO21
GPIO20 + 8051_RX *
GPIIO21
PS2CLK
PS2DAT
GPIO20 + 8051_RX *
8051_TX **
PS2CLK
PS2DAT
GPIO20_DIR bit should be set to 0 when operating as an 8051_RX pin.
** GPIO21_DIR bit must be set to 1 when operating as an 8051_TX pin.
The PS/2 pins on GPIO20 and GPIO21 are disabled (internally pulled high) when the non-PS/2
alternate functions are selected. The PS/2 inputs under this condition are seen as a high to the PS/2
Device Interface logic.
Whenever a PS/2 channel is not enabled, the input signals to that channel must be high. The
FDC37N972 provides this through the use of weak pull-ups since the EM and KB channels share a
common receive path and THE IM AND PS2 CHANNELS ALSO SHARE A COMMON RECEIVE
PATH.
GPIO20_DIR
MISC1
PS2_CLK_OUT
1
GPIO20_OUT
0
GPIO20
GPIO20_IN
PS2_CLK_IN
8051_RX
FIGURE 41 - GPIO20 ALTERNATE FUNCTION STRUCTURE
268
GPIO21_DIR
MISC1
MISC3
8051_TX
1
GPIO21_OUT
0
0
GPIO21
1
PS2_DAT_OUT
GPIO21_IN
PS2_DAT_IN
FIGURE 42 - GPIO21 ALTERNATE FUNCTION STRUCTURE
MISC2 – D2
PIN
IRTX
IRRX
TABLE 180 - MISC2 BIT
MISC2 = 0 (DEFAULT)
MISC2 = 1
FROM IRCC BLOCK
FROM IR DATA REGISTER
FROM IRCC BLOCK
FROM IR DATA REGISTER
MISC1 – D1
See the description of the MISC3 bit, above.
NOTE: the MISC1 bit is not used with the MISC0 bit in the FDC37N972.
MISC0 – D0
The MISC0 bit is used in the FDC37N972 to select the pin function and the buffer mode between
OUT1 and nIRQ8 (TABLE 181).
MISC0
0
1
TABLE 181 - MISC0 BIT
DESCRIPTION
OUT1 Pin Function Selected (DEFAULT)
nIRQ8 Pin Function Selected
269
MULTIPLEXING_2 REGISTER
TABLE 182 - MULTIPLEXING_2 REGISTER
HOST ADDRESS
8051 ADDRESS
POWER PLANE
0x7F40
VCC1
HOST
TYPE
8051
TYPE
BIT
NAME
DEFAULT
0x00
D7
-
D6
-
D5
-
D4
-
D3
-
D2
-
D1
-
D0
-
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
MISC16
MISC15
MISC14
MISC13
MISC12
MISC11
MISC10
MISC9
MISC[16:15], D7 – D6
The function of the GPIO10 pin is RESERVED in the FDC37N972 when MISC[16:15] = 1,1 (TABLE
183).
NOTE: the FDC37N972 supports a single 16C550 UART interface.
TABLE 183 - MISC[16:15] BITS
MULTIPLEXING_2
REGISTER BITS[7:6]
SELECTED PIN FUNCTION
MISC16
MISC15
FDC37C95x
FDC37N972
0
0
GPIO10 (DEFAULT)
GPIO10 (DEFAULT)
0
1
IR_MODE
IR_MODE
1
0
IRRX3
IRRX3
1
1
nRTS2
RESERVED
MISC[14:13], D5 – D4
The MISC14 and MISC13 bits are used in the FDC37N972 to select the pin function and the buffer
mode between GPIO6 and the IrCC 2.0 IRMODE and IRRX3 functions (TABLE 184).
TABLE 184 - MISC14 AND MISC13 BITS
MISC[14:13]
PIN GPIO6
[0:0] (DEFAULT)
GPIO6
[0:1]
IR_MODE
(IRCC 2.0 GP DATA) OUTPUT
[1:0]
IRRX3 INPUT
[1:1]
RESERVED
270
MISC12 – D3
The MISC12 bit in the Multiplexing_2 register is used in the FDC37N972 to select the pin function and
buffer mode between OUT11 and PWM1 for the OUT11 pin (TABLE 185).
NOTE: The MISC12 bit in the FDC37C95X selects between GPIO functions and Serial Port 2. The
FDC37N972 supports a single 16C550 UART interface.
MISC12
0
1
TABLE 185 - MISC12 BIT
DESCRIPTION
OUT11 Pin Function Selected (DEFAULT)
PWM1 Pin Function Selected
MISC11
The MISC11 bit is used in the FDC37N972 to select the pin function and the buffer mode between
GPIO19, OUT9 and DMA Channel 3 (TABLE 186).
TABLE 186 - MISC11 BIT
MISC11
PIN OUT9
PIN GPIO19
0 (DEFAULT)
OUT9
GPIO19
1
DRQ3
nDACK3
MISC10
MISC17
0
0
0
1
1
1
1
TABLE 187 - MISC10, MISC17, AND MISC6 BITS
MISC10
MISC6
PIN OUT8
PIN KSO12
0
0
OUT8
KSO12
0
1
CPU_RESET
KSO12
1
X
DRQ2
KSO12
0
0
OUT8
OUT8
0
1
CPU_RESET
CPU_RESET
1
0
DRQ2
OUT8
1
1
DRQ2
CPU_RESET
With this definition, only the pair [OUT8 & CPU_RESET] can not simultaneously exist on pins OUT8
and KS012.
271
MISC10
MISC6
CPU_RESET
1
0
OUT8
OUT8
0
1
DRQ2
KSO12
1
KSO12
0
MISC17
FIGURE 43 - OUT8 AND KSO12 ALTERNATE FUNCTION OPERATION
MISC9
MISC9
0 (DEFAULT)
1
TABLE 188 - MISC9 BIT
PIN GPIO4
GPIO4
KSO14
GPIO5
GPIO5
KSO15
MULTIPLEXING_3 REGISTER
TABLE 189 - MULTIPLEXING_3 REGISTER
HOST ADDRESS
8051 ADDRESS
POWER PLANE
0x7F30
VCC1
HOST
TYPE
8051
TYPE
BIT
NAME
DEFAULT
0x00
D7
-
D6
-
D5
-
D4
-
D3
-
D2
-
D1
-
D0
-
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
MISC23
MISC22
MISC21
MISC20
MISC19
MISC18
MISC17
MISC8
MISC23 – D7
The buffer type for the GPIO7 pin can be programmed as push-pull or open-drain. This makes GPIO7
useful for other unique functions like nSCI and extended keyboard scan controls like KSO16. The
272
MISC23 bit is used in the FDC37N972 to select the buffer mode for the GPIO7 pin (TABLE 190 MISC23 BIT).
MISC23
0
1
TABLE 190 - MISC23 BIT
DESCRIPTION
Buffer Mode for GPIO7 is Push-Pull (DEFAULT)
Buffer Mode for GPIO7 is Open-Drain
MISC22 – D6
The MISC22 bit is used along with the MISC5 bit in Multiplexing_1 register to select the KBRST
alternate function #2 of the OUT5 pin (Table 191 - MISC22 BIT).
MISC5
1
0
0
MISC22
X
0
1
TABLE 191 - MISC22 BIT
DESCRIPTION
nDS1 Pin Function Selected.
OUT5 Pin Function Selected (DEFAULT)
KBRST Pin Function Selected
MISC21 – D5
The MISC21 bit is used in the FDC37N972 to select the buffer mode for the OUT0 pin (TABLE 192).
MISC21
0
1
TABLE 192 - MISC21 BIT
DESCRIPTION
Buffer Mode for OUT0 is Open-Drain (DEFAULT)
Buffer Mode for OUT0 is Push-Pull
MISC20 – D4
The MISC20 bit in the Multiplexing_3 register is used in the FDC37N972 to select the pin function and
buffer mode between GPIO and ACCESS.bus 2 functions for the GPIO11 and GPIO12 pins (TABLE
193).
MISC20
0
1
TABLE 193 - MISC20 BIT
DESCRIPTION
GPIO Pin Functions Selected (DEFAULT)
ACCESS.bus 2 Pin Functions Selected
MISC19 – D3
The MISC19 bit in the Multiplexing_3 register is used in the FDC37N972 to select the pin function and
buffer mode between nFCS and GPIO0 for the nFCS pin (TABLE 194).
273
TABLE 194 - MISC19 BIT
DESCRIPTION
nFCS Pin Function Selected (DEFAULT)
GPIO0 Pin Function Selected
MISC19
0
1
MISC18 – D2
The MISC18 bit in the Multiplexing_3 register is used in the FDC37N972, along with bit D3 in the
ESMI MASK register, to select the pin function and buffer mode for the OUT7 pin and the SMI transfer
mechanism to the host. (TABLE 195).
When MISC18 = ‘0’, the primary function of the OUT7 pin is selected and the SMI is routed to the
Serial IRQ interface. If the SMI is masked, SIRQ slot3 is available as IRQ2.
When MISC18 = ‘1’, the alternate nSMI function of the OUT7 pin is selected, the pad is driven opendrain, and the Serial IRQ slot3 is available as IRQ2.
TABLE 195 - MISC18 AND ESMI MASK BITS
ESMI MASK
REGISTER1
D3
0
0
MISC18
0
1
1
0
OUT7
IRQ2
1
1
nSMI
IRQ2
OUT7 PIN
OUT7
nSMI
FUNCTION
SIRQ SLOT3
nSMI
IRQ2
DESCRIPTION
SERIAL SMI (DEFAULT)
PARALLEL SMI, SERIAL IRQ
IRQ2 AVAILABLE
MASKED SERIAL SMI, IRQ2
AVAILABLE
PARALLEL SMI MASKED
(INACTIVE), IRQ2 AVAILABLE
NOTE1 The ESMI Mask register is MBX97h (TABLE 162).
MISC17 – D1
MISC17
0
1
TABLE 196 - MISC17
PIN GPIO18
PIN KSO13
GPIO18 +
KSO13
nDACK2 (1)
nDACK2
GPIO18
NOTE 1:nDACK2 can be received on the GPIO18 pin when MISC17 = 0 by setting the GPIO18
Direction bit to 0.
274
GPIO18_DIR
GPIO18_OUT
GPIO18
nDACK2
0
GPIO18_IN
1
MISC17
KSO13
1
KSO13
0
[ (MISC17=0) | (GPIO18_DIR & MISC17=1) ]
FIGURE 44 - GPIO18 AND KSO13 ALTERNATE FUNCTION OPERATION
MISC8 – D0
The MISC8 bit in the Multiplexing_3 register is used in the FDC37N972 to select the pin function and
buffer mode between FA18 and GPIO13 for the FA18 pin (TABLE 197).
NOTE: The MISC8 bit in the FDC37C95X selects between the GPIO16 function and MID1. The
FDC37N972 does not support the Media ID pins (see MID[1:0] FDD INTERFACE PINS on page 37).
MISC8
0
1
TABLE 197 - MISC8 BIT
DESCRIPTION
FA18 Pin Function Selected (DEFAULT)
GPIO13 Pin Function Selected
MISC8
0 (default)
1
PIN GPIO[16]
GPIO[16]
MID1
MISC17 is described in the Multiplexing_2 register section.
275
ACPI PM1 BLOCK
ACPI PM1 BLOCK OVERVIEW
The FDC37N972 supports ACPI as described in
this section. These features comply with the
ACPI Specification, Revision 1.0, through a
combination of hardware and 8051 software.
Block base address is relocatable depending on
the values programmed in FDC37N972
configuration registers CR60 and CR61 in
Logical Device Number 1.
The FDC37N972 implements the ACPI fixed
registers but includes only those bits that apply
to the power button sleep button and RTC alarm
events. The ACPI WAK_STS, SLP_TYPx, and
SLP_EN bits are also supported.
The functions described in the following subsections can generate a SCI event on the
nEC_SCI pin. In the FDC37N972, an SCI event
is considered the same as an ACPI wakeup or
runtime event. The 8051 can also generate a
SCI on the nEC_SCI pin by setting the
8051_SCI_STS bit in the 8051_PM_STS
register (see nEC_SCI INTERFACE on page
287).
The registers in the FDC37N972 ACPI PM1
Block occupy eight addresses in the host I/O
space and are specified as offsets from the
ACPI PM1 Block base address. The ACPI PM1
ACPI PM1 BLOCK SCI EVENT-GENERATING FUNCTIONS
Power Button With Override
The power button has a status and an enable bit
in the PM1_BLK of registers to provide an SCI
upon the button press. The status bit is software
Read/Writeable by the 8051; the enable bit is
Read-only by the 8051. It also has a status and
enable bit in the PM1_BLK of registers to
indicate and control the power button override
(fail-safe) event. These bits are not required by
ACPI. The power button override event status
bit is software Read/Writeable by the 8051; the
enable bit is software read-only by the 8051.
The enable bit for the override event is located
at bit 1 in the PM1_CNTRL2 register.
The power button enable bit is set by the Host to
enable the generation of an SCI due to the
power button event. The status bit is set by the
8051 when it generates a power button event
and is cleared by the Host writing a ‘1’ to this bit
(writing a ‘0’ has no effect); it can also be
cleared by the 8051. If the enable bit is set, the
8051 will generate an SCI power management
event.
276
Sleep Button
The sleep button has a status and an enable bit
in the PM1_BLK of registers to provide an SCI
upon the button press. The status bit is software
Read/Writeable by the 8051; the enable bit is
Read-only by the 8051.
The sleep button enable bit is set by the Host to
enable the generation of an SCI due to the sleep
button event. The status bit is set by the 8051
when it generates a sleep button event and is
cleared by the Host writing a ‘1’ to this bit
(writing a ‘0’ has no effect); it can also be
cleared by the 8051. If the enable bit is set, the
8051 will generate an SCI power management
event.
RTC Alarm
The ACPI specification requires that the RTC
alarm generate a hardware wake-up event from
the sleeping state. The RTC alarm can be
enabled as an SCI event and its status can be
determined through bits in the PM1_BLK of
registers. The status bit is software
Read/Writeable by the 8051; the enable bit is
Read-only by the 8051.
The RTC enable bit is set by the Host to enable
the generation of an SCI due to the RTC alarm
event. The status bit is set by the 8051 when
the RTC generates an alarm event and is
cleared by the Host writing a ‘1’ to this bit
(writing a ‘0’ has no effect); it can also be
cleared by the 8051. If the enable bit is set, the
8051 will generate an SCI power management
event.
ACPI PM1 BLOCK BASE ADDRESS
Logical Device 1 in the FDC37N972
configuration space supports the ACPI PM1
Block registers interface.
Three device configuration registers in LDN1
provide activation control and the base address
programming for the ACPI PM1 Block registers
(TABLE 198).
Register 0x30 is the Activate register. The
activation control (LDN1:CR30.0) qualifies
address decoding for the ACPI PM1 Block
registers; e.g., if the Activate bit D0 in the
Activate register is “0”, the PM1 Block
addresses will not be decoded; if the Activate bit
is “1”, PM1 Block addresses will be decoded
depending on the values programmed in the
ACPI PM1
registers.
Block
Primary
Base
Address
Registers 0x60 and 0x61 are the ACPI PM1
Block Primary Base Address registers. Register
0x60 is the ACPI PM1 Block Primary Base
Address High Byte, register 0x61 is the ACPI
PM1 Block Primary Base Address Low Byte.
NOTE: The ACPI PM1 Block base address must
be located on eight -byte boundaries; i.e., bits
D0 – D2 in the ACPI PM1 Block Primary Base
Address Low Byte must be “0”. Valid ACPI PM1
Block base address values are 0x0000 –
0x0FF8.
TABLE 198 – ACPI PM1 BOCK CONFIGURATION REGISTERS (LDN1)
SOFT
RESET
VCC2
POR
VCC1&VCC0
POR
0x00
0x00
0x00
-
R/W
0x00
0x00
0x00
-
R/W
0x00
0x00
0x00
-
INDEX
TYPE
0x30
R/W
0x60
0x61
HARD
RESET
277
DESCRIPTION
D7
D6
D5
D4
D3
D2
D1
Activate
RESERVED
ACPI PM1 Block Primary Base Address High Byte
“0”
“0”
“0”
“0”
A11
A10
A9
ACPI PM1 Block Primary Base Address Low Byte
A7
A6
A5
A4
A3
“0”
“0”
D0
Activate
A8
“0”
ACPI PM1 BLOCK
DESCRIPTION
The ACPI register model consists of a number
of fixed register blocks that perform designated
functions. A register block consists of a number
of registers that perform Status, Enable and
Control functions. The ACPI specification deals
with events (which have an associated interrupt
status and enable bits, and sometimes an
associated control function) and control
features. The status registers illustrate what
defined function is requesting ACPI interrupt
services (SCI). Any status bit in the ACPI
specification has the following attributes:
Status bits are only set through some defined
hardware or 8051 event.
Unless otherwise noted, Status bits are cleared
by the system writing a “1” to that bit position,
and upon VCC1 POR. Writing a ‘0’ has no
effect.
Status bits only generate interrupts while their
associated bit in the enable register is set.
Function bit positions in the status register have
the same bit position in the enable register
(there are exceptions to this rule, special status
bits have no enables).
Note that this implies that if the respective
enable bit is reset and the hardware event
occurs, the respective status bit is set; however
no interrupt is generated until the enable bit is
set. This allows software to test the state of the
event (by examining the status bit) without
necessarily generating an interrupt. There are a
special class of status bits that have no
respective enable bit, these are called out
specifically, and the respective enable bit in the
enable register is marked as reserved for these
special cases.
The enable registers allow the setting of the
status bit to generate an interrupt (under 8051
control). As a general rule there is an enable bit
in the enable register for every status bit in the
status register. The control register provides
special controls for the associated event, or
special control features that are not associated
with an interrupt event. The order of a register
block is the status registers, followed by enable
registers, followed by control registers.
REGISTERS
The registers in the FDC37N972 ACPI PM1
Block occupy eight addresses in the host I/O
space and are specified as offsets from the
ACPI PM1 Block base address (TABLE 199).
The registers in the PM1 Block are powered by
VCC1.
278
REGISTER
PM1_STS 1
PM1_STS 2
PM1_EN 1
PM1_EN 2
PM1_CNTRL 1
PM1_CNTRL 2
RESERVED
RESERVED
TABLE 199 - ACPI PM1 BLOCK REGISTERS
SIZE (bits)
OFFSET
ADDRESS
8
0
<ACPI PM1 Block Base Address>
8
1
<ACPI PM1 Block Base Address>+1h
8
2
<ACPI PM1 Block Base Address>+2h
8
3
<ACPI PM1 Block Base Address>+3h
8
4
<ACPI PM1 Block Base Address>+4h
8
5
<ACPI PM1 Block Base Address>+5h
8
6
<ACPI PM1 Block Base Address>+6h
8
7
<ACPI PM1 Block Base Address>+7h
POWER MANAGEMENT 1 STATUS REGISTER 1 (PM1_STS 1)
Host Register Location:
8051 Register Location:
Default Value:
Host Attribute:
Size:
BIT
0-7
NAME
Reserved
<ACPI PM1 Block Base Address> System I/O Space
n/a
00h on VCC1 POR
Read
8-bits
DESCRIPTION
Reserved. These bits always return a value of zero.
POWER MANAGEMENT 1 STATUS REGISTER 2 (PM1_STS 2)
Host Register Location:
8051 Register Location:
Default Value:
Host Attribute:
8051 Attribute
Size:
<ACPI PM1 Block Base Address>+1h System I/O Space
0x7F80
00h on VCC1 POR
Read/Write (Note 1)
Read/Write
8-bits
Note 1: These bits are set/cleared by the 8051 directly i.e., writing ‘1’ sets the bit and writing ‘0’ clears
it. These bits can also be cleared by the Host software writing a one to this bit position and by VCC1
POR. Writing a 0 by the Host has no effect.
An interrupt is generated to the 8051 when the Host writes to this register.
BIT
0
NAME
PWRBTN_STS
DESCRIPTION
This bit can be set or cleared by the 8051 to simulate a Power
button status if the power is controlled by the 8051. The Host
writing a one to this bit can also clear this bit. The 8051 must
generate the associated SCI interrupt under software control.
279
1
BIT
NAME
SLPBTN_STS
2
RTC_STS
3
PWRBTNOR_STS
4-6
7
Reserved
WAK_STS
DESCRIPTION
This bit can be set or cleared by the 8051 to simulate a Sleep
button status if the sleep state is controlled by the 8051. The Host
writing a one to this bit can also clear this bit.
This bit can be set or cleared by the 8051 to simulate a RTC
status. The Host writing a one to this bit can also clear this bit.
This bit can be set or cleared by the 8051 to simulate a Power
button override event status if the power is controlled by the 8051.
The Host writing a one to this bit can also clear this bit.
Reserved. These bits always return a value of zero.
This bit can be set or cleared by the 8051. The Host writing a one
to this bit can also clear this bit.
POWER MANAGEMENT 1 ENABLE REGISTER 1 (PM1_EN 1)
Host Register Location:
8051 Register Location:
Default Value:
Host Attribute:
Size:
BIT
0-7
NAME
Reserved
<ACPI PM1 Block Base Address>+2 System I/O Space
n/a
00h on VCC1 POR
Read
8-bits
DESCRIPTION
Reserved. These bits always return a value of zero.
POWER MANAGEMENT 1 ENABLE REGISTER 2 (PM1_EN 2)
Host Register Location:
8051 Register Location:
Default Value:
Host Attribute:
8051 Attribute:
Size:
<ACPI PM1 Block Base Address>+3 System I/O Space
0x7F81
00h on VCC1 POR
Read/Write
Read
8-bits
An interrupt is generated to the 8051 when the Host writes this to register.
0
BIT
NAME
PWRBTN_EN
1
SLPBTN_EN
2
RTC_EN
3-7
RESERVED
DESCRIPTION
This bit can be read or written by the Host. It can be read by the
8051
This bit can be read or written by the Host. It can be read by the
8051
This bit can be read or written by the Host. It can be read by the
8051
RESERVED bits cannot be written and return “0” when read.
280
POWER MANAGEMENT 1 CONTROL REGISTER 1 (PM1_CNTRL 1)
Host Register Location:
8051 Register Location:
Default Value:
Host Attribute:
Size:
BIT
0-7
NAME
RESERVED
<ACPI PM1 Block Base Address>+4 System I/O Space
n/a
00h on VCC1 POR
Read
8-bits
DESCRIPTION
RESERVED bits cannot be written and return “0” when read.
POWER MANAGEMENT 1 CONTROL REGISTER 2 (PM1_CNTRL 2)
Host Register Location:
8051 Register Location:
Default Value:
Host Attribute:
8051 Attribute:
Size:
<ACPI PM1 Block Base Address>+5 System I/O Space
0x7F82
00h on VCC1 POR
Read/Write
Read. NOTE: Bit 5 is Read/Write
8-bits
An interrupt is generated to the 8051 when the Host writes to this register.
BIT
0
1
2-4
5
NAME
Reserved
PWRBTNOR_EN
SLP_TYPx
SLP_EN
6-7
RESERVED
DESCRIPTION
Reserved. This field always returns zero.
This bit can be set or cleared by the Host, read by the 8051
These bits can be set or cleared by the Host, read by the 8051
This bit is R/W by the Host; reads by the Host always return ‘0’.
This bit can be set (written as ‘1’) but not cleared by the Host
(writing ‘0’ has no effect). This bit is R/W by the 8051, and
reads by the 8051 return the true value of the bit. When set by
the Host, this bit is cleared by the 8051 writing a ‘1’ to it; writing
‘0’ has no effect.
RESERVED bits cannot be written and return “0” when read.
281
nEC_SCI INTERFACE
The nEC_SCI pin logic hardware is shown
below in FIGURE 42.
Any or all of the PWRBTN_STS, SLPBTN_STS,
and RTC_STS bits in the PM1_STS 2 register
can assert the nEC_SCI pin if enabled by the
PWRBTN_EN, SLPBTN_EN, and RTC_EN bits
in the PM1_EN 2 register. See descriptions of
these registers, above.
PM1_STS 2
Register
The 8051_SCI_STS bit can assert the nEC_SCI
pin at any time, without being enabled. The
8051_SCI_STS bit is located in the
8051_PM_STS register at MMCR address
0x7F83h (TABLE 200).
The 8051_SCI_STS bit is in the FDC37N972
and is read/write by the 8051.
If the
8051_SCI_STS bit is “1”, an interrupt is
generated on the nEC_SCI pin.
PM1_EN 2
Register
PWRBTN_STS
SLPBTN_STS
nEC_SCI
RTC_STS
8051_PM_STS Register
8051_SCI_STS
FIGURE 45 - HARDWARE nEC_SCI INTERFACE
TABLE 200 - 8051_PM_STS REGISTER
HOST ADDRESS
8051 ADDRESS
POWER PLANE
0x7F83
VCC1
HOST TYPE
8051 TYPE
BIT NAME
D7
D6
D5
D4
D3
D2
D1
R
R
R
R
R
R
R
RESERVED
(RESERVED bits cannot be written and return “0” when read)
282
DEFAULT
0x00
D0
R/W
8051_
SCI_STS
REAL TIME CLOCK
GENERAL DESCRIPTION
The Real Time Clock Supercell (RTC) is a
complete time of day clock with alarm, day of
month alarm, one hundred year calendar, a
century byte, and a programmable periodic
interrupt. The RTC address space consists of
two-128 bytes.banks of CMOS RAM (Bank0 and
Bank1.) Each bank is accessable via address
and data ports. These access ports have
relocatable addresses and are acessable by
both the host and the 8051. Each bank’s last
addressable location accesses the Shared RTC
Control. The remaining 127 bytes of Bank0
contain the following: eleven registers of time,
calendar, century, and alarm data, four control
and status registers, and 111 bytes of general
purpose registers. The remaining 127bytes of
Bank1 contain general purpose registers.
30-day alarm.
RTC/CMOS Bank Addresses are relocatable.
The RTC CMOS Bank0 index register (70h) is
shadowed
RTC Interrupt (IRQ8) is available on the parallel
nIRQ8 pin.
RTC power source is switched internally
between the VCC1 and VCC0 pins according to
VCC1_PWRGD (See FIGURE 4 - VCC2
POWER-UP TIMING and FIGURE 5 – VCC1
PWRGD TIMING).
Lockable CMOS Ram Address Ranges (See
Table 223 - RTC, LOGICAL DEVICE 6
[LOGICAL DEVICE NUMBER = 0X06]
FEATURES:
CONFIGURATION REGISTERS
Allow 32kHz clock input or a 32kHz crystal.
The RTC configuration registers, in Logical
Device Number 6, provide activation control and
the base address for the run-time registers (See
TABLE 201)
Counts seconds, minutes, and hours of the day.
Counts days of the week, date, month and year.
Binary or BCD representation of time, calendar
and alarm.
The activate bit register 0x30, Bit D0 enables
RTC/CMOS Bank0.
The activate bit register 0x30, Bit D1 enables
RTC/CMOS Bank1.
24 hour daily alarm.
283
TABLE 201 - RTC CONFIGURATION REGISTERS
INDEX
TYPE
HARD
RESET
0x30
R/W
0x00
0x60
R/W
0x00
SOFT
RESET
VCC2
POR
VCC1&V
CC0
POR
0x00
0x00
-
0x00
0x00
DESCRIPTION
D
7
R/W
0x70
0x70
0x70
D
5
D
4
D
3
D
2
D1
Activate
Activate
RTC/ CMOS
CMOS
Bank0
Bank1
RTC/CMOS Bank0 Primary Base Address
High Byte
-
-
“
0
”
“
0
”
“
0
”
A
1
1
A
1
0
A9
R/W
0x00
0x00
0x00
-
0xF1
R/W
R
0x74
-
0x74
-
0x74
-
“0”
CMOS Bank1 Primary Base Address High
Byte
“ “ “ “ A A A9
0 0 0 0 1 1
” ” ” ” 1 0
0x63
A8
RTC/CMOS Bank0 Primary Base Address
Low Byte
A A A A A A A1
7 6 5 4 3 2
0x62
D0
Activate
RESERVED
“
0
”
0x61
D
6
-
A8
CMOS Bank1 Primary Base Address Low
Byte
A A A A A A A1
“0”
7 6 5 4 3 2
Shadow RTC/CMOS Bank 0 Index register
-
ISA HOST I/O INTERFACE
Each bank has a CMOS Address Register and a
CMOS Data Register. Each bank’s CMOS
Address Register is located at the corresponding
base address setup by the Configuration
Registers in TABLE 201. Each bank’s CMOS
Data Register is located at an offest of the
coresponding base (see TABLE 202.) Bit D7 of
both CMOS Address Registers is not used for
the CMOS RAM address decoding. All four
CMOS Run Time regesters are fully read/write.
TABLE 202 - CMOS RUN TIME REGISTERS
ISA ADDRESS*
BANK
FUNCTION
Bank0 * (R/W)
RTC/CMOS Bank0
CMOS Address Register
Bank0 * + 1(R/W)
RTC/CMOS Bank0
CMOS Data Register
Bank1 * (R/W)
CMOS Bank1
CMOS Address Register
Bank1 * + 2(R/W)
CMOS Bank1
CMOS Data Register
284
INTERNAL REGISTERS
TABLE 203 shows the address map of the RTC and CMOS RAM, eleven registers of time,
calendar, century , and alarm data, four control and status registers , 239 bytes of CMOS
registers and one :Shared RTC Control register. Each bank’s last addressable location accesses
the same reigister: Shared RTC Control.
BANK
Bank0
Bank0
Bank0
Bank0
Bank0
Bank0
Bank0
Bank0
Bank0
Bank0
Bank0
Bank0
Bank0
Bank0
Bank0
Bank0
Bank0
Bank1
Bank1
TABLE 203 - RTC AND CMOS RAM ADDRESS MAP
BASE OFFEST
REGISTER TYPE
REGISTER FUNCTION
0
R/W
Register 0: Seconds
1
R/W
Register 1: Seconds Alarm
2
R/W
Register 2: Minutes
3
R/W
Register 3: Minutes Alarm
4
R/W
Register 4: Hours
5
R/W
Register 5: Hours Alarm
6
R/W
Register 6: Day of Week
7
R/W
Register 7: Day of Month
8
R/W
Register 8: Month
9
R/W
Register 9: Year
A
R/W
Register A:
B
R/W
Register B: (Bit 0 is Read Only)
C
R
Register C:
D
R/W
Register D: Day of Month Alarm
32
R/W
Century Byte
E-31, 33-7F
R/W
General purpose
7F
R/W
: Shared RTC Control
0-7E
R/W
Bank 1: General purpose
7F
R/W
: Shared RTC Control
All 256 bytes are directly writable and readable by the host with the following exceptions:
Registers C is read only
Bit 7 of Register D is read only which can only be set by a read of Register D.
Bit 6 of Register D is read only .
Bit 7 of Register A is read only
Bits 0 of Register B is read only
Bits 7-1 of the Shared RTC Control register are read only
285
TIME CALENDAR AND ALARM
The processor program obtains time and
calendar information by reading the appropriate
locations. The program may initialize the time,
calendar and alarm by writing to these locations.
The contents of the twelve time, calendar and
alarm registers can be in binary or BCD as
shown in TABLE 204 - RTC REGISTER VALID
RANGE.
Before initializing the internal registers, the SET
bit in Register B should be set to a "1" to prevent
time/calendar updates from occurring. The
program initializes the twelve locations in the
binary or BCD format as defined by the DM bit
in Register B. The SET bit may then be cleared
to allow updates.
The 12/24 bit in Register B establishes whether
the hour locations represent 1 to 12 or 0 to 23.
The 12/24 bit cannot be changed without
reinitializing the hour locations. When the 12
hour format is selected, the high order bit of the
hours byte represents PM when it is a "1".
Once per second, the twelve time, calendar and
alarm registers are updated, Incrementing by
one second and checking for an alarm
ADD
0
1
2
3
4
5
6
7
condition. During the update cycle all the
registers in TABLE 204, except Register D, are
not accessible by the processor program. The
update cycle time is shown in Table TABLE
205. The update logic contains circuitry for
automatic end-of-month recognition as well as
automatic leap year compensation.
The three alarm registers may be used in two
ways. First, when the program inserts an alarm
time in the appropriate hours, minutes and
seconds alarm locations, the alarm interrupt is
initiated at the specified time each day if the
alarm enable bit is high. The second usage is to
insert a "don't care” state in one or more of three
alarms registers. The "don't care" code is any
hexadecimal byte from C0 to FF inclusive. That
is the two most significant bits of each byte,
when set to "1" create a "don't care" situation.
An alarm interrupt each hour is created with a
"don't care" code in the hours alarm location.
Similarly, an alarm is generated every minute
with "don't care" codes in the hours and minutes
alarm bytes. The "don't care" codes in all three
alarm bytes create an interrupt every second.
TABLE 204 - RTC REGISTER VALID RANGE
BCD
REGISTER FUNCTION
RANGE
Register 0: Seconds
00-59
Register 1: Seconds Alarm
00-59
Register 2: Minutes
00-59
Register 3: Minutes Alarm
00-59
Register 4: Hours
01-12 am
(12 hour mode)
81-92 pm
(24 hour mode)
00-23
Register 5: Hours Alarm
01-12 am
(12 hour mode)
81-92 pm
(24 hour mode)
00-23
Register 6: Day of Week
01-07
Register 7: Day of Month
01-31
286
BINARY
RANGE
00-3B
00-3B
00-3B
00-3B
01-0C
81-8C
00-17
01-0C
81-8C
00-17
01-07
01-1F
ADD
8
9
REGISTER FUNCTION
Register 8: Month
Register 9: Year
BCD
RANGE
01-12
00-99
BINARY
RANGE
01-0C
00-63
D
Day of Month Alarm
01-31
01-1F
32
Century Byte
00-99
00-63
UPDATE CYCLE
corresponding time register and issues an alarm
if a match or if a "don't care" code is present.
An update cycle is executed once per second if
the SET bit in Register B is clear and the
DV0-DV2 divider is not clear. The SET bit in the
"1" state permits the program to initialize the
time and calendar registers by stopping an
existing update and preventing a new one from
occurring.
The length of an update cycle is shown in
TABLE 205. During the update cycle the time,
calendar and alarm registers are not accessible
by the processor program. If the processor
reads these locations before the update cycle is
complete the output will be undefined. The UIP
(update in progress) status bit is set during the
interval. When the UIP bit goes high, the update
cycle will begin 244 µs later. Therefore, if a low
is read on the UIP bit the user has at least 244
µs before time/calendar data will be changed.
The primary function of the update cycle is to
increment the seconds register, check for
overflow, increment the minutes register when
appropriate and so forth through to the year of
the century byte. The update cycle also
compares each alarm register with the
TABLE 205 - RTC UPDATE CYCLE TIMING
INPUT CLOCK
FREQUENCY
32.768 kHz
32.768 KHZ
UIP BIT
1
0
UPDATE CYCLE
TIME
1948 µs
-
287
MINIMUM TIME
BEFORE START OF
UPDATE CYCLE
244 µs
CONTROL AND STATUS REGISTERS
The RTC has four registers, which are accessible to the processor program at all times, even during
the update cycle.
REGISTER A
B7
UIP
B6
DV2
B5
DV1
B4
DV0
B3
RS3
B2
RS2
B1
RS1
B0
RS0
UIP
DV2-0
The update in progress bit is a status flag that
may be monitored by the program. When UIP is
a "1" the update cycle is in progress or will soon
begin. When UIP is a "0" the update cycle is not
in progress and will not be for at least 244 µs.
The time, calendar, and alarm information is
fully available to the program when the UIP bit is
“0”. The UIP bit is a read only bit and is not
affected by VCC1 POR. Writing the SET bit in
Register B to a "1" inhibits any update cycle
and then clears the UIP status bit.
Three bits are used to permit the program to
select various conditions of the 22 stage divider
chain. TABLE 206 shows the allowable
combinations. The divider selection bits are also
used to reset the divider chain. When the
time/calendar is first initialized, the program
may start the divider chain at the precise time
stored in the registers. When the divider reset is
removed the first update begins one-half second
later. These three read/write bits are not affected
by VCC1 POR.
TABLE 206 - RTC DIVIDER SELECTION BITS
OSCILLATOR
REGISTER A BITS
FREQUENCY
DV2
DV1
DV0
MODE
0
0
0
Oscillator Disabled
32.768 kHz
0
0
1
Oscillator Disabled
32.768 kHz
0
1
0
Normal Operate
32.768 kHz
0
1
1
Test
32.768 kHz
1
0
X
Test
1
1
X
Reset Divider
RS3-0
The four rate selection bits select one of 15 taps
on the divider chain or disable the divider
output. The selected tap determines rate or
frequency of the periodic interrupt. The program
288
may enable or disable the interrupt with the PIE
bit in Register B. Table 207 lists the periodic
interrupt rates and equivalent output frequencies
that may be chosen with the RS0-RS3 bits.
These four bits are read/write bits which are not
affected by VCC1 POR.
TABLE 207 - RTC PERIODIC INTERRUPT RATES
RATE SELECT
32.768 kHz TIME BASE
RS3 RS2 RS1
PERIOD RATE
FREQUENCY
RS0
OF INTERRUPT
OF INTERRUPT
0 0 0 0
0.0
0 0 0 1
3.90625 ms
256 Hz
0 0 1 0
7.8125 ms
128 Hz
0 0 1 1
8.192 Hz
122.070 µs
0 1 0 0
4.096 kHz
244.141 µs
0 1 0 1
2.048 kHz
488.281 µs
0 1 1 0
1.024 kHz
976.562 µs
0 1 1 1
1.953125 ms
512 Hz
1 0 0 0
3.90625 ms
256 Hz
1 0 0 1
7.8125 ms
128 Hz
1 0 1 0
15.625 ms
64 Hz
1 0 1 1
31.25 ms
32 Hz
1 1 0 0
62.5 ms
16 Hz
1 1 0 1
125 ms
8 Hz
1 1 1 0
250 ms
4 Hz
1 1 1 1
500 ms
2 Hz
REGISTER B
B7
SET
B6
PIE
B5
AIE
B4
UIE
B3
RES
SET
When the SET bit is a "0", the update functions
normally
by
advancing
the
counts
once-per-second. When the SET bit is a "1", an
update cycle in progress is aborted and the
PIE
The periodic interrupt enable bit is a read/write
bit which allows the periodic-interrupt flag (PF)
bit in Register C to cause the IRQB port to be
driven low. The program writes a "1" to the PIE
289
B2
DM
B1
24/12
B0
DSE
program may initialize the time and calendar
bytes without an update occurring in the
middle of initialization. SET is a read/write bit,
which is not modified by VCC1 POR or any
internal functions.
bit in order to receive periodic interrupts at the
rate specified by the RS3 - RS0 bits in Register
A. A “0” in PIE blocks IRQB from being initiated
by a periodic interrupt, but the periodic flag (PF)
is still set at the periodic rate. PIE is not
modified by any internal function, but is
cleared to "0" by a VCC1 POR.
AIE
DM
The alarm interrupt enable bit is a read/write bit,
which when set to a "1" permits the alarm flag
(AF) bit in Register C to assert IRQB. An
alarm interrupt occurs for each second that the
three time bytes equal the three alarm bytes
(including a "don't care" alarm code of binary
11XXXXXX). When the AIE bit is a "0", the AF
bit does not initiate an IRQB signal. The VCC1
POR port clears AIE to "0". The AIE bit is not
affected by any internal functions.
UIE
The data mode bit indicates whether time and
calendar updates are to use binary or BCD
Formats: The DM bit is written by the processor
program and may be read by the program, but
is not modified by any internal functions or by
VCC1 POR. A "1” in DM signifies binary data,
while a "0" in DM specifies BCD data.
24/12
The 24/12 control bit establishes the format of
the hours byte as either the 24 hour mode if set
to a "1", or the 12 hour mode if cleared to a
"0". This is a read/write bit that is not affected
by VCC1 POR or any internal function.
The update-ended interrupt enable bit is a
read/write bit which enables the update-end flag
(UF) bit in Register C to assert IRQB. The
VCC1 POR port or the SET bit going high clears
the UIE bit.
DSE
RES
The daylight savings enable bit is read only and
is always set to a "0" to indicate that the
daylight savings time option is not available.
Reserved - read as zero
REGISTER C
REGISTER C IS A READ ONLY REGISTER
B7
IRQF
B6
PF
B5
AF
B4
UF
290
B3
0
B2
0
B1
0
B0
0
IRQF
AF
The interrupt request flag is set to a "1" when
one or more of the following are true:
PF = PIE = 1
AF = AIE = 1
UF = UIE = 1
The alarm interrupt flag when set to a "1"
indicates that the current time has matched the
alarm time. A "1" in AF causes a "1"to appear in
IRQF and the IRQB port to go low when the AIE
bit is also a "1". A VCC1 POR or a read of
Register C clears the AF bit.
Any time the IRQF bit is a "1", the IRQB signal
is driven low. All flag bits are cleared after
Register C is read or by the VCC1 POR port.
PF
The periodic interrupt flag is a read only bit
which is set to a "1" when a particular edge is
detected on the selected tap of the divider chain.
The RS3 -RS0 bits establish the periodic rate.
PF is set to a "1" independent of the state of
the PIE bit. PF being a "1" sets the IRQF bit
and initiates an IRQB signal when PIE is also a
"1". The PF bit is cleared by VCC1 POR or by a
read of Register C.
UF
The update-ended interrupt flag bit is set after
each update cycle. When the UIE bit is also a
"1", the "1" in UF causes the IRQF bit to be set
and asserts IRQB. A VCC1 POR or a read of
Register C causes UF to be cleared.
B3-0
The unused bits of Register C are read as “0”
and cannot be written.
REGISTER D
MSB
b7
VRT
b6
0
b5
b4
Day of month
b3
b2
b1
VRT
B6
The Valid RAM and Time (VRT) bit is cleared by
the RTC to indicate that both the main power
(VCC1) and the battery power (VCC0) are both
low at the same time. This is the only case
where the contents of the RAM,as well as, the
time and calendar registers are not valid. The
VRT bit can only be set by a read of Register D.
The 8051 can set the VRT bit reading Register
D after both of the following condition are met:
VCC1_PWRGD =1 and the 8051 completes
initialization. The Host can set the VRT bit
reading Register D after PWRGD =1 See
Section 0 Power Management.
Read as zero and cannot be written.
291
LSB
B0
B5:B0
Day of month Alarm; these bits store the day of
month alarm value. If set to 000000b, then a
don’t care state is assumed. The host must
configure the Day of month alarm for these bits
to do anything, yet they can be written at any
time. If the Day of month alarm is not enabled,
these bits will return zeros. These bits are not
affected by RESET_DRV, VCC1_POR or
VCC2_POR. The BCD Range for the Day of
month of month alarm is 1-31 and the Binary
Range is 01-1F.
CENTURY BYTE
The century byte is located at RTC/Bank0
register 0x32. The century byte is incremented
by one when the year byte changes from 99 or
0x63 to 0. The BCD Range for the century byte
is 00-99 and the Binary Range is 00-63.
GENERAL PURPOSE
Registers 0xEh-0x7EH, except 0x32 (The
Century Byte) in Bank0 and 0x0-0x7E in Bank1
are general purpose "CMOS" registers. These
registers can be used by the host or 8051 and
are fully available during the time update cycle.
The contents of these registers are preserved by
VCC0 power. Registers Eh-7Eh are in bank0
and registers 80h-FEh are in bank1.
receive by writing a "1" to the appropriate enable
bits in Register B. A "0" in an enable bit prohibits
the IRQB port from being asserted due to that
interrupt cause. When an interrupt event occurs
a flag bit is set to a "1" in Register C, which are
set independent of the state of the
corresponding enable bits in Register B. Each of
the three interrupt sources have separate flag
bits in Register C. The flag bits may be used
with or without enabling the corresponding
enable bits. The flag bits in Register C are
cleared (record of the interrupt event is erased)
when Register C is read. Double latching is
included in Register C to ensure the bits that are
set are stable throughout the read cycle. All bits
which are high when read by the program are
cleared, and new interrupts are held until after
the read cycle. If an interrupt flag is already set
when the interrupt becomes enabled, the IRQB
port is immediately activated, though the
interrupt initiating the event may have occurred
much earlier.
SHARED RTC CONTROL
Each bank’s last addressable location (0x7F)
accesses the Shared RTC Control. The Shared
RTC Control Register implements an interface
that allows the 8051 to read/write the RTC and
CMOS registers by use of the smart host
protocol. Refer to 8051 RTC CMOS ACCESS
Section for the definition of this register.
When an interrupt flag bit is set and the
corresponding interrupt-enable bit is also set,
the IRQB port is driven low. IRQB is asserted as
long as at least one of the three interrupt
sources has its flag and enable bits both set.
The IRQF bit in Register C is a "1" whenever the
IRQB port is being driven low.
FREQUENCY DIVIDER
INTERRUPTS
The RTC includes three separate fully automatic
sources of interrupts to the processor. The
alarm interrupt may be programmed to occur at
rates from one-per-second to one-a-day. The
periodic interrupt may be selected for rates from
half-a-second to 122.070 µs. The update ended
interrupt may be used to indicate to the program
that an update cycle is completed. Each of these
independent interrupts are described in greater
detail in other sections. The processor program
selects which interrupts, if any, it wishes to
292
The RTC has 22 binary divider stages following
the clock input. The output of the divider is a 1Hertz signal to the update-cycle logic. The
divider is controlled by the three divider bits
(DV3-DV0) in Register A. As shown in Table
206 the divider control bits can select the
operating mode, or be used to hold the divider
chain reset that allows precision setting of the
time. When the divider chain is changed from
reset to the operating mode, the first update
cycle is one-half second later.
PERIODIC INTERRUPT SELECTION
8051 RTC CMOS ACCESS
The periodic interrupt allows the IRQB port to be
triggered from once every 500 ms to once every
122.07 µs. As Table 207 shows, the periodic
interrupt is selected with the RS0-RS3 bits in
Register A. The periodic interrupt is enabled
with the PIE bit in Register B.
The FDC37N972FR implements an interface
that allows the 8051 to read/write the RTC and
CMOS registers under the following conditions:
When nRESET_OUT is active, or when VCC2 is
off, or by use of the smart host protocol.
RTCCNTRL (RTC CONTROL) REGISTER
Host
N/A
8051
0x7FF5
Power
VCC1
Default
0x80
The RTC Control register is mirrored in CMOS register 0x7Fh in both bank0 and bank1.
D7
nSH
D6
0
D5
0
D4
0
D3
KREQH
293
D2
HREQH
D1
KREQL
D0
HREQL
NSH
HREQH
nSmart Host - This bit is controlled by the
8051. When set to a “1”, the host is not a
smart host and does not recognize the sharing
protocol. When set to a “0”, the host is smart
and can recognize the sharing protocol. When
set to “1”, this bit will clear HREQH and
HREQL. Clearing this bit to “0” will allow the
8051 to regain access to the CMOS RAM.
KREQL
Host Request High - This bit can be set by the
host when KREQH is “0”. If the request is not
granted, this bit is read back as a “0” and the
request must be tried again.
nSH
1
0
0
0
Keyboard Request Low - The 8051 can set
this bit when HREQL IS '0'. If the request is
not granted, this bit is read back as a zero and
the request must be tried again. Note: After
regaining control of the CMOS, the 8051 must
re-write the RTC Low Address Register before
accessing the RTC Data Register. This bit
selects access to the CMOS RAM Addresses
0-7F.
KREQX
X
0
1
0
HREQX
X
0
0
1
BUS
ACCESS
Host
None
8051
Host
RTC ADDRESS REGISTER (HIGH AND LOW)
Host
N/A
8051
0x7FF8 & 0x7FF6
Power
VCC1
Default
0x00 & 0x00
When KREQ=1.in the RTC Control register, the
Low Address Register and the High Address
Register are used to access the 256 CMOS RAM
registers. The Low Address Register is used to
provide the address to access the 128 CMOS
RAM registers in bank0 and the High Address
Register is used to provide the address to access
the 128 CMOS RAM registers in bank1. Bit D7 of
the Low Address Register and the High Address
Register are not used for the address decode and
are don’t care bits.
HREQL
Host Request Low - This bit can be set by the
host when KREQL is “0”. If the request is not
granted, this bit is read back as a “0” and the
request must be tried again.
KREQH
Keyboard Request High - This bit can be set
by the 8051 when HREQH is “0” If the request
is not granted, this bit is read back as a “0”
and the request must be tried again. Note:
After regaining control of the CMOS, the 8051
must re-write the RTC High Address Register
before accessing the RTC Data Register. This
bit selects access to the CMOS RAM
Addresses 80-FF.
RTC DATA REGISTER (HIGH AND LOW)
Host
N/A
8051
0x7FF9 & 0x7FF7
Power
VCC1
Default
0x00 & 0x00
The low register is used to access the first bank of
128 bytes, in CMOS RAM the high register is used
to access the second bank of 128 registers. This
register is used to read or write the selected
CMOS register when KREQ=1.
294
32kHz CLOCK INPUT
The FDC37N972 uses the XOSEL pin to select
either a 32.768kHz input clock or a 32.768kHz
crystal to drive the Real Time Clock Interface
(TABLE 2 - PIN FUNCTION DESCRIPTION).
When XOSEL = ‘0’, the RTC uses a 32.768kHz
crystal connected between the XTAL1 and
XTAL2 pins. When XOSEL = ‘1’, the RTC is
driven by a 32.768kHz single-ended clock
source connected to the XTAL2 pin.
NOTE: ICC0 ≥ 10µA for time-keeping operations
under VCC0 using a single-ended clock source.
ICC1 = 30µA under VCC1 using a single-ended
clock source.
POWER MANAGEMENT
The RTC and CMOS RAM utilize VCC0 power
plane (See FIGURE 4 - VCC2 POWER-UP
TIMING and FIGURE 5 - VCC1_PWRGD
TIMING)
The VCC1 POR does not affect the clock,
calendar, or RAM functions. When VCC1 POR
is active the following occurs:
Periodic Interrupt Enable (PIE) is cleared to “0”.
Alarm Interrupt Enable (AIE) bit is cleared to “0”.
Update Ended Interrupt Enable (UIE) bit is
cleared to “0”.
Update Ended Interrupt Flag (UF) bit is cleared
to “0”.
Interrupt Request status Flag (IRQF) bit is
cleared to “0”.
Periodic Interrupt Flag (PIF) is cleared to “0”.
The RTC and CMOS registers are not
accessible.
Alarm Interrupt Flag (AF) is cleared to “0”.
nIRQ pin is in high impedance state.
295
If both the main power (VCC1) and the battery
power (VCC0) are both low at the same time
and then re-applied (ie. a new battery is
installed) the following occurs:
Initialize all registers 00-0D to a “00”
when VCC1 is applied.
The oscillator is disabled immediately.
The VRT bit is cleared to “0”.
When PWRGD = 0, all host inputs are locked
out so that the internal registers cannot be
modified by the host system. The Host lockout
condition continues for 500usec (min) to 1msec
(max) after PWRGD =1. The Host lockout
condition does not occur when either of the
following occur:
RTC Divider Selection mode is not in
normal mode in TABLE 206.
The VRT bit in Register D is a "0".
PCI CLOCK RUN SUPPORT
OVERVIEW
The FDC37N972 supports the PCI nCLKRUN
signal. nCLKRUN is used to indicate the PCI
clock status as well as to request that a stopped
clock be started.
See FIGURE 46 for an
example of a typical system implementation
using nCLKRUN.
nCLKRUN support is required because the
FDC37N972 interrupt interface relies entirely on
Serial IRQs. If an interrupt occurs while the PCI
clock is stopped, nCLKRUN must be asserted
before the interrupt can be serviced.
If the FDC37N972 Serial IRQs are disabled,
nCLKRUN support is also disabled (see
SERIRQ MODE BIT FUNCTION on page 303).
The nCLKRUN pin is an open drain output and
an input. Refer to the PCI Mobile Design Guide
Rev 1.0 for a description of the nCLKRUN
function. Using nCLKRUN If nCLKRUN is
sampled “high”, the PCI clock is stopped or
FDC37N972 must not assert nCLKRUN if it is
already driven low by the central resource; i.e.,
the PCI CLOCK GENERATOR in FIGURE 47.
The FDC37N972 will not assert nCLKRUN
under any conditions if the Serial IRQs are
disabled.
stopping. If nCLKRUN is sampled “low”, the
PCI clock is starting or started (running).
If a device in the FDC37N972 asserts or deasserts an interrupt and nCLKRUN is sampled
“high”, the FDC37N972 can request the
restoration of the clock by asserting the
nCLKRUN signal asynchronously (TABLE 208).
The FDC37N972 holds nCLKRUN low until it
detects two rising edges of the clock. After the
second clock edge, the FDC37N972 must
disable the open drain driver (FIGURE 47). The
SIRQ_EN
0
1
The FDC37N972 must not assert nCLKRUN
unless the line has been deasserted for two
successive clocks; i.e., before the clock was
stopped (FIGURE 47).
TABLE 208 - FDC37N972 nCLKRUN FUNCTION
INTERNAL INTERRUPT
REQUEST
nCLKRUN
ACTION
X
X
None
NO CHANGE
X
None
CHANGE1
0
None
1
Assert nCLKRUN
NOTE1 “Change” means either-edge change on any or all parallel IRQs routed to the Serial IRQ
block. The “change” detection logic must run asynchronously to the PCI Clock and regardless of the
Serial IRQ mode; i.e., “continuous” or “quiet”.
MASTER
TARGET
PCICLK
PCI CLOCK
GENERATOR
nCLKRUN
(Central Resource)
FDC37N972
FIGURE 46 - nCLKRUN SYSTEM IMPLEMENTATION EXAMPLE
296
nCLKRUN
DRIVEN BY
FDC37N972
SIRQ_EN
1,2
ANY IRQ CHANGE
FDC37N972 STOPS
DRIVING nCLKRUN
nCLKRUN
PCI_CLK
2 CLKS
MIN.
FIGURE 47 - CLOCK START ILLUSTRATION
NOTE1 The signal “ANY IRQ CHANGE” is the same as “CHANGE” in TABLE 208.
NOTE2 The FDC37N972 must continually monitor the state of nCLKRUN to maintain the PCI Clock
until an active “ANY IRQ CHANGE” condition has been transferred to the host in a Serial IRQ cycle.
For example, if “ANY IRQ CHANGE” is asserted before nCLKRUN is de-asserted (not shown in
FIGURE 46), the FDC37N972 must assert nCLKRUN as needed until the Serial IRQ cycle has
completed.
297
SERIAL INTERRUPTS
Timing Diagrams For IRQSER Cycle
MSIO will support the serial interrupt scheme,
which is adopted by several companies, to
transmit interrupt information to the system.
The serial interrupt scheme adheres to the
Serial IRQ Specification for PCI Systems
Version 6.0.
PCICLK = 33 MHz_IN pin
IRQSER = SIRQ pin
START FRAME
SL
or
H
H
PCICLK
IRQSER
Start Frame timing with source sampled a low
pulse on IRQ1.
R
IRQ0 FRAME
T
S
R
IRQ1 FRAME
T
S
R
IRQ2 FRAME
T
S
R
START1
Drive Source
Host Controller
IRQ1
IRQ1
None
None
FIGURE 48 - SERIAL INTERRUPTS WAVEFORM "START FRAME"
H=Host Control
SL=Slave Control
R=Recovery
T=Turn-around
S=Sample
Start Frame pulse can be 4-8 clocks wide.
Stop Frame Timing with Host using 17 IRQSER sampling period
IRQ14
FRAME
S R T
IRQ15
FRAME
S R T
IOCHCK#
FRAME
S R T
NEXT CYCLE
STOP FRAME
I2
H
R
T
PCICLK
STOP 1
IRQSER
Driver
None
IRQ15
None
START3
Host Controller
FIGURE 49 - SERIAL INTERRUPT WAVEFORM "STOP FRAME"
H=Host Control
R=Recovery
T=Turn-around
S=Sample
I= Idle
Stop pulse is two clocks wide for Quiet mode, three clocks wide for Continuous mode.
There may be none, one or more Idle states during the Stop Frame.
298
T
The next IRQSER cycle’s Start Frame pulse may or may not start immediately after the turn-around
clock of the Stop Frame.
SERIRQ MODE BIT FUNCTION
In the FDC37N972, the SERIRQ_EN (CR25.2) is used to enable the Serial IRQ interface (TABLE
209). The SERIRQ_EN bit is also used to enable PCI Clock Run support (see Section PCI CLOCK
RUN SUPPORTon page 300).
TABLE 209 - SERIRQ_EN CONFIGURATION CONTROL
CR25 BIT[2]
NAME
DESCRIPTION
0
SERIRQ_EN
Serial IRQ Disabled
1
Serial IRQ Enabled (Default)
IRQSER CYCLE CONTROL
There are two modes of operation for the
IRQSER Start Frame.
QUIET (ACTIVE) MODE
Any device may initiate a Start Frame by driving
the IRQSER low for one clock, while the
IRQSER is Idle. After driving low for one clock
the IRQSER must immediately be tri-stated
without at any time driving high. A Start Frame
may not be initiated while the IRQSER is active.
The IRQSER is Idle between Stop and Start
Frames. The IRQSER is active between Start
and Stop Frames. This mode of operation
allows the IRQSER to be Idle when there are no
IRQ/Data transitions which should be most of
the time.
Once a Start Frame has been initiated the host
controller will take over driving the IRQSER low
in the next clock and will continue driving the
IRQSER low for a programmable period of three
to seven clocks. This makes a total low pulse
width of four to eight clocks. Finally, the host
controller will drive the IRQSER back high for
one clock then tri-state.
299
Any IRQSER Device (i.e., The FDC37N972)
which detects any transition on an IRQ/Data line
for which it is responsible must initiate a Start
Frame in order to update the host controller
unless the IRQSER is already in an IRQSER
Cycle and the IRQ/Data transition can be
delivered in that IRQSER Cycle.
CONTINUOUS (IDLE) MODE
Only the Host controller can initiate a Start
Frame to update IRQ/Data line information. All
other IRQSER agents become passive and may
not initiate a Start Frame. IRQSER will be driven
low for four to eight clocks by host controller.
This mode has two functions. It can be used to
stop or idle the IRQSER or the host controller
can operate IRQSER in a continuous mode by
initiating a Start Frame at the end of every Stop
Frame.
An IRQSER mode transition can only occur
during the Stop Frame. Upon reset, IRQSER
bus is defaulted to continuous mode, therefore
only the host controller can initiate the first Start
Frame. Slaves must continuously sample the
Stop Frames pulse width to determine the next
IRQSER Cycle’s mode.
IRQSER DATA FRAME
Once a Start Frame has been initiated, the
FDC37N972 will watch for the rising edge of the
Start Pulse and start counting IRQ/Data Frames
from there. Each IRQ/Data Frame is three
clocks: Sample phase, Recovery phase, and
Turn-around phase. During the sample phase,
the FDC37N972 must drive the IRQSER (SIRQ
pin) low, if and only if, its last detected IRQ/Data
value was low. If its detected IRQ/Data value is
high, IRQSER must be left tri-stated. During the
recovery phase the FDC37N972 must drive the
SERIRQ high, if and only if, it had driven the
IRQSER low during the previous sample phase.
300
During the turn-around phase the FDC37N972
must tri-state the SERIRQ. The FDC37N972
drives the IRQSER line low at the appropriate
sample point if its associated IRQ/Data line is
low, regardless of which device initiated the start
frame.
The Sample phase for each IRQ/Data follows
the low to high transition of the Start Frame
pulse by a number of clocks equal to the
IRQ/Data Frame times three, minus one e.g.
The IRQ5 Sample clock is the sixth IRQ/Data
Frame, then the sample phase is {(6 x 3) - 1 =
17} the seventeenth clock after the rising edge
of the Start Pulse.
IRQSER PERIOD
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
TABLE 210 – IRQSER SAMPLING PERIODS
SIGNAL SAMPLED
# OF CLOCKS PAST START
Not Used
2
IRQ1
5
nSMI/IRQ2
8
IRQ3
11
IRQ4
14
IRQ5
17
IRQ6
20
IRQ7
23
IRQ8
26
IRQ9
29
IRQ10
32
IRQ11
35
IRQ12
38
IRQ13
41
IRQ14
44
IRQ15
47
The SIRQ data frame will now support IRQ2
from a logical device; previously IRQSER Period
3 was reserved for use by the System
Management Interrupt (nSMI). When using
Period 3 for IRQ2 the user should mask off the
FDC37N972 ’s SMI via the ESMI Mask Register.
Likewise, when using Period 3 for nSMI, the
user should not configure any logical devices as
using IRQ2.
IRQSER Period 14 is used to transfer IRQ13.
Logical devices 0 (FDC), 3 (Par Port), 4 (Ser
Port 1), 5 (Ser Port 2), 6 (RTC), and 7 (KBD)
will have IRQ13 as a choice for their primary
interrupt.
STOP CYCLE CONTROL
Once all IRQ/Data Frames have completed the
host controller will terminate IRQSER activity by
initiating a Stop Frame. Only the host controller
can initiate the Stop Frame. A Stop Frame is
indicated when the IRQSER is low for two or
three clocks. If the Stop Frame’s low time is two
301
clocks then the next IRQSER cycle’s sampled
mode is the Quiet mode; and any IRQSER
device may initiate a Start Frame in the second
clock or more after the rising edge of the Stop
Frame’s pulse. If the Stop Frame’s low time is
three clocks, then the next IRQSER cycle’s
sampled mode is the continuous mode, and
only the host controller may initiate a Start
Frame in the second clock or more after the
rising edge of the Stop Frame’s pulse.
LATENCY
Latency for IRQ/Data updates over the IRQSER
bus in bridge-less systems with the minimum
IRQ/Data Frames of seventeen will range up to
96 clocks (3.84µS with a 25 MHz PCI Bus or
2.88µs with a 33 MHz PCI Bus). If one or more
PCI to PCI Bridge is added to a system, the
latency for IRQ/Data updates from the
secondary or tertiary buses will be a few clocks
longer
for
synchronous
buses,
and
approximately double for asynchronous buses.
EOI/ISR READ LATENCY
Any serialized IRQ scheme has a potential
implementation issue related to IRQ latency.
IRQ latency could cause an EOI or ISR Read to
precede an IRQ transition that it should have
followed. This could cause a system fault. The
host interrupt controller is responsible for
ensuring that these latency issues are mitigated.
The recommended solution is to delay EOIs and
ISR Reads to the interrupt controller by the
same amount as the IRQSER Cycle latency in
order to ensure that these events do not occur
out of order.
AC/DC SPECIFICATION ISSUE
All IRQSER agents must drive/sample IRQSER
synchronously related to the rising edge of the
PCI bus clock. IRQSER (SIRQ) pin uses the
electrical specification of the PCI bus. Electrical
parameters will follow the PCI specification
section 4, sustained tri-state.
RESET AND INITIALIZATION
The IRQSER bus uses nPCIRST as its reset
signal (nPCIRST is equivalent to using
nRESET_OUT) and follows the PCI bus reset
mechanism. The IRQSER pin is tri-stated by all
agents while nPCIRST is active. With reset,
IRQSER slaves and bridges are put into the
(continuous) Idle mode. The host controller is
responsible for starting the initial IRQSER cycle
to collect system’s IRQ/Data default values. The
system then follows with the Continuous/Quiet
mode protocol (Stop Frame pulse width) for
subsequent IRQSER cycles. It is the host
controller’s responsibility to provide the default
values to the 8259’s and other system logic
before the first IRQSER cycle is
302
performed.
For IRQSER system suspend,
insertion, or removal application, the host
controller
should
be
programmed
into
Continuous (IDLE) mode first. This is to
guarantee IRQSER bus is in Idle state before
the system configuration changes.
XNOR-CHAIN TEST MODE
An XNOR-Chain test structure is in to the
FDC37N972 to allow users to confirm that all
pins are in contact with the motherboard during
assembly and test operations (FIGURE 50).
The XNOR-Chain test structure must be
activated to perform these tests. When the
XNOR-Chain is activated, the FDC37N972 pin
functions are disconnected from the device pins,
which all become input pins except for one
output pin at the end of XNOR-Chain.
The tests that are performed when the XNORChain test structure is activated require the
board-level test hardware to control the device
pins and observe the results at the XNOR-Chain
output pin.
The XNOR-Chain test mode is activated and
latched by:
nIOW = nIOR = nMEMWR = nMEMRD = “0”
AND
XOSEL = VCC1_PWRGD = PWRGD = “1”
The XNOR-Chain test mode is deactivated by
VCC1_POR. All pins except for nRESET_OUT,
XOSEL, XTAL1, XTAL2, and VCC1_PWRGD
are included as inputs to the XNOR-Chain test
structure.
The XNOR-Chain output pin is
nRESET_OUT.
I/O#1
I/O#2
I/O#3
I/O#n
XNor
Out
FIGURE 50 - XNOR-CHAIN TEST STRUCTURE
The MODE pin is a hardware configuration pin.
The MODE pin sets the Configuration Port’s
default base address.
Note:
All I/O addresses are qualified with AEN.
FDC37N972 CONFIGURATION
OVERVIEW
The Configuration of the FDC37N972 is very
flexible and is based on the configuration
architecture implemented in typical Plug-andPlay components.
CONFIGURATION REGISTERS
CONFIGURATION REGISTER ACCESS
The FDC37N972 is designed for motherboard
designs in which the resources required by
their components are known. With its flexible
resource
allocation
architecture,
the
FDC37N972 allows the BIOS to assign
resources at POST.
PRIMARY
DECODER
CONFIGURATION
ADDRESS
The logical devices are configured through two
Configuration Access Ports (INDEX and DATA).
The BIOS uses these ports to initialize the logical
devices at POST (TABLE 211).
CONFIGURATION ELEMENTS
PRIMARY
DECODER
CONFIGURATION
The MODE pin is a hardware configuration pin
that sets the default Configuration Access Port
base address at power-up. The Configuration
Ports base address can also be changed using
the configuration ports base address register (see
Configuration
Registers
BASE
ADDRESS
REGISTERS (VCC2) on page 308).
ADDRESS
The logical devices are configured through two
Configuration I/O Ports (INDEX and DATA).
The BIOS uses these Configuration Ports to
initialize the logical devices at POST.
NOTE: All I/O addresses are qualified with AEN.
303
TABLE 211 - FDC37N972 CONFIGURATION ACCESS PORTS
MODE PIN = 1
MODE PIN = 0
(10K PULL-UP
(10K PULL-DOWN
RESISTOR OR TIE
RESISTOR OR TIE TO
TO VCC1)
TYPE
GND)
PORT NAME
CONFIG PORT
0x03F0
0x0370
Write
(Note 1)
(Note 1)
(NOWS ISA I/O)
INDEX PORT
0x03F0
0x0370
Read/Write
(Note 1)
(Note 1)
(NOWS ISA I/O)
DATA PORT
INDEX PORT + 1
Read/Write
(Note 1)
(NOWS ISA I/O)
The INDEX and DATA ports are effective only
when the chip is in the Configuration State.
Note 1: This address can be changed by
configuration registers 26h and 27h.
Entering the Configuration State
The device enters the Configuration State when
the following Config Key is successfully written
to the CONFIG PORT.
Config Key = < 0x55>
Exiting the Configuration State
The device exits the Configuration State when
the following Config Key is successfully written
to the CONFIG PORT address.
CONFIGURATION
REGISTERS
ADDRESS REGISTERS (VCC2)
BASE
The FDC37N972 configuration ports base
address is relocatable beyond the two
addressing options provided by the MODE pin.
Registers CR26 and CR27 enable the
relocatable configuration ports base address
function. CR26 is the configuration ports base
address least significant byte; CR27 is the most
significant byte (TABLE 212).
The configuration ports base address is
relocatable on even-byte boundaries; i.e., A0 =
“0”. Valid configuration ports base address
values are 0x0000 – 0x0FFE.
Config Key = < 0xAA>
READ ACCESING CONFIGURATON PORT
The Configuration Port reads back a float
condition when not in the Configuration State.
The Configuration Port reads back 0x00, after
the Configuration Key 0x55 has been written to
the Configuration Port, but prior any further
writes to the Configuration Port. After the
Configuration Index Register has been written to
at least once (in the Configuration State,) then
the last value written to the Configuration Index
Register (via the Configuration Port) can be read
back.
304
At power-up, the configuration ports base
address is determined by the MODE pin. To
relocate the configuration ports base address
after power-up, first write the lower address byte
(LSB) of the new base address to CR26 and
then write the upper address bits to CR27.
NOTE: writing CR27 changes the configuration
ports base address.
The ability to relocate the configuration ports
base address can prevent address conflicts,
particularly when tape drives are used.
TABLE 212 - CONFIGURATION PORT ADDRESS REGISTERS
DESCRIPTION
SOFT
RESET,
D7 D6 D5 D4
D3
D2
VCC1
HARD
POR &
RESET
VCC0
REGISTER
& VCC2
POR
NAME
POR1
INDEX TYPE
GLOBAL CONFIGURATION REGISTERS
A3
A2
Configuration A7 A6 A5 A4
0x262 R/W MODE =
Port Base
0: 0xF0
Address Byte
MODE =
0 (LSB)
1: 0x70
A11 A10
Configuration “0” “0” “0” “0”
0x273 R/W MODE =
Port Base
0: 0x03
Address Byte
MODE =
1 (MSB)
1: 0x03
NOTE1 The MODE pin determines the
configuration port base address following Hard
Reset and VCC2 POR.
NOTE2 The configuration ports base address is
relocatable on even-byte boundaries; i.e., A0 =
“0”.
NOTE3 Writing
CR27
changes
configuration ports base address.
D1
D0
A1
“0”
A9
A8
The FDC37N972 Configuration register map is
shown below in TABLE 213.
CONFIGURATION
CONDITIONS
REGISTER
RESET
HARD RESET = VCC2 POR or RESET_OUT
pin asserted.
the
SOFT RESET = Configuration Control Register
Bit0 set to a one by host.
305
TABLE 213 - FDC37N972 CONFIGURATION REGISTER MAP
HARD
SOFT
CONFIGURATION REGISTER
INDEX
TYPE
RESET
RESET
NAME
GLOBAL CONFIGURATION REGISTERS
0x02
W
0x00
0x00
Config Control
0x03
RESERVED
0x07
R/W
0x00
0x00
Logical Device Number
0x17
RESERVED
0x20
R
0x0A
0x0A
FDC37N971
0x0B
0x0B
FDC37N972
0x21
R
0x00
0x00
Device Rev - hard wired
0x22
R/W
0x00
n/a
Power Control
0x23
R/W
0x00
n/a
Power Mgmt
0x24
R/W
0x04
n/a
OSC
0x25
R/W
0x04
n/a
DeviceMode
0x26
R/W
See above
Configuration Port Base Address (LSB)
0x27
R/W
See above
Configuration Port Base Address (MSB)
0x28 –
0x00
0x00
RESERVED (Test Mode Registers)
0x2F
LOGICAL DEVICE 0 CONFIGURATION REGISTERS (FDC)
0x30
R/W
0x00
0x00
Activate
0x60,
R/W
0x03,
0x03,
Primary Base I/O Address
0x61
0xF0
0xF0
0x70
R/W
0x06
0x06
Primary Interrupt Select
0x74
R/W
0x02
0x02
DMA channel Select
0xF0
R/W
0x0E
n/a
FDD Mode Register
0xF1
R/W
0x00
n/a
FDD Option Register
0xF2
R/W
0xFF
n/a
FDD Type Register
0xF4
R/W
0x00
n/a
FDD0
0xF5
R/W
0x00
n/a
FDD1
LOGICAL DEVICE 1 CONFIGURATION REGISTERS (PM1)
0x30
R/W
0x00
0x00
Activate
0x60,
R/W
0x00,
0x00,
Primary Base I/O Address
0x61
0x00
0x00
LOGICAL DEVICE 2 CONFIGURATION REGISTERS (RESERVED)
LOGICAL DEVICE 3 CONFIGURATION REGISTERS (PARALLEL PORT)
0x30
R/W
0x00
0x00
Activate
0x60,
R/W
0x00,
0x00,
Primary Base I/O Address
0x61
0x00
0x00
0x70
R/W
0x00
0x00
Primary Interrupt Select
0x74
R/W
0x04
0x04
DMA channel Select
0xF0
R/W
0x3C
n/a
Parallel Port Mode Register
0xF1
R/W
0x00
n/a
Parallel Port CnfgB shadow Register
306
HARD
SOFT
CONFIGURATION REGISTER
INDEX
TYPE
RESET
RESET
NAME
LOGICAL DEVICE 4 CONFIGURATION REGISTERS (SERIAL PORT 1)
0x30
R/W
0x00
0x00
Activate
0x60,
R/W
0x00,
0x00,
UART Register Base I/O Address
0x61
0x00
0x00
0x70
R/W
0x00
0x00
Primary Interrupt Select
0xF0
R/W
0x00
n/a
Serial Port 1 Mode Register
LOGICAL DEVICE 5 CONFIGURATION REGISTERS (INFRARED)
0x30
R/W
0x00
0x00
Activate
0x60,
R/W
0x00,
0x00,
Primary Base I/O Address
0x61
0x00
0x00
0x62, 0x63 R/W
0x00, 0x00 0x00, 0x00 SCE Register Base I/O Address
0x70
R/W
0x00
0x00
Primary Interrupt Select
0x74
R/W
0x04
0x04
IRCC 2.0 DMA Channel Select
0xF0
R/W
0x00
n/a
Mode Register
0xF1
R/W
0x02
n/a
IR Options Register
0xF2
R/W
0x03
n/a
IR Half Duplex Timeout
0xF7
R/W
0x00
0x00
Software Select A
0xF8
R/W
0x00
0x00
Software Select B
LOGICAL DEVICE 7 CONFIGURATION REGISTERS (RTC)
0x30
R/W
0x00
0x00
Activate
0x60,
R/W
0x00,
0x00,
RTC Bank 0 Primary Base Address
0x61
0x70
0x70
0x62, 0x63 R/W
0x00, 0x74 0x00, 0x74 RTC Bank 1 Primary Base Address
0x70
R/W
0x00
0x00
Primary Interrupt Select
0xF0
R/W
0x00
n/a
Real Time Clock Mode Register
00xF1
R
Shadowed RTC/CMOS Bank 0 Index
Register
LOGICAL DEVICE 7 CONFIGURATION REGISTERS (KBD)
0x30
R/W
0x00
0x00
Activate
0x70
R/W
0x00
0x00
Primary Interrupt Select
0x72
R/W
0x00
0x00
Second Interrupt Select
0xF0
R/W
0x00
0x00
KRST_GA20
LOGICAL DEVICE 8 CONFIGURATION REGISTERS (EC)
0x30
R/W
0x00
0x00
Activate
0x60, 0x61 R/W
0x00, 0x62 0x00, 0x62 ECI Register Base I/O Address
LOGICAL DEVICE 9 CONFIGURATION REGISTERS (MAILBOX)
0x30
R/W
0x00
0x00
Activate
0x60, 0x61 R/W
0x00, 0x00 0x00, 0x00 Mailbox Register Base I/O Address
307
CHIP LEVEL (GLOBAL) CONTROL/CONFIGURATION REGISTERS [0X00-0X2F]
The chip-level (global) registers lie in the address range [0x00-0x2F].
The INDEX PORT is used to select a configuration register in the chip. The DATA PORT is then used
to access the selected register. These registers are accessible only in the Configuration State.
TABLE 214 - GLOBAL CONFIGURATION REGISTERS
REGISTER
ADDRESS
DESCRIPTION
Chip (Global) Control Registers
0x00 Reserved, Writes are ignored, reads
0x01
return 0.
Config Control
0x02 W
The hardware automatically clears this bit
after the write; there is no need for
software to clear the bits.
Bit [0] = 1: Soft Reset; Refer to TABLE
213 for the soft reset value for each
register.
Card Level
0x03W
Reserved - Writes are ignored, reads
Reserved
return 0.
0x04 - 0x06
Reserved - Writes are ignored, reads
return 0.
Logical Device #
0x07 R/W
A write to this register selects the current
logical device. This allows access to the
control and configuration registers for
each logical device. Note: The Activate
command operates only on the selected
logical device.
Card Level
0x08 - 0x1F
Reserved - Writes are ignored, reads
Reserved
return 0.
Chip-Level, SMSC Defined
Device ID
0x20 R
A read-only register which provides
Hard Wired
device identification.
Device Rev
Hard Wired
0x21 R
Bit[7-0]
FDC37N971 = 0x0A
FDC37N972 = 0x0B
A read-only register which provides
device revision information.
Bits[7-0] = 0x00 when read
308
STATE
C
C
C
C
REGISTER
PowerControl
ADDRESS
0x22 R/W
Power Mgmt
0x23 R/W
OSC
0x24 R/W
DESCRIPTION
Bit[0] FDC Power
Bit[1:2] Reserved (read as 0)
Bit[3] Parallel Port Power
Bit[4] Serial Port 1 Power
Bit[5] Serial Port 2 Power
Bit[6:7] Reserved (read as 0)
=0 Power off or disabled
=1 Power on or Enabled
Bit[0] FDC
Bit[1:2] Reserved (read as 0)
Bit[3] Parallel Port
Bit[4] Serial Port 1
Bit[5] Serial Port 2
Bit[6:7] Reserved (read as 0)
=0 Power off or disabled
=1 Power on or Enabled
Bit[1:0] Reserved, set to “0”
Bit[3:2] OSC
=01 OSC is on, BRG clock is on when
PWRGD is active, OSC is off and BRG
Clock is disabled (default)
=10 Same as above (01) case
=00 OSC is on, BRG Clock Enabled
=11 OSC is off, BRG Clock is disabled
Bit[6:4] CLK_OUT Select
=[0,0,0] CLK_OUT = 1.8432 MHz
=[0,0,1] CLK_OUT = 14.318 MHz
=[0,1,0] CLK_OUT = 16 MHz
=[0,1,1] CLK_OUT = 24 MHz
=[1,0,0] CLK_OUT = 48 MHz
=[1,0,1] Reserved
=[1,1,X] Reserved
Bit[7] nIRQ8 Polarity
=0 nIRQ8 is active high
=1 nIRQ8 is active low
Note: This polarity bit not only affects the
nIRQ8 pin, but is also reflected in the
Serial IRQ sample phase for the IRQ8
Frame for the Serial IRQ Bus.
309
STATE
C
C
C
REGISTER
Device Mode
ADDRESS
0x25 R/W
Chip Level
Vendor Defined
Test Registers
0x26
TEST 0
0x2C
TEST 1
0x2D R/W
TEST 2
0x2E R/W
TEST 3
0x2F R/W
0x27-0x2B
DESCRIPTION
Bit [1-0] Flash Timing
This register is used to program the width
of Flash Read (nFRD) and Flash Write
(nFWR) signals during Host Flash
accesses.
= 0,0 : nFRD/nFWR width = 3 sclks
= 0,1 : width = 2.5 sclks
= 1,0 : width = 2 sclks
= 1,1 : Reserved, do not use.
Bit[2] SerIRQ Mode
= 0 : Serial IRQ Disabled.
= 1 : Serial IRQ Enabled
(Default).
Bit [4:3] Parallel Port FDC
= [0:0] Normal
= [0:1] PPFD1 Mode
= [1:0] PPFD2 Mode
= [1:1] Reserved
Bit [7:5] Reserved - writes ignored, reads
return “0”.
Reserved - Writes are ignored, reads
return 0.
SMSC Test Mode Registers, Reserved for
SMSC.
Test Modes - Reserved for SMSC. Users
should not write to this register, may
produce undesired results.
Test Modes : Reserved for SMSC. Users
should not write to this register; may
produce undesired results.
Test Modes - Reserved for SMSC. Users
should not write to this register; may
produce undesired results.
Test Modes - Reserved for SMSC. Users
should not write to this register; may
produce undesired results.
310
STATE
C
C
C
LOGICAL DEVICE CONFIGURATION/CONTROL REGISTERS [0X30-0XFF]
Used to access the registers that are assigned
to each logical unit. This chip supports six
logical units and has six sets of logical device
registers. The logical devices are Floppy,
Parallel, Serial 1 and IRCC 2.0
Device and is selected with the Logical Device #
Register (0x07).
The INDEX PORT is used to select a specific
logical device register. These registers are then
accessed through the DATA PORT.
(UART),
Real Time Clock, and Keyboard
Controller. A separate set (bank) of control and
configuration registers exists for each Logical
The Logical Device registers are accessible only
when the device is in the Configuration State
The logical register addresses are listed in
TABLE 215.
TABLE 215 - LOGICAL DEVICE CONFIGURATION REGISTERS
LOGICAL DEVICE
REGISTER
ADDRESS
DESCRIPTION
Activate (1)
(0x30)
Bits[7:1] Reserved, set to “0”.
Bit[0]
=1
Activates the logical device
currently selected through the Logical
Device # register.
=0
Logical device currently selected
is inactive.
Bank Activation
(0x30)
Bits[7:2] Reserved, set to “0”.
FOR RTC ONLY
FOR RTC
Bit[1] Activates Bank 1
ONLY
Bit[0] Activates Bank 0
Bit[1:0]
=1
Activates the logical device
currently selected through the Logical
Device # register.
=0
Logical device currently selected
is inactive.
Logical Device Control
(0x31-0x37)
Reserved - Writes are ignored, reads
return “0”.
Logical Device Control
(0x38-0x3f)
Vendor Defined – Reserved - Writes are
ignored, reads return “0”.
Memory Base Address
(0x40-0x5F)
Reserved - Writes are ignored, reads
return “0”.
I/O Base Address
(0x60-0x6F)
All logical devices contain 0x60, 0x61.
0x60 =
Unused registers will ignore writes and
addr[15:8]
return “0” when read.
(see Table 216)
0x61=
addr[7:0]
311
STATE
C
C
C
C
C
LOGICAL DEVICE
REGISTER
Interrupt Select
ADDRESS
(0x70,072)
(0x71,0x73)
DMA Channel Select
(0x74)
(0x75)
32-Bit Memory Space
Configuration
(0x76-0xA8)
Logical Device
(0xA9-0xDF)
Logical Device
Configuration
(0xE0-0xFE)
Reserved
0xFF
DESCRIPTION
0x70 is implemented for each logical
device. Refer to Interrupt Configuration
Register description. Only the KYBD
controller uses Interrupt Select register
0x72. Unused register (0x72) will ignore
writes and return “0” when read. Interrupts
default to edge high (ISA compatible).
Reserved - not implemented. These
register locations ignore writes and return
“0” when read.
Only 0x74 is implemented for FDC , and
Parallel port. Refer TABLE 218 - DMA
CHANNEL SELECT CONFIGURATION
REGISTERS.
Reserved - not implemented and ignores
writes and returns “0” when read.
Reserved - not implemented. These
register locations ignore writes and return
“0” when read.
Reserved - not implemented. These
register locations ignore writes and return
“0” when read.
Reserved - Vendor Defined (see SMSC
defined Logical Device Configuration
Registers).
Reserved
STATE
C
C
C
C
C
Note1: A logical device will be active and powered up according to the following equation:DEVICE
ON (ACTIVE) = (Activate Bit SET AND Pwr/Control Bit SET) AND (8051 Disable Bit SET)
The Logical device's Activate Bit and its
Pwr/Control Bit are linked such that setting or
clearing one sets or clears the other. Three bits
in the 8051’s Disable Register (see Keyboard
spec), bits D7, D6 and D4 are capable of
overriding the Activate and PWR/Control bit
settings for logical devices 3, 4 and 0
respectivelely. Thus clearing bit D7 of the
Disable register will disable the FDC regardless
312
of the FDC’s Activate and PWR/Control bits.
When D7 of the Disable register is set, the
FDC’s Activate and PWR/Control bits will
determine the on/off state of the FDC. If the I/O
Base Addr of the logical device is not within the
Base I/O range as shown in the Logical Device
I/O map, then read or write is not valid and is
ignored.
I/O BASE ADDRESS CONFIGURATION REGISTER DESCRIPTION
LOGICAL
DEVICE
NUMBER
0x00
0x01
0x02
0x03
0x04
0x05
TABLE 216 - LOGICAL DEVICE, BASE I/O ADDRESSES
BASE I/O
RANGE
FIXED BASE
LOGICAL
REGISTER
(NOTE 1)
OFFSETS
DEVICE
INDEX
FDC
0x60,0x61
[0x100:0x0FF8]
+0 : SRA
+1 : SRB
+2 : DOR
ON 8 BYTE
+3 : TSR
BOUNDARIES
+4 : MSR/DSR
+5 : FIFO
+7 : DIR/CCR
Reserved
Reserved
+0 : Data | ecpAfifo
Parallel
0x60,0x61
[0x100:0x0FFC]
+1 : Status
Port
ON 4 BYTE
+2 : Control
BOUNDARIES
+3 : EPP Address *
(EPP Not supported)
+4 : EPP Data 0 *
or
+5 : EPP Data 1 *
[0x100:0x0FF8]
+6 : EPP Data 2 *
ON 8 BYTE
+7 : EPP Data 3 *
BOUNDARIES
+400h : cfifo | ecpDfifo |
(all modes supported,
tfifo | cnfgA
EPP is only available
+401h : cnfgB
when the base
+402h : ecr
address is on an 8byte boundary)
Serial Port 1 0x60,0x61
[0x100:0x0FF8]
+0 : RB/TB | LSB div
+1 : IER | MSB div
ON 8 BYTE
+2 : IIR/FCR
BOUNDARIES
+3 : LCR
+4 : MCR
+5 : LSR
+6 : MSR
+7 : SCR
IRCC 2.0
0x60,0x61
[0x100:0x0FF8]
+0 : RB/TB | LSB div
(UART)
+1 : IER | MSB div
ON 8 BYTE
+2 : IIR/FCR
BOUNDARIES
+3 : LCR
+4 : MCR
+5 : LSR
+6 : MSR
+7 : SCR
313
LOGICAL
DEVICE
NUMBER
0x05
LOGICAL
DEVICE
IRCC 2.0
(IR-SCE)
REGISTER
INDEX
0x62, 0x63
BASE I/O
RANGE
(NOTE 1)
[0x100:0x0FF8]
ON 8 BYTE
BOUNDARIES
0x06
RTC
0x60, 0x61
[0x00:0x0FFE]
0x62, 0x63
[0x00:0x0FFD]
0x07
KYBD
N/a
Not Relocatable
Fixed Base Address
0x08
ECI
0x60, 0x612
0x09
Mailbox
Register
0x60, 0x61
[0x0000:0xFFA]
Relocatable
[0x0000:0x0FFE]
FIXED BASE
OFFSETS
+0 : Register Block N,
address 0
+1 : Register Block N,
address 1
+2 : Register Block N,
address 2
+3 : Register Block N,
address 3
+4 : Register Block N,
address 4
+5 : Register Block N,
address 5
+6 : Register Block N,
address 6
+7: SCE Master Control
Reg.
Bank 0 Base address
+0 : Address Register
+1 : Data Register *
Bank 1 Base address
+0 : Address Register
+2 : Data Register *
0x60 : Data Register
0x64 : Command/Status
Reg.
+0 : Data Register3
+4 : COMMAND REGISTER
+0 : Index
+1 : Data
Note 1: This chip uses all ISA address bits to decode the base address of each of its logical
devices.
Note 2: Please refer to TABLE 49 for further description.
Note 3: Please refer to TABLE 50 for further description.
Note*: When these registers are accessed the nNOWS line is not asserted. All other registers in
this table assert the nNOWS signal when accessed.
314
INTERRUPT SELECT CONFIGURATION REGISTER DESCRIPTION
Name
Interrupt
request level
select 0
TABLE 217 - INTERRUPT SELECT CONFIGURATION REGISTERS
Reg Index
Definition
0x70 (R/W)
Bit [3-0] Select which interrupt level is used for
Interrupt 0.
State
C
0x00=no interrupt selected.
0x01=IRQ1
0x02=IRQ2
•
•
•
0x0E= IRQ14
0x0F= IRQ15
All pin-type interrupts are edge high (except
ECP/EPP). Each Logical Device’s interrupts selected
through this register physically select the interrupts to
be used by the FDC37N972 for either the Serial IRQ
interface or for the individual pin-type ISA interrupts if
selected. Setting the IRQ through this register for the
Parallel Port is not reflected in the Enhanced Parallel
port cnfgB register, software must set the DMA/IRQ
bits in the Parallel Port logical device config register
0xF1 (Parallel Port CnfgB shadow register).
Note : An interrupt is activated by setting the Interrupt Request Level Select 0 register to a non-zero
value AND :
1. For the FDC logical device by setting DMAEN, bit D3 of the Digital Output Register.
2. For the PP logical device by setting IRQE, bit D4 of the Control Port and in addition
3. For the PP logical device in ECP mode by clearing serviceintr, bit D2 of the ecr.
4. For the Serial Port logical device by setting any combination of bits D0-D3 in the IER and by
setting the OUT2 bit in the UART's Modem Control (MCR) Register.
5. For the RTC by (refer to the RTC section of this specification).
6. For the KYBD by (refer to the KYBD controller section of this specification).
315
DMA CHANNEL SELECT CONFIGURATION REGISTER DESCRIPTION
TABLE 218 - DMA CHANNEL SELECT CONFIGURATION REGISTERS
NAME
REG INDEX
DEFINITION
STATE
C
DMA Channel
0x74 (R/W)
Bit [2:0] Select the DMA Channel.
select 0
0x00=DMA0
0x01=DMA1
0x02=DMA2
0x03=DMA3
0x04-0x07= No DMA active
Note:
AND :
1.
2.
3.
A DMA channel is activated by setting the DMA Channel Select 0 register to [0x00-0x03]
For the FDC logical device by setting DMAEN, bit D3 of the Digital Output Register
For the PP logical device in ECP mode by setting dmaen, bit D3 of the ecr
For the UART2 logical device, by setting the DMA Enable bit. Refer to the IRCC 2.0 specification
available from SMSC
Note:
DMAREQ pins must tri-state if not used/selected by any Logical Device.
316
IRQ AND DMA ENABLE AND DISABLE
Interrupt is disabled when:
Any time the IRQ and/or DMA channels for a
logical device are disabled by a register in that
logical device, the IRQ and/or nDACK must be
disabled. This is in addition to the IRQ and
nDACK disabled by the Configuration Registers
(activate bit cleared or address outside of valid
range or the Interrupt Select register set to 0x00
or the DMA Channel Select register set to 0x04).
Modem Control Register (MCR) bit 2 (OUT2) When OUT2 is a logic “0”, then Logical Device
5’s interrupt is forced to a high impedance state,
i.e., disabled. This applies to all UART/IR
modes of operation.
LOGICAL DEVICE 0 (FDC)
For the following cases, the IRQ and DACK
used by the FDC are disabled (high impedance),
i.e., will not respond to the DREQ Digital Output
Register (Base+2) bit D3 (DMAEN) set to "0".
The FDC is in power down (disabled).
LOGICAL DEVICE 5 (SERIAL PORT1)
Modem Control Register (MCR) Bit D2 (OUT2) When OUT2 is a logic "0", then the serial port
interrupt is forced to a high impedance state disabled.
DRQ is disabled when:
SCE Configuration Register B bit-0 (DMA
Enable) - When the DMA Enable bit is a logic
“0”, then logical device 5’s DRQ pin is forced to
a high impedance state, i.e., disabled. When
the DMA Enable bit is set to logic “1”, then
logical device 5’s DRQ pin is active and drives
low until the device issues a DMA Request at
which point the DRQ pin drives high. This
eliminates the need for an external pull-down
resistor on the logical device 5’s DRQ pin.
PARALLEL PORT
SPP and EPP modes: Control Port (Base+2) bit
D4 (IRQE) set to "0", IRQ is disabled (high
impedance).
LOGICAL DEVICE 5 (SERIAL PORT2/USART)
ECP Mode:
(DMA) dmaEn from ecr register.
000
001
010
011
100
101
110
111
MODE
(FROM ECR REGISTER)
PRINTER
SPP
FIFO
ECP
EPP
RES
TEST
CONFIG
IRQ - See table below.
IRQ PIN
CONTROLLED BY
IRQE
IRQE
(on)
(on)
IRQE
IRQE
(on)
IRQE
317
PDREQ PIN
CONTROLLED BY
dmaEn
dmaEn
dmaEn
dmaEn
dmaEn
dmaEn
dmaEn
dmaEn
REAL TIME CLOCK (RTC)
(refer to the RTC section)
KEYBOARD CONTROLLER (KYBD)
(REFER TO THE KEYBOARD CONTROLLER SECTION)
SMSC DEFINED LOGICAL DEVICE CONFIGURATION REGISTERS
The SMSC Specific Logical Device Configuration Registers reset to their default values only on hard
resets generated by VCC2 POR or the nRESET_OUT signal. These registers are not effected by soft
resets.
318
TABLE 219 - FDC, LOGICAL DEVICE 0 [LOGICAL DEVICE NUMBER = 0X00]
NAME
REG INDEX
DEFINITION
FDD Mode
0xF0 R/W
Bit[0] Floppy Mode
Register
=0 Normal Floppy Mode (default)
=1 Enhanced Floppy Mode 2 (OS2)
Bit[1] FDC DMA Mode
Default = 0x0E
=0 Burst Mode is enabled
=1 Non-Burst Mode (default)
Bit[3:2] Interface Mode
Bit 3 – IDENT
Bit 2 – MFM
=11 AT Mode (default)
=10 (Reserved)
=01 PS/2
=00 Model 30
Bit[4] Swap Drives 0,1 Mode
=0 No swap (default)
=1 Drive and Motor Sel 0 and 1 are swapped
Bit[5] FDC Shutdown
=0 FDC37N972 FDC operates normally, FDC pins are
active (default)
=1 FDC core is shutdown, only I/O Writes to DOR,
TDR, DSR and CCR are enabled, all Floppy Disk
interface pins tri-state except for DRVDEN0, DRVDEN1,
nDS0, nDS1, nMTR0, and nMTR1.
Bit[6] FDC Output Type Control
=0 FDC Outputs are OD24 Open Drain (default)
=1 FDC Outputs are O24 push pull
Bit[7] FDC Output Control
=0 FDC Outputs active (default)
=1 FDC Outputs tri-stated
FDD Option
Register
Default = 0x00
0xF1 R/W
Bits 6 and 7 do not reflect the Parallel Port FDC pins.
Bit[1:0] Reserved, set to “0”
Bit[3-2] Density Select
=00 Normal (default)
=01 Normal (reserved for users)
=10 (forced to logic “1”)
=11 (forced to logic “0”)
Bit[5:4] Reserved
Bit[7:6] Boot Floppy
=00 FDD 0 (default)
=01 FDD 1
=10 FDD 2
=11 FDD 3
319
STATE
C
C
NAME
FDD Type
Register
REG INDEX
0xF2 R/W
Default = 0Xff
0xF3 R
0xF4 R/W
FDD0
Default = 0x00
FDD1
0xF5 R/W
DEFINITION
Bit[1:0] Floppy Drive A Type
Bit[3:2] Floppy Drive B Type
Bit[5:4] Floppy Drive C Type
Bit[7:6] Floppy Drive D Type
Reserved, read as 0 (read only)
Bit[1:0] Drive Type Select
Bit[2] Read as “0” (read only)
Bit[3:4] Data Rate Table Select
Bit[5] Read as “0” (read only)
Bit[6] Precomp Disable
Bit[7] Read as “0” (read only)
Refer to definition and default for 0xF4
DT0
0
DT1
0
DRVDEN0 (1)
DENSEL
DRVDEN1 (1)
DRATE0
0
1
1
1
0
1
DRATE1
nDENSEL
DRATE0
DRATE0
DRATE0
DRATE1
STATE
C
C
C
C
DRIVE TYPE
4/2/1 MB 3.5”
2/1 MB 5.25” FDDS
2/1.6/1 MB 3.5” (3MODE)
There are four of the following registers in the configuration data space, one for each drive.
FDD0 - 0xF4/FDD1 - 0xF5
D7
0
PTS
D6
PTS
D5
0
D4
DRT1
D3
DRT0
D2
0
D1
DT0
D0
DT1
= 0 Use Precompensation, = 1 No Precompensation
DTx = Drive Type Select
DRTx = Data Rate Table Select
DENSEL, DRATE1 and DRATE0 map onto three output pins DRVDEN0 and DRVDEN1.
320
TABLE 220 - PARALLEL PORT, LOGICAL DEVICE 3 [LOGICAL DEVICE NUMBER = 0X03]
REG
NAME
INDEX
DEFINITION
STATE
C
PP Mode Register 0xF0 R/W Bit [2:0] Parallel Port Mode
= 100 Printer Mode (default)
= 000 Standard and Bi-directional (SPP) Mode
Default = 0x3C
= 001 EPP-1.9 and SPP Mode
= 101 EPP-1.7 and SPP Mode
= 010 ECP Mode
= 011 ECP and EPP-1.9 Mode
= 111 ECP and EPP-1.7 Mode
Bit[6:3] ECP FIFO Threshold
0111b (default)
Bit[7] PP Interrupt Type
Not valid when the parallel port is in the Printer
Mode (100) or the Standard $ Bi-Directional
Mode (000)
Parallel Port
CnfgB shadow
Register
Default = 0x00
0xF1 R/W
=1 Pulsed Low, released to high-Z (665/666)
=0 IRW follows nACK when parallel port in EPP
Mode or [Printer, SPP, EPP] under ECP, TEST or
Centronics FIFO Mode.
Bit [2:0] Parallel Port DMA channel Select
= 000 h/w jumpered 8-bit DMA (default)
= 001 DMA channel 1
= 010 DMA channel 2
= 011 DMA channel 3
Bit [5:3] Parallel Port IRQ line Select
= 000 h/w jumpered IRQ (default)
= 001 IRQ 7
= 010 IRQ 9
= 011 IRQ 10
= 100 IRQ 11
= 101 IRQ 14
= 110 IRQ 15
= 111 IRQ 5
Bit [7:6] Reserved, ignores writes returns “0” on
reads.
The DMA/IRQ bits in this register are reflected in
the Enhanced Parallel Port’s read only cnfgB
register.
321
C
TABLE 221 - SERIAL PORT 1, LOGICAL DEVICE 4 [LOGICAL DEVICE NUMBER = 0X04]
REG
NAME
INDEX
DEFINITION
STATE
C
Serial Port 1
0xF0 R/W
Bit[0] MIDI Mode
Mode Register
= 0 MIDI support disabled (default)
= 1 MIDI support enabled
Bit[1] High Speed
Default = 0x00
= 0 High Speed Disabled (default)
= 1 High Speed Enabled
Bit[6:2] Reserved, set to “0”
Bit[7] Reserved
TABLE 222 - INFRARED, LOGICAL DEVICE 5 [LOGICAL DEVICE NUMBER = 0X05]
REG
NAME
INDEX
DEFINITION
STATE
C
Infrared
oxF0 R/W
Bit[0] MIDI Mode
Mode Register
=0 MIDI support disabled (default)
=1 MIDI support enabled
Bit[1] High Speed
Default = 0x00
=0 High Speed Disabled (default)
=1 High Speed Enabled
Bit[7:2] Reserved
322
NAME
IR Option Register
Default = 0x00
This register sets
the IR options and
uses the same bit
definitions as the
FDC37C93x
REG
INDEX
oxF1 R/W
DEFINITION
Bit[0] Receive Polarity
=0 Active High
=1 Active Low (default)
Bit[1] Transmit Polarity
=0 Active High (Default)
=1 Active Low
Bit[2] Duplex Select
=0 Full Duplex (Default)
=1 Half Duplex
Bit[5:3] UART/IR Mode
=000 Standard COMM (default)
=001 IrDA SIR-A
=010 ASK-IR
=011 (IrDA SIR-B)
=100 (IrDA HDLC)
=101 (IrDA 4PPM)
=110 (Consumer)
=111 (Raw IR)
Bit[7:6] IRCC 2.0 Output Mux
=00 Active Device to COM-RX/COMTX port (default)
=01 Active Device to IRRX/IRTX port
=10 Reserved-use AUX port not
mapped to pins thus both IR and COM
ports are inactive
=11 Reserved, all ports are inactive
323
STATE
C
NAME
IR Half Duplex
Timeout
Default = 0x03
REG
INDEX
0xF2 R/W
DEFINITION
Bit[7:0]
These bits set the half duplex time-out
for the IR port. This value is 0 to 10ms
in 100µs increments
STATE
=0x00 blank RX/TX during
Transmit/Receive
=0x01 blank TX/TX during Xmit/Rcv +
100µs
......
=0x64 blank RX/TX during Xmit/Rcv
+10ms
=0x65 - 0xFF : Reserved
EN_1 : Bits [5:0] of the IR Option
Configuration Register must be reconciled
with bits[5:0] of the “SCE Configuration
Register A” control register in the IRCC 2.0
Block, detailed in the IRCC 2.0
specification. Additionally bits [7:6] of the
IR Option Configuration Register must be
reconciled with bits[5:4] of the “SCE
Configuration Register B” control register in
the IRCC 2.0 Block. The last register
written should update the information in
both registers. Both sets of registers can
use common latches to store the
information.
TABLE 223 - RTC, LOGICAL DEVICE 6 [LOGICAL DEVICE NUMBER = 0X06]
REG
NAME
INDEX
DEFINITION
STATE
RTC Mode Register 0xF0 R/W
Bit[0] = 1 : Lock CMOS RAM 80-9Fh
C
Bit[1] = 1 : Lock CMOS RAM A0-BFh
Default = 0x00
Bit[2] = 1 : Lock CMOS RAM C0-DFh
Bit[3] = 1 : Lock CMOS RAM E0-FEh
Bit[7:4] Reserved, set to “0”
Once set, bit[3:0] can not be cleared by a
write; bits[3:0] are cleared on VCC2
Power On Reset, VCC2 Power Off, or
upon a Hard Reset (nRESET_OUT
asserted). Once lock bits are set, both the
Host and the 8051 are locked out of
accessing the locked locations as long as
VCC1 and VCC2 are active. When VCC2
goes to 0V, the lock bits are cleared and
the 8051 can access this RAM while
nRESET_OUT is asserted.
324
NAME
RTC CMOS Bank 0
Index Register
REG
INDEX
OxF1 R
DEFINITION
Shadowed RTC/CMOS Bank 0 Index
Register
STATE
TABLE 224 - KYBD, LOGICAL DEVICE 7 [LOGICAL DEVICE NUMBER = 0X07]
REG
NAME
INDEX
DEFINITION
STATE
Bit[0] : ENAB_P92
= 0 : Port 92 Disabled
KRST_GA20
0xf0 R/W
= 1 : Port 92 Enabled
Bit[7:0] : Reserved, set to “0”.
NOTE : Refer to the 8051 section for descriptions of these registers.
SYSTEM SHADOW REGISTERS
The FDC37N972 makes the following Control Registers readable by supplying a set of Index
Registers accessable either through Logical Device 7 when in Configuration State or through the Open
Mode Index and Data registers when in Run State.
Force
Diskchange
Floppy
Data Rate
Select
Shadow
Register
UART1
FIFO
Control
Shadow
Register
Sys.
index
MBX99
Sys
R/W
R
8051
address
(7F00+)
------
8051
R/W
N/A
Power
Source
VCC2
MBX9A
R
------
N/A
VCC2
N/A
MBX9B
R
------
N/A
VCC2
00h
325
VCC1
POR
VCC2
POR
03h
Zero
Wait
State (9)
Notes
-----------
8051 R/W
System
R/W
Bit Def
Note:
D7
N/A
R
FLOPPY DATA RATE SELECT SHADOW REGISTER
D6
D5
D4
D3
D2
D1
N/A
N/A
N/A
N/A
N/A
N/A
R
R
R
R
R
R
Soft
Reset
Power
Down
PRECOMP 2
PRECOMP 1
PRECOMP 0
Data
Rate
Select 1
Data
Rate
Select 0
D1 and D0 are updated by a write to the Floppy Data Rate or CCR registers. Bits D7-D2
are updated by a write to the Floppy Data Rate register only.
FORCE DISKCHANGE
D1
D7-D2
System
R/W
Bit Def
0
D0
N/A
R
D0
R
R/W
R/W
Reserved
1 = Force a diskchange indication when the DIR register (of the Floppy
controller) is read, gated with Drive Select 0 or 1. These bits can be
written to a “1” but are not clearable by the software. These bits are
reset when nSTEP input is active with the proper drive select to the
drive occurs. D0 is cleared on nSTEP and Drive Select 0; D1 is
cleared on nSTEP and Drive Select 1.
Equivalent logic: when read DIR bit 7 = (Drive_Sel_0 & D0) OR (Drive_Sel_1 & D1) OR DSK_CHG
326
ELECTRICAL SPECIFICATIONS
MAXIMUM GUARANTEED RATINGS*
Operating Temperature Range......................................................................................... 0oC to +70oC
Storage Temperature Range..........................................................................................-55o to +150oC
Lead Temperature Range (soldering, 10 seconds) .................................................................... +325oC
Positive Voltage on any pin, with respect to Ground .................................................................... +5.5V
Negative Voltage on any pin, with respect to Ground.................................................................... -0.3V
Supply Voltage Range VCC1 and VCC2............................................................................VCC1 and VCC2
*Stresses above those listed above could cause permanent damage to the device. This is a stress
rating only and functional operation of the device at any other condition above those indicated in the
operation sections of this specification is not implied.
NOTE: When powering this device from laboratory or system power supplies, it is important that the
Absolute Maximum Ratings not be exceeded or device failure can result. Some power supplies exhibit
voltage spikes on their outputs when the AC power is switched on or off. In addition, voltage
transients on the AC power line may appear on the DC output. If this possibility exists, it is suggested
that a clamp circuit be used.
SYMBOL
Vcc0
Vcc1
Vcc2
PCI_CLK
XTAL1/XTAL2
CLOCKI
VCC2
(VDC)
3.3
VCC1
(VDC)
3.3
3.3
3.3
3.3
3.3
3.3
3.3
0
3.3
0
3.3
TABLE 223 - OPERATING CONDITIONS
PARAMETER
MIN
TYP
Vbat for RTC
2.4
3.0
Vcc for 8051
3.15
3.3
System Vcc
3.15
3.3
PCI Clock
33
RTC Crystal
32.768
14.318 Clock Input
14.318
MAX
3.3
3.45
3.45
UNITS
V
V
V
MHz
kHz
MHz
POWER COMSUMPTION IN VARIOUS STATES
8051
CLOCK
STATE
STATE
SYM
TYP
MAX
COMMENTS
Run
24 MHz
ICC2
15 ma
20 ma
FLOPPY @ 1 Meg Data Rate
ICC1
24 ma
30 ma
I2C @ 24 MHz
Run
12 MHz
ICC2
13 ma
15 ma
Floppy @ 500K Data Rate
ICC1
12 ma
18 ma
I2C @ 12 MHz
Run
Ring
ICC2
>1ma
2 ma
PLL On
OSC
ICC1
8 ma
10 ma
I2C Off
Idle
Ring
ICC2
>1ma
2 ma
PLL Off
OSC
ICC1
5 ma
7 ma
Run
Ring
ICC2
PLL Off
OSC
ICC1
8 ma
10 ma
I2C Off
Idle
Ring
ICC2
PLL Off
OSC
ICC1
6 ma
8 ma
I2C Off
327
VCC2
(VDC)
0
0
0
0
Note:
VCC1
(VDC)
3.3
3.3
0
8051
STATE
Sleep
Sleep
CLOCK
STATE
Stop
Stop
SYM
ICC1
ICC1
ICC0
TYP
MAX
160 µa
10 µa
60 µa
COMMENTS
XOSEL=1
5 µa
XOSEL=0
40 µa
2.4 < Vcc0 < 4 VDC,
XOSEL=1,
0
ICC0
0.4 µa
1.5 µa
2.4 < Vcc0 < 4 VDC,
XOSEL = 0
When a single-ended 32.768kHz clock source is selected (see Section 32kHz Clock Input.
The FDC37N972 uses the XOSEL pin to select either a 32.768kHz input clock or a
32.768kHz crystal to drive the Real Time Clock Interface (Table 2 - PIN FUNCTION
DESCRIPTION). When XOSEL = ‘0’, The RTC uses a 32.768kHz crystal connected between
the XTAL1 and XTAL2 pins. When XOSEL = ‘1’, the RTC is driven by a 32.768kHz singleended clock source connected to the XTAL2 pin.
DC SPECIFICATIONS
DC ELECTRICAL CHARACTERISTICS (TA = 0°C - 70°C, VCC1 and VCC2= VCC1 and VCC2)
PARAMETER
SYMBOL MIN TYP MAX UNITS
COMMENTS
I Type Input Buffer
VILI
0.8
V
TTL Levels
Low Input Level
VIHI
2.0
V
High Input Level
IS Type Input Buffer
VILIS
0.8
V
Schmitt Trigger
Low Input Level
VIHIS
2.2
V
High Input Level
VHYS
250
mV
Schmitt Trigger
Schmitt Trigger Hysteresis
ISP Type Input Buffer
with 90 µA weak pull-up
VILIS
2.2
0.8
V
Schmitt Trigger
Low Input Level
VIHIS
250
V
High Input Level
VHYS
mV
Schmitt Trigger
Schmitt Trigger Hysteresis
ICLK Input Buffer
VILCK
0.4
V
Low Input Level
VIHCK
3.0
V
High Input Level
Use a 32 kHz parallel resonant crystal oscillator. The load capacitors
OCLK2 Crystal Oscillator
are seen by the crystal as two capacitors in series and should be
Output
approximately 2 times the Co of the actual crystal used (C1=2Co).
For example, a 7.5pF crystal should use two 15pF capacitors for
ICLK2 Crystal Oscillator
proper loading.
Input
328
PARAMETER
Input Leakage
(All I and IS buffers
except PWRGD &
VCC1_PWRGD)
Low Input Leakage
High Input Leakage
Input Current
PWRGD
O4 Type Buffer
SYMBOL
MIN
TYP
MAX
UNITS
IIL
IIH
IOH
-10
-10
Low Output Level
High Output Level
Output Leakage
OD4 Type Buffer
VOL
VOH
IOL
Low Output Level
Output Leakage
O8 Type Buffer
VOL
IOH
Low Output Level
VOL
High Output Level
VOH
2.4
Output Leakage
OD8 Type Buffer
IOL
-10
Low Output Level
VOL
Output Leakage
O24 Type Buffer
IOH
75
+10
+10
150
µA
µA
µA
VIN = 0
VIN = VCC
VIN = 0
2.4
0.4
-10
+10
V
V
µA
IOL = 4 mA
IOH = -2 mA
VIN = 0 to VCC
-10
0.4
+10
V
µA
VOL = 4 mA
IOH = 0 to VCC
0.4
V
IOL = 8 mA
V
IOH = -4 mA
+10
µA
VIN = 0 to VCC
0.4
V
VOL = 8 mA
+10
µA
IOH = 0 to VCC
Low Output Level
VOL
0.4
V
IOL = 24 mA
High Output Level
VOH
2.4
V
IOH = -12 mA
Output Leakage
OD24 Type Buffer
IOL
-10
+10
µA
VIN = 0 to VCC
Low Output Level
VOL
0.4
V
IOL = 24 mA
High Output Level
VOH
2.4
V
IOH = -50 mA
Output Leakage
IOL
-10
µA
VIN = 0 to Vcc
-10
+10
329
COMMENTS
PARAMETER
IO12 Type Buffer
Low Output Level
High Output Level
Output Leakage
SYMBOL
MIN
TYP
VOL
VOH
IOL
MAX
UNITS
0.4
V
IOL = 12mA
V
IOH = -6mA
+10
µA
VIN = 0 to VCC
(Note 2)
0.4
V
IOL = 8mA
V
IOH = -4mA
2.4
-10
COMMENTS
IO8 Type Buffer
Low Output Level
High Output Level
Output Leakage
VOL
VOH
IOL
2.4
-10
+10
µA
VIN = 0 to VCC
(Note 2)
Input Leakage
(All I and IS buffers
except
FAD[7:0]
FAD[7:0]
Input Leakage
Low Input Leakage
IIL
-100
+100
nA
VIN = 0
High Input Leakage
IOD8 Type Buffer
Low Output Level
IIH
-100
+100
nA
VIN = VCC
0.5
V
IOL=8 mA
2.0
V
0.8
V
0.5
V
2.0
V
0.8
V
High Input Level
High Inputt Level
Output Leakage
IOD16 Type Buffer
Low Output Level
High Input Level
High Inputt Level
VOL
VIH
VIL
VOL
VIH
VIL
Output Leakage
330
IOL=16 mA
PARAMETER
IOP14 Type Buffer
Low Output Level
High Output Level
Output Leakage
SYMBOL
MIN
TYP
VOL
VOH
IOL
MAX
UNITS
0.4
V
IOL = 14mA
V
IOH = -14mA
+10
µA
VIN = 0 to VCC
(Note 2)
0.8
V
2.4
-10
COMMENTS
IP Type Buffer
Low Input Level
VILI
High Input Level
O12 Type Buffer
VIHI
Low Output Level
VOL
High Output Level
VOH
2.0
V
0.4
V
IOL = 12mA
V
IOH = -6mA
0.4
V
IOL = 12mA
+10
µA
VIN = 0 to VCC
0.4
V
IOL = 14mA
+10
µA
VIN = 0 to VCC
0.4
V
IOL = 16mA
+10
µA
VIN = 0 to VCC
0.4
V
IOL = 14mA
V
IOH = -14mA
µA
VIN = 0 to VCC
(Note 2)
2.4
OD12 Type Buffer
Low Output Level
VOL
Output Leakage
OD14 Type Buffer
IOL
Low Output Level
VOL
Output Leakage
OD16 Type Buffer
IOL
Low Output Level
VOL
Output Leakage
OP14 Type Buffer
IOL
Low Output Level
High Output Level
Output Leakage
-10
-10
-10
VOL
VOH
IOL
2.4
-10
+10
331
PARAMETER
PCI_CLK Type Buffer
SYMBOL
MIN
TYP
MAX
UNITS
0.4
V
PCI_IO Type Buffer
PCI_OD Type Buffer
COMMENTS
See
Specification for PCI
Systems Version 6.0
See
Specification for PCI
Systems Version 6.0
See
Specification for PCI
Systems Version 6.0
ICLK Type Buffer
Low Input Level
High Input Level
ICLK2 Type Buffer
OCLK2 Type Buffer
Supply Current Active
Supply Current Sleep
VILI
VIHCLK
2.4
V
Use a 32 Khz parellel rosinant cystal oscillator. The load copacitors
are seen by the crystal as tow capacitors in series and should be
approximately 2 times the C0 of the actual crystal used (c1- co.) For
example a 7.5 pF cyrstal should use two 15 pF capacitors for proper
loading.
ICC
50
mA
ICC2 + ICC1 (Note 1)
25
ISLP
µA
ICC1 with Vcc2 Off, Sleep
mode
Notes:
1) This value is with the FDC at less than 2 MHz, and the 8051running at the ring oscillator drawing
8mA. The max value is 60mA with the FDC at 2 MHz. The ring oscillator is typically 4 – 8 MHz.
2) All output leakage’s are measured with the current pins in high impedance
AC SPECIFICATIONS
AC TEST CONDITIONS
CAPACITANCE TA = 25°C; fc = 1MHz; Vcc = 5V
LIMITS
PARAMETER
SYMBOL
MIN
TYP MAX UNIT
TEST CONDITION
Clock Input Capacitance CIN
20
pF
All pins except pin
under test tied to AC
Input Capacitance
CIN
10
pF
ground
Output Capacitance
COUT
20
pF
332
TIMING DIAGRAMS
LOAD CAPACITANCE
For the timing diagrams shown, the following capacitive loads are used.
NAME
SD[0:7]
IOCHRDY
nIRQ8
nSMI
DRQ[0:1]
32kHz_OUT
24MHz_OUT
nWGATE
nWDATA
nHDSEL
nDIR
nSTEP
nDS[1:0]
nMTR[1:0]
DRVDEN[1:0]
TXD1
nRTS1
nDTR1
PD[0:7]
nSLCTIN
nINIT
nALF
nSTROBE
TABLE 226 - CAPACITIVE LOADING
CAPACITANCE
TOTAL (pF)
NAME
240
EMCLK
240
EMDAT
120
IMCLK
120
IMDAT
120
KBDAT
50
KBCLK
50
PS2DAT
240
PS2CLK
240
nNOWS
240
FAD[0:7]
240
FA[8:17]
240
nFRD
240
nFWR
240
FALE
240
KSO[0:13]
100
SIRQ
100
FPD
100
AB_DATA
240
AB_CLK
240
IRTX
240
PWM[0:1]
240
nRESET_OUT
240
333
CAPACITANCE
TOTAL (pF)
240
240
240
240
240
240
240
240
240
100
100
50
50
50
100
150
50
100
100
50
50
240
FAST GATEA20 IOW TIMING
t3
SA[x]
t4
SD[7:0]
t2
t1
t5
nIOW
FIGURE 51 - FAST GATEA20 IOW TIMING
In order to use the FastGATEA20 speed-up mechanism, data must be available by the falling
edge of nIOW.
NAME
t1
t2
t3
t4
t5
TABLE 227 - FAST GATEA20 IOW TIMING PARAMETERS
DESCRIPTION
MIN
TYP MAX
SA[x] Valid to nIOW Asserted
10
SD[7:0] Valid to nIOW Asserted
0
nIOW Asserted to SA[x] Invalid
10
nIOW Deasserted to SD[7:0] Invalid
0
nIOW Deasserted to nIOW or nIOR Asserted
100
334
UNITS
ns
ns
ns
ns
ns
ISA IO WRITE
t10
AEN
t3
SA[x]
t2
t1
t4
t6
nIOW
t5
SD[x]
DATA VALID
t7
FINTR
t8
PINTR
t9
IBF
FIGURE 52 - ISA IO WRITE
NAME
t1
t2
t3
t4
t5
t6
t7
t8
t9
t10
TABLE 228 - ISA IO WRITE PARAMETERS
DESCRIPTION
MIN
SA[x] and AEN Valid to nIOW Asserted
10
nIOW Asserted to nIOW Deasserted
80
nIOW Asserted to SA[x] Invalid
10
SD[x] Valid to nIOW Deasserted
45
SD[x] Hold from nIOW Deasserted
0
nIOW Deasserted to nIOW Asserted
25
nIOW Deasserted to FINTR Deasserted (Note 1)
nIOW Deasserted to PINTER Deasserted (Note 2)
IBF (internal signal) Asserted from nIOW Deasserted
nIOW Deasserted to AEN Invalid
10
Note 1: FINTR refers to the IRQ used by the floppy disk logical device.
Note 2: PINTR refers to the IRQ used by the parallel port logical device.
335
TYP
MAX
55
260
40
UNITS
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ISA IO READ CYCLE
t13
AEN
t3
SA[x]
t1
nIOR
SD[x]
t7
t2
t6
t4
t5
DATA VALID
PD[x], nERROR,
PE, SLCT, ACK, BUSY
t10
FINTER
PINTER
t9
t11
PCOBF
t12
AUXOBF1
t8
nIOR/nIOW
FIGURE 53 - ISA IO READ CYCLE
NAME
t1
t2
t3
t4
t5
t6
t8
t8
t7
t9
t10
t11
TABLE 229 - ISA IO READ TIMING PARAMETERS
DESCRIPTION
MIN TYP
SA[x] and AEN Valid to nIOR Asserted
10
nIOR Asserted to nIOR Deasserted
50
nIOR Asserted to SA[x] Invalid
10
nIOR Asserted to Data Valid
Data Hold/Float from nIOR Deasserted
10
nIOR Deasserted to nIOR Asserted
25
nIOR Asserted after nIOW Deasserted
80
nIOR/nIOR, nIOW/nIOW Transfers from/to ECP
150
FIFO
Parallel Port Setup to nIOR Asserted
nIOR Asserted to PINTER Deasserted
nIOR Deasserted to FINTER Deasserted
nIOR Deasserted to PCOBF Deasserted (Notes
3,5)
336
MAX
50
25
20
55
260
80
UNITS
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
NAME
t12
t13
Note 1:
Note 2:
Note 3:
Note 4:
Note 5:
DESCRIPTION
nIOR Deasserted to AUXOBF1 Deasserted (Notes
4,5)
nIOR Deasserted to AEN Invalid
FINTR refers to the IRQ used by the floppy disk.
PINTR refers to the IRQ used by the parallel port.
PCOBF is used for the Keyboard IRQ.
AUXOBF1 is used for the Mouse IRQ.
Applies only if deassertion is performed in hardware.
337
MIN
10
TYP
MAX
80
UNITS
ns
ns
t1
t2
t2
CLOCKI
FIGURE 54 - INPUT CLOCK TIMING
NAME
t1
t2
tr, tf
Note:
TABLE 230 - INPUT CLOCK TIMING PARAMETERS
DESCRIPTION
MIN TYP MAX
Clock Cycle Time for 14.318 MHz (Note)
69.84
Clock High Time/Low Time for 14.318 MHz
15
Clock Rise Time/Fall Time (not shown)
5
Tolerance is ± 0.01%.
338
UNITS
ns
ns
ns
DMA TIMING (SINGLE TRANSFER MODE)
t15
AEN
t16
t3
t2
FDRQ,
PDRQ
t1
t4
nDACK
t12
t14
t11
t6
t5
t8
nIOR
or
nIOW
t10
t9
t7
DATA
(DO-D7)
DATA VALID
t13
TC
FIGURE 55 - DMA TIMING (SINGLE TRANSFER MODE)
NAME
t1
t2
t3
t4
t5
t6
t7
t8
t9
t10
t11
t12
t13
t14
t15
t16
TABLE 231 - DMA TIMING (SINGLE TRANSFER MODE) PARAMETERS
DESCRIPTION
MIN
TYP
MAX
nDACK Delay Time from FDRQ High
0
DRQ Reset Delay from nIOR or nIOW
100
FDRQ Reset Delay from nDACK Low
100
nDACK Width
150
nIOR Delay from FDRQ High
0
nIOW Delay from FDRQ High
0
Data Access Time from nIOR Low
100
Data Set Up Time to nIOW High
40
Data to Float Delay from nIOR High
10
60
Data Hold Time from nIOW High
10
nDACK Set Up to nIOW/nIOR Low
5
nDACK Hold after nIOW/nIOR High
10
TC Pulse Width
60
AEN Set Up to nIOR/nIOW
40
AEN Hold from nDACK
10
TC Active to PDRQ Inactive
100
339
UNITS
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
DMA TIMING (BURST TRANSFER MODE)
t15
AEN
t16
t3
t2
FDRQ,
PDRQ
t1
t4
nDACK
t12
t14
t11
t6
nIOR
or
nIOW
t8
t5
t10
t9
t7
DATA
(DO-D7)
DATA VALID
DATA VALID
t13
TC
FIGURE 56 - DMA TIMING (BURST TRANSFER MODE)
NAME
t1
t2
t3
t4
t5
t6
t7
t8
t9
t10
t11
t12
t13
t14
t15
t16
TABLE 232 - DMA TIMING (BURST TRANSFER MODE) PARAMETERS
DESCRIPTION
MIN
TYP
MAX
nDACK Delay Time from FDRQ High
0
DRQ Reset Delay from nIOR or nIOW
100
FDRQ Reset Delay from nDACK Low
100
nDACK Width
150
nIOR Delay from FDRQ High
0
nIOW Delay from FDRQ High
0
Data Access Time from nIOR Low
100
Data Set Up Time to nIOW High
40
Data to Float Delay from nIOR High
10
60
Data Hold Time from nIOW High
10
nDACK Set Up to nIOW/nIOR Low
5
nDACK Hold after nIOW/nIOR High
10
TC Pulse Width
60
AEN SET UP TO NIOR/NIOW
40
AEN Hold from nDACK
10
TC Active to PDRQ Inactive
100
340
UNITS
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
FLOPPY DISK DRIVE TIMING (AT MODE)
t3
nDIR
t4
t1
t2
nSTEP
t5
nDS0-3
t6
nINDEX
t7
nRDATA
t8
nWDATA
nIOW
t9
t9
nDS0-3,
MTR0-3
FIGURE 57 - FLOPPY DISK DRIVE TIMING (AT MODE)
NAME
t1
t2
t3
t4
t5
t6
t7
t8
t9
TABLE 233 - FLOPPY DISK DRIVE TIMING (AT MODE) PARAMETERS
DESCRIPTION
MIN
TYP
MAX
nDIR Set Up to STEP Low
4
nSTEP Active Time Low
24
nDIR Hold Time after nSTEP
96
nSTEP Cycle Time
132
nDS0-3 Hold Time from nSTEP high
20
nINDEX Pulse Width
2
nRDATA Active Time Low
40
nWDATA Write Data Width Low
.5
nDS0-3, MTRO-3 from End of nIOW
25
*X specifies one MCLK period and Y specifies one WCLK period.
MCLK = Controller Clock to FDC
WCLK = 2 x Data Rate
341
UNITS
X*
X*
X*
X*
X*
X*
ns
Y*
ns
SERIAL PORT TIMING
nIOW
t1
nRTSx,
nDTRx
t5
IRQx
nCTSx,
nDSRx,
nDCDx
t6
t2
t4
IRQx
nIOW
t3
IRQx
nIOR
nRI
FIGURE 58 - SERIAL PORT TIMING
NAME
t1
t2
t3
t4
t5
t6
TABLE 234 - SERIAL PORT TIMING PARAMETERS
DESCRIPTION
MIN
TYP
nRTSx, nDTRx Delay from nIOW
IRQx Active Delay from nCTSx, nDSRx, nDCDx
IRQx Inactive Delay from nIOR (Leading Edge)
IRQx Inactive Delay from nIOW (Trailing Edge)
IRQx Inactive Delay from nIOW
10
IRQx Active Delay from 0x
342
MAX
200
100
120
125
100
100
UNITS
ns
ns
ns
ns
ns
ns
PARALLEL PORT TIMING
PD0- PD7
t6
nIOW
t1
nINIT, nSTROBE.
nAUTOFD, SLCTIN
nACK
t2
nPINTR
(SPP)
t4
PINTR
(ECP or EPP Enabled)
t3
nFAULT (ECP)
nERROR
(ECP)
t5
t2
t3
PINTR
FIGURE 59 - PARALLEL PORT TIMING
NAME
t1
t2
t3
t4
t5
t6
TABLE 235 - PARALLEL PORT TIMING PARAMETERS
DESCRIPTION
MIN
TYP
PD0-7, nINIT, nSTROBE, nALF Delay from nIOW
PINTR Delay from nACK, nFAULT
PINTR Active Low in ECP and EPP Modes
200
PINTR Delay from nACK
nERROR Active to PINTR Active
PD0 - PD7 Delay from IOW Active
343
MAX
100
60
300
105
105
100
UNITS
ns
ns
ns
ns
ns
ns
EPP 1.9 DATA OR ADDRESS WRITE CYCLE
t18
A0-A10
t9
SD<7:0>
nIOW
t17
t8
t12
t10
IOCHRDY
t19
t11
t13
nWRITE
t20
t2
t1
t5
PD<7:0>
nDATAST
t14
t16
t3
t4
nADDRSTB
t15
t6
t7
nWAIT
FIGURE 60 - EPP 1.9 DATA OR ADDRESS WRITE CYCLE
NAME
t1
t2
t3
t4
t5
t6
t7
t8
t9
t10
t11
t12
t13
t14
t15
t16
TABLE 236 - EPP 1.9 DATA OR ADDRESS WRITE PARAMETERS
DESCRIPTION
MIN
TYP
MAX
nIOW Asserted to PDATA Valid
0
50
nWAIT Asserted to nWRITE Change (Note 1)
60
185
nWRITE to Command Asserted
5
35
nWAIT Deasserted to Command Deasserted (Note 1)
60
190
nWAIT Asserted to PDATA Invalid (Note 1)
0
Time Out
10
12
Command Deasserted to nWAIT Asserted
0
SDATA Valid to nIOW Asserted
10
nIOW Deasserted to DATA Invalid
0
nIOW Asserted to IOCHRDY deasserted
0
24
nWAIT Deasserted to IOCHRDY Asserted (Note 1)
60
160
IOCHRDY Asserted to nIOW Deasserted
10
nIOW Asserted to nWRITE Asserted
0
70
nWAIT Asserted to Command Asserted (Note 1)
60
210
Command Asserted to nWAIT Deasserted
0
10
PDATA Valid to Command Asserted
10
344
UNITS
ns
ns
ns
ns
ns
µs
ns
ns
ns
ns
ns
ns
ns
ns
µs
ns
NAME
t17
T18
t19
t20
DESCRIPTION
Ax Valid to nIOW Asserted
nIOW Deasserted to Ax Invalid
nIOW Deasserted to nIOW or nIOR Asserted
nWAIT Asserted to nWRITE Asserted (Note 1)
MIN
40
10
40
60
TYP
MAX
185
Note 1: nWAIT must be filtered to compensate for ringing on the parallel bus cable.
considered to have settled after it does not transition for a minimum of 50 nsec.
345
UNITS
ns
ns
ns
ns
WAIT is
EPP 1.9 DATA OR ADDRESS READ CYCLE
t20
A0-A10
t19
t11
t22
IOR
t13
t12
SD<7:0>
t18
t10
t8
IOCHRDY
t9
t21
t17
nWRITE
t2
t5
PData bus driven
by peripheral
t4
t16
PD<7:0>
t28
t1
t14
t3
DATASTB
ADDRSTB
t15
t7
t6
nWAIT
FIGURE 61 - EPP 1.9 DATA OR ADDRESS READ CYCLE
NAME
t1
t2
t3
t4
t5
t6
t7
t8
t9
t10
t11
t12
t13
t14
TABLE 237 - EPP 1.9 DATA OR ADDRESS READ CYCLE TIMING PARAMETERS
DESCRIPTION
MIN
TYP
MAX
UNITS
PDATA HI-Z TO COMMAND ASSERTED
0
30
ns
nIOR Asserted to PDATA Hi-Z
0
50
ns
nWAIT Deasserted to Command Deasserted (Note 1) 60
180
ns
Command Deasserted to PDATA Hi-Z
0
ns
Command Asserted to PDATA Valid
0
ns
PDATA Hi-Z to nWAIT Deasserted
0
µs
PDATA Valid to nWAIT Deasserted
0
ns
nIOR Asserted to IOCHRDY Deasserted
0
24
ns
nWRITE Deasserted to nIOR Asserted (Note 2)
0
ns
nWAIT Deasserted to IOCHRDY Asserted (Note 1)
60
160
ns
IOCHRDY Asserted to nIOR Deasserted
0
ns
nIOR Deasserted to SDATA Hi-Z (Hold Time)
0
40
ns
PDATA Valid to SDATA Valid
0
75
ns
nWAIT Asserted to Command Asserted
0
195
ns
346
NAME
t15
t16
t17
t18
t19
t20
t21
t22
t28
DESCRIPTION
Time Out
nWAIT Deasserted to PDATA Driven (Note 1)
nWAIT Deasserted to nWRITE Modified (Notes 1,2)
SDATA Valid to IOCHRDY Deasserted (Note 3)
Ax Valid to nIOR Asserted
nIOR Deasserted to Ax Invalid
nWAIT Asserted to nWRITE Deasserted
nIOR Deasserted to nIOW or nIOR Asserted
nWRITE Deasserted to Command
MIN
10
60
60
0
40
10
0
40
1
TYP
MAX
12
190
190
85
10
185
UNITS
µs
ns
ns
ns
ns
ns
ns
ns
ns
Note 1: nWAIT is considered to have settled after it does not transition for a minimum of 50 ns.
Note 2: When not executing a write cycle, EPP nWRITE is inactive high.
Note 3: 85 is true only if t7 = 0.
347
EPP 1.7 DATA OR ADDRESS WRITE CYCLE
t18
A0-A10
t9
SD<7:0>
nIOW
t17
t8
t6
t19
t12
t10
t20
IOCHRDY
t11
t13
t2
t1
t5
nWRITE
PD<7:0>
t16
t3
t4
nDATAST
nADDRSTB
t21
nWAIT
FIGURE 62 - EPP 1.7 DATA OR ADDRESS WRITE CYCLE
TABLE 238 - EPP 1.7 DATA OR ADDRESS WRITE CYCLE TIMING PARAMETERS
NAME
DESCRIPTION
MIN TYP MAX UNITS
t1
nIOW Asserted to PDATA Valid
0
50
ns
t2
Command Deasserted to nWRITE Change
0
40
ns
t3
nWRITE to Command
5
35
ns
t4
nIOW Deasserted to Command Deasserted (Note 2)
50
ns
t5
Command Deasserted to PDATA Invalid
50
ns
t6
Time Out
10
12
µs
t8
SDATA Valid to nIOW Asserted
10
ns
t9
nIOW Deasserted to DATA Invalid
0
ns
t10
nIOW Asserted to IOCHRDY deasserted
0
24
ns
t11
nWAIT Deasserted to IOCHRDY Asserted
40
ns
t12
IOCHRDY Asserted to nIOW Deasserted
10
ns
348
NAME
t13
t16
t17
t18
t19
t20
t21
DESCRIPTION
nIOW Asserted to nWRITE Asserted
PDATA Valid to Command Asserted
Ax Valid to nIOW Asserted
nIOW Deasserted to Ax Invalid
nIOW Deasserted to nIOW or nIOR Asserted
nWAIT Asserted to IOCHRDY Asserted
Command Deasserted to nWAIT Deasserted
MIN
0
10
40
10
100
TYP
MAX
50
35
45
0
UNITS
ns
ns
ns
µs
ns
ns
ns
Note 1: nWRITE is controlled by clearing the PDIR bit to "0" in the control register before performing
an EPP Write.
Note 2: The number is only valid if nWAIT is active when IOW goes active.
349
EPP 1.7 DATA OR ADDRESS READ CYCLE
t20
A0-A10
t15
t11
t19
t22
nIOR
t13
t12
SD<7:0>
t8
t10
t3
IOCHRDY
nWRITE
t5
t4
PD<7:0>
t23
t2
nDATASTB
nADDRSTB
t21
nWAIT
FIGURE 63 - EPP 1.7 DATA OR ADDRESS READ CYCLE
TABLE 239 - EPP 1.7 DATA OR ADDRESS READ CYCLE TIMING PARAMETERS
NAME
DESCRIPTION
MIN
TYP
MAX
UNITS
t2
nIOR Deasserted to Command Deasserted
50
ns
t3
nWAIT Asserted to IOCHRDY Deasserted
0
40
ns
t4
0
ns
Command Deasserted to PDATA Hi-Z
t5
Command Asserted to PDATA Valid
0
ns
t8
nIOR Asserted to IOCHRDY Asserted
24
ns
t10
nWAIT Deasserted to IOCHRDY Deasserted
50
ns
t11
0
ns
IOCHRDY Deasserted to nIOR Asserted
0
40
ns
t12
nIOR Deasserted to SDATA High-Z (Hold
Time)
t13
t15
t19
t20
t21
t22
t23
Note:
PDATA Valid to SDATA Valid
Time Out
10
Ax Valid to nIOR Asserted
40
nIOR Deasserted to Ax Invalid
10
Command Deasserted to nWAIT Deasserted
0
nIOR Deasserted to nIOW or nIOR Asserted
40
nIOR Asserted to Command Asserted
WRITE is controlled by setting the PDIR bit to "1" in the control register
EPP Read.
350
40
12
ns
µs
ns
ns
ns
ns
55
ns
before performing an
This sequence is shown in FIGURE 59. The
timing is designed to provide 3 cable round-trip
times for data setup if Data is driven
simultaneously with HostClk (nSTROBE).
ECP PARALLEL PORT TIMING
PARALLEL PORT FIFO (MODE 101)
The standard parallel port is run at or near the
peak 500Kbytes/sec allowed in the forward
direction using DMA. The state machine does
not examine nACK, but begins the next transfer
based on Busy. Refer to FIGURE 55.
REVERSE-IDLE PHASE
The peripheral has no data to send and keeps
PeriphClk high. The host is idle and keeps
HostAck low.
ECP PARALLEL PORT TIMING
REVERSE DATA TRANSFER PHASE
The timing is designed to allow operation at
approximately 2.0 Mbytes/sec over a 15ft. cable.
If a shorter cable is used then the bandwidth will
increase.
FORWARD-IDLE
When the host has no data to send it keeps
HostClk () high and the peripheral will leave
PeriphClk (Busy) low.
FORWARD DATA TRANSFER PHASE
The interface transfers data and commands
from the host to the peripheral using an interlocked PeriphAck and HostClk. The peripheral
may indicate its desire to send data to the host
by asserting nPeriphRequest.
The Forward Data Transfer Phase may be
entered from the Forward-Idle Phase. While in
the Forward Phase the peripheral may
asynchronously assert the nPeriphRequest
(nFault) to request that the channel be reversed.
When the peripheral is not busy it sets
PeriphAck (Busy) low. The host then sets
HostClk (nSTROBE) low when it is prepared to
send data. The data must be stable for the
specified setup time prior to the falling edge of
HostClk. The peripheral then sets PeriphAck
(Busy) high to acknowledge the handshake. The
host then sets HostClk (nSTROBE) high. The
peripheral then accepts the data and sets
PeriphAck (Busy) low, completing the transfer.
351
The interface transfers data and commands
from the peripheral to the host using an
interlocked HostAck and PeriphClk.
The Reverse Data Transfer Phase may be entered from the Reverse-Idle Phase. After the
previous byte has beed accepted the host sets
HostAck (nALF) low. The peripheral then sets
PeriphClk (nACK) low when it has data to send.
The data must be stable for the specified setup
time prior to the falling edge of PeriphClk. When
the host is ready it to accept a byte it sets
HostAck (nALF) high to acknowledge the
handshake. The peripheral then sets PeriphClk
(nACK) high. After the host has accepted the
data it sets HostAck (nALF) low, completing the
transfer. This sequence is shown in FIGURE 57
- FLOPPY DISK DRIVE TIMING (AT MODE)
OUTPUT DRIVERS
To facilitate higher performance data transfer,
the use of balanced CMOS active drivers for
critical signals (Data, HostAck, HostClk,
PeriphAck, PeriphClk) are used ECP Mode.
Because the use of active drivers can present
compatibility problems in Compatible Mode
(the control signals, by tradition, are specified as open-collector), the drivers are dynamically
changed
from
open-collector
to
totem-pole. The timing for the dynamic driver
change is specified
in
the IEEE 1284
Extended Capabilities Port Protocol and ISA
Interface Standard, Rev. 1.14, July 14, 1996,
available from Microsoft. The dynamic driver
change must be implemented properly to
prevent glitching the outputs.
t6
t3
PDATA
nSTROBE
t1
t2
t5
t4
BUSY
FIGURE 64 - PARALLEL PORT FIFO TIMING
NAME
t1
t2
t3
t4
t5
t6
TABLE 240 - PARALLEL PORT FIFO TIMING PARAMETERS
DESCRIPTION
MIN
TYP
MAX
DATA Valid to nSTROBE Active
600
nSTROBE Active Pulse Width
600
DATA Hold from nSTROBE Inactive (Note 1)
450
nSTROBE Active to BUSY Active
500
BUSY Inactive to nSTROBE Active
680
BUSY Inactive to PDATA Invalid (Note 1)
80
UNITS
ns
ns
ns
ns
ns
ns
Note 1: The data is held until BUSY goes inactive or for time t3, whichever is longer. This only
applies if another data transfer is pending. If no other data transfer is pending, the data is
held indefinitely.
352
t3
nAUTOFD
t4
PDATA<7:0>
t2
t1
t7
t8
nSTROBE
BUSY
t6
t5
t6
FIGURE 65 - ECP PARALLEL PORT FORWARD TIMING
NAME
t1
t2
t3
t4
t5
t6
t7
t8
TABLE 241 - ECP PARALLEL PORT FORWARD TIMING PARAMETERS
DESCRIPTION
MIN TYP MAX
nALF Valid to nSTROBE Asserted
0
60
PDATA Valid to nSTROBE Asserted
0
60
BUSY Deasserted to nALF Changed
80
180
(Notes 1,2)
BUSY Deasserted to PDATA Changed (Notes 1,2) 80
180
nSTROBE Deasserted to Busy Asserted
0
nSTROBE Deasserted to Busy Deasserted
0
BUSY Deasserted to nSTROBE Asserted
(Notes 80
200
1,2)
BUSY Asserted to nSTROBE Deasserted (Note 2)
80
180
UNITS
ns
ns
ns
ns
ns
ns
ns
ns
Note 1: Maximum value only applies if there is data in the FIFO waiting to be written out.
Note 2: BUSY is not considered asserted or deasserted until it is stable for a minimum of 75 to 130
ns.
353
t2
PDATA<7:0>
t1
t5
t6
nACK
t4
t3
t4
nAUTOFD
FIGURE 66 - ECP PARALLEL PORT REVERSE TIMING
NAME
t1
t2
t3
t4
t5
t6
TABLE 242 - ECP PARALLEL PORT REVERSE TIMING
DESCRIPTION
MIN TYP MAX
PDATA Valid to nACK Asserted
0
nALF Deasserted to PDATA Changed
0
nACK Asserted to nALF Deasserted
80
200
(Notes 1,2)
nACK Deasserted to nALF Asserted (Note 2)
80
200
nALF Asserted to nACK Asserted
0
nALF Deasserted to nACK Deasserted
0
UNITS
ns
ns
ns
ns
ns
ns
Note 1: Maximum value only applies if there is room in the FIFO and terminal count has not
been received. ECP can stall by keeping nALF low.
Note 2: nACK is not considered asserted or deasserted until it is stable for a minimum of 75 to 130
ns.
354
ACCESS.BUS TIMING
AB_DATA
tBUF
tLOW
tR
tHD;STA
tF
AB_CLK
tHD;STA
tHD;DAT
tHIGH
tSU;DAT
tSU;STO
tSU;STA
FIGURE 67 - ACCESS.BUS TIMING
SYMBOL
TABLE 243 - ACCESS.BUS TIMING PARAMETERS
PARAMETER
MIN.
TYP.
MAX.
UNIT
fSCL
SCL Clock Frequency
kHz
tBUF
Bus Free Time
4.7
µs
tSU;STA
4.7
µs
tHD;STA
START Condition Set-Up
Time
START Condition Hold Time
4.0
µs
tLOW
SCL LOW Time
4.7
µs
tHIGH
SCL HIGH Time
4.0
µs
tR
SCL and SDA Rise Time
1.0
µs
tF
SCL and SDA Fall Time
0.3
µs
tSU;DAT
Data Set-Up Time
0.25
µs
tHD;DAT
Data Hold Time
0
µs
tSU;STO
STOP Condition Set-Up Time
4.0
µs
100
355
HOST FLASH READ TIMING
8051STOPPED
SA[15:0]
A[15:0]
t10
SD[7:0]
t11
t17
D[7:0]
tsu1
nROM_CS
t5
nMEMRD
nMEMWR
FA[17:16]
KMEM[2:1]
t1
t18
HMEM[1:0]=A[17:16]
KMEM[2:1]
t2
FA[15:8]
8051ADR[14:8],KMEM[0]
t2
FAD[7:0]
8051PORT0
t4
t21
A[15:8]
t19
8051ADR[14:8],KMEM[0]
t4
t8
A[7:0]
tsu2
t14
t15
D[7:0]
A[7:0]
t7
t13
t6
t16
t21
t19
8051PORT0
IOCHRDY
t3
FALE
t9
t12
nFRD
nFWR
FIGURE 68 - HOST FLASH READ TIMING
356
t20
t1
t2
t3
t4
t5
t6
t7
t8
t9
t10
t11
t12
t13
t14
t15
t16
t17
t18
t19
t20
t21
tsu1
tsu2
TABLE 244 - HOST FLASH READ TIMING PARAMETERS
PARAMETER
MIN
TYP
8051 stopped condition met to FA[17:16] sourced by
internal register HMEM[1:0]
8051 stopped condition met to FA[15:0] driven by
SA[15:0]
8051 stopped condition met to FALE asserted
SA[15:0] valid to FA[15:0] valid propogation delay
SA[15:0] valid to nMEMRD asserted
88
nMEMRD asserted to FALE de-asserted
21
nMEMRD asserted to IOCHRDY de-asserted (Note1)
FALE de-asserted to FAD[7:0] tristated
FALE de-asserted to nFRD asserted
nMEMRD asserted to SD[7:0] driven
FAD[7:0] data valid to SD[7:0] data valid propogation
delay
nFRD, Flash Read, asserted pulse width (Note2)
120
[3 sclk]
nFRD de-asserted to IOCHRDY asserted
0
FAD[7:0] Data hold time from nFRD de-asserted
0
SA[7:0] muxed onto FAD[7:0] following the deassertion of nFRD
nFRD de-asserted to FALE asserted for next cycle
SD[7:0] data hold time from nMEMRD de-asserted
10
8051 clock started condition met to FA[17:16] sourced
by internal register KMEM[2:1]
8051 clock started condition met to FA[15] sourced by
KMEM[0] and FA[14:0] driven by the 8051
8051 clock started condition met to FALE de-asserted
SA[15:0] invalid to FA[15:0] invalid propagation delay
nROM_CS asserted to nMEMRD setup time
20
FAD[7:0] Data valid to nFRD de-asserted setup time
20
MAX
40
UNITS
ns
40
ns
40
40
ns
ns
ns
ns
ns
ns
ns
ns
ns
63
24
42
84
30
40
200
[5 sclk]
20
42
42
ns
ns
ns
ns
40
ns
ns
ns
40
ns
40
40
ns
ns
ns
ns
Note 1: Systems designed prior to the EISA Specification, R3.12, which sample CHRDY on the rising
edge of BCLK require that IOCHRDY is deasserted within 24 ns.
Note 2: The Flash Read signal pulse width is programmable through a configuration register, the time
values shown are for an internal sclk=24 MHz derived from the 14.318 MHz input.
357
HOST FLASH READ/WRITE
8051STOPPED
SA[15:0]
A[15:0]
t17
t16
SD[7:0]
D[7:0]
tsu1
nROM_CS
nMEMRD
t5
nMEMWR
t1
FA[17:16]
KMEM[2:1]
t2
FA[15:8]
8051ADR[14:8],KMEM[0]
t2
FAD[7:0]
t18
HMEM[1:0]=A[17:16]
8051PORT0
KMEM[2:1]
t4
t21
A[15:8]
t4
t19
8051ADR[14:8],KMEM[0]
t13
t14
t9
A[7:0]
D[7:0]
t21
A[7:0]
t7
t12
t6
t15
t19
8051PORT0
IOCHRDY
t3
FALE
nFRD
t10
t11
nFWR
FIGURE 69 - HOST FLASH WRITE TIMING PARAMETERS
358
t20
t1
t2
t3
t4
t5
t6
t7
TABLE 245 - HOST FLASH WRITE TIMING PARAMETERS
PARAMETER
MIN
TYP
8051 stopped condition met to FA[17:16] sourced by
internal register HMEM[2:1]
8051 stopped condition met to FA[15] driven by
SA[15:0]
8051 stopped condition met to FALE asserted
SA[15:0] valid to FA[15:0] valid propogation delay
SA[15:0] valid to nMEMWR asserted
88
nMEMWR asserted to FALE de-asserted
21
nMEMWR asserted to IOCHRDY de-asserted
(Note 1)
t9
t10
t11
FALE de-asserted to SD[7:0] driven onto FAD[7:0]
FALE de-asserted to nFWR asserted
nFWR, Flash Write, asserted pulse width (Note 2)
t12
t13
t14
nFWR de-asserted to IOCHRDY asserted
FAD[7:0] Data hold time from nFWR de-asserted
SA[7:0] muxed onto FAD[7:0] following the de-assertion
of nFWR
nFWR deasserted to FALE asserted for next cycle
nMEMWR asserted to SD[7:0] valid
SD[7:0] data hold time from nMEMWR de-asserted
8051 clock started condition met to FA[17:16] sourced
by internal register KMEM[2:1]
8051 clock started condition met to FA[15] sourced by
KMEM[0] and FA[14:0] driven by the 8051
8051 clock started condition met to FALE de-asserted
SA[15:0] invalid to FA[15:0] invalid propagation delay
nROM_CS asserted to nMEMWR setup time
t15
t16
t17
t18
t19
t20
t21
tsu1
120
[3 sclk]
MAX
40
UNITS
ns
40
ns
40
40
ns
ns
ns
ns
ns
63
24
42
84
200
[5 sclk]
20
42
42
ns
ns
ns
42
-10
40
ns
ns
ns
ns
40
ns
40
40
ns
ns
ns
10
20
ns
ns
ns
Note 1: Systems designed prior to the EISA Specification, R3.12, which sample CHRDY on the rising
edge of BCLK require that IOCHRDY is deasserted within 24 ns.
Note 2: The Flash Write signal pulse width is programmable through a configuration register, the
time values shown are for an internal sclk=24 MHz derived from the 14.318 MHz input
359
ZERO WAIT STATE (NOWS) TIMING
t1
t12
SA[15:0]
t11
AEN
t3
t2
t9
nIOR,
nIOW
t4
t5
nNOWS
t6
t7
t8
Read
Data
t10
Write Data
FIGURE 70 - ZERO WAIT STATE (NOWS) TIMING
t1
t2
t3
t4
t5
t6
t7
t8
t9
t10
t11
t12
TABLE 246 - ZERO WAIT-STATE TIMING PARAMETERS
PARAMETER
MIN
TYP MAX
AEN Valid Before nIOR, nIOW Asserted
10
SA[15:0] Valid Before nIOR Asserted
10
nIOR, nIOW Pulse Width
80
nIOR, nIOW Asserted to nNOWS Asserted
50
nIOR, nIOW Negated to nNOWS Floated
35
nIOR Asserted to Read Data Valid
50
nIOR Negated to Read Data Invalid (Hold Time)
0
nIOR Negated to Data Bus Floated
24
Write Data Valid Before nIOW Deasserted
45
nIOW Negated to Write Data Invalid (Hold Time) 0
nIOR, nIOW Negated to AEN Invalid
10
nIOR, nIOW Negated to SA[15:0] Invalid
10
360
UNITS
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
FLASH PROGRAM FETCH TIMING
t1
t5
FALE
t3
t4
nFRD
t7
FAD[7:0]
FA[17:8]
t2
FA[7:0]
t6
t8
insruction
FA[17:8]
FA[7:0
FA[17:8]
FIGURE 71 - 8051 FLASH PROGRAM FETCH TIMING
TABLE 247 - 8051 FLASH PROGRAM FETCH TIMING PARAMETERS
8051 Clock = 12 MHz
PARAMETER
MIN
TYP
MAX
UNITS
t1
Address Valid to FALE Low
38
41
ns
t2
Address Hold Following FALE Low
35
60
ns
t3
FALE Low to nFRD Low
35
45
50
ns
t4
nFRD Pulse Width
150
162
ns
t5
nFRD High to FALE High
0
5
10
ns
t6
nFRD Low to Valid Instruction
135
ns
t7
Instruction Hold Following nFRD
0
ns
t8
Instruction Float Following nFRD
80
ns
8051 Clock = 24 MHz
PARAMETER @24 MHz
MIN
TYP
MAX
UNITS
t1
Address Valid to FALE Low
15
20
ns
t2
Address Hold Following FALE Low
35
40
ns
t3
FALE Low to nFRD Low
18
23
30
ns
t4
nFRD Pulse Width
60
82
ns
t5
nFRD High to FALE High
0
6
10
ns
t6
nFRD Low to Valid Instruction In
40
ns
t7
Instruction Hold Following nFRD
0
ns
t8
Instruction Float Following nFRD
40
ns
Min and Max delays shown for an 8051 clock of 12 MHz and 24 MHz as indicated. Device Mode
Register bits [1:0] = 00 (See Global Configuration Registers, Table 214, address 0x25).
361
8051 FLASH READ TIMING
t1
t5
FALE
t3
t4
nFRD
t7
FAD[7:0]
FA[17:8]
t2
FA[7:0]
t6
t8
DATA IN
FA[17:8]
FA[7:0
FA[17:8]
FIGURE 72 - 8051 FLASH READ TIMIING
t1
t2
t3
t4
t5
t6
t7
t8
t1
t2
t3
t4
t5
t6
t7
t8
TABLE 248 - FLASH READ TIMIING PARAMETERS
8051 Clock = 12 MHz
PARAMETER
MIN
TYP
MAX
Address Valid to FALE Low
38
41
Address Hold Following FALE Low
35
60
FALE Low to nFRD Low
35
45
50
nFRD Pulse Width
150
162
nFRD High to FALE High
0
5
10
nFRD Low to Valid Data In
135
Data Hold Following nFRD
0
Data Float Following nFRD
80
8051 Clock =24 MHz
PARAMETER @24 MHz
MIN
TYP
MAX
Address Valid to FALE Low
15
20
Address Hold Following FALE Low
35
40
FALE Low to nFRD Low
18
23
30
nFRD Pulse Width
60
82
nFRD High to FALE High
0
6
10
nFRD Low to Valid Data In
40
Data Hold Following nFRD
0
Data Float Following nFRD
40
UNITS
ns
ns
ns
ns
ns
ns
ns
ns
UNITS
ns
ns
ns
ns
ns
ns
ns
ns
Min and Max delays shown for an 8051 clock of 12 MHz and 24 MHz as indicated. Device Mode
Register bits [1:0] = 00 (See Global Configuration Registers, Table 214, address 0x25).
362
8051 FLASH WRITE TIMING
t1
t5
FALE
t3
t6
t4
nFWR
t2
FAD[7:0]
FA[17:8]
FA[7:0]
t7
DATA OUT
FA[7:0]
FA[17:8]
FA[17:8]
FIGURE 73 - 8051 FLASH WRITE TIMING
t1
t2
t3
t4
t5
t6
t7
t1
t2
t3
t4
t5
t6
t7
TABLE 249 - FLASH WRITE TIMING PARAMETERS
8051 Clock = 12 MHz
PARAMETER @12MHz
MIN
TYP
MAX
Address Valid to FALE Low
38
42
Address Hold Following FALE Low
38
41
FALE Low to nFWR Low
110
124
140
nFWR Pulse Width
300
332
nFWR High to FALE High
70
85
100
Data Valid to nFWR Falling Edge
70
84
Data Hold Following nFWR
150
172
8051 Clock =24 MHz
PARAMETER @ 24 MHz
MIN
TYP
MAX
Address Valid to FALE Low
14
20
Address Hold Following FALE Low
18
22
FALE Low to nFWR Low
48
62
76
nFWR Pulse Width
130
162
nFWR High to FALE High
40
50
60
Data Valid to nFWR Falling Edge
30
41
Data Hold Following nFWR
60
84
UNITS
ns
ns
ns
ns
ns
ns
ns
UNITS
ns
ns
ns
ns
ns
ns
ns
Min and Max delays shown for an 8051 clock of 12 MHz and 24 MHz as indicated. Device Mode
Register bits [1:0] = 00 (See Global Configuration Registers, Table 214, address 0x25).
363
PS/2 CHANNEL RECEIVE TIMING DIAGRAM
t7
t3
t2
t5
t4
t10
PS2_CLK WR_CLK
t1
PS2_DAT WR_DATA
WR_CLK
t6
b0
b1
b2
b3
b4
b5
b6
b7
P
S
WR_DATA
PS2_EN
PS2_T/R
t8
t9
RDATA_RDY
Read RX Reg
t12
Interrupt
note1
FIGURE 74 - PS/2 CHANNEL RECEIVE TIMING DIAGRAM
t1
t2
t3
t4
t5
t6
t7
t8
t11
PS/2 CHANNEL RECEPTION PARAMETERS
PARAMETER
MIN
TYP
The PS2 Channel’s CLK and DATA lines
are floated following PS2_EN=1 and
PS2_T/R=0.
Period of CLK
60
Duration of CLK high (active)
30
Duration of CLK low (inactive)
30
DATA setup time to falling edge of CLK.
1
FDC37N972 samples the data line on the
falling CLK edge.
DATA hold time from falling edge of CLK. 2
FDC37N972 samples the data line on the
falling CLK edge.
Duration of Data Frame. Falling edge of
Start bit CLK (1st clk) to falling edge of
Parity bit CLK (10th clk).
Falling edge of 11th CLK to RDATA_RDY
asserted.
364
MAX
100
UNITS
ns
302
151
151
us
us
us
us
us
2.002
ms
1.6
us
t9
t10
t11
t12
PARAMETER
Trailing edge of the 8051’s RD signal of
the Receive Register to RDATA_RDY bit
deasserted.
Trailing edge of the 8051’s RD signal of
the Receive Register to the CLK line
released to high-Z.
The PS2 Channel’s CLK and DATA lines
are driven to the values stored in the
WR_CLK and WR_DATA bits of the
Control Register when PS2_EN is written
to 0.
RDATA_RDY asserted to interrupt
generated. Note1- Interrupt is cleared by
reading the 8051 INT0 Source Register.
365
MIN
TYP
MAX
100
UNITS
ns
100
ns
100
ns
100
ns
PS/2 CHANNEL TRANSMIT TIMING DIAGRAM
t2
t5
t6
t7
t10
t8
t9
10 11
PS2_CLK
1
t1
PS2_DAT
2
t4
t11
S
b0 b1 b2 b3 b4 b5 b6 b7
t14
t16
P
PS2_EN
t12
PS2_T/R
t3
t13
XMIT_IDLE
RDATA_RDY
Write TX Reg
t15
Interrupt
note1
ORION005
FIGURE 75 - PS/2 CHANNEL TRANSMIT TIMING DIAGRAM
t1
t2
t3
t4
t5
PS/2 CHANNEL TRANSMISSION TIMING PARAMETERS
PARAMETER
MIN
TYP
MAX
The PS2 Channel’s CLK and DATA lines
100
are floated following PS2_EN=1 and
PS2_T/R=0.
PS2_T/R bit set to CLK driven low
100
preparing the PS2 Channel for data
transmission.
CLK line floated to XMIT_IDLE bit
1.7
deasserted.
Trailing edge of 8051 WR of Transmit
45
90
Register to DATA line driven low.
Trailing edge of 8051 WR of Transmit
90
130
Register to CLK line floated.
366
UNITS
ns
ns
us
ns
ns
t6
t7
t8
t9
t10
t11
t12
t13
t14
t15
t16
PARAMETER
Initiation of Start of Transmit cycle by the
PS2 channel controller to the auxilliary
peripheral’s responding by latching the
Start bit and driving the CLK line low.
Period of CLK
Duration of CLK high (active)
Duration of CLK low (inactive)
Duration of Data Frame. Falling edge of
Start bit CLK (1st clk) to falling edge of
Parity bit CLK (10th clk).
DATA output by FDC37N972 following
the falling edge of CLK. The auxilliary
peripheral device samples DATA
following the rising edge of CLK.
Rising edge following the 11th falling
clock edge to PS_T/R bit driven low.
Trailing edge of PS_T/R to XMIT_IDLE
bit asserted.
DATA released to high-Z following the
PS2_T/R bit going low.
XMIT_IDLE bit driven high to interrupt
generated. Note1- Interrupt is cleared by
reading the 8051 INT0 Source Register.
The PS2 Channel’s CLK and DATA lines
are driven to the values stored in the
WR_CLK and WR_DATA bits of the
Control Register when PS2_EN is written
to 0.
367
MIN
0.002
TYP
MAX
25.003
UNITS
ms
60
30
30
302
151
151
2.002
us
us
us
ms
3.5
7.1
us
400
800
ns
100
ns
100
ns
100
ns
100
ns
PS/2 CHANNEL “BIT-BANG” TIMING
PS2_CLK1
PS2_DAT
note1
note1
t1
t1
note2
Interrupt
note2
PS2_EN
FIGURE 76 - PS/2 CHANNEL “BIT-BANG” TRANSMIT TIMING DIAGRAM
t1
TABLE 250 - PS/2 CHANNEL “BIT-BANG” TRANSMIT TIMING PARAMETERS
PARAMETER
MIN
TYP
MAX
UNITS
Falling Edge of CLK to Interrupt generated.
1.1
us
8051 firmware responds to interrupt and
drives data line before rising edge of
PS2_CLK line.
8051 firmware clears Interrupt by reading the
8051 INT0 Source Register.
PS2_CLK1
PS2_DAT
note1
note1
t1
Interrupt
t1
note2
note2
PS2_EN
FIGURE 77 - PS/2 CHANNEL “BIT-BANG” RECEIVE TIMING DIAGRAM
t1
TABLE 251 - PS/2 CHANNEL “BIT-BANG” RECEIVE TIMING PARAMETERS
PARAMETER
MIN
TYP
MAX
Falling Edge of CLK to Interrupt generated.
100
8051 firmware responds to interrupt and latches data
line before rising edge of PS2_CLK line.
8051 firmware clears Interrupt by reading the 8051 INT0
Source Register.
368
UNITS
ns
10µ s
min.
PWRGD
3V
VCC2
CLOCKI
FIGURE 78 – POWER-FAIL EVENT
PARAMETER
Valid CLOCKI to PWRGD Deasserted
MIN
10
TYP
MAX
UNITS
µs
MAX
UNITS
µs
10µs
min.
PWRGD
3V
VCC2
CLOCKI
FIGURE 79 - VCC2 POWER-UP TIMING
PARAMETER
Valid CLOCKI to PWRGD Asserted
MIN
10
TYP
1µs
min.
1µs
min.
VCC1_PWRGD
VCC1
3V
3V
FIGURE 80 - VCC1_PWRGD TIMING
PARAMETER
Valid VCC1 to VCC1_PWRGD Deasserted
Valid VCC1 to VCC1_PWRGD Asserted
MIN
1
1
369
TYP
MAX
UNITS
µs
µs
IN CIRCUIT TEST (ICT)
The ICT impedance measurement is installed in
the Production Test Program. It is run after
Opens/Shorts
(Vcc
still
at
0V).
The
measurement forces 0.2V on all ICT pins
simultaneously and measures for less than
0.2uA. A failure at this time branches to a pin
by pin test that forces 0.2V and measures 0.2uA
on individual pins. Any pin greater then 0.2uA is
considered a failure.
Table 252 - ICT PIN MAP
PIN #
2
3
9
14
15
16
17
18
19
20
24
25
26
27
28
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
48
50
51
52
53
55
PIN NAME
PIN #
57
59
61
63
76
77
78
81
84
86
88
90
91
92
93
96
97
98
99
109
110
141
151
154
157
190
193
194
195
196
197
203
204
206
207
208
nDS1 / OUT5
nMTR1 / OUT6
nDIR
nINDEX
nTRK0
nWPRTPRT
nRDATA
nDSKCHG
FPD
IRTX
KSO11
KSO10
KSO9
KSO8
KSO7
KSO6
KSO5
KSO4
KSO3
KSO2
KSO1
KSO0
KS17
KS16
KS15
KS14
KS13
KS12
KS11
KS10
IMDAT
KCLK
KDAT
EMCLK
EMDAT
SA1
370
PIN NAME
SA3
SA5
SA7
SA9
nNoWS
nIOR
nIOW
SD1
SD3
SD5
SD7
nDACK0
DRQ0
nDACK1
DRQ1
nROMCS
nMEMRD
nMEMWR
PCI_CLK
VCC1_PWRGD
nPWR_LED
RXD2 / GPIO8
IN3
IN6
XOSEL
GPIO6
nEA
MODE
AB_DATA
AB_CLK
nBAT_LED
OUT7
GPIO16
GPIO17
GPIO18
GPIO19
BOARD LEVEL CONNECTIVITY TEST MODE
To allow the FDC37N972 to be tested efficiently at board level, a test mode is provided to allow board
level connectivity testing to be carried out. The board level connectivity test mode (AND tree mode) is
defined below.
The AND tree test mode is enabled and latched by:
IOWb = IORb = MEMWRb = MEMRDb = 0 and PWRGD = 1
When activated, this test mode forces all output and bidirectional pins to function as inputs. All these
input pins are now input to an AND tree which is output on nRESET_OUT. This will allow one single
input pin, when switched, to toggle the nRESET_OUT output, if all other input pins are high.
This test mode is disabled/reset by a POR.
371
FIGURE 81 - 208 PIN FLEX BGA 15.0X15.0X1.10 (PRELIMINARY)
372
MIN
A
A1
A2
D
D1
E
E1
H
0.05
1.35
29.90
27.90
29.90
27.90
0.09
NOM
30.00
28.00
30.00
28.00
MAX
1.6
0.15
1.45
30.10
28.10
30.10
28.10
0.230
L
L1
e
0
W
R1
R2
ccc
MIN
0.45
NOM
0.60
1.00
0.50BSC
0
0.17
0.08
0.08
MAX
0.75
7
0.27
0.20
0.08
Notes:
1)
Coplanarity is 0.080 mm or 3.2 mils maximum
2)
Tolerance on the position of the leads is 0.080 mm maximum
3)
Package body dimensions D1 and E1 do not include the mold protrusion.
Maximum mold protrusion is 0.25 mm
D imensions for foot length L measured at the gauge plane 0.25 mm above
the seating plane
Details of pin 1 identifier are optional but must be located within the zone
indicated
Controlling dimension: millimeter
4)
5)
6)
FIGURE 82 - 208 PIN TQFP PACKAGE OUTLINE
373
APPENDIX A
HIGH-PERFORMANCE 8051 CYCLE TIMING AND INSTRUCTION SET
The high-performance 8051 processor offers
increased performance by executing instructions
in a 4-clock cycle, as opposed to the standard
8051. The shortened bus timing improves the
instruction execution rate for most instructions
by a factor of three over the standard 8051
architectutres.
8051than they do on the standard 8051. In the
standard 8051, all instructions except for MUL
and DIV take one or two instruction cycles to
complete.
Int the high-performance 8051
architecture, instructions can take between one
and five instructions to complete. The average
speed improvement for the entire instruction set
is approximately 2.5X.
Some instructions require a different number of
instruction cycles on the high-performance
SYMBOL
A
Rn
direct
@Ri
rel
bit
#data
#data 16
addr 16
addr 11
INSTRUCTION
ARITHMETIC
ADD A, Rn
ADD A, direct
ADD A, @Ri
ADD A, #data
ADDC A, Rn
ADDC A, direct
ADDC A, @Ri
ADDC A, #data
LEGEND FOR INSTRUCTION SET TABLE
FUNCTION
Accumulator
Register R7-R0
Internal register address
Internal register pointed to by R0 or R1 (except MOVX)
Two’s complement offset byte
Direct bit address
8-bit constant
16-bit constant
16-bit destination address
11-bit destination address
TABLE 253 - 8051 INSTRUCTION SET
BYTE
INSTRUCTION
DESCRIPTION
COUNT
CYCLES
Add register to A
Add direct byte to A
Add data memory to A
Add immediate to A
Add register to A with
carry
Add direct byte to A with
carry
Add data memory to A
with carry
Add immediate to A with
carry
374
HEX
CODE
1
2
1
2
1
1
2
1
2
1
28-2F
25
26-27
24
38-3F
2
2
35
1
1
36-37
2
2
34
INSTRUCTION
SUBB A, Rn
SUBB A, direct
SUBB A, @Ri
SUBB A, #data
INC A
INC Rn
INC direct
INC @Ri
DEC A
DEC Rn
DEC direct
DEC @Ri
INC DPTR
MUL AB
DIV AB
DA A
LOGICAL
ANL A, Rn
ANL A, direct
ANL A, @Ri
ANL A, #data
ANL direct, A
ANL direct, #data
ORL A, Rn
ORL A, direct
ORL A, @Ri
ORL A, #data
ORL direct, A
ORL direct, #data
XORL A, Rn
XORL A, direct
XORL A, @Ri
DESCRIPTION
Subtract register from A
with borrow
Subtract direct byte
from A with borrow
Subtract data memory
from A with borrow
Subtract immediate
from A with borrow
Increment A
Increment register
Increment direct byte
Increment data memory
Decrement A
Decrement register
Decrement direct byte
Decrement data
memory
Increment data pointer
Multiply A by B
Divide A by B
Decimal adjust A
AND register to A
AND direct byte to A
AND data memory to A
AND immediate to A
AND A to direct byte
AND immediate data to
direct byte
OR register to A
OR direct byte to A
OR data memory to A
OR immediate to A
OR A to direct byte
OR immediate data to
direct byte
Exclusive-OR register to
A
Exclusive-OR direct byte
to A
Exclusive-OR data
memory to A
375
BYTE
COUNT
1
INSTRUCTION
CYCLES
1
HEX
CODE
98-9F
2
2
95
1
1
96-97
2
2
94
1
1
2
1
1
1
2
1
1
1
2
1
1
1
2
1
04
08-0F
05
06-07
14
18-1F
15
16-17
1
1
1
1
3
5
5
1
A3
A4
84
D4
1
2
1
2
2
3
1
2
1
2
2
3
58-5F
55
56-57
54
52
53
1
2
1
2
2
3
1
2
1
2
2
3
48-4F
45
46-47
44
42
43
1
1
68-6F
2
2
65
1
1
66-67
INSTRUCTION
XORL A, #data
XORL direct, A
XORL direct, #data
CLR A
CPL A
RL A
RLC A
RR A
RRC A
DATA TRANSFER
MOV A, RN
MOV A, direct
MOV A, @Ri
MOV A, #data
MOV Rn, A
MOV Rn, direct
MOV Rn, #data
MOV direct, A
MOV direct, Rn
MOV direct, direct
MOV direct, @Ri
MOV direct, #data
MOV @Ri, A
MOV @Ri, direct
MOV @Ri, #data
MOV DPTR, #data
MOVC A, @A+DPTR
DESCRIPTION
Exclusive-OR
immediate to A
Exclusive-OR A to direct
byte
Exclusive-OR
immediate to direct byte
Clear A
Complement A
Rotate A left
Rotate A left through
carry
Rotate A right
Rotate A right through
carry
Move register to A
Move direct byte to A
Move data memory to A
Move immediate to A
Move A to reigster
Move direct byte to
register
Move immediate to
register
Move A to direct byte
Move register to direct
byte
Move direct byte to
direct byte
Move data memory to
direct byte
Move immediate to
direct byte
Move A to data memory
Move direct byte to data
memory
Move immediate to data
memory
Move immediate to data
pointer
Move code byte relative
DPTR to A
376
BYTE
COUNT
2
INSTRUCTION
CYCLES
2
HEX
CODE
64
3
3
63
3
3
63
1
1
1
1
1
1
1
1
E4
F4
23
33
1
1
1
1
03
13
1
2
1
2
1
2
1
2
1
2
1
2
E8-EF
E5
E6-E7
74
F8-FF
A8-AF
2
2
78-7F
2
2
2
2
F5
88-8F
3
3
85
2
2
86-87
3
3
75
1
2
1
2
F6-F7
A6-A7
2
2
76-77
3
3
90
1
3
93
INSTRUCTION
MOVC A, @A+PC
MOVX A, @Ri
MOVX A, @DPTR
MOVX @Ri, A
MOVX @DPTR, A
PUSH direct
POP direct
XCH A, Rn
XCH A, direct
XCH A, @Ri
XCHD A, @Ri
Boolean
CLR C
CLR bit
SETB C
SETB bit
CPL C
CPL bit
ANL C, bit
ANL C, /bit
ORL C, bit
ORL C, /bit
MOV C, bit
MOV bit, C
BRANCHING
ACALL addr 11
LCALL addr 16
RET
RETI
BYTE
COUNT
1
INSTRUCTION
CYCLES
3
HEX
CODE
83
1
2-9
E2-E3
1
2-9
E0
1
2-9
F2-F3
1
2-9
F0
2
2
C0
2
2
D0
1
2
1
2
C8-CF
C5
1
1
C6-C7
1
1
D6-D7
Clear carry
Clear direct bit
Set Carry
Set direct bit
Complement carry
Complement direct bit
AND direct bit to carry
AND direct bit inverse to
carry
OR direct bit to carry
OR direct bit inverse to
carry
Move direct bit to carry
Move carry to direct bit
1
2
1
2
1
2
2
2
1
2
1
2
1
2
2
2
C3
C2
D3
D2
B3
B2
82
B0
2
2
2
2
72
A0
2
2
2
2
A2
92
Absolute call to
subroutine
Long call to subroutine
Return from subroutine
Return from interrupt
2
3
11-F1
3
1
1
4
4
4
12
22
32
DESCRIPTION
Move code byte relative
PC to A
Move external data (A8)
to A
Move external data
(A16) to A
Move A to external data
(A8)
Move A to external data
(A16)
Push direct byte onto
stack
Pop direct byte from
stack
Exchange A and register
Exchange A and direct
byte
Exchange A and data
memory
Exchange A and data
memory nibble
377
INSTRUCTION
AJMP addr 11
LJMP addr 16
SJMP rel
JC rel
JNC rel
JB bit, rel
JNB bit, rel
JMP @A+DPTR
JZ rel
JNZ rel
CJNE A, direct, rel
CJNE A, #d, rel
CJNE Rn, #d, rel
CJNE @Ri, #d, rel
DJNZ Rn, rel
DJNZ direct, rel
MISCELLANEOUS
NOP
DESCRIPTION
Absolute jump
unconditional
Long jump unconditional
Short jump (relative
address)
Jump on carry = 1
Jump on carry = 0
Jump on direct bit = 1
Jump on direct bit = 0
Jump indirect relative
DPTR
Jump on accumulator =
0
Jump on accumulator /=
0
Compare A, direct JNE
relative
Compare A, immediate
JNE relative
Compare reg,
immediate JNE relative
Compare Ind,
immediate JNE relative
Decrement register, JNZ
relative
Decrement direct byte,
JNZ relative
No operation
378
BYTE
COUNT
2
INSTRUCTION
CYCLES
3
HEX
CODE
01-E1
3
2
4
3
02
80
2
2
3
3
1
3
3
4
4
3
40
50
20
30
73
2
3
60
2
3
70
3
4
B5
3
4
B4
3
4
B8-BF
3
4
B6-B7
2
3
D8-DF
3
4
D5
1
1
00
APPENDIX B
HIGH PERFORMANCE 8051 EXTENDED INTERRUPT UNIT
Interrupts
The EXIF, EICON, EIE, and EIP registers
provide flags, enable control, and priority control
for the extended interrupt unit in the
FDC37N972 high-performance 8051.
When EA = 0, all interrupts are masked. The
only exception is the power-fail interrupt, which
is not affected by the EA bit. When EPFI = 1,
the power-fail interrupt is enabled, regardless of
the state of the EA bit. TABLE 92 on page 169
provides a summary of interrupt sources, flags,
enables, and priorities.
Interrupt Processing
Interrupt Priorities
When an enabled interrupt occurs, the CPU
vectors to the address of the interrupt service
routine (ISR) associated with that interrupt (See
TABLE 92 - 8051 INTERRUPTS on page 169).
The CPU executes the ISR to completion unless
another interrupt of higher priority occurs. Each
ISR ends with a RETI (return from interrupt)
instruction. After executing the RETI, the CPU
returns to the next instruction that would have
been executed if the interrupt had not occurred.
There are two stages of interrupt priority
assignment, interrupt level and natural priority.
The interrupt level (highest, high, or low) takes
precedence over natural priority. The power-fail
interrupt, if enabled, always has highest priority
and is the only interrupt that can have highest
priority. All other interrupts can be assigned
either high or low priority.
An ISR can only be interrupted by a higher
priority interrupt. That is, an ISR for a low-level
interrupt can only be interrupted by high-level
interrupt. An ISR for a high-level interrupt can
only be interrupted by the power-fail interrupt
(extended interrupt unit only).
In addition to an assigned priority level (high or
low), each interrupt also has a natural priority,
as listed in TABLE 92 - on page 169.
Simultaneous interrupts with the same priority
level (for example, both high) are resolved
according to their natural priority. For example,
if int0_n and int2 are both programmed as high
priority, int0_n takes precedence.
The 8051 always completes the instruction in
progress before servicing an interrupt. If the
instruction in progress is RETI, or a write access
to any of the IP, IE, EIP, or EIE SFRs, the 8051
completes one additional instruction before
servicing the interrupt.
Once an interrupt is being serviced, only an
interrupt of higher priority level can interrupt the
service routine of the interrupt currently being
serviced.
Interrupt Sampling
Interrupt Masking
The EA bit in the IE SFR (IE.7) is a global
enable for all interrupts except the power-fail
interrupt. When EA = 1, each interrupt is
enabled/masked by its individual enable bit.
379
The internal timers and serial ports generate
interrupts by setting their respective SFR
interrupt flag bits. External interrupts are
sampled once per instruction cycle.
int0_n and int1_n are both active low and can
be programmed to be either edge-sensitive or
level-sensitive, through the IT0 and IT1 bits in
the TCON SFR. For example, when IT0 = 0,
int0_n is level-sensitive and the 8051 sets the
IE0 flag when the int0_n pin is sampled low.
When IT0 = 1, int0_n is edge-sensitive and 8051
sets the IE0 flag when the int0_n pin is sampled
high then low on consecutive samples.
The remaining four external interrupts are edgesensitive only. int2 and int4 are active high,
int3_n and int5_n are active low. The power-fail
(pfi) interrupt is edge-sensitive, active high, and
sampled once per instruction cycle. To ensure
that edge-sensitive interrupts are detected, the
corresponding ports should be held high for 4
clk cycles and then low for 4 clk cycles. Levelsensitive interrupts are not latched and must
remain active until serviced.
at SFR locations 82h and 83h.
It is not
necessary to modify code to use DPTR0.
The FDC37N972 adds a second data pointer
(DPTR1) at SFR locations 84h and 85h. The
SEL bit in the DPTR Select Register, DPS (SFR
86h), selects the active pointer (see sections
DPL1, DPH1 and DPS below).
All DPTR-related instructions use the currently
selected data pointer. To switch the active
pointer, toggle the SEL bit. The fastest way to
do so is to use the increment instruction (INC
DPS). This requires only one instruction to
switch from a source address to a destination
address, saving application code from having to
save source and destination addresses when
doing a block move.
Timer 2
Interrupt Latency
Overview
Interrupt response time depends on the current
state of the 8051. The fastest response time is
5 instruction cycles: 1 to detect the interrupt,
and 4 to perform the LCALL to the ISR. The
maximum latency (13 instruction cycles) occurs
when the 8051 is currently executing a RETI
instruction followed by a MUL or DIV instruction.
The 13 instruction cycles in this case are: 1 to
detect the interrupt, 3 to complete the RETI, 5 to
execute the DIV or MUL, and 4 to execute the
LCALL to the ISR. For the maximum latency
case, the response time is 13 x 4 = 52 clk
cycles.
The high-performance 8051 in the FDC37N972
includes a third timer/counter (Timer 2). Timer
2 runs only in 16-bit mode and offers several
capabilities not available with Timers 0 and 1.
The modes available with Timer 2 are 16-bit
auto-reload timer/counter and baud rate
generator. The SFRs associated with Timer 2
are:
•
T2CON (SFR C8h)
•
RCAP2L (SFR CAh) – Used as the
16-bit LSB reload value when
Timer 2 is configured for autoreload mode.
•
RCAP2H (SFR CBh) – Used as the
16-bit MSB reload value when
Timer 2 is configured for autoreload mode.
•
TL2 (SFR CCh) – Lower 8 bits of
16-bit count.
•
TH2 (SFR CDh) – Upper 8 bits of
16-bit count.
Dual Data Pointers
The high-performance 8051 in the FDC37N972
employs dual data pointers to accelerate data
memory block moves. The standard 8051 data
pointer (DPTR) is a 16-bit value used to address
external RAM or peripherals. The FDC37N972
maintains the standard data pointer as DPTR0
380
operating mode.
TABLE 254 summarizes how the T2CON SFR
bits (TABLE 259) determine the Timer 2
RCLK
0
1
X
X
TABLE 254 - TIMER 2 MODE CONTROL SUMMARY
TCLK
TR2
MODE
0
1
16-bit Timer/Counter w/Auto-reload
X
1
Baud Rate Generator
1
1
Baud Rate Generator
X
0
Off
16-bit Timer/Counter Mode with Auto-reload
FIGURE 83 illustrates how Timer 2 operates in timer/counter mode with auto-reload. The 16-bit timer
counts CLK cycles (divided by 4 or 12). The TR2 bit enables the counter. When the count increments
from FFFFh, the overflow occurs. The overflow causes the TF2 flag is set, and t2_out goes high for
one CLK cycle. The overflow also causes the preloaded start value in the RCAP2L and RCAP2H
registers to be reloaded into the TL2 and TH2 registers.
T2M
DIVIDE BY 12
0
CLK
clk
DIVIDE BY 4
1
TL2
TH2
TF2
TR2
RCAP2L
INT
RCAP2H
FIGURE 83 - TIMER 2 TIMER/COUNTER WITH AUTO-RELOAD
Baud Rate Generator Mode
Setting either RCLK or TCLK to 1 configures Timer 2 to generate baud rates for Serial Port 0 in serial
mode 1 or 3. In baud rate generator mode, Timer 2 functions in auto-reload mode. However, instead
of setting the TF2 flag, the counter overflow is used to generate a shift clock for the serial port
function. As in normal auto-reload mode, the overflow also causes the preloaded start value in the
RCAP2L and RCAP2H registers to be reloaded into the TL2 and TH2 registers.
When either TCLK = 1 or RCLK = 1, Timer 2 is forced into auto-reload operation. The counter time
base in baud rate generator mode is clk/2.
381
Special Function Registers
The following SFRs are not part of the sandard 8051 architecture.
DPL1
The DPL1 register (TABLE 255) is the LSB of DPTR1 (see the section interrupts above).
TABLE 255 - DPL1 REGISTER - SFR 84H
84h
SFR ADDRESS
VCC1
POWER
0x00
DEFAULT
TYPE
BIT NAME
D7
R/W
A7
D6
R/W
A6
D5
R/W
A5
D4
R/W
A4
D3
R/W
A3
D2
R/W
A2
D1
R/W
A1
D0
R/W
A0
DPH1
The DPH1 register (TABLE 256) is the MSB of DPTR1 (see the section interrupts above).
TABLE 256 - DPH1 REGISTER - SFR 85H
85h
SFR ADDRESS
VCC1
POWER
0x00
DEFAULT
TYPE
BIT NAME
D7
R/W
A15
D6
R/W
A14
D5
R/W
A13
D4
R/W
A12
D3
R/W
A11
D2
R/W
A10
D1
R/W
A9
D0
R/W
A8
DPS
The DPS register (TABLE 257) is used to select the active DPTR (see the section interrupts above).
TABLE 257 - DPS REGISTER - SFR 86H
86h
SFR ADDRESS
VCC1
POWER
0x00
DEFAULT
D7
D6
D5
D4
D3
D2
D1
TYPE
R
R
R
R
R
R
R
RESERVED
BIT NAME
NOTE1 When SEL = ‘0’, instructions that use the DPTR will use DPL0 and DPH0. When SEL
instructions that use the DPTR will use DPL1 and DPH1.
382
D0
R/W
SEL1
= ‘1’,
CKCON
The default timer clock scheme for the DW8051 timers is 12 clk cycles per increment, the same as in
the standard 8051. However, in the DW8051, the instruction cycle is 4 clk cycles. Using the default
rate (12 clocks per timer increment) allows existing application code with real-time dependencies,
such as baud rate, to operate properly. However, applications that require fast timing can set the
timers to increment every 4 clk cycles by setting bits in the Clock Control register (CKCON) at SFR
location 8Eh (TABLE 258 and TABLE 259).
The CKCON bits that control the timer clock rates are:
CKCON BIT
5
4
3
COUNTER/TIMER
Timer 2
Timer 1
Timer 0
When a CKCON register bit is set to 1, the associated counter increments at 4-clk intervals. When a
CKCON bit is cleared, the associated counter increments at 12-clk intervals. The timer controls are
independent of each other. The default setting for all three timers is 0 (12-clk intervals). These bits
have no effect in counter mode.
TABLE 258 - CKCON REGISTER - SFR 8EH
8EH
SFR ADDRESS
VCC1
POWER
0x01
DEFAULT
TYPE
BIT NAME
D7
D6
R
R
RESERVED
D5
R/W
T2M
D4
R/W
T1M
D3
R/W
T0M
D2
R/W
MD2
D1
R/W
MD1
TABLE 259 - CKCON REGISTER BIT DESCRIPTIONS
FUNCTION
Reserved
T2M. Timer 2 clock select. When T2M = 0, Timer 2 uses
clk/12 (for compatibility with 80C32); when T2M = 1, Timer
2 uses clk/4. This bit has no effect when Timer 2 is
configured for baud rate generation.
CKCON.4
T1M. Timer 1 clock select. When T1M = 0, Timer 1 uses
clk/12 (for compatibility with 80C32); when T1M = 1, Timer
1 uses clk/4.
CKCON.3
T0M. Timer 0 clock select. When T0M = 0, Timer 0 uses
clk/12 (for compatibility with 80C32); when T0M = 1, Timer
0 uses clk/4.
CKCON.2-0
MD2, MD1, MD0 -- Control the number of cycles to be used
for external MOVX instructions.
BIT
CKCON.7-6
CKCON.5
383
D0
R/W
MD0
MPAGE
The MPAGE special function register (TABLE 260) replaces the function of the Port 2 latch in the
FDC37N972. During MOVX A, @Ri and MOVX @Ri, A instructions, the 8051 places the contents of
the MPAGE register on the upper eight address bits. This provides the paging function that is
normally provided by the Port 2 latch.
TABLE 260 - MPAGE REGISTER – SFR 92H
92H
SFR ADDRESS
VCC1
POWER
0x00
DEFAULT
TYPE
BIT NAME
D7
R/W
A15
D6
R/W
A14
D5
R/W
A13
D4
R/W
A12
D3
R/W
A11
D2
R/W
A10
D1
R/W
A9
D0
R/W
A8
T2CON
The T2CON register (TABLE 261 and TABLE 263) is used to configure Timer 2 (see the section
Interrupts above).
TABLE 261 – T2CON REGISTER - SFR C8H
C8h
SFR ADDRESS
VCC1
POWER
0x00
DEFAULT
TYPE
BIT NAME
D7
R/W
TF2
BIT
T2CON.7
T2CON.6
T2CON.5
T2CON.4
D6
R/W
RESERV
ED
D5
R/W
RCLK
D4
R/W
TCLK
D3
R/W
RESERV
ED
D2
R/W
TR2
D1
D0
R/W
R/W
RESERVED
TABLE 263 – T2CON REGISTER BIT DESCRIPTIONS
FUNCTION
TF2 Timer 2 overflow flag. Hardware will set TF2 when the
Timer 2 overflows from FFFFh. TF2 must be cleared to 0
by the software. TF2 will only be set to a 1 if RCLK and
TCLK are both cleared to 0. Writing a 1 to TF2 forces a
Timer 2 interrupt if enabled.
Reserved. This bit should be written as ‘0’.
RCLK Receive clock flag. Determines whether Timer 1 or
Timer 2 is used for Serial Port 0 timing of received data in
serial mode 1 or 3. RCLK =1 selects Timer 2 overflow as
the receive clock. RCLK =0 selects Timer 1 overflow as the
receive clock.
TCLK Transmit clock flag. Determines whether Timer 1 or
Timer 2 is used for Serial Port 0 timing of transmit data in
384
BIT
FUNCTION
serial mode 1 or 3. RCLK =1 selects Timer 2 overflow as
the transmit clock. RCLK =0 selects Timer 1 overflow as
the transmit clock.
Reserved. This bit should be written as ‘0’.
TR2. Timer 2 run control flag. TR2 = 1 starts Timer 2.
TR2 = 0 stops Timer 2.
Reserved. This bit should be written as ‘0’.
T2CON.3
T2CON.2
T2CON.1-0
RCAP2L
The RCAP2L register (TABLE 263) is the 16-bit LSB reload value (RV[7:0]) when Timer 2 is
configured for auto-reload mode (see the section interrupts above).
TABLE 263 - RCAP2L REGISTER – SFR CAH
CAh
SFR ADDRESS
VCC1
POWER
0x00
DEFAULT
TYPE
BIT NAME
D7
R/W
RV7
D6
R/W
RV6
D5
R/W
RV5
D4
R/W
RV4
D3
R/W
RV3
D2
R/W
RV2
D1
R/W
RV1
D0
R/W
RV0
RCAP2H
The RCAP2H register (TABLE 264) is the 16-bit MSB reload value (RV[15:8]) when Timer 2 is
configured for auto-reload mode (see the section interrupts above).
TABLE 264 - RCAP2H REGISTER - SFR CBH
CBh
SFR ADDRESS
VCC1
POWER
0x00
DEFAULT
TYPE
BIT NAME
D7
R/W
RV15
D6
R/W
RV14
D5
R/W
RV13
D4
R/W
RV12
385
D3
R/W
RV11
D2
R/W
RV10
D1
R/W
RV9
D0
R/W
RV8
TL2
The TL2 register (TABLE 265) is the 16-bit LSB Timer 2 count value (CV[7:0]) (see the section
Interrupts above).
TABLE 265 - TL2 REGISTER - SFR CCH
SFR ADDRESS
POWER
DEFAULT
TYPE
BIT NAME
D7
R/W
CV7
D6
R/W
CV6
D5
R/W
CV5
CCh
VCC1
0x00
D4
R/W
CV4
D3
R/W
CV3
D2
R/W
CV2
D1
R/W
CV1
D0
R/W
CV0
TH2
The TH2 register (Table 266
TABLE 266) is the 16-bit MSB Timer 2 count value (CV[15:8]) (see the section interrupts above).
TABLE 266 - TH2 REGISTER - SFR CDH
CDh
SFR ADDRESS
VCC1
POWER
0x00
DEFAULT
TYPE
BIT NAME
D7
R/W
CV15
D6
R/W
CV14
D5
R/W
CV13
D4
R/W
CV12
D3
R/W
CV11
D2
R/W
CV10
D1
R/W
CV9
D0
R/W
CV8
EXIF
The EXIF register (Table 268 and Table 269) contains the external interrupt flags for the extended
interrupt unit (see the section interrupts above).
TABLE 267 - EXIF REGISTER - SFR 91H
91h
SFR ADDRESS
VCC1
POWER
0x08
DEFAULT
TYPE
BIT NAME
D7
R/W
IE5
D6
R/W
IE4
D5
R/W
IE3
D4
R/W
IE2
386
D3
D2
R
R
RESERVED
D1
R
D0
R
BIT
EXIF.7
EXIF.6
EXIF.5
EXIF.4
EXIF.3
EXIF.2-0
TABLE 268 - EXIF REGISTER BIT DESCRIPTIONS
FUNCTION
IE5 External Interrupt 5 flag. IE5 = 1 indicates a falling
edge was detected at the int5_n pin. IE5 must be cleared
by software. Setting IE5 in software generates an interrupt,
if enabled.
IE4 External Interrupt 4 flag. IE4 = 1 indicates a rising
edge was detected at the int4 pin. IE4 must be cleared by
software. Setting IE4 in software generates an interrupt, if
enabled.
IE3 External Interrupt 3 flag. IE3 = 1 indicates a falling
edge was detected at the int3_n pin. IE3 must be cleared
by software. Setting IE3 in software generates an interrupt,
if enabled.
IE2 External Interrupt 2 flag. IE2 = 1 indicates a rising
edge was detected at the int2 pin. IE2 must be cleared by
software. Setting IE2 in software generates an interrupt, if
enabled.
Reserved. Read as ‘1’.
Reserved. Read as ‘0’.
EICON
The EICON register (TABLE 269 and TABLE 270) contains pfi and serial port 1 controls for the
extended interrupt unit (see the section interrupts above).
TABLE 269 - EICON REGISTER - SFR D8H
D8h
SFR ADDRESS
VCC1
POWER
0x40
DEFAULT
TYPE
BIT NAME
D7
R/W
SMOD1
BIT
EICON.7
EICON.6
EICON.5
EICON.4
D6
R/W
RESERV
ED
D5
R/W
EPFI
D4
R/W
PFI
D3
D2
R
R
RESERVED
D1
R
TABLE 270 - EICON REGISTER BIT DESCRIPTIONS
FUNCTION
SMOD1 Serial Port 1 baud rate doubler enable. When
SMOD1 = 1, the baud rate for Serial Port 1 is doubled.
Reserved. Read as ‘1’.
EPFI Enable power-fail interrupt. EPFI = 0 disables powerfail interrupt (pfi). EPFI = 1 enables interrupts generated by
the pfi pin.
PFI Power-fail interrupt flag. PFI = 1 indicates a power-fail
387
D0
R
BIT
FUNCTION
interrupt was detected at the pfi pin. PFI must be cleared
by software before exiting the interrupt service routine.
Otherwise, the interrupt occurs again. Setting PFI in
software generates a power-fail interrupt, if enabled.
Reserved. Read as ‘0’.
EICON.3-0
EIE
The EIE register (Table 273 and Table 275) contains the external interrupt enables for the extended
interrupt unit (see the section interrupts above).
TABLE 271 - EIE REGISTER - SFR E8H
E8h
SFR ADDRESS
VCC1
POWER
0xE0
DEFAULT
TYPE
BIT NAME
D7
D6
R
R
RESERVED
BIT
EIE.7-5
EIE.4
EIE.3
EIE.2
EIE.1
EIE.0
D5
R
D4
R
D3
R/W
EX5
D2
R/W
EX4
D1
R/W
EX3
TABLE 272 - EIE REGISTER BIT DESCRIPTIONS
FUNCTION
Reserved. Read as ‘1’.
Reserved. Read and Write as ‘0’.
EX5 Enable external interrupt 5. EX5 = 0 disables external
interrupt 5 (int5_n). EX5 = 1 enables interrupts generated
by the int5_n pin.
EX4 Enable external interrupt 4. EX4 = 0 disables external
interrupt 4 (int4). EX4 = 1 enables interrupts generated by
the int4 pin.
EX3 Enable external interrupt 3. EX3 = 0 disables external
interrupt 3 (int3_n). EX3 = 1 enables interrupts generated
by the int3_n pin.
EX2 Enable external interrupt 2. EX2 = 0 disables external
interrupt 2 (int2). EX2 = 1 enables interrupts generated by
the int2 pin.
388
D0
R/W
EX2
EIP
The EIP register (Table 273 and Table 274) contains the external interrupt priority controls for the
extended interrupt unit (see the section interrupts above).
TABLE 273 - EIP REGISTER - SFR F8H
F8h
SFR ADDRESS
VCC1
POWER
0xE0
DEFAULT
TYPE
BIT NAME
D7
D6
R
R
RESERVED
BIT
EIP.7-5
EIP.4
EIP.3
EIP.2
EIP.1
EIP.0
D5
R
D4
R
D3
R/W
PX5
D2
R/W
PX4
TABLE 274 - EIP REGSITER BIT DESCRIPTIONS
FUNCTION
Reserved. Read as ‘1’.
Reserved. Read and Write as ‘0’.
PX5 External interrupt 5 priority control. PX5 =
external interrupt 5 (int5_n) to low priority. PX5 =
external interrupt 5 to high priority.
PX4 External interrupt 4 priority control. PX4 =
external interrupt 4 (int4) to low priority. PX2 =
external interrupt 4 to high priority.
PX3 External interrupt 3 priority control. PX3 =
external interrupt 3 (int3_n) to low priority. PX3 =
external interrupt 3 to high priority.
PX2 External interrupt 2 priority control. PX2 =
external interrupt 2 (int2) to low priority. PX2 =
external interrupt 2 to high priority.
389
D1
R/W
PX3
0 sets
1 sets
0 sets
1 sets
0 sets
1 sets
0 sets
1 sets
D0
R/W
PX2
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FDC37N972 Rev. 03/28/2000