MSAN-216
Applications of the MDS108/MVTX1100
XLink Interface
Application Note
1.0
Purpose
Application note describing the XLink interface for the
MDS108 & MVTX1100 devices.
2.0
Scope
This document will cover clock requirements and
interface connections for the XLink interface. The
reader should be familiar with the MDS108/MVTX1100
datasheet before reading this application note.
3.0
Introduction
Port 8 on the MDS108/MVTX1100 is the XLink port.
The XLink port provides a high-speed communication
link between two chips. When cascaded via the XLink
port, two devices are capable of providing up to
sixteen 10/100Mbps ports.
When two devices are cascaded, the XLink port on
each device is treated as if it were a standard switch
output. Standard Ethernet packet protocols are
utilized, traditional packet integrity checks are
performed at the receiving XLink port, and standard
length Ethernet packets are transmitted.
4.0 XLink Speed and System Clock
Requirement
DSxxxx
Issue 1
November 2002
than 200Mbps, the device must utilize a higher
frequency system clock in order to be able to support
the greater switching bandwidth requirements. With a
66MHz system clock (S_CLK) the device can support
full wire-speed forwarding on all 8 ports, and full wire
speed on the XLink port for expansion port data rates
up to 200Mbps. With an 80MHz system clock (S_CLK),
the device can support full wire-speed operation on all
8 ports and the XLink at data rates up to 400Mbps.
The XLink frequency of operation is determined by
strap options during power-up. The frame buffer
memory address pins L_A[10:9] provide the maximum
frequency of operation selection as shown in the
following table.
XLink Data
Rate
L_A[10:9]
Strap Level
100Mbps
11
200Mbps
10
300Mbps
01
400Mbps
00
The XLink port utilizes an industry standard MII
interface. This XLink expansion port is capable of
operating at several data rates depending upon
configuration. Multiple data rates are achieved by
multiplying the MII reference clock for the XLink
interface (M8_REFCLK). When operating at greater
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MSAN-216
Application Note
To achieve higher overall bandwidth, the S_CLK frequency must be adjusted based on the system configuration
and its maximum aggregated switching bandwidth. The following table provides a general guideline for determining
the S_CLK frequency. Any frequency higher than the value specified below up to 80MHz is acceptable. The last 3
rows are for the high-speed XLink MII communication mode, which is described in the next section.
Configuration
M_CLK
(RMII)
Output
Port 0-7
Port 8
S_CLK
10M RMII
10/100M MII
50M
--
Not Used
55M
--
10/100M MII
60M
200M MII
66.66M
50M
300M MII
75M
75M
400M RMII
80M
100M
100M RMII
2
Input
M8_REF
--
50M
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L_CLK
M_MDC
SCL
S_CLK
S_CLK/32
50K
MSAN-216
Application Note
5.0
XLink MII Interface Connection
5.1
100M Interface
The basic XLink MII interface connection between two devices is shown in the figure below. In the figure, the device
at the left can be MDS108 or MVTX1100. The device at the right can be any device that has a MII interface. The
communication speed between two devices is the standard 100Mbps. To enable basic 100Mbps communication
speed, the bootstrap option on both L_A[10] and L_A[9] must be floating (with weak internal pull high) or pull high.
A 25MHz clock is connected to the TX and RX clocks on both devices. The speed and duplex pins on both devices
should be float or pull-high to enable 100Mbps full duplex mode of operation.
As shown in the figure below, the TXEN of a device must be connected to the RXDV of another device, and the
TXDATA of a device must be connected to the RXDATA of another device. The M8_REFCLK is not used in this
mode (it outputs a clock which is equal to M_CLK/2).
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3
MSAN-216
5.2
Application Note
200/300/400M Interface
To achieve more than 100Mbps communication bandwidth, a high speed communication mode is supported in the
XLink interface. The signal connection for high-speed communication mode is shown in the figure below. Both
devices can be MDS108 or MVTX1100. The maximum communication speed between two devices is controlled by
the L_A[10:9] bootstrap option. The L_A[10:9] must not be 11 for this connection set-up. As shown in the figure
below, the TXEN of a device must be connected to the RXDV of another device, and the TXDATA of a device must
be connected to the RXDATA of another device.
To enable 200Mbps communication speed, the bootstrap option for L_A[10: 9] must be 10. A 50MHz clock is
connected to the M8_REFCLK pin on both devices. To enable 300Mbps communication speed, the bootstrap
option for L_A[10: 9] must be 01. A 75MHz clock is connected to the M8_REFCLK pin on both devices. To enable
400Mbps communication speed, the bootstrap option for L_A[10: 9] must be 00. A 100MHz clock is connected to
the M8_REFCLK pin on both devices.
50 ~ 100
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