MSAN-209
IMA over G.SHDSL
Interfacing ZL30228 to Metalink’s MTS870
Application Note
Issue 1
1.0
October 2002
Introduction
Traditionally, IMA (Inverse Multiplexing for ATM) is widely adopted in E1/DS1 applications. With emerging G.SHDSL
(Single-pair High rate Digital Subscribe Line) standard, it is now viable to apply IMA over SHDSL lines.
This application note provides a solution of IMA over up to 16 G.SHDSL lines. It serves as a reference design of
interfacing ZL30228 to Metalink's MTS870 chipset.
ZL30228 is the second-generation IMA device from Zarlink, which supports IMA over 16 serial bit streams running
at a maximum of 2.5Mbps. It also incorporates UTOPIA Level 2 (and Level 1) bus as ATM interface.
The MTS870 chipset contains 8 channels DSL framers that support multiple modes of Symmetrical DSL like ITU
G.SHDSL, the ETSI SDSL, and the ANSI HDSL2
ZL30228 together with MTS870 and Metalink's AFE chipsets together provide a complete solution for IMA over
G.SHDSL that meets both IMA version 1.1/1.0 specification and G.SHDSL specification.
2.0
Notification
This reference design is showing how to connect ZL30228 to MTS870 chipset. In the schematic that follows,
ZL30228 is shown with full pinout and surrounding circuitry. Only the data interface pins on MTS870 chipset are
presented to illustrate the interconnection. For detailed reference design of MTS870 chipset please contact
Metalink.
The ZL30228 device shown in this reference design can be replaced by ZL30227 (Octal) or ZL30226 (Quad), two
IMA devices from the same family. Both ZL30227 and ZL30226 are pin and functional compatible to ZL30228.
3.0
-
Schematics Content
The top-level diagram is represented on the first page.
Second and third pages contain the detailed schematics of ZL30228.
Data interface of MTS870 is shown on the fourth page.
Zarlink products and associated documents marked "Eng" ("ENGineering Samples") are or relate to products in development and not released to production. All
ENGineering Samples are supplied only for testing and on the express understanding that (i) they have not been fully tested or characterized under intended modes
of operation and may contain defects; (ii) Zarlink makes no representation or warranty regarding them; and (iii) Zarlink disclaims any liability for claims, demands and
damages, including without limitation special, indirect and consequential damages, resulting from any loss arising out of the application, use or performance of them.
ENGineering Samples may be changed or discontinued by Zarlink at any time without notice.
1
MSAN-209
4.0
Application Note
Modes of Operation
The following modes of operation must be selected and programmed:
1. ZL30228 mode: Unframed, serial bit stream mode up to 2.5Mbit/s.
2. ZL30228 Recommended register settings:
TDM Tx Link Control Register
0x0600
should be set to 0x00A3,
0x0601
should be set to 0x04A3,
0x0602
should be set to 0x08A3,
0x0603
should be set to 0x0CA3,
0x0604
should be set to 0x10A3,
0x0605
should be set to 0x14A3,
0x0606
should be set to 0x18A3,
0x0607
should be set to 0x1CA3,
0x0608
should be set to 0x20A3,
0x0609
should be set to 0x24A3,
0x060A
should be set to 0x28A3,
0x060B
should be set to 0x2CA3,
0x060C
should be set to 0x30A3,
0x060D
should be set to 0x34A3,
0x060E
should be set to 0x38A3,
0x060F
should be set to 0x3CA3.
TDM Tx Mapping Registers
(0x0610 - 0x061F)
should be set to 0xFFFF.
TDM Tx Mapping Registers
(0x0620 - 0x062F)
should be set to 0xFFFF.
TDM Rx Link Control Register
(0x0700 - 0x070F)
should be set to 0x04A3.
TDM Rx Mapping Registers
(0x0710 - 0x071F)
should be set to 0xFFFF.
TDM Rx Mapping Registers
(0x0720 - 0x072F)
should be set to 0xFFFF.
Rx Automatic ATM Synchronization Register
(0x0741)
should be set to 0x0036
3. MTS870 chipset provides RxCLK to ZL30228, while the TxCLK is generated by ZL30228 (from respective
RxCLK) and output to ZL30228.
4. MTS870 chipset should be configured in transparent (datapump) mode.
For detailed programming and pinout of MTS870, please refer to Metalink's data sheet and G.SHDSL Transceiver
Reference Design.
2
Zarlink Semiconductor Inc.
5
4
3
2
1
Interfacing Zarlink ZL30228 IMA device to Metalink MTS870
Octal G.SHDSL/SDSL/HDSL2/HDSL/IDSL Transceiver Chip
Set
D
D
Link 0
Link 1
UTOPIA
Interface
Link 2
Link 3
Metalink
MTS870
Metalink
AFE
Link 4
C
C
Link 5
ZL30228
Link 6
Link 7
Link 8
Microport
Interface
Link 9
B
B
Link 10
Link 11
Metalink
AFE
Metalink
MTS870
Link 12
Link 13
Link 14
Link 15
A
A
Note 1:
Decoupling capacitors are not shown in the reference design.
They should be placed where needed.
Title
ZL30228 to MTS870, Block Diagram
Size
Date:
5
4
3
2
Document Number
Rev
1.0
Monday, October 07, 2002
Sheet
1
1
of
4
5
4
3
2
1
IMA_RST
RW_IMA
OE_IMA
CS_IMA
IRQ_IMA
U1sr_a18
U1sr_a17
U1sr_a16
U1sr_a15
U1sr_a14
U1sr_a13
U1sr_a12
U1sr_a11
U1sr_a10
U1sr_a9
U1sr_a8
U1sr_a7
U1sr_a6
U1sr_a5
U1sr_a4
U1sr_a3
U1sr_a2
U1sr_a1
U1sr_a0
41
40
39
38
30
29
28
27
26
20
19
18
17
16
7
6
5
4
3
A18
A17
A16
A15
A14
A13
A12
A11
A10
A09
A08
A07
A06
A05
A04
A03
A02
A01
A00
33
VDD3.3
VDD3.3
33
CE
36
35
32
31
14
13
10
9
I/O7
I/O6
I/O5
I/O4
U1 I/O3
I/O2
I/O1
I/O0
34
URx_A[4..0]
U1sr_d[7..0]
URxData15
URxData14
URxData13
URxData12
URxData11
URxData10
URxData09
URxData08
URxData07
URxData06
URxData05
URxData04
URxData03
URxData02
URxData01
URxData00
URxParity
URx_A4
URx_A3
URx_A2
URx_A1
URx_A0
L1
L2
L4
L3
K1
URxAddr4
URxAddr3
URxAddr2
URxAddr1
URxAddr0
J4
K3
K2
J3
URx_SOC
URx_Clk
URx_EN/
URx_Clav
VCC3.3
R3
R6
R8
R9
R10
R13
R11
R14
R15
R16
R5
500
R12
4.7K
JP1
6
5
4
3
2
1
R17
39
R18
39
1K
1K
1K
1K
1K
1K
1K
1K
1K
1K
IMA_RST
LatchClk
IMA_RST
R19
RxRing_D7
RxRing_D6
RxRing_D5
RxRing_D4
RxRing_D3
RxRing_D2
RxRing_D1
RxRing_D0
RxRingSync
RxRingClk
R20
R21
1K
10K
VCC3.3
A
OSC1
1
2
OE
GND
VCC
OUTPUT
4
3
R22
A4
C19
AC1
U1sr_d7
U1sr_d6
U1sr_d5
U1sr_d4
U1sr_d3
U1sr_d2
U1sr_d1
U1sr_d0
B16
D15
A16
RxRingData7
RxRingData6
RxRingData5
RxRingData4
RxRingData3
RxRingData2
RxRingData1
RxRingData0
RxRingSync
RxRingClk
TMS
TDI
TDO
TRST
TCK
Reset
LatchClk
Clk
sr_cs_0
sr_we
sr_cs_1
B7
A7
D8
C8
B8
D9
C9
B9
URxSOC
URxClk
URxEnB
URxClav
AE12
up_a11
AC12
up_a10
AF11
up_a09
AE11
up_a08
AC11
up_a07
AD11
up_a06
AF10
up_a05
AE10
up_a04
AD10
up_a03
AF9
up_a02
AE9
up_a01
AD9 up_a00
10K
AC16
AE16
AF16
AC15
AE15
AF15
AD14
AE14
AF14
AF13
A5
B6
C6
B5
D7
U3B
ZL30228
UTxData15
UTxData14
UTxData13
UTxData12
UTxData11
UTxData10
UTxData09
UTxData08
UTxData07
UTxData06
UTxData05
UTxData04
UTxData03
UTxData02
UTxData01
UTxData00
UTxParity
U2
U1
T4
T2
T1
R3
R4
R2
R1
P3
P1
N1
N2
N3
M2
M4
U3
UTx_D15
UTx_D14
UTx_D13
UTx_D12
UTx_D11
UTx_D10
UTx_D9
UTx_D8
UTx_D7
UTx_D6
UTx_D5
UTx_D4
UTx_D3
UTx_D2
UTx_D1
UTx_D0
UTxAddr4
UTxAddr3
UTxAddr2
UTxAddr1
UTxAddr0
Y4
W3
W4
W2
W1
UTx_A4
UTx_A3
UTx_A2
UTx_A1
UTx_A0
UTxSOC
UTxClk
UTxEnb
UTxClav
V1
V4
V3
V2
TxRingData7
TxRingData6
TxRingData5
TxRingData4
TxRingData3
TxRingData2
TxRingData1
TxRingData0
TxRingSync
TxRingClk
J3
UTx_Parity
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
UTx_A[4..0]
B17
C17
A18
B18
D18
C18
A19
B19
A17
D16
B
UTOPIA Tx
R7
500
A
VCC3.3
P_A11
P_A10
P_A09
P_A08
P_A07
P_A06
P_A05
P_A04
P_A03
P_A02
P_A01
P_A00
P_A[11..0]
RW_IMA
OE_IMA
CS_IMA
R23
4.7K
RW_IMA
OE_IMA
CS_IMA
Title
ZL30228 to MTS870, ZL30228 Part B
IRQ_IMA
P_D[15..0]
Size
Date:
4
UTx_D[15..0]
UTx_SOC
UTx_Clk
UTx_EN\
UTx_Clav
40
CB3LV3I50
P_D15
P_D14
P_D13
P_D12
P_D11
P_D10
P_D9
P_D8
P_D7
P_D6
P_D5
P_D4
P_D3
P_D2
P_D1
P_D0
R4
500
C
AC9
up_irq
AE13
up_cs
AD13
up_oe/up_rd
AF12
up_rw/up_wr
H3
H4
G1
G2
G3
G4
F1
F2
F3
E1
E3
D1
D2
C1
D3
C2
H2
UTOPIA Rx
up_d15
up_d14
up_d13
up_d12
up_d11
up_d10
up_d09
up_d08
up_d07
up_d06
up_d05
up_d04
up_d03
up_d02
up_d01
up_d00
B
URx_D15
URx_D14
URx_D13
URx_D12
URx_D11
URx_D10
URx_D9
URx_D8
URx_D7
URx_D6
URx_D5
URx_D4
URx_D3
URx_D2
URx_D1
URx_D0
AE8
AD8
AF7
AE7
AD7
AC7
AF6
AD6
AF5
AE5
AD5
AE4
AF3
AD4
AE3
AF2
URx_D[15..0]
URx_SOC
URx_Clk
URx_EN/
URx_Clav
sr_d7
sr_d6
sr_d5
sr_d4
sr_d3
sr_d2
sr_d1
sr_d0
U1sr_a18
U1sr_a17
U1sr_a16
U1sr_a15
U1sr_a14
U1sr_a13
U1sr_a12
U1sr_a11
U1sr_a10
U1sr_a9
U1sr_a8
U1sr_a7
U1sr_a6
U1sr_a5
U1sr_a4
U1sr_a3
U1sr_a2
U1sr_a1
U1sr_a0
A9
C10
B10
A10
C11
D11
B11
A11
C12
D12
B12
A12
C13
B13
A14
B14
C14
A15
B15
P_D[15..0]
URx_Parity
URx_A[4..0]
5
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
URx_Parity
IS61LV5128-10T
D
J1
URx_D[15..0]
U1sr_d[7..0]
U1sr_a[18..0]
IS61LV5128-10T
U1sr_d7
U1sr_d6
U1sr_d5
U1sr_d4
U1sr_d3
U1sr_d2
U1sr_d1
U1sr_d0
U1sr_a[18..0]
P_A[11..0]
JTAG
VDD3.3
U1sr_d[7..0]
U1sr_a[18..0]
Microport Connector
TMS
TDI
TDO
TRST
TCK
GND
R2
1K
U1sr_d7
U1sr_d6
U1sr_d5
U1sr_d4
U1sr_d3
U1sr_d2
U1sr_d1
U1sr_d0
sr_a18
sr_a17
sr_a16
sr_a15
sr_a14
sr_a13
sr_a12
sr_a11
sr_a10
sr_a09
sr_a08
sr_a07
sr_a06
sr_a05
sr_a04
sr_a03
sr_a02
sr_a01
sr_a00
C
IMA_RST
RW_IMA
OE_IMA
CS_IMA
IRQ_IMA
P_D15
P_D14
P_D13
P_D12
P_D11
P_D10
P_D9
P_D8
P_D7
P_D6
P_D5
P_D4
P_D3
P_D2
P_D1
P_D0
P_A11
P_A10
P_A9
P_A8
P_A7
P_A6
P_A5
P_A4
P_A3
P_A2
P_A1
P_A0
36
35
32
31
14
13
10
9
I/O7
U2 I/O6
I/O5
I/O4
I/O3
I/O2
I/O1
I/O0
12
33
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
33
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
Note 2:
The amount of memory and the number of SRAM chips needed can be more
or less than specified in the reference design,depending on the links differential
delay. Please refer to ZL30228 datasheet.
GND
J2A
CE
A18
A17
A16
A15
A14
A13
A12
A11
A10
A09
A08
A07
A06
A05
A04
A03
A02
A01
A00
VCC3.3
34
D
41
40
39
38
30
29
28
27
26
20
19
18
17
16
7
6
5
4
3
WE
8
WE
GND
U1sr_a18
U1sr_a17
U1sr_a16
U1sr_a15
U1sr_a14
U1sr_a13
U1sr_a12
U1sr_a11
U1sr_a10
U1sr_a9
U1sr_a8
U1sr_a7
U1sr_a6
U1sr_a5
U1sr_a4
U1sr_a3
U1sr_a2
U1sr_a1
U1sr_a0
OE
15
12
8
R1
1K
37
GND
15
OE
GND
37
VDD3.3
11
11
VCC3.3
3
2
Document Number
Monday, October 07, 2002
Rev
1.0
Sheet
1
2
of
4
R45
R46
R47
R48
R49
R50
R51
R52
R53
R54
R55
R56
R57
R58
R59
R60
51
51
51
51
51
51
51
51
51
51
51
51
51
51
51
51
A
R29
1K
R30
1K
R31
1K
R32
1K
R33
1K
R34
1K
R35
1K
R36
1K
R37
1K
R38
1K
R39
1K
R40
1K
R41
1K
R42
1K
R43
1K
R44
1K
TxCKio0
TxCKio1
TxCKio2
TxCKio3
TxCKio4
TxCKio5
TxCKio6
TxCKio7
TxCKio8
TxCKio9
TxCKio10
TxCKio11
TxCKio12
TxCKio13
TxCKio14
TxCKio15
DSTo0
DSTo1
DSTo2
DSTo3
DSTo4
DSTo5
DSTo6
DSTo7
DSTo8
DSTo9
DSTo10
DSTo11
DSTo12
DSTo13
DSTo14
DSTo15
VCC3.3
VCC3.3
VCC3.3
VCC3.3
VCC3.3
VCC3.3
VCC3.3
VCC3.3
VCC3.3
C
VCC3.3
B
5
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
E2
H1
J1
M3
T3
AB3
AE6
AF8
AD12
AD15
AC19
AD25
AA25
N25
C5
H26
F26
D20
C16
A13
A8
VCC5
VCC5
VCC5
VCC5
VCC5
VCC5
VCC5
VCC5
VCC5
VCC5
VCC5
VCC5
VCC5
VCC5
VCC5
VCC5
VCC5
VCC5
VCC5
VCC5
VCC5
AA23
AB4
AC6
AC13
AC17
AC22
D6
VCC3.3
VCC3.3
VCC3.3
VCC3.3
VCC3.3
VCC3.3
VCC3.3
Test4
Test3
Test2
Test1
REFCK0
REFCK1
REFCK2
REFCK3
IC
IC
IC
IC
IC
IC
IC
IC
IC
IC
IC
IC
IC
IC
IC
IC
RxCKi00
RxCKi01
RxCKi02
RxCKi03
RxCKi04
RxCKi05
RxCKi06
RxCKi07
RxCKi08
RxCKi09
RxCKi10
RxCKi11
RxCKi12
RxCKi13
RxCKi14
RxCKi15
DSTi00
DSTi01
DSTi02
DSTi03
DSTi04
DSTi05
DSTi06
DSTi07
DSTi08
DSTi09
DSTi10
DSTi11
DSTi12
DSTi13
DSTi14
DSTi15
A2
B3
C4
A3
A6
C15
D24
B26
C25
E25
L23
R24
AE26
AD23
AF25
AE24
AF24
AE23
AD22
AF23
B1
J2
M1
Y1
AA2
AC2
AD2
AE1
AC3
AF4
AC8
AE17
AC20
AD21
AF22
AB1 PLLREF0
AB2
PLLREF1
AD16PD
AF18
PD
AD18
PD
AD19
PD
AD20
PD
AC21PD
AD26
PD
AB24 PD
AA24
PD
Y24 PD
W23
PD
W26
PD
V25 PD
U26
PD
T25 PD
R25
PD
AF17 TxCKio00
AE18
TxCKio01
AF19 TxCKio02
AF20
TxCKio03
AF21
TxCKio04
AE22 TxCKio05
AC25
TxCKio06
AB25 TxCKio07
AA26
TxCKio08
Y25 TxCKio09
W24
TxCKio10
V23 TxCKio11
U24 TxCKio12
T24
TxCKio13
T26 TxCKio14
R26
TxCKio15
AD17DSTo00
AC18
DSTo01
AE19 DSTo02
AE20
DSTo03
AE21 DSTo04
AC24DSTo05
AC26
DSTo06
AB26 DSTo07
Y23
DSTo08
Y26 DSTo09
W25
DSTo10
V24 DSTo11
U25 DSTo12
T23
DSTo13
R23 DSTo14
P24
DSTo15
D10
D14
D22
E23
F4
K23
N4
P23
U4
B4
C7
D19
AD1
Y3
AA1
AA4
AA3
A20
A21
C21
C22
B24
D25
D26
F23
G23
H24
J24
J26
K26
L26
M25
N26
C20
D21
B22
A24
C23
E24
F24
G24
G26
H25
J25
K25
L25
M23
N24
P25
B20
B21
A22
B23
A25
C26
E26
F25
G25
H23
J23
K24
L24
M24
M26
P26
D
RxCK0
RxCK1
RxCK2
RxCK3
RxCK4
RxCK5
RxCK6
RxCK7
RxCK8
RxCK9
RxCK10
RxCK11
RxCK12
RxCK13
RxCK14
RxCK15
DSTi0
DSTi1
DSTi2
DSTi3
DSTi4
DSTi5
DSTi6
DSTi7
DSTi8
DSTi9
DSTi10
DSTi11
DSTi12
DSTi13
DSTi14
DSTi15
5
4 RxCK[7..0]
4
4
4
3
RxCK[15..8]
DSTi[7..0]
U4A
ZL30228
TCLK[7..0]
TCLK[15..8]
3
2
R24 R25 R26 R27
1K 1K 1K 1K
DSTi[15..8]
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
VCC2.5
VCC2.5
VCC2.5
VCC2.5
VCC2.5
VCC2.5
VCC2.5
VCC2.5
VCC5
VCC5
VCC5
VCC5
AB23
AC4
AC5
AC23
AD3
AD24
AE2
AE25
B2
B25
C3
C24
D4
D5
D23
E4
L11
L12
L13
L14
L15
L16
M11
M12
M13
M14
M15
M16
N11
N12
N13
N14
N15
N16
P11
P12
P13
P14
P15
P16
R11
R12
R13
R14
R15
R16
T11
T12
T13
T14
T15
T16
D13
D17
N23
U23
AC10
AC14
K4
P4
A23
P2
V26
Y2
DSTo[15..8]
2
1
4
4
4
VCC3.3
R28
4.7K
D
C
B
VCC2.5
VCC3.3
VCC3.3
A
DSTo[7..0] 4
4
4
Title
Size
Date:
Document Number
ZL30228 to MTS870, ZL30228 Part A
Friday, October 04, 2002
Rev
1.0
Sheet
1
3
of
4
5
4
3
2
1
D
D
3
TCLK[7..0]
RxCK[7..0]
3
3
TCLK[15..8]
RxCK[15..8]
U5
3
U6
C
3
TDATA[7..0]
TCKLK7
TCKLK6
TCKLK5
TCKLK4
TCKLK3
TCKLK2
TCKLK1
TCKLK0
V13
V11
V9
V7
V5
V3
V1
R2
TDATA7
TDATA6
TDATA5
TDATA4
TDATA3
TDATA2
TDATA1
TDATA0
W13
W11
W9
W7
W5
W3
W1
R1
TDATA7
TDATA6
TDATA5
TDATA4
TDATA3
TDATA2
TDATA1
TDATA0
Y13
Y11
Y9
Y7
Y5
Y3
Y1
T3
TSYNC7
TSYNC6
TSYNC5
TSYNC4
TSYNC3
TSYNC2
TSYNC1
TSYNC0
TCLK7
TCLK6
TCLK5
TCLK4
TCLK3
TCLK2
TCLK1
TCLK0
V14
V12
V10
V8
V6
V4
V2
T2
RCLK7
RCLK6
RCLK5
RCLK4
RCLK3
RCLK2
RCLK1
RCLK0
R61
R62
R64
R66
R68
R70
R72
R74
51
51
51
51
51
51
51
51
RDATA7
RDATA6
RDATA5
RDATA4
RDATA3
RDATA2
RDATA1
RDATA0
W14
W12
W10
W8
W6
W4
W2
T1
RDATA7
RDATA6
RDATA5
RDATA4
RDATA3
RDATA2
RDATA1
RDATA0
R77
R78
R80
R82
R84
R86
R88
R90
51
51
51
51
51
51
51
51
RSYNC7
RSYNC6
RSYNC5
RSYNC4
RSYNC3
RSYNC2
RSYNC1
RSYNC0
Y14
Y12
Y10
Y8
Y6
Y4
Y2
U1
RCLK7
RCLK6
RCLK5
RCLK4
RCLK3
RCLK2
RCLK1
RCLK0
DSTi[7..0]
R93
R94
R96
R98
R100
R102
R104
R106
1K
1K
1K
1K
1K
1K
1K
1K
3
3
TDATA[15..8]
TCLK15
TCLK14
TCLK13
TCLK12
TCLK11
TCLK10
TCLK9
TCLK8
V13
V11
V9
V7
V5
V3
V1
R2
TCLK7
TCLK6
TCLK5
TCLK4
TCLK3
TCLK2
TCLK1
TCLK0
RCLK7
RCLK6
RCLK5
RCLK4
RCLK3
RCLK2
RCLK1
RCLK0
V14
V12
V10
V8
V6
V4
V2
T2
RCLK15
RCLK14
RCLK13
RCLK12
RCLK11
RCLK10
RCLK9
RCLK8
R63
R65
R67
R69
R71
R73
R75
R76
51
51
51
51
51
51
51
51
RDATA15
RDATA14
RDATA13
RDATA12
RDATA11
RDATA10
RDATA9
RDATA8
R79
R81
R83
R85
R87
R89
R91
R92
51
51
51
51
51
51
51
51
C
DSTi[15..8]
TDATA15
TDATA14
TDATA13
TDATA12
TDATA11
TDATA10
TDATA9
TDATA8
R95
R97
R99
R101
R103
R105
R107
R108
1K
1K
1K
1K
1K
1K
1K
1K
W13
W11
W9
W7
W5
W3
W1
R1
TDATA7
TDATA6
TDATA5
TDATA4
TDATA3
TDATA2
TDATA1
TDATA0
RDATA7
RDATA6
RDATA5
RDATA4
RDATA3
RDATA2
RDATA1
RDATA0
W14
W12
W10
W8
W6
W4
W2
T1
Y13
Y11
Y9
Y7
Y5
Y3
Y1
T3
TSYNC7
TSYNC6
TSYNC5
TSYNC4
TSYNC3
TSYNC2
TSYNC1
TSYNC0
RSYNC7
RSYNC6
RSYNC5
RSYNC4
RSYNC3
RSYNC2
RSYNC1
RSYNC0
Y14
Y12
Y10
Y8
Y6
Y4
Y2
U1
3
MTS870
MTS870
B
B
Note 3:
A
MTS870 chipset configuration:
- Datapump or unframed mode.
- Refer to Metalink's documents: MTS870 datasheet and Metalink's
G.SHDSL Transceiver Reference Design
A
Title
ZL30228 to MTS870, MTS870
Size
Date:
5
4
3
2
Document Number
Rev
1.0
Friday, October 04, 2002
Sheet
1
4
of
4
For more information about all Zarlink products
visit our Web Site at
www.zarlink.com
Information relating to products and services furnished herein by Zarlink Semiconductor Inc. trading as Zarlink Semiconductor or its subsidiaries (collectively
“Zarlink”) is believed to be reliable. However, Zarlink assumes no liability for errors that may appear in this publication, or for liability otherwise arising from the
application or use of any such information, product or service or for any infringement of patents or other intellectual property rights owned by third parties which may
result from such application or use. Neither the supply of such information or purchase of product or service conveys any license, either express or implied, under
patents or other intellectual property rights owned by Zarlink or licensed from third parties by Zarlink, whatsoever. Purchasers of products are also hereby notified
that the use of product in certain ways or in combination with Zarlink, or non-Zarlink furnished goods or services may infringe patents or other intellectual property
rights owned by Zarlink.
This publication is issued to provide information only and (unless agreed by Zarlink in writing) may not be used, applied or reproduced for any purpose nor form part
of any order or contract nor to be regarded as a representation relating to the products or services concerned. The products, their specifications, services and other
information appearing in this publication are subject to change by Zarlink without notice. No warranty or guarantee express or implied is made regarding the
capability, performance or suitability of any product or service. Information concerning possible methods of use is provided as a guide only and does not constitute
any guarantee that such methods of use will be satisfactory in a specific piece of equipment. It is the user’s responsibility to fully determine the performance and
suitability of any equipment using such information and to ensure that any publication or data used is up to date and has not been superseded. Manufacturing does
not necessarily include testing of all functions or parameters. These products are not suitable for use in any medical products whose failure to perform may result in
significant injury or death to the user. All products and materials are sold and services provided subject to Zarlink’s conditions of sale which are available on request.
Purchase of Zarlink’s I2C components conveys a licence under the Philips I2C Patent rights to use these components in an I2C System, provided that the system
conforms to the I2C Standard Specification as defined by Philips.
Zarlink and the Zarlink Semiconductor logo are trademarks of Zarlink Semiconductor Inc.
Copyright 2002, Zarlink Semiconductor Inc. All Rights Reserved.
TECHNICAL DOCUMENTATION - NOT FOR RESALE